1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_clk_mss_cfm.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_CLK_MSS_CFM_H_ 28 #define HW_CLK_MSS_CFM_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_MSS_BCLKMUX) 36 /*Input mux selections */ 37 #define LIBERO_SETTING_MSS_BCLKMUX 0x00000208UL 38 /* BCLK0_SEL [0:5] RW value= 0x8 */ 39 /* BCLK1_SEL [5:5] RW value= 0x10 */ 40 /* BCLK2_SEL [10:5] RW value= 0x0 */ 41 /* BCLK3_SEL [15:5] RW value= 0x0 */ 42 /* BCLK4_SEL [20:5] RW value= 0x0 */ 43 /* BCLK5_SEL [25:5] RW value= 0x0 */ 44 /* RESERVED [30:2] RW value= 0x0 */ 45 #endif 46 #if !defined (LIBERO_SETTING_MSS_PLL_CKMUX) 47 /*Input mux selections */ 48 #define LIBERO_SETTING_MSS_PLL_CKMUX 0x00000155UL 49 /* CLK_IN_MAC_TSU_SEL [0:2] RW value= 0x1 */ 50 /* PLL0_RFCLK0_SEL [2:2] RW value= 0x1 */ 51 /* PLL0_RFCLK1_SEL [4:2] RW value= 0x1 */ 52 /* PLL1_RFCLK0_SEL [6:2] RW value= 0x1 */ 53 /* PLL1_RFCLK1_SEL [8:2] RW value= 0x1 */ 54 /* PLL1_FDR_SEL [10:5] RW value= 0x0 */ 55 /* RESERVED [15:17] RW value= 0x0 */ 56 #endif 57 #if !defined (LIBERO_SETTING_MSS_MSSCLKMUX) 58 /*MSS Clock mux selections */ 59 #define LIBERO_SETTING_MSS_MSSCLKMUX 0x00000003UL 60 /* MSSCLK_MUX_SEL [0:2] RW value= 0x3 */ 61 /* MSSCLK_MUX_MD [2:2] RW value= 0x0 */ 62 /* CLK_STANDBY_SEL [4:1] RW value= 0x0 */ 63 /* RESERVED [5:27] RW value= 0x0 */ 64 #endif 65 #if !defined (LIBERO_SETTING_MSS_SPARE0) 66 /*spare logic */ 67 #define LIBERO_SETTING_MSS_SPARE0 0x00000000UL 68 /* SPARE0 [0:32] RW value= 0x0 */ 69 #endif 70 #if !defined (LIBERO_SETTING_MSS_FMETER_ADDR) 71 /*Frequency_meter_address_selections */ 72 #define LIBERO_SETTING_MSS_FMETER_ADDR 0x00000000UL 73 /* ADDR10 [0:2] RSVD */ 74 /* ADDR [2:4] RW value= 0x0 */ 75 /* RESERVE18 [6:26] RSVD */ 76 #endif 77 #if !defined (LIBERO_SETTING_MSS_FMETER_DATAW) 78 /*Frequency_meter_data_write */ 79 #define LIBERO_SETTING_MSS_FMETER_DATAW 0x00000000UL 80 /* DATA [0:24] RW value= 0x0 */ 81 /* STROBE [24:1] W1P */ 82 /* RESERVE19 [25:7] RSVD */ 83 #endif 84 #if !defined (LIBERO_SETTING_MSS_FMETER_DATAR) 85 /*Frequency_meter_data_read */ 86 #define LIBERO_SETTING_MSS_FMETER_DATAR 0x00000000UL 87 /* DATA [0:24] RO */ 88 /* RESERVE20 [24:8] RSVD */ 89 #endif 90 #if !defined (LIBERO_SETTING_MSS_IMIRROR_TRIM) 91 /*Imirror TRIM Bits */ 92 #define LIBERO_SETTING_MSS_IMIRROR_TRIM 0x00000000UL 93 /* BG_CODE [0:3] RW value= 0x0 */ 94 /* CC_CODE [3:8] RW value= 0x0 */ 95 /* RESERVE21 [11:21] RSVD */ 96 #endif 97 #if !defined (LIBERO_SETTING_MSS_TEST_CTRL) 98 /*Test MUX Controls */ 99 #define LIBERO_SETTING_MSS_TEST_CTRL 0x00000000UL 100 /* OSC_ENABLE [0:4] RW value= 0x0 */ 101 /* ATEST_EN [4:1] RW value= 0x0 */ 102 /* ATEST_SEL [5:5] RW value= 0x0 */ 103 /* DTEST_EN [10:1] RW value= 0x0 */ 104 /* DTEST_SEL [11:5] RW value= 0x0 */ 105 /* RESERVE22 [16:16] RSVD */ 106 #endif 107 108 #ifdef __cplusplus 109 } 110 #endif 111 112 113 #endif /* #ifdef HW_CLK_MSS_CFM_H_ */ 114 115
