1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_clk_sysreg.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_CLK_SYSREG_H_ 28 #define HW_CLK_SYSREG_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_MSS_CLOCK_CONFIG_CR) 36 /*Master clock config (00=/1 01=/2 10=/4 11=/8 ) */ 37 #define LIBERO_SETTING_MSS_CLOCK_CONFIG_CR 0x00000024UL 38 /* DIVIDER_CPU [0:2] RW value= 0x0 */ 39 /* DIVIDER_AXI [2:2] RW value= 0x1 */ 40 /* DIVIDER_APB_AHB [4:2] RW value= 0x2 */ 41 #endif 42 #if !defined (LIBERO_SETTING_MSS_RTC_CLOCK_CR) 43 /*RTC clock divider */ 44 #define LIBERO_SETTING_MSS_RTC_CLOCK_CR 0x0000007DUL 45 /* PERIOD [0:12] RW value= 0x7D */ 46 #endif 47 #if !defined (LIBERO_SETTING_MSS_ENVM_CR) 48 /*ENVM AHB Controller setup - - Clock period = (Value+1) * (1000/AHBFREQMHZ) 49 e.g. 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz */ 50 #define LIBERO_SETTING_MSS_ENVM_CR 0x40050006UL 51 /* CLOCK_PERIOD [0:6] RW value= 0x6 */ 52 /* CLOCK_CONTINUOUS [8:1] RW value= 0x0 */ 53 /* CLOCK_SUPPRESS [9:1] RW value= 0x0 */ 54 /* READAHEAD [16:1] RW value= 0x1 */ 55 /* SLOWREAD [17:1] RW value= 0x0 */ 56 /* INTERRUPT_ENABLE [18:1] RW value= 0x1 */ 57 /* TIMER [24:8] RW value= 0x40 */ 58 #endif 59 60 #ifdef __cplusplus 61 } 62 #endif 63 64 65 #endif /* #ifdef HW_CLK_SYSREG_H_ */ 66 67
