1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_mssio_mux.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_MSSIO_MUX_H_ 28 #define HW_MSSIO_MUX_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_IOMUX0_CR) 36 /*Selects whether the peripheral is connected to the Fabric or IOMUX structure. 37 */ 38 #define LIBERO_SETTING_IOMUX0_CR 0x00000F9DUL 39 /* SPI0_FABRIC [0:1] RW value= 0x1 */ 40 /* SPI1_FABRIC [1:1] RW value= 0x0 */ 41 /* I2C0_FABRIC [2:1] RW value= 0x1 */ 42 /* I2C1_FABRIC [3:1] RW value= 0x1 */ 43 /* CAN0_FABRIC [4:1] RW value= 0x1 */ 44 /* CAN1_FABRIC [5:1] RW value= 0x0 */ 45 /* QSPI_FABRIC [6:1] RW value= 0x0 */ 46 /* MMUART0_FABRIC [7:1] RW value= 0x1 */ 47 /* MMUART1_FABRIC [8:1] RW value= 0x1 */ 48 /* MMUART2_FABRIC [9:1] RW value= 0x1 */ 49 /* MMUART3_FABRIC [10:1] RW value= 0x1 */ 50 /* MMUART4_FABRIC [11:1] RW value= 0x1 */ 51 /* MDIO0_FABRIC [12:1] RW value= 0x0 */ 52 /* MDIO1_FABRIC [13:1] RW value= 0x0 */ 53 #endif 54 #if !defined (LIBERO_SETTING_IOMUX1_CR) 55 /*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies 56 EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies 57 I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved 58 (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies 59 Logic 0,0xE implies Logic 1, 0xF implies Tristate */ 60 #define LIBERO_SETTING_IOMUX1_CR 0x11111111UL 61 /* PAD0 [0:4] RW value= 0x1 */ 62 /* PAD1 [4:4] RW value= 0x1 */ 63 /* PAD2 [8:4] RW value= 0x1 */ 64 /* PAD3 [12:4] RW value= 0x1 */ 65 /* PAD4 [16:4] RW value= 0x1 */ 66 /* PAD5 [20:4] RW value= 0x1 */ 67 /* PAD6 [24:4] RW value= 0x1 */ 68 /* PAD7 [28:4] RW value= 0x1 */ 69 #endif 70 #if !defined (LIBERO_SETTING_IOMUX2_CR) 71 /*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies 72 EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies 73 I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved 74 (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies 75 Logic 0,0xE implies Logic 1, 0xF implies Tristate */ 76 #define LIBERO_SETTING_IOMUX2_CR 0x00FF1111UL 77 /* PAD8 [0:4] RW value= 0x1 */ 78 /* PAD9 [4:4] RW value= 0x1 */ 79 /* PAD10 [8:4] RW value= 0x1 */ 80 /* PAD11 [12:4] RW value= 0x1 */ 81 /* PAD12 [16:4] RW value= 0xF */ 82 /* PAD13 [20:4] RW value= 0xF */ 83 #endif 84 #if !defined (LIBERO_SETTING_IOMUX3_CR) 85 /*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies 86 EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies 87 I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved 88 (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies 89 Logic 0,0xE implies Logic 1, 0xF implies Tristate */ 90 #define LIBERO_SETTING_IOMUX3_CR 0x44444444UL 91 /* PAD14 [0:4] RW value= 0x4 */ 92 /* PAD15 [4:4] RW value= 0x4 */ 93 /* PAD16 [8:4] RW value= 0x4 */ 94 /* PAD17 [12:4] RW value= 0x4 */ 95 /* PAD18 [16:4] RW value= 0x4 */ 96 /* PAD19 [20:4] RW value= 0x4 */ 97 /* PAD20 [24:4] RW value= 0x4 */ 98 /* PAD21 [28:4] RW value= 0x4 */ 99 #endif 100 #if !defined (LIBERO_SETTING_IOMUX4_CR) 101 /*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies 102 EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies 103 I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved 104 (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies 105 Logic 0,0xE implies Logic 1, 0xF implies Tristate */ 106 #define LIBERO_SETTING_IOMUX4_CR 0x88CC4444UL 107 /* PAD22 [0:4] RW value= 0x4 */ 108 /* PAD23 [4:4] RW value= 0x4 */ 109 /* PAD24 [8:4] RW value= 0x4 */ 110 /* PAD25 [12:4] RW value= 0x4 */ 111 /* PAD26 [16:4] RW value= 0xC */ 112 /* PAD27 [20:4] RW value= 0xC */ 113 /* PAD28 [24:4] RW value= 0x8 */ 114 /* PAD29 [28:4] RW value= 0x8 */ 115 #endif 116 #if !defined (LIBERO_SETTING_IOMUX5_CR) 117 /*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies 118 EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies 119 I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved 120 (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies 121 Logic 0,0xE implies Logic 1, 0xF implies Tristate */ 122 #define LIBERO_SETTING_IOMUX5_CR 0xF7772222UL 123 /* PAD30 [0:4] RW value= 0x2 */ 124 /* PAD31 [4:4] RW value= 0x2 */ 125 /* PAD32 [8:4] RW value= 0x2 */ 126 /* PAD33 [12:4] RW value= 0x2 */ 127 /* PAD34 [16:4] RW value= 0x7 */ 128 /* PAD35 [20:4] RW value= 0x7 */ 129 /* PAD36 [24:4] RW value= 0x7 */ 130 /* PAD37 [28:4] RW value= 0xF */ 131 #endif 132 #if !defined (LIBERO_SETTING_IOMUX6_CR) 133 /*Sets whether the MMC/SD Voltage select lines are inverted on entry to the 134 IOMUX structure */ 135 #define LIBERO_SETTING_IOMUX6_CR 0x00000000UL 136 /* VLT_SEL [0:1] RW value= 0x0 */ 137 /* VLT_EN [1:1] RW value= 0x0 */ 138 /* VLT_CMD_DIR [2:1] RW value= 0x0 */ 139 /* VLT_DIR_0 [3:1] RW value= 0x0 */ 140 /* VLT_DIR_1_3 [4:1] RW value= 0x0 */ 141 /* SD_LED [5:1] RW value= 0x0 */ 142 /* SD_VOLT_0 [6:1] RW value= 0x0 */ 143 /* SD_VOLT_1 [7:1] RW value= 0x0 */ 144 /* SD_VOLT_2 [8:1] RW value= 0x0 */ 145 #endif 146 #if !defined (LIBERO_SETTING_MSSIO_BANK4_CFG_CR) 147 /*Configures the MSSIO block using SCB write */ 148 #define LIBERO_SETTING_MSSIO_BANK4_CFG_CR 0x00040A0DUL 149 /* BANK_PCODE [0:6] RW value= 0xD */ 150 /* RESERVED0 [6:2] RW value= 0x00 */ 151 /* BANK_NCODE [8:6] RW value= 0xA */ 152 /* RESERVED1 [14:2] RW value= 0x0 */ 153 /* VS [16:4] RW value= 0x4 */ 154 /* RESERVED2 [20:12] RW value= 0x0 */ 155 #endif 156 #if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR) 157 /*IO electrical configuration for MSSIO pad */ 158 #define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR 0x09280928UL 159 /* IO_CFG_0 [0:16] RW value= 0x0928 */ 160 /* IO_CFG_1 [16:16] RW value= 0x0928 */ 161 #endif 162 #if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR) 163 /*IO electrical configuration for MSSIO pad */ 164 #define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR 0x09280928UL 165 /* IO_CFG_2 [0:16] RW value= 0x0928 */ 166 /* IO_CFG_3 [16:16] RW value= 0x0928 */ 167 #endif 168 #if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR) 169 /*IO electrical configuration for MSSIO pad */ 170 #define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR 0x09280928UL 171 /* IO_CFG_4 [0:16] RW value= 0x0928 */ 172 /* IO_CFG_5 [16:16] RW value= 0x0928 */ 173 #endif 174 #if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR) 175 /*IO electrical configuration for MSSIO pad */ 176 #define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR 0x09280928UL 177 /* IO_CFG_6 [0:16] RW value= 0x0928 */ 178 /* IO_CFG_7 [16:16] RW value= 0x0928 */ 179 #endif 180 #if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR) 181 /*IO electrical configuration for MSSIO pad */ 182 #define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR 0x09280928UL 183 /* IO_CFG_8 [0:16] RW value= 0x0928 */ 184 /* IO_CFG_9 [16:16] RW value= 0x0928 */ 185 #endif 186 #if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR) 187 /*IO electrical configuration for MSSIO pad */ 188 #define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR 0x09280928UL 189 /* IO_CFG_10 [0:16] RW value= 0x0928 */ 190 /* IO_CFG_11 [16:16] RW value= 0x0928 */ 191 #endif 192 #if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR) 193 /*IO electrical configuration for MSSIO pad */ 194 #define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR 0x09280928UL 195 /* IO_CFG_12 [0:16] RW value= 0x0928 */ 196 /* IO_CFG_13 [16:16] RW value= 0x0928 */ 197 #endif 198 #if !defined (LIBERO_SETTING_MSSIO_BANK2_CFG_CR) 199 /*Configures the MSSIO block using SCB write */ 200 #define LIBERO_SETTING_MSSIO_BANK2_CFG_CR 0x00080907UL 201 /* BANK_PCODE [0:6] RW value= 0x7 */ 202 /* RESERVED0 [6:2] RW value= 0x00 */ 203 /* BANK_NCODE [8:6] RW value= 0x9 */ 204 /* RESERVED1 [14:2] RW value= 0x0 */ 205 /* VS [16:4] RW value= 0x8 */ 206 /* RESERVED2 [20:12] RW value= 0x0 */ 207 #endif 208 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR) 209 /*IO electrical configuration for MSSIO pad */ 210 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR 0x08290829UL 211 /* IO_CFG_0 [0:16] RW value= 0x0829 */ 212 /* IO_CFG_1 [16:16] RW value= 0x0829 */ 213 #endif 214 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR) 215 /*IO electrical configuration for MSSIO pad */ 216 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR 0x08290829UL 217 /* IO_CFG_2 [0:16] RW value= 0x0829 */ 218 /* IO_CFG_3 [16:16] RW value= 0x0829 */ 219 #endif 220 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR) 221 /*IO electrical configuration for MSSIO pad */ 222 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR 0x08290829UL 223 /* IO_CFG_4 [0:16] RW value= 0x0829 */ 224 /* IO_CFG_5 [16:16] RW value= 0x0829 */ 225 #endif 226 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR) 227 /*IO electrical configuration for MSSIO pad */ 228 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR 0x08290829UL 229 /* IO_CFG_6 [0:16] RW value= 0x0829 */ 230 /* IO_CFG_7 [16:16] RW value= 0x0829 */ 231 #endif 232 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR) 233 /*IO electrical configuration for MSSIO pad */ 234 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR 0x08290829UL 235 /* IO_CFG_8 [0:16] RW value= 0x0829 */ 236 /* IO_CFG_9 [16:16] RW value= 0x0829 */ 237 #endif 238 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR) 239 /*IO electrical configuration for MSSIO pad */ 240 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR 0x08290829UL 241 /* IO_CFG_10 [0:16] RW value= 0x0829 */ 242 /* IO_CFG_11 [16:16] RW value= 0x0829 */ 243 #endif 244 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR) 245 /*IO electrical configuration for MSSIO pad */ 246 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR 0x08290829UL 247 /* IO_CFG_12 [0:16] RW value= 0x0829 */ 248 /* IO_CFG_13 [16:16] RW value= 0x0829 */ 249 #endif 250 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR) 251 /*IO electrical configuration for MSSIO pad */ 252 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR 0x08290829UL 253 /* IO_CFG_14 [0:16] RW value= 0x0829 */ 254 /* IO_CFG_15 [16:16] RW value= 0x0829 */ 255 #endif 256 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR) 257 /*IO electrical configuration for MSSIO pad */ 258 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR 0x08290829UL 259 /* IO_CFG_16 [0:16] RW value= 0x0829 */ 260 /* IO_CFG_17 [16:16] RW value= 0x0829 */ 261 #endif 262 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR) 263 /*IO electrical configuration for MSSIO pad */ 264 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR 0x08290829UL 265 /* IO_CFG_18 [0:16] RW value= 0x0829 */ 266 /* IO_CFG_19 [16:16] RW value= 0x0829 */ 267 #endif 268 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR) 269 /*IO electrical configuration for MSSIO pad */ 270 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR 0x08290829UL 271 /* IO_CFG_20 [0:16] RW value= 0x0829 */ 272 /* IO_CFG_21 [16:16] RW value= 0x0829 */ 273 #endif 274 #if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR) 275 /*IO electrical configuration for MSSIO pad */ 276 #define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR 0x08290829UL 277 /* IO_CFG_22 [0:16] RW value= 0x0829 */ 278 /* IO_CFG_23 [16:16] RW value= 0x0829 */ 279 #endif 280 #if !defined (LIBERO_SETTING_MSSIO_VB2_CFG) 281 /*default dpc values for MSSIO bank 2 */ 282 #define LIBERO_SETTING_MSSIO_VB2_CFG 0x00000828UL 283 /* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */ 284 /* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */ 285 /* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */ 286 /* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */ 287 /* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */ 288 /* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */ 289 /* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */ 290 /* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */ 291 /* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */ 292 /* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */ 293 /* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */ 294 /* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */ 295 /* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */ 296 /* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */ 297 /* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */ 298 /* RESERVED [15:17] R */ 299 #endif 300 #if !defined (LIBERO_SETTING_MSSIO_VB4_CFG) 301 /*default dpc values for MSSIO bank 4 */ 302 #define LIBERO_SETTING_MSSIO_VB4_CFG 0x00000828UL 303 /* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */ 304 /* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */ 305 /* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */ 306 /* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */ 307 /* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */ 308 /* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */ 309 /* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */ 310 /* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */ 311 /* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */ 312 /* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */ 313 /* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */ 314 /* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */ 315 /* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */ 316 /* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */ 317 /* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */ 318 /* RESERVED [15:17] R */ 319 #endif 320 #if !defined (LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS) 321 /*Indicates if eMMC is configured for use (bit 0 == 1), If SD is configued for 322 use (bit 1 == 1). Bit 2 indicates which one should be used by default on MSS 323 embedded software startup ( bit2 == 0, implies default is eMMC, bit2 == 1, 324 implies default is SD). The eMMC configuration is always defined in xml tag 325 (io_mux, the SD configuration is always defined in xml tag (io_mux_alt). All 326 other elements in the (o_mux) and (io_mux_alt) not releating to eMMC/SD 327 differences should be the same values. */ 328 #define LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS 0x00000000UL 329 /* EMMC_CONFIGURED [0:1] RW value= 0x0 */ 330 /* SD_CONFIGURED [1:1] RW value= 0x0 */ 331 /* DEFAULT_ON_START [2:1] RW value= 0x0 */ 332 #endif 333 334 #ifdef __cplusplus 335 } 336 #endif 337 338 339 #endif /* #ifdef HW_MSSIO_MUX_H_ */ 340 341
