1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_clk_ddr_pll.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_CLK_DDR_PLL_H_ 28 #define HW_CLK_DDR_PLL_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_DDR_SOFT_RESET) 36 /*This is a compulsory register for all SCB slaves and must be at the same 37 offset in all slaves to facilitate global soft reset of all SCB registers with 38 a single broadcast write from the SCB master. */ 39 #define LIBERO_SETTING_DDR_SOFT_RESET 0x00000000UL 40 /* NV_MAP [0:1] RST */ 41 /* V_MAP [1:1] RST */ 42 /* PERIPH [8:1] RST */ 43 /* BLOCKID [16:16] ID */ 44 #endif 45 #if !defined (LIBERO_SETTING_DDR_PLL_CTRL) 46 /*PLL control register */ 47 #define LIBERO_SETTING_DDR_PLL_CTRL 0x0100003FUL 48 /* REG_POWERDOWN_B [0:1] RW value= 0x1 */ 49 /* REG_RFDIV_EN [1:1] RW value= 0x1 */ 50 /* REG_DIVQ0_EN [2:1] RW value= 0x1 */ 51 /* REG_DIVQ1_EN [3:1] RW value= 0x1 */ 52 /* REG_DIVQ2_EN [4:1] RW value= 0x1 */ 53 /* REG_DIVQ3_EN [5:1] RW value= 0x1 */ 54 /* REG_RFCLK_SEL [6:1] RW value= 0x0 */ 55 /* RESETONLOCK [7:1] RW value= 0x0 */ 56 /* BYPCK_SEL [8:4] RW value= 0x0 */ 57 /* REG_BYPASS_GO_B [12:1] RW value= 0x0 */ 58 /* RESERVE10 [13:3] RSVD */ 59 /* REG_BYPASSPRE [16:4] RW value= 0x0 */ 60 /* REG_BYPASSPOST [20:4] RW value= 0x0 */ 61 /* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */ 62 /* LOCK [25:1] RO */ 63 /* LOCK_INT_EN [26:1] RW value= 0x0 */ 64 /* UNLOCK_INT_EN [27:1] RW value= 0x0 */ 65 /* LOCK_INT [28:1] SW1C */ 66 /* UNLOCK_INT [29:1] SW1C */ 67 /* RESERVE11 [30:1] RSVD */ 68 /* LOCK_B [31:1] RO */ 69 #endif 70 #if !defined (LIBERO_SETTING_DDR_PLL_REF_FB) 71 /*PLL reference and feedback registers */ 72 #define LIBERO_SETTING_DDR_PLL_REF_FB 0x00000500UL 73 /* FSE_B [0:1] RW value= 0x0 */ 74 /* FBCK_SEL [1:2] RW value= 0x0 */ 75 /* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */ 76 /* RESERVE12 [4:4] RSVD */ 77 /* RFDIV [8:6] RW value= 0x5 */ 78 /* RESERVE13 [14:2] RSVD */ 79 /* RESERVE14 [16:12] RSVD */ 80 /* RESERVE15 [28:4] RSVD */ 81 #endif 82 #if !defined (LIBERO_SETTING_DDR_PLL_FRACN) 83 /*PLL fractional register */ 84 #define LIBERO_SETTING_DDR_PLL_FRACN 0x00000000UL 85 /* FRACN_EN [0:1] RW value= 0x0 */ 86 /* FRACN_DAC_EN [1:1] RW value= 0x0 */ 87 /* RESERVE16 [2:6] RSVD */ 88 /* RESERVE17 [8:24] RSVD */ 89 #endif 90 #if !defined (LIBERO_SETTING_DDR_PLL_DIV_0_1) 91 /*PLL 0/1 division registers */ 92 #define LIBERO_SETTING_DDR_PLL_DIV_0_1 0x02000100UL 93 /* VCO0PH_SEL [0:3] RO */ 94 /* DIV0_START [3:3] RW value= 0x0 */ 95 /* RESERVE18 [6:2] RSVD */ 96 /* POST0DIV [8:7] RW value= 0x1 */ 97 /* RESERVE19 [15:1] RSVD */ 98 /* VCO1PH_SEL [16:3] RO */ 99 /* DIV1_START [19:3] RW value= 0x0 */ 100 /* RESERVE20 [22:2] RSVD */ 101 /* POST1DIV [24:7] RW value= 0x2 */ 102 /* RESERVE21 [31:1] RSVD */ 103 #endif 104 #if !defined (LIBERO_SETTING_DDR_PLL_DIV_2_3) 105 /*PLL 2/3 division registers */ 106 #define LIBERO_SETTING_DDR_PLL_DIV_2_3 0x01000100UL 107 /* VCO2PH_SEL [0:3] RO */ 108 /* DIV2_START [3:3] RW value= 0x0 */ 109 /* RESERVE22 [6:2] RSVD */ 110 /* POST2DIV [8:7] RW value= 0x1 */ 111 /* RESERVE23 [15:1] RSVD */ 112 /* VCO3PH_SEL [16:3] RO */ 113 /* DIV3_START [19:3] RW value= 0x0 */ 114 /* RESERVE24 [22:2] RSVD */ 115 /* POST3DIV [24:7] RW value= 0x1 */ 116 /* CKPOST3_SEL [31:1] RW value= 0x0 */ 117 #endif 118 #if !defined (LIBERO_SETTING_DDR_PLL_CTRL2) 119 /*PLL control register */ 120 #define LIBERO_SETTING_DDR_PLL_CTRL2 0x00001020UL 121 /* BWI [0:2] RW value= 0x0 */ 122 /* BWP [2:2] RW value= 0x0 */ 123 /* IREF_EN [4:1] RW value= 0x0 */ 124 /* IREF_TOGGLE [5:1] RW value= 0x1 */ 125 /* RESERVE25 [6:3] RSVD */ 126 /* LOCKCNT [9:4] RW value= 0x8 */ 127 /* RESERVE26 [13:4] RSVD */ 128 /* ATEST_EN [17:1] RW value= 0x0 */ 129 /* ATEST_SEL [18:3] RW value= 0x0 */ 130 /* RESERVE27 [21:11] RSVD */ 131 #endif 132 #if !defined (LIBERO_SETTING_DDR_PLL_CAL) 133 /*PLL calibration register */ 134 #define LIBERO_SETTING_DDR_PLL_CAL 0x00000D06UL 135 /* DSKEWCALCNT [0:3] RW value= 0x6 */ 136 /* DSKEWCAL_EN [3:1] RW value= 0x0 */ 137 /* DSKEWCALBYP [4:1] RW value= 0x0 */ 138 /* RESERVE28 [5:3] RSVD */ 139 /* DSKEWCALIN [8:7] RW value= 0xd */ 140 /* RESERVE29 [15:1] RSVD */ 141 /* DSKEWCALOUT [16:7] RO */ 142 /* RESERVE30 [23:9] RSVD */ 143 #endif 144 #if !defined (LIBERO_SETTING_DDR_PLL_PHADJ) 145 /*PLL phase registers */ 146 #define LIBERO_SETTING_DDR_PLL_PHADJ 0x00005003UL 147 /* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */ 148 /* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */ 149 /* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */ 150 /* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */ 151 /* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */ 152 /* REG_OUT3_PHSINIT [11:3] RW value= 0x2 */ 153 /* REG_LOADPHS_B [14:1] RW value= 0x1 */ 154 /* RESERVE31 [15:17] RSVD */ 155 #endif 156 #if !defined (LIBERO_SETTING_DDR_SSCG_REG_0) 157 /*SSCG registers 0 */ 158 #define LIBERO_SETTING_DDR_SSCG_REG_0 0x00000000UL 159 /* DIVVAL [0:6] RW value= 0x0 */ 160 /* FRACIN [6:24] RW value= 0x0 */ 161 /* RESERVE00 [30:2] RSVD */ 162 #endif 163 #if !defined (LIBERO_SETTING_DDR_SSCG_REG_1) 164 /*SSCG registers 1 */ 165 #define LIBERO_SETTING_DDR_SSCG_REG_1 0x00000000UL 166 /* DOWNSPREAD [0:1] RW value= 0x0 */ 167 /* SSMD [1:5] RW value= 0x0 */ 168 /* FRACMOD [6:24] RO */ 169 /* RESERVE01 [30:2] RSVD */ 170 #endif 171 #if !defined (LIBERO_SETTING_DDR_SSCG_REG_2) 172 /*SSCG registers 2 */ 173 #define LIBERO_SETTING_DDR_SSCG_REG_2 0x00000080UL 174 /* INTIN [0:12] RW value= 0x80 */ 175 /* INTMOD [12:12] RO */ 176 /* RESERVE02 [24:8] RSVD */ 177 #endif 178 #if !defined (LIBERO_SETTING_DDR_SSCG_REG_3) 179 /*SSCG registers 3 */ 180 #define LIBERO_SETTING_DDR_SSCG_REG_3 0x00000001UL 181 /* SSE_B [0:1] RW value= 0x1 */ 182 /* SEL_EXTWAVE [1:2] RW value= 0x0 */ 183 /* EXT_MAXADDR [3:8] RW value= 0x0 */ 184 /* TBLADDR [11:8] RO */ 185 /* RANDOM_FILTER [19:1] RW value= 0x0 */ 186 /* RANDOM_SEL [20:2] RW value= 0x0 */ 187 /* RESERVE03 [22:1] RSVD */ 188 /* RESERVE04 [23:9] RSVD */ 189 #endif 190 191 #ifdef __cplusplus 192 } 193 #endif 194 195 196 #endif /* #ifdef HW_CLK_DDR_PLL_H_ */ 197 198
