1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_apb_split.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_APB_SPLIT_H_ 28 #define HW_APB_SPLIT_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_APB_SPLIT_VERSION) 36 /*This version incrments when change to format of this file */ 37 #define LIBERO_SETTING_APB_SPLIT_VERSION 0x00000001UL 38 /* VERSION [0:32] RW value= 0x1 */ 39 #endif 40 #if !defined (LIBERO_SETTING_MEM_CONFIGS_ENABLED) 41 /*Enabled in configurator when bit set to 1 */ 42 #define LIBERO_SETTING_MEM_CONFIGS_ENABLED 0x00000003UL 43 /* PMP [0:0] RW value= 0x1 */ 44 /* MPU [1:0] RW value= 0x1 */ 45 #endif 46 #if !defined (LIBERO_SETTING_APBBUS_CR) 47 /*AMP Mode peripheral mapping register. When the register bit is '0' the 48 peripheral is mapped into the 0x2000000 address range using AXI bus 5 from the 49 Coreplex. When the register bit is '1' the peripheral is mapped into the 50 0x28000000 address range using AXI bus 6 from the Coreplex. */ 51 #define LIBERO_SETTING_APBBUS_CR 0x0012A818UL 52 /* MMUART0 [0:1] RW value= 0x0 */ 53 /* MMUART1 [1:1] RW value= 0x0 */ 54 /* MMUART2 [2:1] RW value= 0x0 */ 55 /* MMUART3 [3:1] RW value= 0x1 */ 56 /* MMUART4 [4:1] RW value= 0x1 */ 57 /* WDOG0 [5:1] RW value= 0x0 */ 58 /* WDOG1 [6:1] RW value= 0x0 */ 59 /* WDOG2 [7:1] RW value= 0x0 */ 60 /* WDOG3 [8:1] RW value= 0x0 */ 61 /* WDOG4 [9:1] RW value= 0x0 */ 62 /* SPI0 [10:1] RW value= 0x0 */ 63 /* SPI1 [11:1] RW value= 0x1 */ 64 /* I2C0 [12:1] RW value= 0x0 */ 65 /* I2C1 [13:1] RW value= 0x1 */ 66 /* CAN0 [14:1] RW value= 0x0 */ 67 /* CAN1 [15:1] RW value= 0x1 */ 68 /* GEM0 [16:1] RW value= 0x0 */ 69 /* GEM1 [17:1] RW value= 0x1 */ 70 /* TIMER [18:1] RW value= 0x0 */ 71 /* GPIO0 [19:1] RW value= 0x0 */ 72 /* GPIO1 [20:1] RW value= 0x1 */ 73 /* GPIO2 [21:1] RW value= 0x0 */ 74 /* RTC [22:1] RW value= 0x0 */ 75 /* H2FINT [23:1] RW value= 0x0 */ 76 #endif 77 #if !defined (LIBERO_SETTING_CONTEXT_A_EN) 78 /*AMP context A. When the register bit is '0' the peripheral is not allowed 79 access from context A. */ 80 #define LIBERO_SETTING_CONTEXT_A_EN 0x4F695406UL 81 /* MMUART0 [0:1] RW value= 0x0 */ 82 /* MMUART1 [1:1] RW value= 0x1 */ 83 /* MMUART2 [2:1] RW value= 0x1 */ 84 /* MMUART3 [3:1] RW value= 0x0 */ 85 /* MMUART4 [4:1] RW value= 0x0 */ 86 /* WDOG0 [5:1] RW value= 0x0 */ 87 /* WDOG1 [6:1] RW value= 0x0 */ 88 /* WDOG2 [7:1] RW value= 0x0 */ 89 /* WDOG3 [8:1] RW value= 0x0 */ 90 /* WDOG4 [9:1] RW value= 0x0 */ 91 /* SPI0 [10:1] RW value= 0x1 */ 92 /* SPI1 [11:1] RW value= 0x0 */ 93 /* I2C0 [12:1] RW value= 0x1 */ 94 /* I2C1 [13:1] RW value= 0x0 */ 95 /* CAN0 [14:1] RW value= 0x1 */ 96 /* CAN1 [15:1] RW value= 0x0 */ 97 /* GEM0 [16:1] RW value= 0x1 */ 98 /* GEM1 [17:1] RW value= 0x0 */ 99 /* TIMER [18:1] RW value= 0x0 */ 100 /* GPIO0 [19:1] RW value= 0x1 */ 101 /* GPIO1 [20:1] RW value= 0x0 */ 102 /* GPIO2 [21:1] RW value= 0x1 */ 103 /* RTC [22:1] RW value= 0x1 */ 104 /* H2FINT [23:1] RW value= 0x0 */ 105 /* CRYPTO [24:1] RW value= 0x1 */ 106 /* USB [25:1] RW value= 0x1 */ 107 /* QSPIXIP [26:1] RW value= 0x1 */ 108 /* ATHENA [27:1] RW value= 0x1 */ 109 /* TRACE [28:1] RW value= 0x0 */ 110 /* MAILBOX_SC [29:1] RW value= 0x0 */ 111 /* EMMC [30:1] RW value= 0x1 */ 112 #endif 113 #if !defined (LIBERO_SETTING_CONTEXT_B_EN) 114 /*AMP context B. When the register bit is '0' the peripheral is not allowed 115 access from context B. */ 116 #define LIBERO_SETTING_CONTEXT_B_EN 0x0012A818UL 117 /* MMUART0 [0:1] RW value= 0x0 */ 118 /* MMUART1 [1:1] RW value= 0x0 */ 119 /* MMUART2 [2:1] RW value= 0x0 */ 120 /* MMUART3 [3:1] RW value= 0x1 */ 121 /* MMUART4 [4:1] RW value= 0x1 */ 122 /* WDOG0 [5:1] RW value= 0x0 */ 123 /* WDOG1 [6:1] RW value= 0x0 */ 124 /* WDOG2 [7:1] RW value= 0x0 */ 125 /* WDOG3 [8:1] RW value= 0x0 */ 126 /* WDOG4 [9:1] RW value= 0x0 */ 127 /* SPI0 [10:1] RW value= 0x0 */ 128 /* SPI1 [11:1] RW value= 0x1 */ 129 /* I2C0 [12:1] RW value= 0x0 */ 130 /* I2C1 [13:1] RW value= 0x1 */ 131 /* CAN0 [14:1] RW value= 0x0 */ 132 /* CAN1 [15:1] RW value= 0x1 */ 133 /* GEM0 [16:1] RW value= 0x0 */ 134 /* GEM1 [17:1] RW value= 0x1 */ 135 /* TIMER [18:1] RW value= 0x0 */ 136 /* GPIO0 [19:1] RW value= 0x0 */ 137 /* GPIO1 [20:1] RW value= 0x1 */ 138 /* GPIO2 [21:1] RW value= 0x0 */ 139 /* RTC [22:1] RW value= 0x0 */ 140 /* H2FINT [23:1] RW value= 0x0 */ 141 /* CRYPTO [24:1] RW value= 0x0 */ 142 /* USB [25:1] RW value= 0x0 */ 143 /* QSPIXIP [26:1] RW value= 0x0 */ 144 /* ATHENA [27:1] RW value= 0x0 */ 145 /* TRACE [28:1] RW value= 0x0 */ 146 /* MAILBOX_SC [29:1] RW value= 0x0 */ 147 /* EMMC [30:1] RW value= 0x0 */ 148 #endif 149 #if !defined (LIBERO_SETTING_CONTEXT_A_HART_EN) 150 /*When the register bit is '0' hart is not associated with context A. */ 151 #define LIBERO_SETTING_CONTEXT_A_HART_EN 0x00000006UL 152 /* HART0 [0:1] RW value= 0x0 */ 153 /* HART1 [1:1] RW value= 0x1 */ 154 /* HART2 [2:1] RW value= 0x1 */ 155 /* HART3 [3:1] RW value= 0x0 */ 156 /* HART4 [4:1] RW value= 0x0 */ 157 #endif 158 #if !defined (LIBERO_SETTING_CONTEXT_B_HART_EN) 159 /*When the register bit is '0' hart is not associated with context B. */ 160 #define LIBERO_SETTING_CONTEXT_B_HART_EN 0x00000018UL 161 /* HART0 [0:1] RW value= 0x0 */ 162 /* HART1 [1:1] RW value= 0x0 */ 163 /* HART2 [2:1] RW value= 0x0 */ 164 /* HART3 [3:1] RW value= 0x1 */ 165 /* HART4 [4:1] RW value= 0x1 */ 166 #endif 167 168 #ifdef __cplusplus 169 } 170 #endif 171 172 173 #endif /* #ifdef HW_APB_SPLIT_H_ */ 174 175
