1 /* 2 * Copyright (c) 2020 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _NUVOTON_NPCX_SOC_CLOCK_H_ 8 #define _NUVOTON_NPCX_SOC_CLOCK_H_ 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 13 #include <zephyr/devicetree.h> 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 /* Common clock control device node for all NPCX series */ 20 #define NPCX_CLK_CTRL_NODE DT_NODELABEL(pcc) 21 22 /** 23 * @brief NPCX clock configuration structure 24 * 25 * Used to indicate the device's clock bus type and corresponding PWDWN_CTL 26 * register/bit to turn on/off its source clock. 27 */ 28 struct npcx_clk_cfg { 29 uint16_t bus:8; 30 uint16_t ctrl:5; 31 uint16_t bit:3; 32 }; 33 34 /* Clock settings from pcc node */ 35 /* Target OFMCLK freq */ 36 #define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency) 37 /* Core clock prescaler */ 38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1) 39 /* APB1 clock divider */ 40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1) 41 /* APB2 clock divider */ 42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1) 43 /* APB3 clock divider */ 44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1) 45 /* APB4 clock divider if supported */ 46 #if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler) 47 #if !defined(CONFIG_SOC_SERIES_NPCX7) /* Supported in NPCX9 and later series */ 48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1) 49 #else 50 #error "APB4 clock divider is not supported but defined in pcc node!" 51 #endif /* !CONFIG_SOC_SERIES_NPCX7 */ 52 #endif 53 54 /* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */ 55 #define NPCX_PWDWN_CTL_ITEMS_INIT(node, prop, idx) DT_PROP_BY_IDX(node, prop, idx), 56 #define NPCX_PWDWN_CTL_INIT DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), \ 57 pwdwn_ctl_val, NPCX_PWDWN_CTL_ITEMS_INIT) 58 59 /* 60 * NPCX7 and later series clock tree macros: 61 * (Please refer Figure 58. for more information.) 62 * 63 * Maximum OFMCLK in npcx7/9 series is 100MHz, 64 * Maximum OFMCLK in npcx4 series is 120MHz, 65 * 66 * Suggestion for npcx series: 67 * - OFMCLK > MAX_OFMCLK/2, XF_RANGE should be 1, else 0. 68 * - CORE_CLK > MAX_OFMCLK/2, AHB6DIV should be 1, else 0. 69 * - CORE_CLK > MAX_OFMCLK/2, FIUDIV should be 1, else 0. 70 */ 71 #if defined(CONFIG_SOC_SERIES_NPCX4) 72 #define MAX_OFMCLK 120000000 73 #else 74 #define MAX_OFMCLK 100000000 75 #endif /* CONFIG_SOC_SERIES_NPCX4 */ 76 77 /* Core domain clock */ 78 #define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler)) 79 /* Low Frequency clock */ 80 #define LFCLK 32768 81 82 /* FMUL clock */ 83 #if (OFMCLK > (MAX_OFMCLK / 2)) 84 #define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */ 85 #else 86 #define FMCLK OFMCLK /* FMUL clock = OFMCLK */ 87 #endif 88 89 /* APBs source clock */ 90 #define APBSRC_CLK OFMCLK 91 92 /* AHB6 clock */ 93 #if (CORE_CLK > (MAX_OFMCLK / 2)) 94 #define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */ 95 #else 96 #define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */ 97 #endif 98 99 /* FIU clock divider */ 100 #if (CORE_CLK > (MAX_OFMCLK / 2)) 101 #define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */ 102 #else 103 #define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */ 104 #endif 105 106 #if defined(CONFIG_SOC_SERIES_NPCX4) 107 #if (CORE_CLK > (MAX_OFMCLK / 2)) 108 #define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */ 109 #else 110 #define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */ 111 #endif 112 #endif /* CONFIG_SOC_SERIES_NPCX4 */ 113 114 /* Get APB clock freq */ 115 #define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1)) 116 117 /* 118 * Frequency multiplier M/N value definitions according to the requested 119 * OFMCLK (Unit:Hz). 120 */ 121 #if (OFMCLK > (MAX_OFMCLK / 2)) 122 #define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 */ 123 #else 124 #define HFCGN_VAL 0x02 125 #endif 126 #if (OFMCLK == 120000000) 127 #define HFCGMH_VAL 0x0E 128 #define HFCGML_VAL 0x4E 129 #elif (OFMCLK == 100000000) 130 #define HFCGMH_VAL 0x0B 131 #define HFCGML_VAL 0xEC 132 #elif (OFMCLK == 96000000) 133 #define HFCGMH_VAL 0x0B 134 #define HFCGML_VAL 0x72 135 #elif (OFMCLK == 90000000) 136 #define HFCGMH_VAL 0x0A 137 #define HFCGML_VAL 0xBA 138 #elif (OFMCLK == 80000000) 139 #define HFCGMH_VAL 0x09 140 #define HFCGML_VAL 0x89 141 #elif (OFMCLK == 66000000) 142 #define HFCGMH_VAL 0x07 143 #define HFCGML_VAL 0xDE 144 #elif (OFMCLK == 50000000) 145 #define HFCGMH_VAL 0x0B 146 #define HFCGML_VAL 0xEC 147 #elif (OFMCLK == 48000000) 148 #define HFCGMH_VAL 0x0B 149 #define HFCGML_VAL 0x72 150 #else 151 #error "Unsupported OFMCLK Frequency" 152 #endif 153 154 /* Clock prescaler configurations in different series */ 155 #define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL) 156 #if defined(FIU1DIV_VAL) 157 #define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2)) 158 #else 159 #define VAL_HFCBCD (FIUDIV_VAL << 4) 160 #endif /* FIU1DIV_VAL */ 161 #define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4)) 162 #if defined(APB4DIV_VAL) 163 #define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4)) 164 #else 165 #define VAL_HFCBCD2 APB3DIV_VAL 166 #endif /* APB4DIV_VAL */ 167 168 /** 169 * @brief Function to notify clock driver that backup the counter value of 170 * low-frequency timer before ec entered deep idle state. 171 */ 172 void npcx_clock_capture_low_freq_timer(void); 173 174 /** 175 * @brief Function to notify clock driver that compensate the counter value of 176 * system timer by low-frequency timer after ec left deep idle state. 177 * 178 */ 179 void npcx_clock_compensate_system_timer(void); 180 181 /** 182 * @brief Function to get time ticks in system sleep/deep sleep state. The unit 183 * is ticks. 184 * 185 */ 186 uint64_t npcx_clock_get_sleep_ticks(void); 187 188 /** 189 * @brief Function to configure system sleep settings. After ec received "wfi" 190 * instruction, ec will enter sleep/deep sleep state for better power 191 * consumption. 192 * 193 * @param is_deep A boolean indicating ec enters deep sleep or sleep state 194 * @param is_instant A boolean indicating 'Instant Wake-up' from deep idle is 195 * enabled 196 */ 197 void npcx_clock_control_turn_on_system_sleep(bool is_deep, bool is_instant); 198 199 /** 200 * @brief Function to turn off system sleep mode. 201 */ 202 void npcx_clock_control_turn_off_system_sleep(void); 203 204 #ifdef __cplusplus 205 } 206 #endif 207 208 #endif /* _NUVOTON_NPCX_SOC_CLOCK_H_ */ 209
