1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_LFAST.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_LFAST 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_LFAST_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_LFAST_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LFAST Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LFAST_Peripheral_Access_Layer LFAST Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LFAST - Size of Registers Arrays */ 72 #define LFAST_UNSTDR_COUNT 9u 73 #define LFAST_UNSRDR_COUNT 9u 74 #define LFAST_GPR_COUNT 1u 75 76 /** LFAST - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t MCR; /**< LFAST Mode Configuration Register, offset: 0x0 */ 79 __IO uint32_t SCR; /**< LFAST Speed Control Register, offset: 0x4 */ 80 __IO uint32_t COCR; /**< LFAST Correlator Control Register, offset: 0x8 */ 81 __IO uint32_t TMCR; /**< LFAST Test Mode Control Register, offset: 0xC */ 82 __IO uint32_t ALCR; /**< LFAST Auto Loopback Control Register, offset: 0x10 */ 83 __IO uint32_t RCDCR; /**< LFAST Rate Change Delay Control Register, offset: 0x14 */ 84 __IO uint32_t SLCR; /**< LFAST Wakeup Delay Control Register, offset: 0x18 */ 85 __IO uint32_t ICR; /**< LFAST ICLC Control Register, offset: 0x1C */ 86 __IO uint32_t PICR; /**< LFAST Ping Control Register, offset: 0x20 */ 87 uint8_t RESERVED_0[8]; 88 __IO uint32_t RFCR; /**< LFAST Rx FIFO CTS Control Register, offset: 0x2C */ 89 __IO uint32_t TIER; /**< LFAST Tx Interrupt Enable Register, offset: 0x30 */ 90 __IO uint32_t RIER; /**< LFAST Rx Interrupt Enable Register, offset: 0x34 */ 91 __IO uint32_t RIIER; /**< LFAST Rx ICLC Interrupt Enable Register, offset: 0x38 */ 92 __IO uint32_t PLLCR; /**< LFAST PLL Control Register, offset: 0x3C */ 93 uint8_t RESERVED_1[4]; 94 __IO uint32_t UNSTCR; /**< LFAST Unsolicited Tx Control Register, offset: 0x44 */ 95 __IO uint32_t UNSTDR[LFAST_UNSTDR_COUNT]; /**< LFAST Unsolicited Tx Data Registers, array offset: 0x48, array step: 0x4 */ 96 uint8_t RESERVED_2[20]; 97 __I uint32_t GSR; /**< LFAST Global Status Register, offset: 0x80 */ 98 __I uint32_t PISR; /**< LFAST Ping Status Register, offset: 0x84 */ 99 uint8_t RESERVED_3[12]; 100 __I uint32_t DFSR; /**< LFAST Data Frame Status Register, offset: 0x94 */ 101 __IO uint32_t TISR; /**< LFAST Tx Interrupt Status Register, offset: 0x98 */ 102 __IO uint32_t RISR; /**< LFAST Rx Interrupt Status Register, offset: 0x9C */ 103 __IO uint32_t RIISR; /**< LFAST Rx ICLC Interrupt Status Register, offset: 0xA0 */ 104 __I uint32_t PLLLSR; /**< LFAST PLL and LVDS Status Register, offset: 0xA4 */ 105 __IO uint32_t UNSRSR; /**< LFAST Unsolicited Rx Status Register, offset: 0xA8 */ 106 __I uint32_t UNSRDR[LFAST_UNSRDR_COUNT]; /**< LFAST Unsolicited Rx Data Register, array offset: 0xAC, array step: 0x4 */ 107 uint8_t RESERVED_4[4]; 108 __IO uint32_t GPR[LFAST_GPR_COUNT]; /**< General Purpose registers, array offset: 0xD4, array step: 0x4 */ 109 } LFAST_Type, *LFAST_MemMapPtr; 110 111 /** Number of instances of the LFAST module. */ 112 #define LFAST_INSTANCE_COUNT (2u) 113 114 /* LFAST - Peripheral instance base addresses */ 115 /** Peripheral LFAST_0 base address */ 116 #define IP_LFAST_0_BASE (0x40A10000u) 117 /** Peripheral LFAST_0 base pointer */ 118 #define IP_LFAST_0 ((LFAST_Type *)IP_LFAST_0_BASE) 119 /** Peripheral LFAST_1 base address */ 120 #define IP_LFAST_1_BASE (0x40A30000u) 121 /** Peripheral LFAST_1 base pointer */ 122 #define IP_LFAST_1 ((LFAST_Type *)IP_LFAST_1_BASE) 123 /** Array initializer of LFAST peripheral base addresses */ 124 #define IP_LFAST_BASE_ADDRS { IP_LFAST_0_BASE, IP_LFAST_1_BASE } 125 /** Array initializer of LFAST peripheral base pointers */ 126 #define IP_LFAST_BASE_PTRS { IP_LFAST_0, IP_LFAST_1 } 127 128 /* ---------------------------------------------------------------------------- 129 -- LFAST Register Masks 130 ---------------------------------------------------------------------------- */ 131 132 /*! 133 * @addtogroup LFAST_Register_Masks LFAST Register Masks 134 * @{ 135 */ 136 137 /*! @name MCR - LFAST Mode Configuration Register */ 138 /*! @{ */ 139 140 #define LFAST_MCR_DATAEN_MASK (0x1U) 141 #define LFAST_MCR_DATAEN_SHIFT (0U) 142 #define LFAST_MCR_DATAEN_WIDTH (1U) 143 #define LFAST_MCR_DATAEN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_DATAEN_SHIFT)) & LFAST_MCR_DATAEN_MASK) 144 145 #define LFAST_MCR_DRFRST_MASK (0x2U) 146 #define LFAST_MCR_DRFRST_SHIFT (1U) 147 #define LFAST_MCR_DRFRST_WIDTH (1U) 148 #define LFAST_MCR_DRFRST(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_DRFRST_SHIFT)) & LFAST_MCR_DRFRST_MASK) 149 150 #define LFAST_MCR_CTSEN_MASK (0x8U) 151 #define LFAST_MCR_CTSEN_SHIFT (3U) 152 #define LFAST_MCR_CTSEN_WIDTH (1U) 153 #define LFAST_MCR_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_CTSEN_SHIFT)) & LFAST_MCR_CTSEN_MASK) 154 155 #define LFAST_MCR_TXARBD_MASK (0x10U) 156 #define LFAST_MCR_TXARBD_SHIFT (4U) 157 #define LFAST_MCR_TXARBD_WIDTH (1U) 158 #define LFAST_MCR_TXARBD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_TXARBD_SHIFT)) & LFAST_MCR_TXARBD_MASK) 159 160 #define LFAST_MCR_TXEN_MASK (0x2000U) 161 #define LFAST_MCR_TXEN_SHIFT (13U) 162 #define LFAST_MCR_TXEN_WIDTH (1U) 163 #define LFAST_MCR_TXEN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_TXEN_SHIFT)) & LFAST_MCR_TXEN_MASK) 164 165 #define LFAST_MCR_RXEN_MASK (0x4000U) 166 #define LFAST_MCR_RXEN_SHIFT (14U) 167 #define LFAST_MCR_RXEN_WIDTH (1U) 168 #define LFAST_MCR_RXEN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_RXEN_SHIFT)) & LFAST_MCR_RXEN_MASK) 169 170 #define LFAST_MCR_DRFEN_MASK (0x8000U) 171 #define LFAST_MCR_DRFEN_SHIFT (15U) 172 #define LFAST_MCR_DRFEN_WIDTH (1U) 173 #define LFAST_MCR_DRFEN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_DRFEN_SHIFT)) & LFAST_MCR_DRFEN_MASK) 174 175 #define LFAST_MCR_LSSEL_MASK (0x10000U) 176 #define LFAST_MCR_LSSEL_SHIFT (16U) 177 #define LFAST_MCR_LSSEL_WIDTH (1U) 178 #define LFAST_MCR_LSSEL(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_LSSEL_SHIFT)) & LFAST_MCR_LSSEL_MASK) 179 180 #define LFAST_MCR_IPGDBG_MASK (0x1000000U) 181 #define LFAST_MCR_IPGDBG_SHIFT (24U) 182 #define LFAST_MCR_IPGDBG_WIDTH (1U) 183 #define LFAST_MCR_IPGDBG(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_IPGDBG_SHIFT)) & LFAST_MCR_IPGDBG_MASK) 184 185 #define LFAST_MCR_MSEN_MASK (0x80000000U) 186 #define LFAST_MCR_MSEN_SHIFT (31U) 187 #define LFAST_MCR_MSEN_WIDTH (1U) 188 #define LFAST_MCR_MSEN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_MCR_MSEN_SHIFT)) & LFAST_MCR_MSEN_MASK) 189 /*! @} */ 190 191 /*! @name SCR - LFAST Speed Control Register */ 192 /*! @{ */ 193 194 #define LFAST_SCR_TDR_MASK (0x1U) 195 #define LFAST_SCR_TDR_SHIFT (0U) 196 #define LFAST_SCR_TDR_WIDTH (1U) 197 #define LFAST_SCR_TDR(x) (((uint32_t)(((uint32_t)(x)) << LFAST_SCR_TDR_SHIFT)) & LFAST_SCR_TDR_MASK) 198 199 #define LFAST_SCR_RDR_MASK (0x100U) 200 #define LFAST_SCR_RDR_SHIFT (8U) 201 #define LFAST_SCR_RDR_WIDTH (1U) 202 #define LFAST_SCR_RDR(x) (((uint32_t)(((uint32_t)(x)) << LFAST_SCR_RDR_SHIFT)) & LFAST_SCR_RDR_MASK) 203 204 #define LFAST_SCR_DRMD_MASK (0x10000U) 205 #define LFAST_SCR_DRMD_SHIFT (16U) 206 #define LFAST_SCR_DRMD_WIDTH (1U) 207 #define LFAST_SCR_DRMD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_SCR_DRMD_SHIFT)) & LFAST_SCR_DRMD_MASK) 208 /*! @} */ 209 210 /*! @name COCR - LFAST Correlator Control Register */ 211 /*! @{ */ 212 213 #define LFAST_COCR_PHSSEL_MASK (0x1U) 214 #define LFAST_COCR_PHSSEL_SHIFT (0U) 215 #define LFAST_COCR_PHSSEL_WIDTH (1U) 216 #define LFAST_COCR_PHSSEL(x) (((uint32_t)(((uint32_t)(x)) << LFAST_COCR_PHSSEL_SHIFT)) & LFAST_COCR_PHSSEL_MASK) 217 218 #define LFAST_COCR_CORRTH_MASK (0xEU) 219 #define LFAST_COCR_CORRTH_SHIFT (1U) 220 #define LFAST_COCR_CORRTH_WIDTH (3U) 221 #define LFAST_COCR_CORRTH(x) (((uint32_t)(((uint32_t)(x)) << LFAST_COCR_CORRTH_SHIFT)) & LFAST_COCR_CORRTH_MASK) 222 223 #define LFAST_COCR_SMPSEL_MASK (0xFF000000U) 224 #define LFAST_COCR_SMPSEL_SHIFT (24U) 225 #define LFAST_COCR_SMPSEL_WIDTH (8U) 226 #define LFAST_COCR_SMPSEL(x) (((uint32_t)(((uint32_t)(x)) << LFAST_COCR_SMPSEL_SHIFT)) & LFAST_COCR_SMPSEL_MASK) 227 /*! @} */ 228 229 /*! @name TMCR - LFAST Test Mode Control Register */ 230 /*! @{ */ 231 232 #define LFAST_TMCR_LPFRMTH_MASK (0xFFFFU) 233 #define LFAST_TMCR_LPFRMTH_SHIFT (0U) 234 #define LFAST_TMCR_LPFRMTH_WIDTH (16U) 235 #define LFAST_TMCR_LPFRMTH(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TMCR_LPFRMTH_SHIFT)) & LFAST_TMCR_LPFRMTH_MASK) 236 237 #define LFAST_TMCR_LPMOD_MASK (0x70000U) 238 #define LFAST_TMCR_LPMOD_SHIFT (16U) 239 #define LFAST_TMCR_LPMOD_WIDTH (3U) 240 #define LFAST_TMCR_LPMOD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TMCR_LPMOD_SHIFT)) & LFAST_TMCR_LPMOD_MASK) 241 242 #define LFAST_TMCR_LPON_MASK (0x1000000U) 243 #define LFAST_TMCR_LPON_SHIFT (24U) 244 #define LFAST_TMCR_LPON_WIDTH (1U) 245 #define LFAST_TMCR_LPON(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TMCR_LPON_SHIFT)) & LFAST_TMCR_LPON_MASK) 246 247 #define LFAST_TMCR_CLKTST_MASK (0x2000000U) 248 #define LFAST_TMCR_CLKTST_SHIFT (25U) 249 #define LFAST_TMCR_CLKTST_WIDTH (1U) 250 #define LFAST_TMCR_CLKTST(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TMCR_CLKTST_SHIFT)) & LFAST_TMCR_CLKTST_MASK) 251 /*! @} */ 252 253 /*! @name ALCR - LFAST Auto Loopback Control Register */ 254 /*! @{ */ 255 256 #define LFAST_ALCR_LPFMCNT_MASK (0xFFFFU) 257 #define LFAST_ALCR_LPFMCNT_SHIFT (0U) 258 #define LFAST_ALCR_LPFMCNT_WIDTH (16U) 259 #define LFAST_ALCR_LPFMCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_ALCR_LPFMCNT_SHIFT)) & LFAST_ALCR_LPFMCNT_MASK) 260 261 #define LFAST_ALCR_LPCNTEN_MASK (0x10000U) 262 #define LFAST_ALCR_LPCNTEN_SHIFT (16U) 263 #define LFAST_ALCR_LPCNTEN_WIDTH (1U) 264 #define LFAST_ALCR_LPCNTEN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_ALCR_LPCNTEN_SHIFT)) & LFAST_ALCR_LPCNTEN_MASK) 265 /*! @} */ 266 267 /*! @name RCDCR - LFAST Rate Change Delay Control Register */ 268 /*! @{ */ 269 270 #define LFAST_RCDCR_DRCNT_MASK (0xF0000U) 271 #define LFAST_RCDCR_DRCNT_SHIFT (16U) 272 #define LFAST_RCDCR_DRCNT_WIDTH (4U) 273 #define LFAST_RCDCR_DRCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RCDCR_DRCNT_SHIFT)) & LFAST_RCDCR_DRCNT_MASK) 274 /*! @} */ 275 276 /*! @name SLCR - LFAST Wakeup Delay Control Register */ 277 /*! @{ */ 278 279 #define LFAST_SLCR_LWKCNT_MASK (0xFU) 280 #define LFAST_SLCR_LWKCNT_SHIFT (0U) 281 #define LFAST_SLCR_LWKCNT_WIDTH (4U) 282 #define LFAST_SLCR_LWKCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_SLCR_LWKCNT_SHIFT)) & LFAST_SLCR_LWKCNT_MASK) 283 284 #define LFAST_SLCR_HWKCNT_MASK (0xFF00U) 285 #define LFAST_SLCR_HWKCNT_SHIFT (8U) 286 #define LFAST_SLCR_HWKCNT_WIDTH (8U) 287 #define LFAST_SLCR_HWKCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_SLCR_HWKCNT_SHIFT)) & LFAST_SLCR_HWKCNT_MASK) 288 289 #define LFAST_SLCR_LSCNT_MASK (0xF0000U) 290 #define LFAST_SLCR_LSCNT_SHIFT (16U) 291 #define LFAST_SLCR_LSCNT_WIDTH (4U) 292 #define LFAST_SLCR_LSCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_SLCR_LSCNT_SHIFT)) & LFAST_SLCR_LSCNT_MASK) 293 294 #define LFAST_SLCR_HSCNT_MASK (0xFF000000U) 295 #define LFAST_SLCR_HSCNT_SHIFT (24U) 296 #define LFAST_SLCR_HSCNT_WIDTH (8U) 297 #define LFAST_SLCR_HSCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_SLCR_HSCNT_SHIFT)) & LFAST_SLCR_HSCNT_MASK) 298 /*! @} */ 299 300 /*! @name ICR - LFAST ICLC Control Register */ 301 /*! @{ */ 302 303 #define LFAST_ICR_ICLCPLD_MASK (0xFFU) 304 #define LFAST_ICR_ICLCPLD_SHIFT (0U) 305 #define LFAST_ICR_ICLCPLD_WIDTH (8U) 306 #define LFAST_ICR_ICLCPLD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_ICR_ICLCPLD_SHIFT)) & LFAST_ICR_ICLCPLD_MASK) 307 308 #define LFAST_ICR_SNDICLC_MASK (0x10000U) 309 #define LFAST_ICR_SNDICLC_SHIFT (16U) 310 #define LFAST_ICR_SNDICLC_WIDTH (1U) 311 #define LFAST_ICR_SNDICLC(x) (((uint32_t)(((uint32_t)(x)) << LFAST_ICR_SNDICLC_SHIFT)) & LFAST_ICR_SNDICLC_MASK) 312 313 #define LFAST_ICR_ICLCSEQ_MASK (0x20000U) 314 #define LFAST_ICR_ICLCSEQ_SHIFT (17U) 315 #define LFAST_ICR_ICLCSEQ_WIDTH (1U) 316 #define LFAST_ICR_ICLCSEQ(x) (((uint32_t)(((uint32_t)(x)) << LFAST_ICR_ICLCSEQ_SHIFT)) & LFAST_ICR_ICLCSEQ_MASK) 317 /*! @} */ 318 319 /*! @name PICR - LFAST Ping Control Register */ 320 /*! @{ */ 321 322 #define LFAST_PICR_PNGPYLD_MASK (0xFFU) 323 #define LFAST_PICR_PNGPYLD_SHIFT (0U) 324 #define LFAST_PICR_PNGPYLD_WIDTH (8U) 325 #define LFAST_PICR_PNGPYLD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PICR_PNGPYLD_SHIFT)) & LFAST_PICR_PNGPYLD_MASK) 326 327 #define LFAST_PICR_PNGAUTO_MASK (0x8000U) 328 #define LFAST_PICR_PNGAUTO_SHIFT (15U) 329 #define LFAST_PICR_PNGAUTO_WIDTH (1U) 330 #define LFAST_PICR_PNGAUTO(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PICR_PNGAUTO_SHIFT)) & LFAST_PICR_PNGAUTO_MASK) 331 332 #define LFAST_PICR_PNGREQ_MASK (0x10000U) 333 #define LFAST_PICR_PNGREQ_SHIFT (16U) 334 #define LFAST_PICR_PNGREQ_WIDTH (1U) 335 #define LFAST_PICR_PNGREQ(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PICR_PNGREQ_SHIFT)) & LFAST_PICR_PNGREQ_MASK) 336 /*! @} */ 337 338 /*! @name RFCR - LFAST Rx FIFO CTS Control Register */ 339 /*! @{ */ 340 341 #define LFAST_RFCR_RCTSMN_MASK (0x3FU) 342 #define LFAST_RFCR_RCTSMN_SHIFT (0U) 343 #define LFAST_RFCR_RCTSMN_WIDTH (6U) 344 #define LFAST_RFCR_RCTSMN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RFCR_RCTSMN_SHIFT)) & LFAST_RFCR_RCTSMN_MASK) 345 346 #define LFAST_RFCR_RCTSMX_MASK (0x3F0000U) 347 #define LFAST_RFCR_RCTSMX_SHIFT (16U) 348 #define LFAST_RFCR_RCTSMX_WIDTH (6U) 349 #define LFAST_RFCR_RCTSMX(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RFCR_RCTSMX_SHIFT)) & LFAST_RFCR_RCTSMX_MASK) 350 /*! @} */ 351 352 /*! @name TIER - LFAST Tx Interrupt Enable Register */ 353 /*! @{ */ 354 355 #define LFAST_TIER_TXDTIE_MASK (0x1U) 356 #define LFAST_TIER_TXDTIE_SHIFT (0U) 357 #define LFAST_TIER_TXDTIE_WIDTH (1U) 358 #define LFAST_TIER_TXDTIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TIER_TXDTIE_SHIFT)) & LFAST_TIER_TXDTIE_MASK) 359 360 #define LFAST_TIER_TXICLCIE_MASK (0x2U) 361 #define LFAST_TIER_TXICLCIE_SHIFT (1U) 362 #define LFAST_TIER_TXICLCIE_WIDTH (1U) 363 #define LFAST_TIER_TXICLCIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TIER_TXICLCIE_SHIFT)) & LFAST_TIER_TXICLCIE_MASK) 364 365 #define LFAST_TIER_TXUNSIE_MASK (0x4U) 366 #define LFAST_TIER_TXUNSIE_SHIFT (2U) 367 #define LFAST_TIER_TXUNSIE_WIDTH (1U) 368 #define LFAST_TIER_TXUNSIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TIER_TXUNSIE_SHIFT)) & LFAST_TIER_TXUNSIE_MASK) 369 370 #define LFAST_TIER_TXPNGIE_MASK (0x10U) 371 #define LFAST_TIER_TXPNGIE_SHIFT (4U) 372 #define LFAST_TIER_TXPNGIE_WIDTH (1U) 373 #define LFAST_TIER_TXPNGIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TIER_TXPNGIE_SHIFT)) & LFAST_TIER_TXPNGIE_MASK) 374 375 #define LFAST_TIER_TXOVIE_MASK (0x10000U) 376 #define LFAST_TIER_TXOVIE_SHIFT (16U) 377 #define LFAST_TIER_TXOVIE_WIDTH (1U) 378 #define LFAST_TIER_TXOVIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TIER_TXOVIE_SHIFT)) & LFAST_TIER_TXOVIE_MASK) 379 380 #define LFAST_TIER_TXIIE_MASK (0x20000U) 381 #define LFAST_TIER_TXIIE_SHIFT (17U) 382 #define LFAST_TIER_TXIIE_WIDTH (1U) 383 #define LFAST_TIER_TXIIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TIER_TXIIE_SHIFT)) & LFAST_TIER_TXIIE_MASK) 384 /*! @} */ 385 386 /*! @name RIER - LFAST Rx Interrupt Enable Register */ 387 /*! @{ */ 388 389 #define LFAST_RIER_RXUNSIE_MASK (0x2U) 390 #define LFAST_RIER_RXUNSIE_SHIFT (1U) 391 #define LFAST_RIER_RXUNSIE_WIDTH (1U) 392 #define LFAST_RIER_RXUNSIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXUNSIE_SHIFT)) & LFAST_RIER_RXUNSIE_MASK) 393 394 #define LFAST_RIER_RXDIE_MASK (0x4U) 395 #define LFAST_RIER_RXDIE_SHIFT (2U) 396 #define LFAST_RIER_RXDIE_WIDTH (1U) 397 #define LFAST_RIER_RXDIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXDIE_SHIFT)) & LFAST_RIER_RXDIE_MASK) 398 399 #define LFAST_RIER_RXCTSIE_MASK (0x8U) 400 #define LFAST_RIER_RXCTSIE_SHIFT (3U) 401 #define LFAST_RIER_RXCTSIE_WIDTH (1U) 402 #define LFAST_RIER_RXCTSIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXCTSIE_SHIFT)) & LFAST_RIER_RXCTSIE_MASK) 403 404 #define LFAST_RIER_RXLCEIE_MASK (0x10000U) 405 #define LFAST_RIER_RXLCEIE_SHIFT (16U) 406 #define LFAST_RIER_RXLCEIE_WIDTH (1U) 407 #define LFAST_RIER_RXLCEIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXLCEIE_SHIFT)) & LFAST_RIER_RXLCEIE_MASK) 408 409 #define LFAST_RIER_RXICIE_MASK (0x20000U) 410 #define LFAST_RIER_RXICIE_SHIFT (17U) 411 #define LFAST_RIER_RXICIE_WIDTH (1U) 412 #define LFAST_RIER_RXICIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXICIE_SHIFT)) & LFAST_RIER_RXICIE_MASK) 413 414 #define LFAST_RIER_RXSZIE_MASK (0x40000U) 415 #define LFAST_RIER_RXSZIE_SHIFT (18U) 416 #define LFAST_RIER_RXSZIE_WIDTH (1U) 417 #define LFAST_RIER_RXSZIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXSZIE_SHIFT)) & LFAST_RIER_RXSZIE_MASK) 418 419 #define LFAST_RIER_RXOFIE_MASK (0x80000U) 420 #define LFAST_RIER_RXOFIE_SHIFT (19U) 421 #define LFAST_RIER_RXOFIE_WIDTH (1U) 422 #define LFAST_RIER_RXOFIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXOFIE_SHIFT)) & LFAST_RIER_RXOFIE_MASK) 423 424 #define LFAST_RIER_RXUFIE_MASK (0x100000U) 425 #define LFAST_RIER_RXUFIE_SHIFT (20U) 426 #define LFAST_RIER_RXUFIE_WIDTH (1U) 427 #define LFAST_RIER_RXUFIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXUFIE_SHIFT)) & LFAST_RIER_RXUFIE_MASK) 428 429 #define LFAST_RIER_RXMXIE_MASK (0x200000U) 430 #define LFAST_RIER_RXMXIE_SHIFT (21U) 431 #define LFAST_RIER_RXMXIE_WIDTH (1U) 432 #define LFAST_RIER_RXMXIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXMXIE_SHIFT)) & LFAST_RIER_RXMXIE_MASK) 433 434 #define LFAST_RIER_RXMNIE_MASK (0x400000U) 435 #define LFAST_RIER_RXMNIE_SHIFT (22U) 436 #define LFAST_RIER_RXMNIE_WIDTH (1U) 437 #define LFAST_RIER_RXMNIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXMNIE_SHIFT)) & LFAST_RIER_RXMNIE_MASK) 438 439 #define LFAST_RIER_RXUOIE_MASK (0x800000U) 440 #define LFAST_RIER_RXUOIE_SHIFT (23U) 441 #define LFAST_RIER_RXUOIE_WIDTH (1U) 442 #define LFAST_RIER_RXUOIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIER_RXUOIE_SHIFT)) & LFAST_RIER_RXUOIE_MASK) 443 /*! @} */ 444 445 /*! @name RIIER - LFAST Rx ICLC Interrupt Enable Register */ 446 /*! @{ */ 447 448 #define LFAST_RIIER_ICPONIE_MASK (0x1U) 449 #define LFAST_RIIER_ICPONIE_SHIFT (0U) 450 #define LFAST_RIIER_ICPONIE_WIDTH (1U) 451 #define LFAST_RIIER_ICPONIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICPONIE_SHIFT)) & LFAST_RIIER_ICPONIE_MASK) 452 453 #define LFAST_RIIER_ICPOFIE_MASK (0x2U) 454 #define LFAST_RIIER_ICPOFIE_SHIFT (1U) 455 #define LFAST_RIIER_ICPOFIE_WIDTH (1U) 456 #define LFAST_RIIER_ICPOFIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICPOFIE_SHIFT)) & LFAST_RIIER_ICPOFIE_MASK) 457 458 #define LFAST_RIIER_ICTSIE_MASK (0x4U) 459 #define LFAST_RIIER_ICTSIE_SHIFT (2U) 460 #define LFAST_RIIER_ICTSIE_WIDTH (1U) 461 #define LFAST_RIIER_ICTSIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICTSIE_SHIFT)) & LFAST_RIIER_ICTSIE_MASK) 462 463 #define LFAST_RIIER_ICTFIE_MASK (0x8U) 464 #define LFAST_RIIER_ICTFIE_SHIFT (3U) 465 #define LFAST_RIIER_ICTFIE_WIDTH (1U) 466 #define LFAST_RIIER_ICTFIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICTFIE_SHIFT)) & LFAST_RIIER_ICTFIE_MASK) 467 468 #define LFAST_RIIER_ICRSIE_MASK (0x10U) 469 #define LFAST_RIIER_ICRSIE_SHIFT (4U) 470 #define LFAST_RIIER_ICRSIE_WIDTH (1U) 471 #define LFAST_RIIER_ICRSIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICRSIE_SHIFT)) & LFAST_RIIER_ICRSIE_MASK) 472 473 #define LFAST_RIIER_ICRFIE_MASK (0x20U) 474 #define LFAST_RIIER_ICRFIE_SHIFT (5U) 475 #define LFAST_RIIER_ICRFIE_WIDTH (1U) 476 #define LFAST_RIIER_ICRFIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICRFIE_SHIFT)) & LFAST_RIIER_ICRFIE_MASK) 477 478 #define LFAST_RIIER_ICTEIE_MASK (0x40U) 479 #define LFAST_RIIER_ICTEIE_SHIFT (6U) 480 #define LFAST_RIIER_ICTEIE_WIDTH (1U) 481 #define LFAST_RIIER_ICTEIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICTEIE_SHIFT)) & LFAST_RIIER_ICTEIE_MASK) 482 483 #define LFAST_RIIER_ICTDIE_MASK (0x80U) 484 #define LFAST_RIIER_ICTDIE_SHIFT (7U) 485 #define LFAST_RIIER_ICTDIE_WIDTH (1U) 486 #define LFAST_RIIER_ICTDIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICTDIE_SHIFT)) & LFAST_RIIER_ICTDIE_MASK) 487 488 #define LFAST_RIIER_ICCTIE_MASK (0x100U) 489 #define LFAST_RIIER_ICCTIE_SHIFT (8U) 490 #define LFAST_RIIER_ICCTIE_WIDTH (1U) 491 #define LFAST_RIIER_ICCTIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICCTIE_SHIFT)) & LFAST_RIIER_ICCTIE_MASK) 492 493 #define LFAST_RIIER_ICLPIE_MASK (0x200U) 494 #define LFAST_RIIER_ICLPIE_SHIFT (9U) 495 #define LFAST_RIIER_ICLPIE_WIDTH (1U) 496 #define LFAST_RIIER_ICLPIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICLPIE_SHIFT)) & LFAST_RIIER_ICLPIE_MASK) 497 498 #define LFAST_RIIER_ICTOIE_MASK (0x400U) 499 #define LFAST_RIIER_ICTOIE_SHIFT (10U) 500 #define LFAST_RIIER_ICTOIE_WIDTH (1U) 501 #define LFAST_RIIER_ICTOIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICTOIE_SHIFT)) & LFAST_RIIER_ICTOIE_MASK) 502 503 #define LFAST_RIIER_ICPRIE_MASK (0x800U) 504 #define LFAST_RIIER_ICPRIE_SHIFT (11U) 505 #define LFAST_RIIER_ICPRIE_WIDTH (1U) 506 #define LFAST_RIIER_ICPRIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICPRIE_SHIFT)) & LFAST_RIIER_ICPRIE_MASK) 507 508 #define LFAST_RIIER_ICPSIE_MASK (0x1000U) 509 #define LFAST_RIIER_ICPSIE_SHIFT (12U) 510 #define LFAST_RIIER_ICPSIE_WIDTH (1U) 511 #define LFAST_RIIER_ICPSIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICPSIE_SHIFT)) & LFAST_RIIER_ICPSIE_MASK) 512 513 #define LFAST_RIIER_ICPFIE_MASK (0x2000U) 514 #define LFAST_RIIER_ICPFIE_SHIFT (13U) 515 #define LFAST_RIIER_ICPFIE_WIDTH (1U) 516 #define LFAST_RIIER_ICPFIE(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIIER_ICPFIE_SHIFT)) & LFAST_RIIER_ICPFIE_MASK) 517 /*! @} */ 518 519 /*! @name PLLCR - LFAST PLL Control Register */ 520 /*! @{ */ 521 522 #define LFAST_PLLCR_PREDIV_MASK (0x3U) 523 #define LFAST_PLLCR_PREDIV_SHIFT (0U) 524 #define LFAST_PLLCR_PREDIV_WIDTH (2U) 525 #define LFAST_PLLCR_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLCR_PREDIV_SHIFT)) & LFAST_PLLCR_PREDIV_MASK) 526 527 #define LFAST_PLLCR_FBDIV_MASK (0xFCU) 528 #define LFAST_PLLCR_FBDIV_SHIFT (2U) 529 #define LFAST_PLLCR_FBDIV_WIDTH (6U) 530 #define LFAST_PLLCR_FBDIV(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLCR_FBDIV_SHIFT)) & LFAST_PLLCR_FBDIV_MASK) 531 532 #define LFAST_PLLCR_FDIVEN_MASK (0x100U) 533 #define LFAST_PLLCR_FDIVEN_SHIFT (8U) 534 #define LFAST_PLLCR_FDIVEN_WIDTH (1U) 535 #define LFAST_PLLCR_FDIVEN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLCR_FDIVEN_SHIFT)) & LFAST_PLLCR_FDIVEN_MASK) 536 537 #define LFAST_PLLCR_PLCKCW_MASK (0x600U) 538 #define LFAST_PLLCR_PLCKCW_SHIFT (9U) 539 #define LFAST_PLLCR_PLCKCW_WIDTH (2U) 540 #define LFAST_PLLCR_PLCKCW(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLCR_PLCKCW_SHIFT)) & LFAST_PLLCR_PLCKCW_MASK) 541 542 #define LFAST_PLLCR_LPCFG_MASK (0x6000U) 543 #define LFAST_PLLCR_LPCFG_SHIFT (13U) 544 #define LFAST_PLLCR_LPCFG_WIDTH (2U) 545 #define LFAST_PLLCR_LPCFG(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLCR_LPCFG_SHIFT)) & LFAST_PLLCR_LPCFG_MASK) 546 547 #define LFAST_PLLCR_REFINV_MASK (0x8000U) 548 #define LFAST_PLLCR_REFINV_SHIFT (15U) 549 #define LFAST_PLLCR_REFINV_WIDTH (1U) 550 #define LFAST_PLLCR_REFINV(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLCR_REFINV_SHIFT)) & LFAST_PLLCR_REFINV_MASK) 551 552 #define LFAST_PLLCR_SWPON_MASK (0x10000U) 553 #define LFAST_PLLCR_SWPON_SHIFT (16U) 554 #define LFAST_PLLCR_SWPON_WIDTH (1U) 555 #define LFAST_PLLCR_SWPON(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLCR_SWPON_SHIFT)) & LFAST_PLLCR_SWPON_MASK) 556 557 #define LFAST_PLLCR_SWPOFF_MASK (0x20000U) 558 #define LFAST_PLLCR_SWPOFF_SHIFT (17U) 559 #define LFAST_PLLCR_SWPOFF_WIDTH (1U) 560 #define LFAST_PLLCR_SWPOFF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLCR_SWPOFF_SHIFT)) & LFAST_PLLCR_SWPOFF_MASK) 561 /*! @} */ 562 563 /*! @name UNSTCR - LFAST Unsolicited Tx Control Register */ 564 /*! @{ */ 565 566 #define LFAST_UNSTCR_UNSHDR_MASK (0x7FU) 567 #define LFAST_UNSTCR_UNSHDR_SHIFT (0U) 568 #define LFAST_UNSTCR_UNSHDR_WIDTH (7U) 569 #define LFAST_UNSTCR_UNSHDR(x) (((uint32_t)(((uint32_t)(x)) << LFAST_UNSTCR_UNSHDR_SHIFT)) & LFAST_UNSTCR_UNSHDR_MASK) 570 571 #define LFAST_UNSTCR_USNDRQ_MASK (0x10000U) 572 #define LFAST_UNSTCR_USNDRQ_SHIFT (16U) 573 #define LFAST_UNSTCR_USNDRQ_WIDTH (1U) 574 #define LFAST_UNSTCR_USNDRQ(x) (((uint32_t)(((uint32_t)(x)) << LFAST_UNSTCR_USNDRQ_SHIFT)) & LFAST_UNSTCR_USNDRQ_MASK) 575 /*! @} */ 576 577 /*! @name UNSTDR - LFAST Unsolicited Tx Data Registers */ 578 /*! @{ */ 579 580 #define LFAST_UNSTDR_UNTXD_MASK (0xFFFFFFFFU) 581 #define LFAST_UNSTDR_UNTXD_SHIFT (0U) 582 #define LFAST_UNSTDR_UNTXD_WIDTH (32U) 583 #define LFAST_UNSTDR_UNTXD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_UNSTDR_UNTXD_SHIFT)) & LFAST_UNSTDR_UNTXD_MASK) 584 /*! @} */ 585 586 /*! @name GSR - LFAST Global Status Register */ 587 /*! @{ */ 588 589 #define LFAST_GSR_LPCSDV_MASK (0x1U) 590 #define LFAST_GSR_LPCSDV_SHIFT (0U) 591 #define LFAST_GSR_LPCSDV_WIDTH (1U) 592 #define LFAST_GSR_LPCSDV(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_LPCSDV_SHIFT)) & LFAST_GSR_LPCSDV_MASK) 593 594 #define LFAST_GSR_LPCHDV_MASK (0x2U) 595 #define LFAST_GSR_LPCHDV_SHIFT (1U) 596 #define LFAST_GSR_LPCHDV_WIDTH (1U) 597 #define LFAST_GSR_LPCHDV(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_LPCHDV_SHIFT)) & LFAST_GSR_LPCHDV_MASK) 598 599 #define LFAST_GSR_LPCPDV_MASK (0x4U) 600 #define LFAST_GSR_LPCPDV_SHIFT (2U) 601 #define LFAST_GSR_LPCPDV_WIDTH (1U) 602 #define LFAST_GSR_LPCPDV(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_LPCPDV_SHIFT)) & LFAST_GSR_LPCPDV_MASK) 603 604 #define LFAST_GSR_LPFPDV_MASK (0x8U) 605 #define LFAST_GSR_LPFPDV_SHIFT (3U) 606 #define LFAST_GSR_LPFPDV_WIDTH (1U) 607 #define LFAST_GSR_LPFPDV(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_LPFPDV_SHIFT)) & LFAST_GSR_LPFPDV_MASK) 608 609 #define LFAST_GSR_LPTXDN_MASK (0x10U) 610 #define LFAST_GSR_LPTXDN_SHIFT (4U) 611 #define LFAST_GSR_LPTXDN_WIDTH (1U) 612 #define LFAST_GSR_LPTXDN(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_LPTXDN_SHIFT)) & LFAST_GSR_LPTXDN_MASK) 613 614 #define LFAST_GSR_DRSM_MASK (0x10000U) 615 #define LFAST_GSR_DRSM_SHIFT (16U) 616 #define LFAST_GSR_DRSM_WIDTH (1U) 617 #define LFAST_GSR_DRSM(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_DRSM_SHIFT)) & LFAST_GSR_DRSM_MASK) 618 619 #define LFAST_GSR_LDSM_MASK (0x20000U) 620 #define LFAST_GSR_LDSM_SHIFT (17U) 621 #define LFAST_GSR_LDSM_WIDTH (1U) 622 #define LFAST_GSR_LDSM(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_LDSM_SHIFT)) & LFAST_GSR_LDSM_MASK) 623 624 #define LFAST_GSR_LRMD_MASK (0x40000U) 625 #define LFAST_GSR_LRMD_SHIFT (18U) 626 #define LFAST_GSR_LRMD_WIDTH (1U) 627 #define LFAST_GSR_LRMD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_LRMD_SHIFT)) & LFAST_GSR_LRMD_MASK) 628 629 #define LFAST_GSR_DUALMD_MASK (0x80000000U) 630 #define LFAST_GSR_DUALMD_SHIFT (31U) 631 #define LFAST_GSR_DUALMD_WIDTH (1U) 632 #define LFAST_GSR_DUALMD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GSR_DUALMD_SHIFT)) & LFAST_GSR_DUALMD_MASK) 633 /*! @} */ 634 635 /*! @name PISR - LFAST Ping Status Register */ 636 /*! @{ */ 637 638 #define LFAST_PISR_RXPNGD_MASK (0xFFU) 639 #define LFAST_PISR_RXPNGD_SHIFT (0U) 640 #define LFAST_PISR_RXPNGD_WIDTH (8U) 641 #define LFAST_PISR_RXPNGD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PISR_RXPNGD_SHIFT)) & LFAST_PISR_RXPNGD_MASK) 642 /*! @} */ 643 644 /*! @name DFSR - LFAST Data Frame Status Register */ 645 /*! @{ */ 646 647 #define LFAST_DFSR_TXFCNT_MASK (0x7U) 648 #define LFAST_DFSR_TXFCNT_SHIFT (0U) 649 #define LFAST_DFSR_TXFCNT_WIDTH (3U) 650 #define LFAST_DFSR_TXFCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_DFSR_TXFCNT_SHIFT)) & LFAST_DFSR_TXFCNT_MASK) 651 652 #define LFAST_DFSR_TXDCNT_MASK (0x3F00U) 653 #define LFAST_DFSR_TXDCNT_SHIFT (8U) 654 #define LFAST_DFSR_TXDCNT_WIDTH (6U) 655 #define LFAST_DFSR_TXDCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_DFSR_TXDCNT_SHIFT)) & LFAST_DFSR_TXDCNT_MASK) 656 657 #define LFAST_DFSR_RXFCNT_MASK (0x70000U) 658 #define LFAST_DFSR_RXFCNT_SHIFT (16U) 659 #define LFAST_DFSR_RXFCNT_WIDTH (3U) 660 #define LFAST_DFSR_RXFCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_DFSR_RXFCNT_SHIFT)) & LFAST_DFSR_RXFCNT_MASK) 661 662 #define LFAST_DFSR_RXDCNT_MASK (0x3F000000U) 663 #define LFAST_DFSR_RXDCNT_SHIFT (24U) 664 #define LFAST_DFSR_RXDCNT_WIDTH (6U) 665 #define LFAST_DFSR_RXDCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_DFSR_RXDCNT_SHIFT)) & LFAST_DFSR_RXDCNT_MASK) 666 /*! @} */ 667 668 /*! @name TISR - LFAST Tx Interrupt Status Register */ 669 /*! @{ */ 670 671 #define LFAST_TISR_TXDTF_MASK (0x1U) 672 #define LFAST_TISR_TXDTF_SHIFT (0U) 673 #define LFAST_TISR_TXDTF_WIDTH (1U) 674 #define LFAST_TISR_TXDTF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TISR_TXDTF_SHIFT)) & LFAST_TISR_TXDTF_MASK) 675 676 #define LFAST_TISR_TXICLCF_MASK (0x2U) 677 #define LFAST_TISR_TXICLCF_SHIFT (1U) 678 #define LFAST_TISR_TXICLCF_WIDTH (1U) 679 #define LFAST_TISR_TXICLCF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TISR_TXICLCF_SHIFT)) & LFAST_TISR_TXICLCF_MASK) 680 681 #define LFAST_TISR_TXUNSF_MASK (0x4U) 682 #define LFAST_TISR_TXUNSF_SHIFT (2U) 683 #define LFAST_TISR_TXUNSF_WIDTH (1U) 684 #define LFAST_TISR_TXUNSF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TISR_TXUNSF_SHIFT)) & LFAST_TISR_TXUNSF_MASK) 685 686 #define LFAST_TISR_TXPNGF_MASK (0x10U) 687 #define LFAST_TISR_TXPNGF_SHIFT (4U) 688 #define LFAST_TISR_TXPNGF_WIDTH (1U) 689 #define LFAST_TISR_TXPNGF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TISR_TXPNGF_SHIFT)) & LFAST_TISR_TXPNGF_MASK) 690 691 #define LFAST_TISR_TXOVF_MASK (0x10000U) 692 #define LFAST_TISR_TXOVF_SHIFT (16U) 693 #define LFAST_TISR_TXOVF_WIDTH (1U) 694 #define LFAST_TISR_TXOVF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TISR_TXOVF_SHIFT)) & LFAST_TISR_TXOVF_MASK) 695 696 #define LFAST_TISR_TXIEF_MASK (0x20000U) 697 #define LFAST_TISR_TXIEF_SHIFT (17U) 698 #define LFAST_TISR_TXIEF_WIDTH (1U) 699 #define LFAST_TISR_TXIEF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_TISR_TXIEF_SHIFT)) & LFAST_TISR_TXIEF_MASK) 700 /*! @} */ 701 702 /*! @name RISR - LFAST Rx Interrupt Status Register */ 703 /*! @{ */ 704 705 #define LFAST_RISR_RXUNSF_MASK (0x2U) 706 #define LFAST_RISR_RXUNSF_SHIFT (1U) 707 #define LFAST_RISR_RXUNSF_WIDTH (1U) 708 #define LFAST_RISR_RXUNSF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXUNSF_SHIFT)) & LFAST_RISR_RXUNSF_MASK) 709 710 #define LFAST_RISR_RXDF_MASK (0x4U) 711 #define LFAST_RISR_RXDF_SHIFT (2U) 712 #define LFAST_RISR_RXDF_WIDTH (1U) 713 #define LFAST_RISR_RXDF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXDF_SHIFT)) & LFAST_RISR_RXDF_MASK) 714 715 #define LFAST_RISR_RXCTSF_MASK (0x8U) 716 #define LFAST_RISR_RXCTSF_SHIFT (3U) 717 #define LFAST_RISR_RXCTSF_WIDTH (1U) 718 #define LFAST_RISR_RXCTSF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXCTSF_SHIFT)) & LFAST_RISR_RXCTSF_MASK) 719 720 #define LFAST_RISR_RXLCEF_MASK (0x10000U) 721 #define LFAST_RISR_RXLCEF_SHIFT (16U) 722 #define LFAST_RISR_RXLCEF_WIDTH (1U) 723 #define LFAST_RISR_RXLCEF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXLCEF_SHIFT)) & LFAST_RISR_RXLCEF_MASK) 724 725 #define LFAST_RISR_RXICF_MASK (0x20000U) 726 #define LFAST_RISR_RXICF_SHIFT (17U) 727 #define LFAST_RISR_RXICF_WIDTH (1U) 728 #define LFAST_RISR_RXICF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXICF_SHIFT)) & LFAST_RISR_RXICF_MASK) 729 730 #define LFAST_RISR_RXSZF_MASK (0x40000U) 731 #define LFAST_RISR_RXSZF_SHIFT (18U) 732 #define LFAST_RISR_RXSZF_WIDTH (1U) 733 #define LFAST_RISR_RXSZF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXSZF_SHIFT)) & LFAST_RISR_RXSZF_MASK) 734 735 #define LFAST_RISR_RXOFF_MASK (0x80000U) 736 #define LFAST_RISR_RXOFF_SHIFT (19U) 737 #define LFAST_RISR_RXOFF_WIDTH (1U) 738 #define LFAST_RISR_RXOFF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXOFF_SHIFT)) & LFAST_RISR_RXOFF_MASK) 739 740 #define LFAST_RISR_RXUFF_MASK (0x100000U) 741 #define LFAST_RISR_RXUFF_SHIFT (20U) 742 #define LFAST_RISR_RXUFF_WIDTH (1U) 743 #define LFAST_RISR_RXUFF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXUFF_SHIFT)) & LFAST_RISR_RXUFF_MASK) 744 745 #define LFAST_RISR_RXMXF_MASK (0x200000U) 746 #define LFAST_RISR_RXMXF_SHIFT (21U) 747 #define LFAST_RISR_RXMXF_WIDTH (1U) 748 #define LFAST_RISR_RXMXF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXMXF_SHIFT)) & LFAST_RISR_RXMXF_MASK) 749 750 #define LFAST_RISR_RXMNF_MASK (0x400000U) 751 #define LFAST_RISR_RXMNF_SHIFT (22U) 752 #define LFAST_RISR_RXMNF_WIDTH (1U) 753 #define LFAST_RISR_RXMNF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXMNF_SHIFT)) & LFAST_RISR_RXMNF_MASK) 754 755 #define LFAST_RISR_RXUOF_MASK (0x800000U) 756 #define LFAST_RISR_RXUOF_SHIFT (23U) 757 #define LFAST_RISR_RXUOF_WIDTH (1U) 758 #define LFAST_RISR_RXUOF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RISR_RXUOF_SHIFT)) & LFAST_RISR_RXUOF_MASK) 759 /*! @} */ 760 761 /*! @name RIISR - LFAST Rx ICLC Interrupt Status Register */ 762 /*! @{ */ 763 764 #define LFAST_RIISR_ICPONF_MASK (0x1U) 765 #define LFAST_RIISR_ICPONF_SHIFT (0U) 766 #define LFAST_RIISR_ICPONF_WIDTH (1U) 767 #define LFAST_RIISR_ICPONF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICPONF_SHIFT)) & LFAST_RIISR_ICPONF_MASK) 768 769 #define LFAST_RIISR_ICPOFF_MASK (0x2U) 770 #define LFAST_RIISR_ICPOFF_SHIFT (1U) 771 #define LFAST_RIISR_ICPOFF_WIDTH (1U) 772 #define LFAST_RIISR_ICPOFF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICPOFF_SHIFT)) & LFAST_RIISR_ICPOFF_MASK) 773 774 #define LFAST_RIISR_ICTSF_MASK (0x4U) 775 #define LFAST_RIISR_ICTSF_SHIFT (2U) 776 #define LFAST_RIISR_ICTSF_WIDTH (1U) 777 #define LFAST_RIISR_ICTSF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICTSF_SHIFT)) & LFAST_RIISR_ICTSF_MASK) 778 779 #define LFAST_RIISR_ICTFF_MASK (0x8U) 780 #define LFAST_RIISR_ICTFF_SHIFT (3U) 781 #define LFAST_RIISR_ICTFF_WIDTH (1U) 782 #define LFAST_RIISR_ICTFF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICTFF_SHIFT)) & LFAST_RIISR_ICTFF_MASK) 783 784 #define LFAST_RIISR_ICRSF_MASK (0x10U) 785 #define LFAST_RIISR_ICRSF_SHIFT (4U) 786 #define LFAST_RIISR_ICRSF_WIDTH (1U) 787 #define LFAST_RIISR_ICRSF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICRSF_SHIFT)) & LFAST_RIISR_ICRSF_MASK) 788 789 #define LFAST_RIISR_ICRFF_MASK (0x20U) 790 #define LFAST_RIISR_ICRFF_SHIFT (5U) 791 #define LFAST_RIISR_ICRFF_WIDTH (1U) 792 #define LFAST_RIISR_ICRFF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICRFF_SHIFT)) & LFAST_RIISR_ICRFF_MASK) 793 794 #define LFAST_RIISR_ICTEF_MASK (0x40U) 795 #define LFAST_RIISR_ICTEF_SHIFT (6U) 796 #define LFAST_RIISR_ICTEF_WIDTH (1U) 797 #define LFAST_RIISR_ICTEF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICTEF_SHIFT)) & LFAST_RIISR_ICTEF_MASK) 798 799 #define LFAST_RIISR_ICTDF_MASK (0x80U) 800 #define LFAST_RIISR_ICTDF_SHIFT (7U) 801 #define LFAST_RIISR_ICTDF_WIDTH (1U) 802 #define LFAST_RIISR_ICTDF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICTDF_SHIFT)) & LFAST_RIISR_ICTDF_MASK) 803 804 #define LFAST_RIISR_ICCTF_MASK (0x100U) 805 #define LFAST_RIISR_ICCTF_SHIFT (8U) 806 #define LFAST_RIISR_ICCTF_WIDTH (1U) 807 #define LFAST_RIISR_ICCTF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICCTF_SHIFT)) & LFAST_RIISR_ICCTF_MASK) 808 809 #define LFAST_RIISR_ICLPF_MASK (0x200U) 810 #define LFAST_RIISR_ICLPF_SHIFT (9U) 811 #define LFAST_RIISR_ICLPF_WIDTH (1U) 812 #define LFAST_RIISR_ICLPF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICLPF_SHIFT)) & LFAST_RIISR_ICLPF_MASK) 813 814 #define LFAST_RIISR_ICTOF_MASK (0x400U) 815 #define LFAST_RIISR_ICTOF_SHIFT (10U) 816 #define LFAST_RIISR_ICTOF_WIDTH (1U) 817 #define LFAST_RIISR_ICTOF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICTOF_SHIFT)) & LFAST_RIISR_ICTOF_MASK) 818 819 #define LFAST_RIISR_ICPRF_MASK (0x800U) 820 #define LFAST_RIISR_ICPRF_SHIFT (11U) 821 #define LFAST_RIISR_ICPRF_WIDTH (1U) 822 #define LFAST_RIISR_ICPRF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICPRF_SHIFT)) & LFAST_RIISR_ICPRF_MASK) 823 824 #define LFAST_RIISR_ICPSF_MASK (0x1000U) 825 #define LFAST_RIISR_ICPSF_SHIFT (12U) 826 #define LFAST_RIISR_ICPSF_WIDTH (1U) 827 #define LFAST_RIISR_ICPSF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICPSF_SHIFT)) & LFAST_RIISR_ICPSF_MASK) 828 829 #define LFAST_RIISR_ICPFF_MASK (0x2000U) 830 #define LFAST_RIISR_ICPFF_SHIFT (13U) 831 #define LFAST_RIISR_ICPFF_WIDTH (1U) 832 #define LFAST_RIISR_ICPFF(x) (((uint32_t)(((uint32_t)(x)) << LFAST_RIISR_ICPFF_SHIFT)) & LFAST_RIISR_ICPFF_MASK) 833 /*! @} */ 834 835 /*! @name PLLLSR - LFAST PLL and LVDS Status Register */ 836 /*! @{ */ 837 838 #define LFAST_PLLLSR_LDSLPS_MASK (0x4U) 839 #define LFAST_PLLLSR_LDSLPS_SHIFT (2U) 840 #define LFAST_PLLLSR_LDSLPS_WIDTH (1U) 841 #define LFAST_PLLLSR_LDSLPS(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLLSR_LDSLPS_SHIFT)) & LFAST_PLLLSR_LDSLPS_MASK) 842 843 #define LFAST_PLLLSR_LRSLPS_MASK (0x8U) 844 #define LFAST_PLLLSR_LRSLPS_SHIFT (3U) 845 #define LFAST_PLLLSR_LRSLPS_WIDTH (1U) 846 #define LFAST_PLLLSR_LRSLPS(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLLSR_LRSLPS_SHIFT)) & LFAST_PLLLSR_LRSLPS_MASK) 847 848 #define LFAST_PLLLSR_PLDCR_MASK (0x10000U) 849 #define LFAST_PLLLSR_PLDCR_SHIFT (16U) 850 #define LFAST_PLLLSR_PLDCR_WIDTH (1U) 851 #define LFAST_PLLLSR_PLDCR(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLLSR_PLDCR_SHIFT)) & LFAST_PLLLSR_PLDCR_MASK) 852 853 #define LFAST_PLLLSR_PLLDIS_MASK (0x20000U) 854 #define LFAST_PLLLSR_PLLDIS_SHIFT (17U) 855 #define LFAST_PLLLSR_PLLDIS_WIDTH (1U) 856 #define LFAST_PLLLSR_PLLDIS(x) (((uint32_t)(((uint32_t)(x)) << LFAST_PLLLSR_PLLDIS_SHIFT)) & LFAST_PLLLSR_PLLDIS_MASK) 857 /*! @} */ 858 859 /*! @name UNSRSR - LFAST Unsolicited Rx Status Register */ 860 /*! @{ */ 861 862 #define LFAST_UNSRSR_URPCNT_MASK (0x7U) 863 #define LFAST_UNSRSR_URPCNT_SHIFT (0U) 864 #define LFAST_UNSRSR_URPCNT_WIDTH (3U) 865 #define LFAST_UNSRSR_URPCNT(x) (((uint32_t)(((uint32_t)(x)) << LFAST_UNSRSR_URPCNT_SHIFT)) & LFAST_UNSRSR_URPCNT_MASK) 866 867 #define LFAST_UNSRSR_URXDV_MASK (0x100U) 868 #define LFAST_UNSRSR_URXDV_SHIFT (8U) 869 #define LFAST_UNSRSR_URXDV_WIDTH (1U) 870 #define LFAST_UNSRSR_URXDV(x) (((uint32_t)(((uint32_t)(x)) << LFAST_UNSRSR_URXDV_SHIFT)) & LFAST_UNSRSR_URXDV_MASK) 871 /*! @} */ 872 873 /*! @name UNSRDR - LFAST Unsolicited Rx Data Register */ 874 /*! @{ */ 875 876 #define LFAST_UNSRDR_UNRXD_MASK (0xFFFFFFFFU) 877 #define LFAST_UNSRDR_UNRXD_SHIFT (0U) 878 #define LFAST_UNSRDR_UNRXD_WIDTH (32U) 879 #define LFAST_UNSRDR_UNRXD(x) (((uint32_t)(((uint32_t)(x)) << LFAST_UNSRDR_UNRXD_SHIFT)) & LFAST_UNSRDR_UNRXD_MASK) 880 /*! @} */ 881 882 /*! @name GPR - General Purpose registers */ 883 /*! @{ */ 884 885 #define LFAST_GPR_GPR_MASK (0xFFFFFFFFU) 886 #define LFAST_GPR_GPR_SHIFT (0U) 887 #define LFAST_GPR_GPR_WIDTH (32U) 888 #define LFAST_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << LFAST_GPR_GPR_SHIFT)) & LFAST_GPR_GPR_MASK) 889 /*! @} */ 890 891 /*! 892 * @} 893 */ /* end of group LFAST_Register_Masks */ 894 895 /*! 896 * @} 897 */ /* end of group LFAST_Peripheral_Access_Layer */ 898 899 #endif /* #if !defined(S32Z2_LFAST_H_) */ 900
