1 /** 2 ****************************************************************************** 3 * @file l3gd20h_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * l3gd20h_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef L3GD20H_REGS_H 23 #define L3GD20H_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup L3GD20H 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup L3GD20H_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0xD5 if SA0=1 -> 0xD7 **/ 172 #define L3GD20H_I2C_ADD_L 0xD5U 173 #define L3GD20H_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define L3GD20H_ID 0xD7U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define L3GD20H_WHO_AM_I 0x0FU 184 #define L3GD20H_CTRL1 0x20U 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t xen : 1; 189 uint8_t yen : 1; 190 uint8_t zen : 1; 191 uint8_t pd : 1; 192 uint8_t bw : 2; 193 uint8_t dr : 2; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t dr : 2; 196 uint8_t bw : 2; 197 uint8_t pd : 1; 198 uint8_t zen : 1; 199 uint8_t yen : 1; 200 uint8_t xen : 1; 201 #endif /* DRV_BYTE_ORDER */ 202 } l3gd20h_ctrl1_t; 203 204 #define L3GD20H_CTRL2 0x21U 205 typedef struct 206 { 207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 208 uint8_t hpcf : 4; 209 uint8_t hpm : 2; 210 uint8_t lvlen : 1; 211 uint8_t extren : 1; 212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 213 uint8_t extren : 1; 214 uint8_t lvlen : 1; 215 uint8_t hpm : 2; 216 uint8_t hpcf : 4; 217 #endif /* DRV_BYTE_ORDER */ 218 } l3gd20h_ctrl2_t; 219 220 #define L3GD20H_CTRL3 0x22U 221 typedef struct 222 { 223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 224 uint8_t int2_empty : 1; 225 uint8_t int2_orun : 1; 226 uint8_t int2_fth : 1; 227 uint8_t int2_drdy : 1; 228 uint8_t pp_od : 1; 229 uint8_t h_lactive : 1; 230 uint8_t int1_boot : 1; 231 uint8_t int1_ig : 1; 232 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 233 uint8_t int1_ig : 1; 234 uint8_t int1_boot : 1; 235 uint8_t h_lactive : 1; 236 uint8_t pp_od : 1; 237 uint8_t int2_drdy : 1; 238 uint8_t int2_fth : 1; 239 uint8_t int2_orun : 1; 240 uint8_t int2_empty : 1; 241 #endif /* DRV_BYTE_ORDER */ 242 } l3gd20h_ctrl3_t; 243 244 #define L3GD20H_CTRL4 0x23U 245 typedef struct 246 { 247 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 248 uint8_t sim : 1; 249 uint8_t st : 2; 250 uint8_t impen : 1; 251 uint8_t fs : 2; 252 uint8_t ble : 1; 253 uint8_t bdu : 1; 254 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 255 uint8_t bdu : 1; 256 uint8_t ble : 1; 257 uint8_t fs : 2; 258 uint8_t impen : 1; 259 uint8_t st : 2; 260 uint8_t sim : 1; 261 #endif /* DRV_BYTE_ORDER */ 262 } l3gd20h_ctrl4_t; 263 264 #define L3GD20H_CTRL5 0x24U 265 typedef struct 266 { 267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 268 uint8_t out_sel : 2; 269 uint8_t ig_sel : 2; 270 uint8_t hpen : 1; 271 uint8_t stoponfth : 1; 272 uint8_t fifo_en : 1; 273 uint8_t boot : 1; 274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 275 uint8_t boot : 1; 276 uint8_t fifo_en : 1; 277 uint8_t stoponfth : 1; 278 uint8_t hpen : 1; 279 uint8_t ig_sel : 2; 280 uint8_t out_sel : 2; 281 #endif /* DRV_BYTE_ORDER */ 282 } l3gd20h_ctrl5_t; 283 284 #define L3GD20H_REFERENCE 0x25U 285 #define L3GD20H_OUT_TEMP 0x26U 286 #define L3GD20H_STATUS 0x27U 287 typedef struct 288 { 289 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 290 uint8_t xda : 1; 291 uint8_t yda : 1; 292 uint8_t zda : 1; 293 uint8_t zyxda : 1; 294 uint8_t _xor : 1; 295 uint8_t yor : 1; 296 uint8_t zor : 1; 297 uint8_t zyxor : 1; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t zyxor : 1; 300 uint8_t zor : 1; 301 uint8_t yor : 1; 302 uint8_t _xor : 1; 303 uint8_t zyxda : 1; 304 uint8_t zda : 1; 305 uint8_t yda : 1; 306 uint8_t xda : 1; 307 #endif /* DRV_BYTE_ORDER */ 308 } l3gd20h_status_t; 309 310 #define L3GD20H_OUT_X_L 0x28U 311 #define L3GD20H_OUT_X_H 0x29U 312 #define L3GD20H_OUT_Y_L 0x2AU 313 #define L3GD20H_OUT_Y_H 0x2BU 314 #define L3GD20H_OUT_Z_L 0x2CU 315 #define L3GD20H_OUT_Z_H 0x2DU 316 #define L3GD20H_FIFO_CTRL 0x2EU 317 typedef struct 318 { 319 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 320 uint8_t fth : 5; 321 uint8_t fm : 3; 322 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 323 uint8_t fm : 3; 324 uint8_t fth : 5; 325 #endif /* DRV_BYTE_ORDER */ 326 } l3gd20h_fifo_ctrl_t; 327 328 #define L3GD20H_FIFO_SRC 0x2FU 329 typedef struct 330 { 331 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 332 uint8_t fss : 5; 333 uint8_t empty : 1; 334 uint8_t ovrn : 1; 335 uint8_t fth : 1; 336 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 337 uint8_t fth : 1; 338 uint8_t ovrn : 1; 339 uint8_t empty : 1; 340 uint8_t fss : 5; 341 #endif /* DRV_BYTE_ORDER */ 342 } l3gd20h_fifo_src_t; 343 344 #define L3GD20H_IG_CFG 0x30U 345 typedef struct 346 { 347 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 348 uint8_t xlie : 1; 349 uint8_t xhie : 1; 350 uint8_t ylie : 1; 351 uint8_t yhie : 1; 352 uint8_t zlie : 1; 353 uint8_t zhie : 1; 354 uint8_t lir : 1; 355 uint8_t and_or : 1; 356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 357 uint8_t and_or : 1; 358 uint8_t lir : 1; 359 uint8_t zhie : 1; 360 uint8_t zlie : 1; 361 uint8_t yhie : 1; 362 uint8_t ylie : 1; 363 uint8_t xhie : 1; 364 uint8_t xlie : 1; 365 #endif /* DRV_BYTE_ORDER */ 366 } l3gd20h_ig_cfg_t; 367 368 #define L3GD20H_IG_SRC 0x31U 369 typedef struct 370 { 371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 372 uint8_t xl : 1; 373 uint8_t xh : 1; 374 uint8_t yl : 1; 375 uint8_t yh : 1; 376 uint8_t zl : 1; 377 uint8_t zh : 1; 378 uint8_t ia : 1; 379 uint8_t not_used_01 : 1; 380 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 381 uint8_t not_used_01 : 1; 382 uint8_t ia : 1; 383 uint8_t zh : 1; 384 uint8_t zl : 1; 385 uint8_t yh : 1; 386 uint8_t yl : 1; 387 uint8_t xh : 1; 388 uint8_t xl : 1; 389 #endif /* DRV_BYTE_ORDER */ 390 } l3gd20h_ig_src_t; 391 392 #define L3GD20H_IG_THS_XH 0x32U 393 typedef struct 394 { 395 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 396 uint8_t thsx : 7; 397 uint8_t dcrm : 1; 398 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 399 uint8_t dcrm : 1; 400 uint8_t thsx : 7; 401 #endif /* DRV_BYTE_ORDER */ 402 } l3gd20h_ig_ths_xh_t; 403 404 #define L3GD20H_IG_THS_XL 0x33U 405 typedef struct 406 { 407 uint8_t thsx : 8; 408 } l3gd20h_ig_ths_xl_t; 409 410 #define L3GD20H_IG_THS_YH 0x34U 411 typedef struct 412 { 413 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 414 uint8_t thsy : 7; 415 uint8_t not_used_01 : 1; 416 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 417 uint8_t not_used_01 : 1; 418 uint8_t thsy : 7; 419 #endif /* DRV_BYTE_ORDER */ 420 } l3gd20h_ig_ths_yh_t; 421 422 #define L3GD20H_IG_THS_YL 0x35U 423 typedef struct 424 { 425 uint8_t thsy : 8; 426 } l3gd20h_ig_ths_yl_t; 427 428 #define L3GD20H_IG_THS_ZH 0x36U 429 typedef struct 430 { 431 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 432 uint8_t thsz : 7; 433 uint8_t not_used_01 : 1; 434 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 435 uint8_t not_used_01 : 1; 436 uint8_t thsz : 7; 437 #endif /* DRV_BYTE_ORDER */ 438 } l3gd20h_ig_ths_zh_t; 439 440 #define L3GD20H_IG_THS_ZL 0x37U 441 typedef struct 442 { 443 uint8_t thsz : 8; 444 } l3gd20h_ig_ths_zl_t; 445 446 #define L3GD20H_IG_DURATION 0x38U 447 typedef struct 448 { 449 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 450 uint8_t d : 7; 451 uint8_t wait : 1; 452 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 453 uint8_t wait : 1; 454 uint8_t d : 7; 455 #endif /* DRV_BYTE_ORDER */ 456 } l3gd20h_ig_duration_t; 457 458 #define L3GD20H_LOW_ODR 0x39U 459 typedef struct 460 { 461 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 462 uint8_t low_odr : 1; 463 uint8_t not_used_01 : 1; 464 uint8_t sw_res : 1; 465 uint8_t i2c_dis : 1; 466 uint8_t not_used_02 : 1; 467 uint8_t drdy_hl : 1; 468 uint8_t not_used_03 : 2; 469 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 470 uint8_t not_used_03 : 2; 471 uint8_t drdy_hl : 1; 472 uint8_t not_used_02 : 1; 473 uint8_t i2c_dis : 1; 474 uint8_t sw_res : 1; 475 uint8_t not_used_01 : 1; 476 uint8_t low_odr : 1; 477 #endif /* DRV_BYTE_ORDER */ 478 } l3gd20h_low_odr_t; 479 480 /** 481 * @defgroup L3GD20H_Register_Union 482 * @brief This union group all the registers having a bit-field 483 * description. 484 * This union is useful but it's not needed by the driver. 485 * 486 * REMOVING this union you are compliant with: 487 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 488 * 489 * @{ 490 * 491 */ 492 typedef union 493 { 494 l3gd20h_ctrl1_t ctrl1; 495 l3gd20h_ctrl2_t ctrl2; 496 l3gd20h_ctrl3_t ctrl3; 497 l3gd20h_ctrl4_t ctrl4; 498 l3gd20h_ctrl5_t ctrl5; 499 l3gd20h_status_t status; 500 l3gd20h_fifo_ctrl_t fifo_ctrl; 501 l3gd20h_fifo_src_t fifo_src; 502 l3gd20h_ig_cfg_t ig_cfg; 503 l3gd20h_ig_src_t ig_src; 504 l3gd20h_ig_ths_xh_t ig_ths_xh; 505 l3gd20h_ig_ths_xl_t ig_ths_xl; 506 l3gd20h_ig_ths_yh_t ig_ths_yh; 507 l3gd20h_ig_ths_yl_t ig_ths_yl; 508 l3gd20h_ig_ths_zh_t ig_ths_zh; 509 l3gd20h_ig_ths_zl_t ig_ths_zl; 510 l3gd20h_ig_duration_t ig_duration; 511 l3gd20h_low_odr_t low_odr; 512 bitwise_t bitwise; 513 uint8_t byte; 514 } l3gd20h_reg_t; 515 516 /** 517 * @} 518 * 519 */ 520 521 #ifndef __weak 522 #define __weak __attribute__((weak)) 523 #endif /* __weak */ 524 525 /* 526 * These are the basic platform dependent I/O routines to read 527 * and write device registers connected on a standard bus. 528 * The driver keeps offering a default implementation based on function 529 * pointers to read/write routines for backward compatibility. 530 * The __weak directive allows the final application to overwrite 531 * them with a custom implementation. 532 */ 533 534 int32_t l3gd20h_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 535 uint8_t *data, 536 uint16_t len); 537 int32_t l3gd20h_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 538 uint8_t *data, 539 uint16_t len); 540 541 float_t l3gd20h_from_fs245_to_mdps(int16_t lsb); 542 float_t l3gd20h_from_fs500_to_mdps(int16_t lsb); 543 float_t l3gd20h_from_fs2000_to_mdps(int16_t lsb); 544 545 float_t l3gd20h_from_lsb_to_celsius(int16_t lsb); 546 547 typedef struct 548 { 549 uint8_t xen : 1; 550 uint8_t yen : 1; 551 uint8_t zen : 1; 552 } l3gd20h_gy_axis_t; 553 int32_t l3gd20h_gy_axis_set(const stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val); 554 int32_t l3gd20h_gy_axis_get(const stmdev_ctx_t *ctx, 555 l3gd20h_gy_axis_t *val); 556 557 typedef enum 558 { 559 L3GD20H_POWER_DOWN = 0x00, 560 L3GD20H_12Hz5 = 0x90, 561 L3GD20H_25Hz = 0x91, 562 L3GD20H_50Hz = 0x92, 563 L3GD20H_100Hz = 0x80, 564 L3GD20H_200Hz = 0x81, 565 L3GD20H_400Hz = 0x82, 566 L3GD20H_800Hz = 0x83, 567 } l3gd20h_gy_data_rate_t; 568 int32_t l3gd20h_gy_data_rate_set(const stmdev_ctx_t *ctx, 569 l3gd20h_gy_data_rate_t val); 570 int32_t l3gd20h_gy_data_rate_get(const stmdev_ctx_t *ctx, 571 l3gd20h_gy_data_rate_t *val); 572 573 574 typedef enum 575 { 576 L3GD20H_245dps = 0x00, 577 L3GD20H_500dps = 0x01, 578 L3GD20H_2000dps = 0x02, 579 } l3gd20h_gy_fs_t; 580 int32_t l3gd20h_gy_full_scale_set(const stmdev_ctx_t *ctx, 581 l3gd20h_gy_fs_t val); 582 int32_t l3gd20h_gy_full_scale_get(const stmdev_ctx_t *ctx, 583 l3gd20h_gy_fs_t *val); 584 585 int32_t l3gd20h_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 586 int32_t l3gd20h_block_data_update_get(const stmdev_ctx_t *ctx, 587 uint8_t *val); 588 589 int32_t l3gd20h_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 590 uint8_t *val); 591 592 int32_t l3gd20h_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); 593 594 int32_t l3gd20h_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 595 596 int32_t l3gd20h_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 597 598 typedef enum 599 { 600 L3GD20H_LSB_LOW_ADDRESS = 0, 601 L3GD20H_MSB_LOW_ADDRESS = 1, 602 } l3gd20h_ble_t; 603 int32_t l3gd20h_dev_data_format_set(const stmdev_ctx_t *ctx, 604 l3gd20h_ble_t val); 605 int32_t l3gd20h_dev_data_format_get(const stmdev_ctx_t *ctx, 606 l3gd20h_ble_t *val); 607 608 int32_t l3gd20h_dev_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 609 int32_t l3gd20h_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 610 611 typedef struct 612 { 613 uint8_t xda : 1; 614 uint8_t yda : 1; 615 uint8_t zda : 1; 616 uint8_t zyxda : 1; 617 uint8_t _xor : 1; 618 uint8_t yor : 1; 619 uint8_t zor : 1; 620 uint8_t zyxor : 1; 621 } l3gd20h_status_reg_t; 622 int32_t l3gd20h_dev_status_get(const stmdev_ctx_t *ctx, 623 l3gd20h_status_reg_t *val); 624 625 int32_t l3gd20h_dev_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 626 int32_t l3gd20h_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 627 628 typedef enum 629 { 630 L3GD20H_16Hz6_USE_ODR_50Hz = 0xA0, 631 L3GD20H_12Hz5_USE_ODR_100Hz = 0x00, 632 L3GD20H_25Hz_USE_ODR_100Hz = 0x01, 633 L3GD20H_12Hz5_USE_ODR_200Hz = 0x10, 634 L3GD20H_70Hz_USE_ODR_200Hz = 0x13, 635 L3GD20H_20Hz_USE_ODR_400Hz = 0x20, 636 L3GD20H_25Hz_USE_ODR_400Hz = 0x21, 637 L3GD20H_50Hz_USE_ODR_400Hz = 0x22, 638 L3GD20H_110Hz_USE_ODR_400Hz = 0x23, 639 L3GD20H_30Hz_USE_ODR_800Hz = 0x30, 640 L3GD20H_35Hz_USE_ODR_800Hz = 0x31, 641 L3GD20H_100Hz_USE_ODR_800Hz = 0x33, 642 } l3gd20h_lpbw_t; 643 int32_t l3gd20h_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, 644 l3gd20h_lpbw_t val); 645 int32_t l3gd20h_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, 646 l3gd20h_lpbw_t *val); 647 648 typedef enum 649 { 650 L3GD20H_NORMAL_MODE_LIGHT = 0x00, 651 L3GD20H_NORMAL_MODE_NORMAL = 0x01, 652 L3GD20H_NORMAL_MODE_STRONG = 0x02, 653 L3GD20H_NORMAL_MODE_EXTREME = 0x03, 654 L3GD20H_USE_REFERENCE_LIGHT = 0x10, 655 L3GD20H_USE_REFERENCE_NORMAL = 0x11, 656 L3GD20H_USE_REFERENCE_STRONG = 0x12, 657 L3GD20H_USE_REFERENCE_EXTREME = 0x13, 658 L3GD20H_AUTORESET_LIGHT = 0x30, 659 L3GD20H_AUTORESET_NORMAL = 0x31, 660 L3GD20H_AUTORESET_STRONG = 0x32, 661 L3GD20H_AUTORESET_EXTREME = 0x33, 662 } l3gd20h_gy_hp_bw_t; 663 int32_t l3gd20h_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, 664 l3gd20h_gy_hp_bw_t val); 665 int32_t l3gd20h_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, 666 l3gd20h_gy_hp_bw_t *val); 667 668 typedef enum 669 { 670 L3GD20H_LPF1_OUT = 0x00, 671 L3GD20H_LPF1_HPF_OUT = 0x11, 672 L3GD20H_LPF1_LPF2_OUT = 0x02, 673 L3GD20H_LPF1_HPF_LPF2_OUT = 0x12, 674 } l3gd20h_gy_out_path_t; 675 int32_t l3gd20h_gy_filter_out_path_set(const stmdev_ctx_t *ctx, 676 l3gd20h_gy_out_path_t val); 677 int32_t l3gd20h_gy_filter_out_path_get(const stmdev_ctx_t *ctx, 678 l3gd20h_gy_out_path_t *val); 679 typedef enum 680 { 681 L3GD20H_LPF1_INT = 0x00, 682 L3GD20H_LPF1_HPF_INT = 0x11, 683 L3GD20H_LPF1_LPF2_INT = 0x02, 684 L3GD20H_LPF1_HPF_LPF2_INT = 0x12, 685 } l3gd20h_gy_int_path_t; 686 int32_t l3gd20h_gy_filter_int_path_set(const stmdev_ctx_t *ctx, 687 l3gd20h_gy_int_path_t val); 688 int32_t l3gd20h_gy_filter_int_path_get(const stmdev_ctx_t *ctx, 689 l3gd20h_gy_int_path_t *val); 690 691 int32_t l3gd20h_gy_filter_reference_set(const stmdev_ctx_t *ctx, 692 uint8_t *buff); 693 int32_t l3gd20h_gy_filter_reference_get(const stmdev_ctx_t *ctx, 694 uint8_t *buff); 695 696 typedef enum 697 { 698 L3GD20H_SPI_4_WIRE = 0, 699 L3GD20H_SPI_3_WIRE = 1, 700 } l3gd20h_sim_t; 701 int32_t l3gd20h_spi_mode_set(const stmdev_ctx_t *ctx, l3gd20h_sim_t val); 702 int32_t l3gd20h_spi_mode_get(const stmdev_ctx_t *ctx, l3gd20h_sim_t *val); 703 704 typedef enum 705 { 706 L3GD20H_I2C_ENABLE = 0, 707 L3GD20H_I2C_DISABLE = 1, 708 } l3gd20h_i2c_dis_t; 709 int32_t l3gd20h_i2c_interface_set(const stmdev_ctx_t *ctx, 710 l3gd20h_i2c_dis_t val); 711 int32_t l3gd20h_i2c_interface_get(const stmdev_ctx_t *ctx, 712 l3gd20h_i2c_dis_t *val); 713 714 typedef struct 715 { 716 uint8_t int2_empty : 1; 717 uint8_t int2_orun : 1; 718 uint8_t int2_fth : 1; 719 uint8_t int2_drdy : 1; 720 } l3gd20h_pin_int2_rt_t; 721 int32_t l3gd20h_pin_int2_route_set(const stmdev_ctx_t *ctx, 722 l3gd20h_pin_int2_rt_t val); 723 int32_t l3gd20h_pin_int2_route_get(const stmdev_ctx_t *ctx, 724 l3gd20h_pin_int2_rt_t *val); 725 726 typedef enum 727 { 728 L3GD20H_PUSH_PULL = 0, 729 L3GD20H_OPEN_DRAIN = 1, 730 } l3gd20h_pp_od_t; 731 int32_t l3gd20h_pin_mode_set(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t val); 732 int32_t l3gd20h_pin_mode_get(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val); 733 734 typedef enum 735 { 736 L3GD20H_ACTIVE_HIGH = 0, 737 L3GD20H_ACTIVE_LOW = 1, 738 } l3gd20h_pin_pol_t; 739 int32_t l3gd20h_pin_polarity_set(const stmdev_ctx_t *ctx, 740 l3gd20h_pin_pol_t val); 741 int32_t l3gd20h_pin_polarity_get(const stmdev_ctx_t *ctx, 742 l3gd20h_pin_pol_t *val); 743 744 typedef struct 745 { 746 uint8_t int1_boot : 1; 747 uint8_t int1_ig : 1; 748 } l3gd20h_pin_int1_rt_t; 749 int32_t l3gd20h_pin_int1_route_set(const stmdev_ctx_t *ctx, 750 l3gd20h_pin_int1_rt_t val); 751 int32_t l3gd20h_pin_int1_route_get(const stmdev_ctx_t *ctx, 752 l3gd20h_pin_int1_rt_t *val); 753 754 typedef enum 755 { 756 L3GD20H_INT_PULSED = 0, 757 L3GD20H_INT_LATCHED = 1, 758 } l3gd20h_lir_t; 759 int32_t l3gd20h_pin_notification_set(const stmdev_ctx_t *ctx, 760 l3gd20h_lir_t val); 761 int32_t l3gd20h_pin_notification_get(const stmdev_ctx_t *ctx, 762 l3gd20h_lir_t *val); 763 typedef enum 764 { 765 L3GD20H_LOGIC_OR = 0, 766 L3GD20H_LOGIC_AND = 1, 767 } l3gd20h_pin_logic_t; 768 int32_t l3gd20h_pin_logic_set(const stmdev_ctx_t *ctx, 769 l3gd20h_pin_logic_t val); 770 int32_t l3gd20h_pin_logic_get(const stmdev_ctx_t *ctx, 771 l3gd20h_pin_logic_t *val); 772 773 typedef struct 774 { 775 uint8_t xlie : 1; 776 uint8_t xhie : 1; 777 uint8_t ylie : 1; 778 uint8_t yhie : 1; 779 uint8_t zlie : 1; 780 uint8_t zhie : 1; 781 } l3gd20h_gy_trshld_en_t; 782 int32_t l3gd20h_gy_trshld_axis_set(const stmdev_ctx_t *ctx, 783 l3gd20h_gy_trshld_en_t val); 784 int32_t l3gd20h_gy_trshld_axis_get(const stmdev_ctx_t *ctx, 785 l3gd20h_gy_trshld_en_t *val); 786 787 typedef struct 788 { 789 uint8_t xl : 1; 790 uint8_t xh : 1; 791 uint8_t yl : 1; 792 uint8_t yh : 1; 793 uint8_t zl : 1; 794 uint8_t zh : 1; 795 uint8_t ia : 1; 796 } l3gd20h_gy_trshld_src_t; 797 int32_t l3gd20h_gy_trshld_src_get(const stmdev_ctx_t *ctx, 798 l3gd20h_gy_trshld_src_t *val); 799 800 int32_t l3gd20h_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val); 801 int32_t l3gd20h_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val); 802 803 typedef enum 804 { 805 L3GD20H_RESET_MODE = 0x00, 806 L3GD20H_DECREMENT_MODE = 0x01, 807 } l3gd20h_dcrm_g_t; 808 int32_t l3gd20h_gy_trshld_mode_set(const stmdev_ctx_t *ctx, 809 l3gd20h_dcrm_g_t val); 810 int32_t l3gd20h_gy_trshld_mode_get(const stmdev_ctx_t *ctx, 811 l3gd20h_dcrm_g_t *val); 812 813 int32_t l3gd20h_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val); 814 int32_t l3gd20h_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val); 815 816 int32_t l3gd20h_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val); 817 int32_t l3gd20h_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val); 818 819 int32_t l3gd20h_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx, 820 uint8_t val); 821 int32_t l3gd20h_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, 822 uint8_t *val); 823 824 int32_t l3gd20h_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 825 int32_t l3gd20h_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 826 827 typedef enum 828 { 829 L3GD20H_BYPASS_MODE = 0x00, 830 L3GD20H_FIFO_MODE = 0x11, 831 L3GD20H_STREAM_MODE = 0x12, 832 L3GD20H_STREAM_TO_FIFO_MODE = 0x13, 833 L3GD20H_BYPASS_TO_STREAM_MODE = 0x14, 834 L3GD20H_DYNAMIC_STREAM_MODE = 0x16, 835 L3GD20H_BYPASS_TO_FIFO_MODE = 0x17, 836 } l3gd20h_fifo_m_t; 837 int32_t l3gd20h_fifo_mode_set(const stmdev_ctx_t *ctx, 838 l3gd20h_fifo_m_t val); 839 int32_t l3gd20h_fifo_mode_get(const stmdev_ctx_t *ctx, 840 l3gd20h_fifo_m_t *val); 841 842 int32_t l3gd20h_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 843 int32_t l3gd20h_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 844 845 typedef struct 846 { 847 uint8_t fss : 1; 848 uint8_t empty : 1; 849 uint8_t ovrn : 1; 850 uint8_t fth : 1; 851 } l3gd20h_fifo_srs_t; 852 int32_t l3gd20h_fifo_src_get(const stmdev_ctx_t *ctx, 853 l3gd20h_fifo_srs_t *val); 854 855 int32_t l3gd20h_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 856 857 int32_t l3gd20h_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 858 859 int32_t l3gd20h_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 860 861 typedef enum 862 { 863 L3GD20H_DEN_DISABLE = 0x00, 864 L3GD20H_DEN_ON_LEVEL_TRIGGER = 0x04, 865 L3GD20H_DEN_ON_EDGE_TRIGGER = 0x02, 866 L3GD20H_DEN_IMPULSE_TRIGGER = 0x05, 867 } l3gd20h_den_md_t; 868 int32_t l3gd20h_den_mode_set(const stmdev_ctx_t *ctx, l3gd20h_den_md_t val); 869 int32_t l3gd20h_den_mode_get(const stmdev_ctx_t *ctx, 870 l3gd20h_den_md_t *val); 871 872 typedef enum 873 { 874 L3GD20H_ST_DISABLE = 0x00, 875 L3GD20H_ST_POSITIVE = 0x01, 876 L3GD20H_ST_NEGATIVE = 0x03, 877 } l3gd20h_st_t; 878 int32_t l3gd20h_gy_self_test_set(const stmdev_ctx_t *ctx, l3gd20h_st_t val); 879 int32_t l3gd20h_gy_self_test_get(const stmdev_ctx_t *ctx, 880 l3gd20h_st_t *val); 881 882 /** 883 *@} 884 * 885 */ 886 887 #ifdef __cplusplus 888 } 889 #endif 890 891 #endif /* L3GD20H_REGS_H */ 892 893 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 894
