1 /* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Header for agregating all defines for mm 10 * 11 */ 12 #ifndef ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ 13 #define ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ 14 15 #define DT_DRV_COMPAT intel_adsp_mtl_tlb 16 17 #include <zephyr/device.h> 18 #include <zephyr/kernel.h> 19 #include <zephyr/spinlock.h> 20 #include <zephyr/sys/__assert.h> 21 #include <zephyr/sys/check.h> 22 #include <zephyr/sys/mem_manage.h> 23 #include <zephyr/sys/util.h> 24 #include <zephyr/drivers/mm/system_mm.h> 25 #include <zephyr/sys/mem_blocks.h> 26 27 #include <soc.h> 28 #include <adsp_memory.h> 29 #include <adsp_memory_regions.h> 30 31 #include "mm_drv_common.h" 32 33 DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0)); 34 35 #define TLB_BASE \ 36 ((mm_reg_t)DEVICE_MMIO_TOPLEVEL_GET(tlb_regs)) 37 38 /* 39 * Number of significant bits in the page index (defines the size of 40 * the table) 41 */ 42 #define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size) 43 #define TLB_EXEC_BIT BIT(DT_INST_PROP(0, exec_bit_idx)) 44 #define TLB_WRITE_BIT BIT(DT_INST_PROP(0, write_bit_idx)) 45 46 #define TLB_ENTRY_NUM (1 << TLB_PADDR_SIZE) 47 #define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1) 48 #define TLB_ENABLE_BIT BIT(TLB_PADDR_SIZE) 49 50 /* This is used to translate from TLB entry back to physical address. */ 51 /* base address of TLB table */ 52 #define TLB_PHYS_BASE \ 53 (((L2_SRAM_BASE / CONFIG_MM_DRV_PAGE_SIZE) & ~TLB_PADDR_MASK) * CONFIG_MM_DRV_PAGE_SIZE) 54 #define HPSRAM_SEGMENTS(hpsram_ebb_quantity) \ 55 ((ROUND_DOWN((hpsram_ebb_quantity) + 31u, 32u) / 32u) - 1u) 56 57 #define L2_SRAM_PAGES_NUM (L2_SRAM_SIZE / CONFIG_MM_DRV_PAGE_SIZE) 58 #define MAX_EBB_BANKS_IN_SEGMENT 32 59 #define SRAM_BANK_SIZE (128 * 1024) 60 #define L2_SRAM_BANK_NUM (L2_SRAM_SIZE / SRAM_BANK_SIZE) 61 #define IS_BIT_SET(value, idx) ((value) & (1 << (idx))) 62 63 /** 64 * Calculate TLB entry based on physical address. 65 * 66 * @param pa Page-aligned virutal address. 67 * @return TLB entry value. 68 */ pa_to_tlb_entry(uintptr_t pa)69static inline uint16_t pa_to_tlb_entry(uintptr_t pa) 70 { 71 return (((pa) / CONFIG_MM_DRV_PAGE_SIZE) & TLB_PADDR_MASK); 72 } 73 74 /** 75 * Calculate physical address based on TLB entry. 76 * 77 * @param tlb_entry TLB entry value. 78 * @return physcial address pointer. 79 */ tlb_entry_to_pa(uint16_t tlb_entry)80static inline uintptr_t tlb_entry_to_pa(uint16_t tlb_entry) 81 { 82 return ((((tlb_entry) & TLB_PADDR_MASK) * 83 CONFIG_MM_DRV_PAGE_SIZE) + TLB_PHYS_BASE); 84 } 85 86 /** 87 * Calculate virtual memory regions allocation based on 88 * info from linker script. 89 * 90 * @param End address of staticaly allocated memory. 91 * @return Error Code. 92 */ 93 int calculate_memory_regions(uintptr_t static_alloc_end_ptr); 94 95 #endif /* ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ */ 96
