1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2017 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 * Rander Wang <rander.wang@intel.com> 8 */ 9 10 #ifdef __SOF_LIB_MEMORY_H__ 11 12 #ifndef __PLATFORM_LIB_MEMORY_H__ 13 #define __PLATFORM_LIB_MEMORY_H__ 14 15 #include <cavs/lib/memory.h> 16 #include <sof/lib/cpu.h> 17 18 19 /* physical DSP addresses */ 20 21 /* shim */ 22 #define SHIM_BASE 0x00071F00 23 #define SHIM_SIZE 0x00000100 24 25 /* Digital Mic Shim Registers */ 26 #define DMIC_SHIM_BASE 0x00071E80 27 #define DMICLCTL_OFFSET 0x04 28 #define DMICLCTL (DMIC_SHIM_BASE + DMICLCTL_OFFSET) 29 30 /* cmd IO to audio codecs */ 31 #define CMD_BASE 0x00001100 32 #define CMD_SIZE 0x00000010 33 34 /* resource allocation */ 35 #define RES_BASE 0x00001110 36 #define RES_SIZE 0x00000010 37 38 /* IPC to the host */ 39 #define IPC_HOST_BASE 0x00071E00 40 #define IPC_HOST_SIZE 0x00000020 41 42 /* intra DSP IPC */ 43 #define IPC_DSP_SIZE 0x00000080 44 #define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE) 45 46 /* SRAM window for HOST */ 47 #define HOST_WIN_SIZE 0x00000008 48 #define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE) 49 50 /* IRQ controller */ 51 #define IRQ_BASE 0x00078800 52 #define IRQ_SIZE 0x00000200 53 54 /* time stamping */ 55 #define TIME_BASE 0x00071800 56 #define TIME_SIZE 0x00000200 57 58 /* M/N dividers */ 59 #define MN_BASE 0x00078C00 60 #define MN_SIZE 0x00000200 61 62 /* low power DMA position */ 63 #define LP_GP_DMA_LINK_SIZE 0x00000010 64 #define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE) 65 66 /* high performance DMA position */ 67 #define HP_GP_DMA_LINK_SIZE 0x00000010 68 #define HP_GP_DMA_LINK_BASE(x) (0x00001D00 + x * HP_GP_DMA_LINK_SIZE) 69 70 /* link DMAC stream */ 71 #define GTW_LINK_OUT_STREAM_SIZE 0x00000020 72 #define GTW_LINK_OUT_STREAM_BASE(x) \ 73 (0x00072400 + x * GTW_LINK_OUT_STREAM_SIZE) 74 75 #define GTW_LINK_IN_STREAM_SIZE 0x00000020 76 #define GTW_LINK_IN_STREAM_BASE(x) \ 77 (0x00072600 + x * GTW_LINK_IN_STREAM_SIZE) 78 79 /* host DMAC stream */ 80 #define GTW_HOST_OUT_STREAM_SIZE 0x00000040 81 #define GTW_HOST_OUT_STREAM_BASE(x) \ 82 (0x00072800 + x * GTW_HOST_OUT_STREAM_SIZE) 83 84 #define GTW_HOST_IN_STREAM_SIZE 0x00000040 85 #define GTW_HOST_IN_STREAM_BASE(x) \ 86 (0x00072C00 + x * GTW_HOST_IN_STREAM_SIZE) 87 88 /* code loader */ 89 #define GTW_CODE_LDR_SIZE 0x00000040 90 #define GTW_CODE_LDR_BASE 0x00002BC0 91 92 /* L2 TLBs */ 93 #define L2_HP_SRAM_TLB_SIZE 0x00001000 94 #define L2_HP_SRAM_TLB_BASE 0x00003000 95 96 /* DMICs */ 97 #define DMIC_BASE 0x00010000 98 #define DMIC_SIZE 0x00008000 99 100 /* SSP */ 101 #define SSP_BASE(x) (0x00077000 + x * SSP_SIZE) 102 #define SSP_SIZE 0x0000200 103 104 /* ALH */ 105 #define ALH_BASE 0x000071000 106 #define ALH_TXDA_OFFSET 0x000000400 107 #define ALH_RXDA_OFFSET 0x000000500 108 #define ALH_STREAM_OFFSET 0x000000004 109 110 /* Timestamping */ 111 #define TIMESTAMP_BASE 0x00071800 112 113 /* low power DMACs */ 114 #define LP_GP_DMA_SIZE 0x00001000 115 #define LP_GP_DMA_BASE(x) (0x0007C000 + x * LP_GP_DMA_SIZE) 116 117 /* high performance DMACs */ 118 #define HP_GP_DMA_SIZE 0x00001000 119 #define HP_GP_DMA_BASE(x) (0x0000E000 + x * HP_GP_DMA_SIZE) 120 121 /* ROM */ 122 #define ROM_BASE 0xBEFE0000 123 #define ROM_SIZE 0x00002000 124 125 #define L2_VECTOR_SIZE 0x1000 126 127 #define UUID_ENTRY_ELF_BASE 0x1FFFA000 128 #define UUID_ENTRY_ELF_SIZE 0x6000 129 130 #define LOG_ENTRY_ELF_BASE 0x20000000 131 #define LOG_ENTRY_ELF_SIZE 0x2000000 132 133 #define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) 134 #define EXT_MANIFEST_ELF_SIZE 0x2000000 135 136 /* 137 * The HP SRAM Region on Tigerlake is organised like this :- 138 * +----------------------------------------------------------------------------+ 139 * | Offset | Region | Size | 140 * +--------------------+-------------------------+-----------------------------+ 141 * | SRAM_SW_REG_BASE | SW Registers W0 | SRAM_SW_REG_SIZE | 142 * +--------------------+-------------------------+-----------------------------+ 143 * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_OUTBOX_SIZE | 144 * +--------------------+-------------------------+-----------------------------+ 145 * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | 146 * +--------------------+-------------------------+-----------------------------+ 147 * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | 148 * +--------------------+-------------------------+-----------------------------+ 149 * | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE | 150 * +--------------------+-------------------------+-----------------------------+ 151 * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE | 152 * +--------------------+-------------------------+-----------------------------+ 153 * | SRAM_TRACE_BASE | Trace Buffer W3 | SRAM_TRACE_SIZE | 154 * +--------------------+-------------------------+-----------------------------+ 155 * | HEAP_HP_BUFFER_BASE| DMA | HEAP_HP_BUFFER_SIZE | 156 * +--------------------+-------------------------+-----------------------------+ 157 * | SOF_FW_START | text | | 158 * | | data | | 159 * | | BSS | | 160 * +--------------------+-------------------------+-----------------------------+ 161 * | | Runtime Heap | HEAP_RUNTIME_SIZE | 162 * +--------------------+-------------------------+-----------------------------+ 163 * | | Runtime shared Heap | HEAP_RUNTIME_SHARED_SIZE | 164 * | |-------------------------+-----------------------------+ 165 * | | System shared Heap | HEAP_SYSTEM_SHARED_SIZE | 166 * | |-------------------------+-----------------------------+ 167 * | | Module Buffers | HEAP_BUFFER_SIZE | 168 * +--------------------+-------------------------+-----------------------------+ 169 * | | Primary core Sys Heap | HEAP_SYSTEM_M_SIZE | 170 * +--------------------+-------------------------+-----------------------------+ 171 * | | Pri. Sys Runtime Heap | HEAP_SYS_RUNTIME_M_SIZE | 172 * +--------------------+-------------------------+-----------------------------+ 173 * | | Primary core Stack | SOF_STACK_SIZE | 174 * +--------------------+-------------------------+-----------------------------+ 175 * | | Sec. core Sys Heap | SOF_CORE_S_T_SIZE | 176 * | | Sec. Sys Runtime Heap | | 177 * | | Secondary core Stack | | 178 * +--------------------+-------------------------+-----------------------------+ 179 */ 180 181 /* HP SRAM */ 182 #define HP_SRAM_BASE 0xBE000000 183 184 /* HP SRAM windows */ 185 /* window 0 */ 186 #define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) 187 #define SRAM_SW_REG_SIZE 0x1000 188 189 #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) 190 #define SRAM_OUTBOX_SIZE 0x1000 191 192 /* window 1 */ 193 #define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) 194 #define SRAM_INBOX_SIZE 0x2000 195 /* window 2 */ 196 #define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) 197 #define SRAM_DEBUG_SIZE 0x800 198 199 #define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) 200 #define SRAM_EXCEPT_SIZE 0x800 201 202 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) 203 #define SRAM_STREAM_SIZE 0x1000 204 205 /* window 3 */ 206 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) 207 #if CONFIG_TRACE 208 #define SRAM_TRACE_SIZE 0x2000 209 #else 210 #define SRAM_TRACE_SIZE 0x0 211 #endif 212 213 #define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE 214 #define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) 215 #define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE 216 #define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE 217 #define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE 218 #define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \ 219 SRAM_STREAM_SIZE) 220 #define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE 221 #define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE 222 223 #define HEAP_HP_BUFFER_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) 224 #define HEAP_HP_BUFFER_SIZE 0x20000 225 #define HEAP_HP_BUFFER_BLOCK_SIZE 0x180 226 #define HEAP_HP_BUFFER_COUNT \ 227 (HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE) 228 229 /* HP SRAM Base */ 230 #define HP_SRAM_VECBASE_RESET (HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE) 231 232 /* text and data share the same HP L2 SRAM on Tigerlake */ 233 #define SOF_FW_START (HP_SRAM_VECBASE_RESET + 0x400) 234 #define SOF_FW_BASE (SOF_FW_START) 235 236 /* max size for all var-size sections (text/rodata/bss) */ 237 #define SOF_FW_MAX_SIZE (HP_SRAM_BASE + HP_SRAM_SIZE - SOF_FW_BASE) 238 239 #define SOF_TEXT_START (SOF_FW_START) 240 #define SOF_TEXT_BASE (SOF_FW_START) 241 242 /* Heap section sizes for system runtime heap for primary core */ 243 #define HEAP_SYS_RT_0_COUNT64 128 244 #define HEAP_SYS_RT_0_COUNT512 16 245 #define HEAP_SYS_RT_0_COUNT1024 4 246 247 /* Heap section sizes for system runtime heap for secondary core */ 248 #define HEAP_SYS_RT_X_COUNT64 64 249 #define HEAP_SYS_RT_X_COUNT512 8 250 #define HEAP_SYS_RT_X_COUNT1024 4 251 252 /* Heap section counts base */ 253 #define HEAP_COUNT64 128 254 #define HEAP_COUNT128 128 255 #define HEAP_COUNT256 96 256 #define HEAP_COUNT512 8 257 #define HEAP_COUNT1024 4 258 #define HEAP_COUNT2048 2 259 #define HEAP_COUNT4096 1 260 261 #if HP_SRAM_SIZE < 0x200000 262 #define RT_TIMES 3 263 #define RT_SHARED_TIMES 6 264 #else 265 #ifdef CONFIG_COMP_RTNR 266 #define RT_TIMES 6 267 #define RT_SHARED_TIMES 11 268 #else 269 #define RT_TIMES 8 270 #define RT_SHARED_TIMES 16 271 #endif /* CONFIG_COMP_RTNR */ 272 #endif 273 274 /* Heap section sizes for module pool */ 275 #define HEAP_RT_COUNT64 (HEAP_COUNT64 * RT_TIMES) 276 #define HEAP_RT_COUNT128 (HEAP_COUNT128 * RT_TIMES) 277 #define HEAP_RT_COUNT256 (HEAP_COUNT256 * RT_TIMES) 278 #define HEAP_RT_COUNT512 (HEAP_COUNT512 * RT_TIMES) 279 #define HEAP_RT_COUNT1024 (HEAP_COUNT1024 * RT_TIMES) 280 #define HEAP_RT_COUNT2048 (HEAP_COUNT2048 * RT_TIMES) 281 #define HEAP_RT_COUNT4096 (HEAP_COUNT4096 * RT_TIMES) 282 283 /* Heap configuration */ 284 #define HEAP_RUNTIME_SIZE \ 285 (HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \ 286 HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \ 287 HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + \ 288 HEAP_RT_COUNT4096 * 4096) 289 290 /* Heap section sizes for runtime shared heap */ 291 #define HEAP_RUNTIME_SHARED_COUNT64 (HEAP_COUNT64 * RT_SHARED_TIMES) 292 #define HEAP_RUNTIME_SHARED_COUNT128 (HEAP_COUNT128 * RT_SHARED_TIMES) 293 #define HEAP_RUNTIME_SHARED_COUNT256 (HEAP_COUNT256 * RT_SHARED_TIMES) 294 #define HEAP_RUNTIME_SHARED_COUNT512 (HEAP_COUNT512 * RT_SHARED_TIMES) 295 #define HEAP_RUNTIME_SHARED_COUNT1024 (HEAP_COUNT1024 * RT_SHARED_TIMES) 296 297 #define HEAP_RUNTIME_SHARED_SIZE \ 298 (HEAP_RUNTIME_SHARED_COUNT64 * 64 + HEAP_RUNTIME_SHARED_COUNT128 * 128 + \ 299 HEAP_RUNTIME_SHARED_COUNT256 * 256 + HEAP_RUNTIME_SHARED_COUNT512 * 512 + \ 300 HEAP_RUNTIME_SHARED_COUNT1024 * 1024) 301 302 /* Heap section sizes for system shared heap */ 303 #define HEAP_SYSTEM_SHARED_SIZE 0x1500 304 305 #define HEAP_BUFFER_SIZE 0x80000 306 #define HEAP_BUFFER_BLOCK_SIZE 0x100 307 #define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) 308 309 #define HEAP_SYSTEM_M_SIZE 0x8000 /* heap primary core size */ 310 #define HEAP_SYSTEM_S_SIZE 0x6000 /* heap secondary core size */ 311 #define HEAP_SYSTEM_T_SIZE \ 312 (HEAP_SYSTEM_M_SIZE + ((CONFIG_CORE_COUNT - 1) * HEAP_SYSTEM_S_SIZE)) 313 314 #define HEAP_SYS_RUNTIME_M_SIZE \ 315 (HEAP_SYS_RT_0_COUNT64 * 64 + HEAP_SYS_RT_0_COUNT512 * 512 + \ 316 HEAP_SYS_RT_0_COUNT1024 * 1024) 317 318 #define HEAP_SYS_RUNTIME_S_SIZE \ 319 (HEAP_SYS_RT_X_COUNT64 * 64 + HEAP_SYS_RT_X_COUNT512 * 512 + \ 320 HEAP_SYS_RT_X_COUNT1024 * 1024) 321 322 #define HEAP_SYS_RUNTIME_T_SIZE \ 323 (HEAP_SYS_RUNTIME_M_SIZE + ((CONFIG_CORE_COUNT - 1) * \ 324 HEAP_SYS_RUNTIME_S_SIZE)) 325 326 /* Stack configuration */ 327 #define SOF_STACK_SIZE 0x1000 328 #define SOF_STACK_TOTAL_SIZE (CONFIG_CORE_COUNT * SOF_STACK_SIZE) 329 330 /* SOF Core S configuration */ 331 #define SOF_CORE_S_SIZE \ 332 ALIGN((HEAP_SYSTEM_S_SIZE + HEAP_SYS_RUNTIME_S_SIZE + SOF_STACK_SIZE),\ 333 SRAM_BANK_SIZE) 334 #define SOF_CORE_S_T_SIZE ((CONFIG_CORE_COUNT - 1) * SOF_CORE_S_SIZE) 335 336 /* 337 * The LP SRAM Heap and Stack on Tigerlake are organised like this :- 338 * 339 * +--------------------------------------------------------------------------+ 340 * | Offset | Region | Size | 341 * +---------------------+----------------+-----------------------------------+ 342 * | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE | 343 * | | Data | | 344 * | | BSS | | 345 * +---------------------+----------------+-----------------------------------+ 346 * | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE | 347 * +---------------------+----------------+-----------------------------------+ 348 * | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE | 349 * +---------------------+----------------+-----------------------------------+ 350 * | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE | 351 * +---------------------+----------------+-----------------------------------+ 352 * | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE | 353 * +---------------------+----------------+-----------------------------------+ 354 * | SOF_STACK_BASE | | | 355 * +---------------------+----------------+-----------------------------------+ 356 */ 357 358 /* LP SRAM */ 359 #define LP_SRAM_BASE 0xBE800000 360 361 #if CONFIG_MULTICORE 362 /* alternate reset vector */ 363 #define LP_SRAM_ALT_RESET_VEC_BASE LP_SRAM_BASE 364 #define LP_SRAM_ALT_RESET_VEC_SIZE 0x180 365 366 #define LP_SRAM_ALT_RESET_INT_VEC_BASE (LP_SRAM_ALT_RESET_VEC_BASE + \ 367 LP_SRAM_ALT_RESET_VEC_SIZE) 368 #define LP_SRAM_ALT_RESET_INT_VEC_SIZE 0x10 369 370 #define LP_SRAM_CODE_BASE (LP_SRAM_ALT_RESET_INT_VEC_BASE + \ 371 LP_SRAM_ALT_RESET_INT_VEC_SIZE) 372 #define LP_SRAM_CODE_SIZE 0x220 373 374 #define LP_SRAM_START (LP_SRAM_CODE_BASE + LP_SRAM_CODE_SIZE) 375 #else 376 #define LP_SRAM_START LP_SRAM_BASE 377 #endif 378 379 #if (CONFIG_CAVS_LPS) 380 #define LPS_RESTORE_VECTOR_OFFSET 0x1000 381 #define LPS_RESTORE_VECTOR_SIZE 0x800 382 #define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET) 383 #define HEAP_LP_BUFFER_BASE (LPS_RESTORE_VECTOR_ADDR + LPS_RESTORE_VECTOR_SIZE) 384 #define HEAP_LP_BUFFER_SIZE (LP_SRAM_SIZE - LPS_RESTORE_VECTOR_SIZE -\ 385 LPS_RESTORE_VECTOR_OFFSET) 386 #else 387 #define HEAP_LP_BUFFER_BASE LP_SRAM_START 388 #define HEAP_LP_BUFFER_SIZE (LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)) 389 #endif 390 391 #define HEAP_LP_BUFFER_BLOCK_SIZE 0x180 392 393 #if CONFIG_LP_MEMORY_BANKS 394 #define HEAP_LP_BUFFER_COUNT \ 395 (HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE) 396 #else 397 #define HEAP_LP_BUFFER_COUNT 0 398 #endif 399 400 #define PLATFORM_HEAP_SYSTEM CONFIG_CORE_COUNT /* one per core */ 401 #define PLATFORM_HEAP_SYSTEM_RUNTIME CONFIG_CORE_COUNT /* one per core */ 402 #define PLATFORM_HEAP_RUNTIME 1 403 #define PLATFORM_HEAP_RUNTIME_SHARED 1 404 #define PLATFORM_HEAP_SYSTEM_SHARED 1 405 #define PLATFORM_HEAP_BUFFER 2 406 407 /* Stack configuration */ 408 #define SOF_LP_STACK_SIZE 0x1000 409 #define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE) 410 #define SOF_LP_STACK_END (SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE) 411 412 413 /* Vector and literal sizes - do not use core-isa.h */ 414 #define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET 415 #define SOF_MEM_VECT_LIT_SIZE 0x8 416 #define SOF_MEM_VECT_TEXT_SIZE 0x38 417 #define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + \ 418 SOF_MEM_VECT_LIT_SIZE) 419 420 /* Size of dynamic vectors unpacked from WindowOverflow4 */ 421 #define SOF_DYNAMIC_VECTORS_SIZE 0x400 422 423 #define SOF_MEM_ERROR_TEXT_SIZE 0x180 424 #define SOF_MEM_ERROR_LIT_SIZE 0x8 425 426 #define SOF_MEM_RESET_TEXT_SIZE 0x268 427 #define SOF_MEM_RESET_LIT_SIZE 0x8 428 #define SOF_MEM_VECBASE_LIT_SIZE 0x178 429 430 #define SOF_MEM_RO_SIZE 0x8 431 432 /* VM ROM sizes */ 433 #define ROM_RESET_TEXT_SIZE 0x400 434 #define ROM_RESET_LIT_SIZE 0x200 435 436 /* boot loader in IMR */ 437 #define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 438 #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 439 440 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000 441 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120 442 #define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \ 443 IMR_BOOT_LDR_TEXT_ENTRY_SIZE) 444 #define IMR_BOOT_LDR_LIT_SIZE 0x22 445 #define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + \ 446 IMR_BOOT_LDR_LIT_SIZE) 447 #define IMR_BOOT_LDR_TEXT_SIZE 0x1C00 448 #define IMR_BOOT_LDR_DATA_BASE 0xB0039000 449 #define IMR_BOOT_LDR_DATA_SIZE 0x1000 450 #define IMR_BOOT_LDR_BSS_BASE 0xB0100000 451 #define IMR_BOOT_LDR_BSS_SIZE 0x10000 452 453 /* Temporary stack place for boot_ldr */ 454 #define BOOT_LDR_STACK_BASE HEAP_HP_BUFFER_BASE 455 #define BOOT_LDR_STACK_SIZE SOF_STACK_TOTAL_SIZE 456 457 /* L1 memory */ 458 #define L1_MEM_BASE 0x9F000000 459 #define L1_DRAM_SIZE (CONFIG_L1_DRAM_BANKS * CONFIG_L1_DRAM_BANK_SIZE) 460 #define L1_MEM_REG_BASE 0x9F080000 461 #define L1_MEM_CAP (L1_MEM_REG_BASE + 0x00) 462 #define L1_MEM_DRAM_PGCTL (L1_MEM_REG_BASE + 0x20) 463 #define L1_MEM_DRAM_PGISTS (L1_MEM_REG_BASE + 0x28) 464 465 /* L1 init */ 466 #define L1CC_ADDR (0x9F080080) 467 #define CxL1CCAP (L1CC_ADDR + 0x0000) 468 #define CxL1CCFG (L1CC_ADDR + 0x0004) 469 #define CxL1PCFG (L1CC_ADDR + 0x0008) 470 471 #define L1_CACHE_ALL_DATA_WAY_ENABLED_MASK (BIT(XCHAL_DCACHE_WAYS) - 1) 472 #define L1_CACHE_ALL_INSTR_WAY_ENABLED_MASK ((BIT(XCHAL_ICACHE_WAYS) - 1) << 8) 473 #define L1_CACHE_ALL_WAY_ENABLED_MASK ((L1_CACHE_ALL_DATA_WAY_ENABLED_MASK) \ 474 | (L1_CACHE_ALL_INSTR_WAY_ENABLED_MASK)) 475 #define L1_CACHE_ALL_WAY_ACTIVE_MASK (L1_CACHE_ALL_WAY_ENABLED_MASK << 16) 476 477 #define L1_CACHE_ONE_DATA_WAY_ENABLED_MASK BIT(0) 478 #define L1_CACHE_ONE_INSTR_WAY_ENABLED_MASK BIT(8) 479 #define L1_CACHE_ONE_WAY_ENABLED_MASK (L1_CACHE_ONE_DATA_WAY_ENABLED_MASK \ 480 | L1_CACHE_ONE_INSTR_WAY_ENABLED_MASK) 481 #define L1_CACHE_ONE_WAY_ACTIVE_MASK (L1_CACHE_ONE_WAY_ENABLED_MASK << 16) 482 483 #define L1_CACHE_PREFETCHER_ENABLED 1 484 #define L1_CACHE_PREFETCHER_ACTIVE 0x10000 485 486 #define L1_CACHE_PREFCTL_VALUE 0x1038 487 488 #define host_to_local(addr) (addr) 489 #define local_to_host(addr) (addr) 490 491 #endif /* __PLATFORM_LIB_MEMORY_H__ */ 492 493 #else 494 495 #error "This file shouldn't be included from outside of sof/lib/memory.h" 496 497 #endif /* __SOF_LIB_MEMORY_H__ */ 498
