1 /* 2 * Copyright (c) 2023 Meshium 3 * Aleksandr Senin <al@meshium.net> 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __DSA_KSZ8463_H__ 8 #define __DSA_KSZ8463_H__ 9 10 /* SPI commands */ 11 #define KSZ8463_SPI_CMD_WR (BIT(7)) 12 #define KSZ8463_SPI_CMD_RD (0) 13 14 #define KSZ8463_REG_ADDR_HI_PART(x) (((x) & 0x7FF) >> 4) 15 #define KSZ8463_REG_ADDR_LO_PART(x) (((x) & 0x00C) << 4) 16 #define KSZ8463_SPI_BYTE_ENABLE(x) (BIT(((x) & 0x3) + 2)) 17 18 /* PHY registers */ 19 #define KSZ8463_BMCR 0x00 20 #define KSZ8463_BMSR 0x01 21 #define KSZ8463_PHYID1 0x02 22 #define KSZ8463_PHYID2 0x03 23 #define KSZ8463_ANAR 0x04 24 #define KSZ8463_ANLPAR 0x05 25 #define KSZ8463_LINKMD 0x1D 26 #define KSZ8463_PHYSCS 0x1F 27 28 /* SWITCH registers */ 29 #define KSZ8463_CHIP_ID0 0x01 30 #define KSZ8463_CHIP_ID1 0x00 31 #define KSZ8463_GLOBAL_CTRL_1L 0x02 32 #define KSZ8463_GLOBAL_CTRL_1H 0x03 33 #define KSZ8463_GLOBAL_CTRL_2L 0x04 34 #define KSZ8463_GLOBAL_CTRL_2H 0x05 35 #define KSZ8463_GLOBAL_CTRL_3L 0x06 36 #define KSZ8463_GLOBAL_CTRL_3H 0x07 37 #define KSZ8463_GLOBAL_CTRL_6L 0x0C 38 #define KSZ8463_GLOBAL_CTRL_6H 0x0D 39 #define KSZ8463_GLOBAL_CTRL_7L 0x0E 40 #define KSZ8463_GLOBAL_CTRL_7H 0x0F 41 #define KSZ8463_GLOBAL_CTRL_8L 0xAC 42 #define KSZ8463_GLOBAL_CTRL_8H 0xAD 43 #define KSZ8463_GLOBAL_CTRL_9L 0xAE 44 #define KSZ8463_GLOBAL_CTRL_9H 0xAF 45 46 #define KSZ8463_CFGR_L 0xD8 47 48 #define KSZ8463_DSP_CNTRL_6L 0x734 49 #define KSZ8463_DSP_CNTRL_6H 0x735 50 51 #define KSZ8463_GLOBAL_CTRL1_TAIL_TAG_EN BIT(0) 52 #define KSZ8463_GLOBAL_CTRL2_LEG_MAX_PKT_SIZ_CHK_ENA BIT(1) 53 54 #define KSZ8463_CTRL2L_PORTn(n) (0x6E + ((n) * 0x18)) 55 #define KSZ8463_CTRL2L_VLAN_PORTS_MASK 0xF8 56 #define KSZ8463_CTRL2H_PORTn(n) (0x6F + ((n) * 0x18)) 57 #define KSZ8463_CTRL2_TRANSMIT_EN BIT(2) 58 #define KSZ8463_CTRL2_RECEIVE_EN BIT(1) 59 #define KSZ8463_CTRL2_LEARNING_DIS BIT(0) 60 61 #define KSZ8463_STAT2_PORTn(n) (0x80 + ((n) * 0x18)) 62 #define KSZ8463_STAT2_LINK_GOOD BIT(5) 63 64 #define KSZ8463_CHIP_ID0_ID_DEFAULT 0x84 65 #define KSZ8463_CHIP_ID1_ID_DEFAULT 0x43 66 #define KSZ8463F_CHIP_ID1_ID_DEFAULT 0x53 67 #define KSZ8463_RESET_REG 0x127 68 #define KSZ8463_SOFTWARE_RESET_SET BIT(0) 69 #define KSZ8463_SOFTWARE_RESET_CLEAR 0 70 71 #define KSZ8463_P2_COPPER_MODE BIT(7) 72 #define KSZ8463_P1_COPPER_MODE BIT(6) 73 #define KSZ8463_RECV_ADJ BIT(5) 74 75 enum { 76 /* LAN ports for the ksz8463 switch */ 77 KSZ8463_PORT1 = 0, 78 KSZ8463_PORT2, 79 /* SWITCH <-> CPU port */ 80 KSZ8463_PORT3, 81 }; 82 83 #define KSZ8463_REG_IND_CTRL_0 0x31 84 #define KSZ8463_REG_IND_CTRL_1 0x30 85 #define KSZ8463_REG_IND_DATA_8 0x26 86 #define KSZ8463_REG_IND_DATA_7 0x2B 87 #define KSZ8463_REG_IND_DATA_6 0x2A 88 #define KSZ8463_REG_IND_DATA_5 0x29 89 #define KSZ8463_REG_IND_DATA_4 0x28 90 #define KSZ8463_REG_IND_DATA_3 0x2F 91 #define KSZ8463_REG_IND_DATA_2 0x2E 92 #define KSZ8463_REG_IND_DATA_1 0x2D 93 #define KSZ8463_REG_IND_DATA_0 0x2C 94 95 #define KSZ8463_STATIC_MAC_TABLE_VALID BIT(3) 96 #define KSZ8463_STATIC_MAC_TABLE_OVRD BIT(4) 97 #define KSZ8463_STATIC_MAC_TABLE_USE_FID BIT(5) 98 99 #define KSZ8XXX_CHIP_ID0 KSZ8463_CHIP_ID0 100 #define KSZ8XXX_CHIP_ID1 KSZ8463_CHIP_ID1 101 #define KSZ8XXX_CHIP_ID0_ID_DEFAULT KSZ8463_CHIP_ID0_ID_DEFAULT 102 #define KSZ8XXX_CHIP_ID1_ID_DEFAULT KSZ8463F_CHIP_ID1_ID_DEFAULT 103 #define KSZ8XXX_FIRST_PORT KSZ8463_PORT1 104 #define KSZ8XXX_LAST_PORT KSZ8463_PORT3 105 #define KSZ8XXX_CPU_PORT KSZ8463_PORT3 106 #define KSZ8XXX_REG_IND_CTRL_0 KSZ8463_REG_IND_CTRL_0 107 #define KSZ8XXX_REG_IND_CTRL_1 KSZ8463_REG_IND_CTRL_1 108 #define KSZ8XXX_REG_IND_DATA_8 KSZ8463_REG_IND_DATA_8 109 #define KSZ8XXX_REG_IND_DATA_7 KSZ8463_REG_IND_DATA_7 110 #define KSZ8XXX_REG_IND_DATA_6 KSZ8463_REG_IND_DATA_6 111 #define KSZ8XXX_REG_IND_DATA_5 KSZ8463_REG_IND_DATA_5 112 #define KSZ8XXX_REG_IND_DATA_4 KSZ8463_REG_IND_DATA_4 113 #define KSZ8XXX_REG_IND_DATA_3 KSZ8463_REG_IND_DATA_3 114 #define KSZ8XXX_REG_IND_DATA_2 KSZ8463_REG_IND_DATA_2 115 #define KSZ8XXX_REG_IND_DATA_1 KSZ8463_REG_IND_DATA_1 116 #define KSZ8XXX_REG_IND_DATA_0 KSZ8463_REG_IND_DATA_0 117 #define KSZ8XXX_STATIC_MAC_TABLE_VALID KSZ8463_STATIC_MAC_TABLE_VALID 118 #define KSZ8XXX_STATIC_MAC_TABLE_OVRD KSZ8463_STATIC_MAC_TABLE_OVRD 119 #define KSZ8XXX_STAT2_LINK_GOOD KSZ8463_STAT2_LINK_GOOD 120 #define KSZ8XXX_RESET_REG KSZ8463_RESET_REG 121 #define KSZ8XXX_RESET_SET KSZ8463_SOFTWARE_RESET_SET 122 #define KSZ8XXX_RESET_CLEAR KSZ8463_SOFTWARE_RESET_CLEAR 123 #define KSZ8XXX_STAT2_PORTn KSZ8463_STAT2_PORTn 124 #define KSZ8XXX_CTRL1_PORTn KSZ8463_CTRL2L_PORTn 125 #define KSZ8XXX_CTRL1_VLAN_PORTS_MASK KSZ8463_CTRL2L_VLAN_PORTS_MASK 126 #define KSZ8XXX_SPI_CMD_RD KSZ8463_SPI_CMD_RD 127 #define KSZ8XXX_SPI_CMD_WR KSZ8463_SPI_CMD_WR 128 #define KSZ8XXX_SOFT_RESET_DURATION 1000 129 #define KSZ8XXX_HARD_RESET_WAIT 10000 130 131 #endif /* __DSA_KSZ8463_H__ */ 132
