1 /* 2 * Copyright (c) 2016-2021 ARM Limited 3 * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. 4 * 5 * Licensed under the Apache License Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing software 12 * distributed under the License is distributed on an "AS IS" BASIS 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 /** 19 * \file device_definition.c 20 * \brief This file defines exports the structures based on the peripheral 21 * definitions from device_cfg.h. 22 * This retarget file is meant to be used as a helper for baremetal 23 * applications and/or as an example of how to configure the generic 24 * driver structures. 25 */ 26 27 #include "device_definition.h" 28 #include "platform_base_address.h" 29 #include "tfm_peripherals_def.h" 30 #include "tfm_plat_defs.h" 31 32 /* UART configuration */ 33 const cy_stc_scb_uart_config_t KITPROG_UART_config = 34 { 35 .uartMode = CY_SCB_UART_STANDARD, 36 .enableMutliProcessorMode = false, 37 .smartCardRetryOnNack = false, 38 .irdaInvertRx = false, 39 .irdaEnableLowPowerReceiver = false, 40 .oversample = 8, 41 .enableMsbFirst = false, 42 .dataWidth = 8UL, 43 .parity = CY_SCB_UART_PARITY_NONE, 44 .stopBits = CY_SCB_UART_STOP_BITS_1, 45 .enableInputFilter = false, 46 .breakWidth = 11UL, 47 .dropOnFrameError = false, 48 .dropOnParityError = false, 49 .receiverAddress = 0x0UL, 50 .receiverAddressMask = 0x0UL, 51 .acceptAddrInFifo = false, 52 .enableCts = false, 53 .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, 54 .rtsRxFifoLevel = 0UL, 55 .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, 56 .rxFifoTriggerLevel = 63UL, 57 .rxFifoIntEnableMask = 0UL, 58 .txFifoTriggerLevel = 63UL, 59 .txFifoIntEnableMask = 0UL, 60 }; 61 62 63 /* TCPWM Timer driver structures */ 64 #if defined(CY_TCPWM0_TIMER0_S) 65 cy_stc_tcpwm_counter_config_t tcpwm_config_timer0 66 #if defined(TFM_PARTITION_SLIH_TEST) 67 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 68 #elif defined(TFM_PARTITION_FLIH_TEST) 69 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_FLIH_TEST", "APP-ROT") 70 #endif /* TFM_PARTITION_SLIH_TEST */ 71 = { 72 .period = TIMER0_MATCH, /* Upper limit (wrap around) */ 73 .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_8, /* Clk_counter = Clk_input / 8 */ 74 .runMode = CY_TCPWM_COUNTER_CONTINUOUS, /* Wrap around */ 75 .countDirection = CY_TCPWM_COUNTER_COUNT_UP, 76 .compareOrCapture = CY_TCPWM_COUNTER_MODE_COMPARE,/* match compare0 */ 77 .compare0 = TIMER0_MATCH, 78 .compare1 = 0, 79 .enableCompareSwap = false, /* swap compare0 & compare1 upon compare event */ 80 .interruptSources = CY_TCPWM_INT_ON_CC, 81 .captureInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */ 82 .captureInput = CY_TCPWM_INPUT_0, 83 .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */ 84 .reloadInput = CY_TCPWM_INPUT_0, 85 .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */ 86 .startInput = CY_TCPWM_INPUT_0, 87 .stopInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */ 88 .stopInput = CY_TCPWM_INPUT_0, 89 .countInputMode = CY_TCPWM_INPUT_LEVEL, 90 .countInput = CY_TCPWM_INPUT_1, /* count Clk_counter */ 91 }; 92 93 #if (CY_CPU_CORTEX_M0P) 94 cy_stc_sysint_t CY_TCPWM_NVIC_CFG_S 95 #if defined(TFM_PARTITION_SLIH_TEST) 96 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 97 #elif defined(TFM_PARTITION_FLIH_TEST) 98 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_FLIH_TEST", "APP-ROT") 99 #endif /* TFM_PARTITION_SLIH_TEST */ 100 = { 101 .intrSrc = TFM_TIMER0_IRQ, /* NVIC #3 */ 102 .cm0pSrc = tcpwm_0_interrupts_0_IRQn, /* IRQ 123 */ 103 .intrPriority = 2U, /* ?: Flash is 0U, IPC is 1U */ 104 }; 105 #endif 106 tfm_timer_irq_test_dev_t CY_TCPWM0_TIMER0_DEV_S 107 #if defined(TFM_PARTITION_SLIH_TEST) 108 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 109 #elif defined(TFM_PARTITION_FLIH_TEST) 110 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_FLIH_TEST", "APP-ROT") 111 #endif /* TFM_PARTITION_SLIH_TEST */ 112 = { 113 .is_initialized = false, 114 .tcpwm_base = TCPWM0, 115 .tcpwm_counter_num = 0, 116 .timer_match_value = TIMER0_MATCH, 117 .tcpwm_config = &tcpwm_config_timer0, 118 }; 119 #endif /* CY_TCPWM0_TIMER0_S */ 120 121 #if defined(CY_TCPWM0_TIMER1_NS) 122 cy_stc_tcpwm_counter_config_t tcpwm_config_timer1 123 = { 124 .period = TIMER1_MATCH, /* Upper limit (wrap around) */ 125 .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_8, /* Clk_counter = Clk_input / 8 */ 126 .runMode = CY_TCPWM_COUNTER_CONTINUOUS, /* Wrap around */ 127 .countDirection = CY_TCPWM_COUNTER_COUNT_UP, 128 .compareOrCapture = CY_TCPWM_COUNTER_MODE_COMPARE,/* match compare0 */ 129 .compare0 = TIMER1_MATCH, 130 .compare1 = 0, 131 .enableCompareSwap = false, /* swap compare0 & compare1 upon compare event */ 132 .interruptSources = CY_TCPWM_INT_ON_CC, 133 .captureInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */ 134 .captureInput = CY_TCPWM_INPUT_0, 135 .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */ 136 .reloadInput = CY_TCPWM_INPUT_0, 137 .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */ 138 .startInput = CY_TCPWM_INPUT_0, 139 .stopInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */ 140 .stopInput = CY_TCPWM_INPUT_0, 141 .countInputMode = CY_TCPWM_INPUT_LEVEL, 142 .countInput = CY_TCPWM_INPUT_1, /* count Clk_counter */ 143 }; 144 145 tfm_timer_irq_test_dev_t CY_TCPWM0_TIMER1_DEV_NS = { 146 .is_initialized = false, 147 .tcpwm_base = TCPWM0, 148 .tcpwm_counter_num = 1, 149 .timer_match_value = TIMER1_MATCH, 150 .tcpwm_config = &tcpwm_config_timer1, 151 }; 152 #endif /* CY_TCPWM0_TIMER1_NS */ 153
