1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #include <stdint.h> 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /* 16 * PMS register configuration structure for I/D splitting address. 17 * Category bits define the splitting address being below, inside or above specific memory level range: 18 * - for details of ESP32S3 memory layout, see 725_mem_map.* documents 19 * - for category bits settings, see MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS* 20 * (components/hal/include/hal/memprot_types.h) 21 * - for details on assembling full splitting address 22 * see function memprot_ll_get_split_addr_from_reg() (components/hal/esp32s3/include/hal/memprot_ll.h) 23 */ 24 typedef union { 25 struct { 26 uint32_t cat0 : 2; /**< category bits - level 2 */ 27 uint32_t cat1 : 2; /**< category bits - level 3 */ 28 uint32_t cat2 : 2; /**< category bits - level 4 */ 29 uint32_t cat3 : 2; /**< category bits - level 5 */ 30 uint32_t cat4 : 2; /**< category bits - level 6 */ 31 uint32_t cat5 : 2; /**< category bits - level 7 */ 32 uint32_t cat6 : 2; /**< category bits - level 8 */ 33 uint32_t splitaddr : 8; /**< splitting address significant bits */ 34 uint32_t reserved : 10; 35 }; 36 uint32_t val; 37 } constrain_reg_fields_t; 38 39 #define I_D_SRAM_SEGMENT_SIZE 0x10000 40 #define I_D_SPLIT_LINE_ALIGN 0x100 41 #define I_D_SPLIT_LINE_SHIFT 0x8 42 #define I_FAULT_ADDR_SHIFT 0x2 43 #define D_FAULT_ADDR_SHIFT 0x4 44 45 #define IRAM0_VIOLATE_STATUS_ADDR_OFFSET 0x40000000 46 #define DRAM0_VIOLATE_STATUS_ADDR_OFFSET 0x3C000000 47 48 //Icache 49 #define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 50 #define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 51 #define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 52 53 //IRAM0 54 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 55 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 56 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 57 58 //DRAM0 59 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 60 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 61 62 //RTC FAST 63 #define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1 64 #define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2 65 #define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4 66 67 #ifdef __cplusplus 68 } 69 #endif 70
