1 /* 2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef CHIP_CHIPREGS_H 7 #define CHIP_CHIPREGS_H 8 9 #include <zephyr/sys/util.h> 10 11 #define EC_REG_BASE_ADDR 0x00f00000 12 13 #ifdef _ASMLANGUAGE 14 #define ECREG(x) x 15 #else 16 17 /* 18 * Macros for hardware registers access. 19 */ 20 #define ECREG(x) (*((volatile unsigned char *)(x))) 21 #define ECREG_u16(x) (*((volatile unsigned short *)(x))) 22 #define ECREG_u32(x) (*((volatile unsigned long *)(x))) 23 24 /* 25 * MASK operation macros 26 */ 27 #define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) 28 #define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) 29 #define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0) 30 #endif /* _ASMLANGUAGE */ 31 32 #ifndef REG_BASE_ADDR 33 #define REG_BASE_ADDR EC_REG_BASE_ADDR 34 #endif 35 36 /* Common definition */ 37 /* 38 * EC clock frequency (PWM and tachometer driver need it to reply 39 * to api or calculate RPM) 40 */ 41 #define EC_FREQ MHZ(8) 42 43 44 /* --- General Control (GCTRL) --- */ 45 #define IT8XXX2_GCTRL_BASE 0x00F02000 46 #define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31) 47 48 /** 49 * 50 * (11xxh) Interrupt controller (INTC) 51 * 52 */ 53 #define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00) 54 #define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01) 55 #define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02) 56 #define ISR3 ECREG(EC_REG_BASE_ADDR + 0x3F03) 57 #define ISR4 ECREG(EC_REG_BASE_ADDR + 0x3F14) 58 #define ISR5 ECREG(EC_REG_BASE_ADDR + 0x3F18) 59 #define ISR6 ECREG(EC_REG_BASE_ADDR + 0x3F1C) 60 #define ISR7 ECREG(EC_REG_BASE_ADDR + 0x3F20) 61 #define ISR8 ECREG(EC_REG_BASE_ADDR + 0x3F24) 62 #define ISR9 ECREG(EC_REG_BASE_ADDR + 0x3F28) 63 #define ISR10 ECREG(EC_REG_BASE_ADDR + 0x3F2C) 64 #define ISR11 ECREG(EC_REG_BASE_ADDR + 0x3F30) 65 #define ISR12 ECREG(EC_REG_BASE_ADDR + 0x3F34) 66 #define ISR13 ECREG(EC_REG_BASE_ADDR + 0x3F38) 67 #define ISR14 ECREG(EC_REG_BASE_ADDR + 0x3F3C) 68 #define ISR15 ECREG(EC_REG_BASE_ADDR + 0x3F40) 69 #define ISR16 ECREG(EC_REG_BASE_ADDR + 0x3F44) 70 #define ISR17 ECREG(EC_REG_BASE_ADDR + 0x3F48) 71 #define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C) 72 #define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50) 73 #define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54) 74 #define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58) 75 #define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C) 76 #define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90) 77 78 #define IER0 ECREG(EC_REG_BASE_ADDR + 0x3F04) 79 #define IER1 ECREG(EC_REG_BASE_ADDR + 0x3F05) 80 #define IER2 ECREG(EC_REG_BASE_ADDR + 0x3F06) 81 #define IER3 ECREG(EC_REG_BASE_ADDR + 0x3F07) 82 #define IER4 ECREG(EC_REG_BASE_ADDR + 0x3F15) 83 #define IER5 ECREG(EC_REG_BASE_ADDR + 0x3F19) 84 #define IER6 ECREG(EC_REG_BASE_ADDR + 0x3F1D) 85 #define IER7 ECREG(EC_REG_BASE_ADDR + 0x3F21) 86 #define IER8 ECREG(EC_REG_BASE_ADDR + 0x3F25) 87 #define IER9 ECREG(EC_REG_BASE_ADDR + 0x3F29) 88 #define IER10 ECREG(EC_REG_BASE_ADDR + 0x3F2D) 89 #define IER11 ECREG(EC_REG_BASE_ADDR + 0x3F31) 90 #define IER12 ECREG(EC_REG_BASE_ADDR + 0x3F35) 91 #define IER13 ECREG(EC_REG_BASE_ADDR + 0x3F39) 92 #define IER14 ECREG(EC_REG_BASE_ADDR + 0x3F3D) 93 #define IER15 ECREG(EC_REG_BASE_ADDR + 0x3F41) 94 #define IER16 ECREG(EC_REG_BASE_ADDR + 0x3F45) 95 #define IER17 ECREG(EC_REG_BASE_ADDR + 0x3F49) 96 #define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D) 97 #define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51) 98 #define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55) 99 #define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59) 100 #define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D) 101 #define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91) 102 103 #define IELMR0 ECREG(EC_REG_BASE_ADDR + 0x3F08) 104 #define IELMR1 ECREG(EC_REG_BASE_ADDR + 0x3F09) 105 #define IELMR2 ECREG(EC_REG_BASE_ADDR + 0x3F0A) 106 #define IELMR3 ECREG(EC_REG_BASE_ADDR + 0x3F0B) 107 #define IELMR4 ECREG(EC_REG_BASE_ADDR + 0x3F16) 108 #define IELMR5 ECREG(EC_REG_BASE_ADDR + 0x3F1A) 109 #define IELMR6 ECREG(EC_REG_BASE_ADDR + 0x3F1E) 110 #define IELMR7 ECREG(EC_REG_BASE_ADDR + 0x3F22) 111 #define IELMR8 ECREG(EC_REG_BASE_ADDR + 0x3F26) 112 #define IELMR9 ECREG(EC_REG_BASE_ADDR + 0x3F2A) 113 #define IELMR10 ECREG(EC_REG_BASE_ADDR + 0x3F2E) 114 #define IELMR11 ECREG(EC_REG_BASE_ADDR + 0x3F32) 115 #define IELMR12 ECREG(EC_REG_BASE_ADDR + 0x3F36) 116 #define IELMR13 ECREG(EC_REG_BASE_ADDR + 0x3F3A) 117 #define IELMR14 ECREG(EC_REG_BASE_ADDR + 0x3F3E) 118 #define IELMR15 ECREG(EC_REG_BASE_ADDR + 0x3F42) 119 #define IELMR16 ECREG(EC_REG_BASE_ADDR + 0x3F46) 120 #define IELMR17 ECREG(EC_REG_BASE_ADDR + 0x3F4A) 121 #define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E) 122 #define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52) 123 #define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56) 124 #define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A) 125 #define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E) 126 #define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92) 127 128 #define IPOLR0 ECREG(EC_REG_BASE_ADDR + 0x3F0C) 129 #define IPOLR1 ECREG(EC_REG_BASE_ADDR + 0x3F0D) 130 #define IPOLR2 ECREG(EC_REG_BASE_ADDR + 0x3F0E) 131 #define IPOLR3 ECREG(EC_REG_BASE_ADDR + 0x3F0F) 132 #define IPOLR4 ECREG(EC_REG_BASE_ADDR + 0x3F17) 133 #define IPOLR5 ECREG(EC_REG_BASE_ADDR + 0x3F1B) 134 #define IPOLR6 ECREG(EC_REG_BASE_ADDR + 0x3F1F) 135 #define IPOLR7 ECREG(EC_REG_BASE_ADDR + 0x3F23) 136 #define IPOLR8 ECREG(EC_REG_BASE_ADDR + 0x3F27) 137 #define IPOLR9 ECREG(EC_REG_BASE_ADDR + 0x3F2B) 138 #define IPOLR10 ECREG(EC_REG_BASE_ADDR + 0x3F2F) 139 #define IPOLR11 ECREG(EC_REG_BASE_ADDR + 0x3F33) 140 #define IPOLR12 ECREG(EC_REG_BASE_ADDR + 0x3F37) 141 #define IPOLR13 ECREG(EC_REG_BASE_ADDR + 0x3F3B) 142 #define IPOLR14 ECREG(EC_REG_BASE_ADDR + 0x3F3F) 143 #define IPOLR15 ECREG(EC_REG_BASE_ADDR + 0x3F43) 144 #define IPOLR16 ECREG(EC_REG_BASE_ADDR + 0x3F47) 145 #define IPOLR17 ECREG(EC_REG_BASE_ADDR + 0x3F4B) 146 #define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F) 147 #define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53) 148 #define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57) 149 #define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B) 150 #define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F) 151 #define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93) 152 153 #define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10) 154 155 156 /* 157 * TODO: use pinctrl node instead of following register declarations 158 * to fix in tcpm\it83xx_pd.h. 159 */ 160 /* GPIO control register */ 161 #define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C) 162 #define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D) 163 #define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649) 164 #define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A) 165 166 /* 167 * IT8XXX2 register structure size/offset checking macro function to mitigate 168 * the risk of unexpected compiling results. 169 */ 170 #define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \ 171 BUILD_ASSERT(sizeof(struct reg_def) == size, \ 172 "Failed in size check of register structure!") 173 #define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \ 174 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \ 175 "Failed in offset check of register structure member!") 176 177 /** 178 * 179 * (18xxh) PWM & SmartAuto Fan Control (PWM) 180 * 181 */ 182 #ifndef __ASSEMBLER__ 183 struct pwm_it8xxx2_regs { 184 /* 0x000: Channel0 Clock Prescaler */ 185 volatile uint8_t C0CPRS; 186 /* 0x001: Cycle Time0 */ 187 volatile uint8_t CTR; 188 /* 0x002~0x00A: Reserved1 */ 189 volatile uint8_t Reserved1[9]; 190 /* 0x00B: Prescaler Clock Frequency Select */ 191 volatile uint8_t PCFSR; 192 /* 0x00C~0x00F: Reserved2 */ 193 volatile uint8_t Reserved2[4]; 194 /* 0x010: Cycle Time1 MSB */ 195 volatile uint8_t CTR1M; 196 /* 0x011~0x022: Reserved3 */ 197 volatile uint8_t Reserved3[18]; 198 /* 0x023: PWM Clock Control */ 199 volatile uint8_t ZTIER; 200 /* 0x024~0x026: Reserved4 */ 201 volatile uint8_t Reserved4[3]; 202 /* 0x027: Channel4 Clock Prescaler */ 203 volatile uint8_t C4CPRS; 204 /* 0x028: Channel4 Clock Prescaler MSB */ 205 volatile uint8_t C4MCPRS; 206 /* 0x029~0x02A: Reserved5 */ 207 volatile uint8_t Reserved5[2]; 208 /* 0x02B: Channel6 Clock Prescaler */ 209 volatile uint8_t C6CPRS; 210 /* 0x02C: Channel6 Clock Prescaler MSB */ 211 volatile uint8_t C6MCPRS; 212 /* 0x02D: Channel7 Clock Prescaler */ 213 volatile uint8_t C7CPRS; 214 /* 0x02E: Channel7 Clock Prescaler MSB */ 215 volatile uint8_t C7MCPRS; 216 /* 0x02F~0x040: Reserved6 */ 217 volatile uint8_t reserved6[18]; 218 /* 0x041: Cycle Time1 */ 219 volatile uint8_t CTR1; 220 /* 0x042: Cycle Time2 */ 221 volatile uint8_t CTR2; 222 /* 0x043: Cycle Time3 */ 223 volatile uint8_t CTR3; 224 /* 0x044~0x048: Reserved7 */ 225 volatile uint8_t reserved7[5]; 226 /* 0x049: PWM Output Open-Drain Enable */ 227 volatile uint8_t PWMODENR; 228 }; 229 #endif /* !__ASSEMBLER__ */ 230 231 /* PWM register fields */ 232 /* 0x023: PWM Clock Control */ 233 #define IT8XXX2_PWM_PCCE BIT(1) 234 /* 0x048: Tachometer Switch Control */ 235 #define IT8XXX2_PWM_T0DVS BIT(3) 236 #define IT8XXX2_PWM_T0CHSEL BIT(2) 237 #define IT8XXX2_PWM_T1DVS BIT(1) 238 #define IT8XXX2_PWM_T1CHSEL BIT(0) 239 240 241 /* --- Wake-Up Control (WUC) --- */ 242 #define IT8XXX2_WUC_BASE 0x00F01B00 243 244 /* TODO: should a defined interface for configuring wake-up interrupts */ 245 #define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00) 246 #define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c) 247 #define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04) 248 #define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d) 249 #define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c) 250 #define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f) 251 252 /** 253 * 254 * (1Dxxh) Keyboard Matrix Scan control (KSCAN) 255 * 256 */ 257 #ifndef __ASSEMBLER__ 258 struct kscan_it8xxx2_regs { 259 /* 0x000: Keyboard Scan Out */ 260 volatile uint8_t KBS_KSOL; 261 /* 0x001: Keyboard Scan Out */ 262 volatile uint8_t KBS_KSOH1; 263 /* 0x002: Keyboard Scan Out Control */ 264 volatile uint8_t KBS_KSOCTRL; 265 /* 0x003: Keyboard Scan Out */ 266 volatile uint8_t KBS_KSOH2; 267 /* 0x004: Keyboard Scan In */ 268 volatile uint8_t KBS_KSI; 269 /* 0x005: Keyboard Scan In Control */ 270 volatile uint8_t KBS_KSICTRL; 271 /* 0x006: Keyboard Scan In [7:0] GPIO Control */ 272 volatile uint8_t KBS_KSIGCTRL; 273 /* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */ 274 volatile uint8_t KBS_KSIGOEN; 275 /* 0x008: Keyboard Scan In [7:0] GPIO Data */ 276 volatile uint8_t KBS_KSIGDAT; 277 /* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */ 278 volatile uint8_t KBS_KSIGDMRR; 279 /* 0x00A: Keyboard Scan Out [15:8] GPIO Control */ 280 volatile uint8_t KBS_KSOHGCTRL; 281 /* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */ 282 volatile uint8_t KBS_KSOHGOEN; 283 /* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */ 284 volatile uint8_t KBS_KSOHGDMRR; 285 /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */ 286 volatile uint8_t KBS_KSOLGCTRL; 287 /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */ 288 volatile uint8_t KBS_KSOLGOEN; 289 }; 290 #endif /* !__ASSEMBLER__ */ 291 292 /* KBS register fields */ 293 /* 0x002: Keyboard Scan Out Control */ 294 #define IT8XXX2_KBS_KSOPU BIT(2) 295 #define IT8XXX2_KBS_KSOOD BIT(0) 296 /* 0x005: Keyboard Scan In Control */ 297 #define IT8XXX2_KBS_KSIPU BIT(2) 298 /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */ 299 #define IT8XXX2_KBS_KSO2GCTRL BIT(2) 300 /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */ 301 #define IT8XXX2_KBS_KSO2GOEN BIT(2) 302 303 304 /** 305 * 306 * (1Fxxh) External Timer & External Watchdog (ETWD) 307 * 308 */ 309 #ifndef __ASSEMBLER__ 310 struct wdt_it8xxx2_regs { 311 /* 0x000: Reserved1 */ 312 volatile uint8_t reserved1; 313 /* 0x001: External Timer1/WDT Configuration */ 314 volatile uint8_t ETWCFG; 315 /* 0x002: External Timer1 Prescaler */ 316 volatile uint8_t ET1PSR; 317 /* 0x003: External Timer1 Counter High Byte */ 318 volatile uint8_t ET1CNTLHR; 319 /* 0x004: External Timer1 Counter Low Byte */ 320 volatile uint8_t ET1CNTLLR; 321 /* 0x005: External Timer1/WDT Control */ 322 volatile uint8_t ETWCTRL; 323 /* 0x006: External WDT Counter Low Byte */ 324 volatile uint8_t EWDCNTLR; 325 /* 0x007: External WDT Key */ 326 volatile uint8_t EWDKEYR; 327 /* 0x008: Reserved2 */ 328 volatile uint8_t reserved2; 329 /* 0x009: External WDT Counter High Byte */ 330 volatile uint8_t EWDCNTHR; 331 /* 0x00A: External Timer2 Prescaler */ 332 volatile uint8_t ET2PSR; 333 /* 0x00B: External Timer2 Counter High Byte */ 334 volatile uint8_t ET2CNTLHR; 335 /* 0x00C: External Timer2 Counter Low Byte */ 336 volatile uint8_t ET2CNTLLR; 337 /* 0x00D: Reserved3 */ 338 volatile uint8_t reserved3; 339 /* 0x00E: External Timer2 Counter High Byte2 */ 340 volatile uint8_t ET2CNTLH2R; 341 }; 342 #endif /* !__ASSEMBLER__ */ 343 344 /* WDT register fields */ 345 /* 0x001: External Timer1/WDT Configuration */ 346 #define IT8XXX2_WDT_EWDKEYEN BIT(5) 347 #define IT8XXX2_WDT_EWDSRC BIT(4) 348 #define IT8XXX2_WDT_LEWDCNTL BIT(3) 349 #define IT8XXX2_WDT_LET1CNTL BIT(2) 350 #define IT8XXX2_WDT_LET1PS BIT(1) 351 #define IT8XXX2_WDT_LETWCFG BIT(0) 352 /* 0x002: External Timer1 Prescaler */ 353 #define IT8XXX2_WDT_ETPS_32P768_KHZ 0x00 354 #define IT8XXX2_WDT_ETPS_1P024_KHZ 0x01 355 #define IT8XXX2_WDT_ETPS_32_HZ 0x02 356 /* 0x005: External Timer1/WDT Control */ 357 #define IT8XXX2_WDT_EWDSCEN BIT(5) 358 #define IT8XXX2_WDT_EWDSCMS BIT(4) 359 #define IT8XXX2_WDT_ET2TC BIT(3) 360 #define IT8XXX2_WDT_ET2RST BIT(2) 361 #define IT8XXX2_WDT_ET1TC BIT(1) 362 #define IT8XXX2_WDT_ET1RST BIT(0) 363 364 /* External Timer register fields */ 365 /* External Timer 3~8 control */ 366 #define IT8XXX2_EXT_ETX_COMB_RST_EN (IT8XXX2_EXT_ETXCOMB | \ 367 IT8XXX2_EXT_ETXRST | \ 368 IT8XXX2_EXT_ETXEN) 369 #define IT8XXX2_EXT_ETXCOMB BIT(3) 370 #define IT8XXX2_EXT_ETXRST BIT(1) 371 #define IT8XXX2_EXT_ETXEN BIT(0) 372 373 /* Control external timer3~8 */ 374 #define IT8XXX2_EXT_TIMER_BASE DT_REG_ADDR(DT_NODELABEL(timer)) /*0x00F01F10*/ 375 #define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3)) 376 #define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3)) 377 #define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \ 378 (n << 3)) 379 #define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \ 380 (n << 2)) 381 382 /* Free run timer configurations */ 383 #define FREE_RUN_TIMER EXT_TIMER_4 384 #define FREE_RUN_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq) 385 /* Free run timer configurations */ 386 #define FREE_RUN_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags) 387 /* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */ 388 #define FREE_RUN_TIMER_MAX_CNT 0xFFFFFFFFUL 389 390 #ifndef __ASSEMBLER__ 391 enum ext_clk_src_sel { 392 EXT_PSR_32P768K = 0, 393 EXT_PSR_1P024K, 394 EXT_PSR_32, 395 EXT_PSR_8M, 396 }; 397 /* 398 * 24-bit timers: external timer 3, 5, and 7 399 * 32-bit timers: external timer 4, 6, and 8 400 */ 401 enum ext_timer_idx { 402 EXT_TIMER_3 = 0, /* Event timer */ 403 EXT_TIMER_4, /* Free run timer */ 404 EXT_TIMER_5, /* Busy wait low timer */ 405 EXT_TIMER_6, /* Busy wait high timer */ 406 EXT_TIMER_7, 407 EXT_TIMER_8, 408 }; 409 #endif 410 411 412 /* 413 * 414 * (2Cxxh) Platform Environment Control Interface (PECI) 415 * 416 */ 417 #ifndef __ASSEMBLER__ 418 struct peci_it8xxx2_regs { 419 /* 0x00: Host Status */ 420 volatile uint8_t HOSTAR; 421 /* 0x01: Host Control */ 422 volatile uint8_t HOCTLR; 423 /* 0x02: Host Command */ 424 volatile uint8_t HOCMDR; 425 /* 0x03: Host Target Address */ 426 volatile uint8_t HOTRADDR; 427 /* 0x04: Host Write Length */ 428 volatile uint8_t HOWRLR; 429 /* 0x05: Host Read Length */ 430 volatile uint8_t HORDLR; 431 /* 0x06: Host Write Data */ 432 volatile uint8_t HOWRDR; 433 /* 0x07: Host Read Data */ 434 volatile uint8_t HORDDR; 435 /* 0x08: Host Control 2 */ 436 volatile uint8_t HOCTL2R; 437 /* 0x09: Received Write FCS value */ 438 volatile uint8_t RWFCSV; 439 /* 0x0A: Received Read FCS value */ 440 volatile uint8_t RRFCSV; 441 /* 0x0B: Write FCS Value */ 442 volatile uint8_t WFCSV; 443 /* 0x0C: Read FCS Value */ 444 volatile uint8_t RFCSV; 445 /* 0x0D: Assured Write FCS Value */ 446 volatile uint8_t AWFCSV; 447 /* 0x0E: Pad Control */ 448 volatile uint8_t PADCTLR; 449 }; 450 #endif /* !__ASSEMBLER__ */ 451 452 /** 453 * 454 * (2Fxxh) USB Device Controller (USBDC) Registers 455 * 456 */ 457 #define EP_EXT_REGS_9X 1 458 #define EP_EXT_REGS_BX 2 459 #define EP_EXT_REGS_DX 3 460 461 #ifndef __ASSEMBLER__ 462 463 /* EP0 to EP15 Enumeration */ 464 enum usb_dc_endpoints { 465 EP0, 466 EP1, 467 EP2, 468 EP3, 469 EP4, 470 EP5, 471 EP6, 472 EP7, 473 EP8, 474 EP9, 475 EP10, 476 EP11, 477 EP12, 478 EP13, 479 EP14, 480 EP15 481 }; 482 483 struct it82xx2_usb_ep_regs { 484 volatile uint8_t ep_ctrl; 485 volatile uint8_t ep_status; 486 volatile uint8_t ep_transtype_sts; 487 volatile uint8_t ep_nak_transtype_sts; 488 }; 489 490 /* Reserved EP Extended Registers */ 491 struct ep_ext_regs_7x { 492 /* 0x75 Reserved */ 493 volatile uint8_t ep_ext_ctrl_75; 494 /* 0x76 Reserved */ 495 volatile uint8_t ep_ext_ctrl_76; 496 /* 0x77 Reserved */ 497 volatile uint8_t ep_ext_ctrl_77; 498 /* 0x78 Reserved */ 499 volatile uint8_t ep_ext_ctrl_78; 500 /* 0x79 Reserved */ 501 volatile uint8_t ep_ext_ctrl_79; 502 /* 0x7A Reserved */ 503 volatile uint8_t ep_ext_ctrl_7a; 504 /* 0x7B Reserved */ 505 volatile uint8_t ep_ext_ctrl_7b; 506 /* 0x7C Reserved */ 507 volatile uint8_t ep_ext_ctrl_7c; 508 /* 0x7D Reserved */ 509 volatile uint8_t ep_ext_ctrl_7d; 510 /* 0x7E Reserved */ 511 volatile uint8_t ep_ext_ctrl_7e; 512 /* 0x7F Reserved */ 513 volatile uint8_t ep_ext_ctrl_7f; 514 }; 515 516 /* From 98h to 9Dh, the EP45/67/89/1011/1213/1415 Extended Control Registers 517 * are defined, and their bits definitions are as follows: 518 * 519 * Bit Description 520 * 7 Reserved 521 * 6 EPPOINT5_ISO_ENABLE 522 * 5 EPPOINT5_SEND_STALL 523 * 4 EPPOINT5_OUT_DATA_SEQUENCE 524 * 3 Reserved 525 * 2 EPPOINT4_ISO_ENABLE 526 * 1 EPPOINT4_SEND_STALL 527 * 0 EPPOINT4_OUT_DATA_SEQUENCE 528 * 529 * Apparently, we can tell that the EP4 and EP5 share the same register, and 530 * the EP6 and EP7 share the same one, and the rest EPs are defined in the 531 * same way. 532 */ 533 struct ep_ext_regs_9x { 534 /* 0x95 Reserved */ 535 volatile uint8_t ep_ext_ctrl_95; 536 /* 0x96 Reserved */ 537 volatile uint8_t ep_ext_ctrl_96; 538 /* 0x97 Reserved */ 539 volatile uint8_t ep_ext_ctrl_97; 540 /* 0x98 ~ 0x9D EP45/67/89/1011/1213/1415 Extended Control Registers */ 541 volatile uint8_t epn0n1_ext_ctrl[6]; 542 /* 0x9E Reserved */ 543 volatile uint8_t ep_ext_ctrl_9e; 544 /* 0x9F Reserved */ 545 volatile uint8_t ep_ext_ctrl_9f; 546 }; 547 548 /* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their 549 * definitions as as follows: 550 * B8h: EP_FIFO1_CONTROL0_REG 551 * B9h: EP_FIFO1_CONTROL1_REG 552 * BAh: EP_FIFO2_CONTROL0_REG 553 * BBh: EP_FIFO2_CONTROL1_REG 554 * BCh: EP_FIFO3_CONTROL0_REG 555 * BDh: EP_FIFO3_CONTROL1_REG 556 * 557 * For each one, its bits definitions are as follows: 558 * (take EP_FIFO1_CONTROL1_REG as example, which controls from EP8 to EP15) 559 * 560 * Bit Description 561 * 562 * 7 EP15 select FIFO1 as data buffer 563 * 6 EP14 select FIFO1 as data buffer 564 * 5 EP13 select FIFO1 as data buffer 565 * 4 EP12 select FIFO1 as data buffer 566 * 3 EP11 select FIFO1 as data buffer 567 * 2 EP10 select FIFO1 as data buffer 568 * 1 EP9 select FIFO1 as data buffer 569 * 0 EP8 select FIFO1 as data buffer 570 * 571 * 1: Select 572 * 0: Not select 573 */ 574 struct ep_ext_regs_bx { 575 /* 0xB5 Reserved */ 576 volatile uint8_t ep_ext_ctrl_b5; 577 /* 0xB6 Reserved */ 578 volatile uint8_t ep_ext_ctrl_b6; 579 /* 0xB7 Reserved */ 580 volatile uint8_t ep_ext_ctrl_b7; 581 /* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */ 582 volatile uint8_t ep_fifo_ctrl[6]; 583 /* 0xBE Reserved */ 584 volatile uint8_t ep_ext_ctrl_be; 585 /* 0xBF Reserved */ 586 volatile uint8_t ep_ext_ctrl_bf; 587 }; 588 589 590 /* From D6h to DDh are EP Extended Control Registers, and their 591 * definitions as as follows: 592 * D6h: EP0_EXT_CTRL1 593 * D7h: EP0_EXT_CTRL2 594 * D8h: EP1_EXT_CTRL1 595 * D9h: EP1_EXT_CTRL2 596 * DAh: EP2_EXT_CTRL1 597 * DBh: EP2_EXT_CTRL2 598 * DCh: EP3_EXT_CTRL1 599 * DDh: EP3_EXT_CTRL2 600 * 601 * We classify them into 4 groups which each of them contains Control 1 and 2 602 * according to the EP number as follows: 603 */ 604 struct epn_ext_ctrl_regs { 605 /* 0xD6/0xD8/0xDA/0xDC EPN Extended Control1 Register */ 606 volatile uint8_t epn_ext_ctrl1; 607 /* 0xD7/0xD9/0xDB/0xDD EPB Extended Control2 Register */ 608 volatile uint8_t epn_ext_ctrl2; 609 }; 610 611 struct ep_ext_regs_dx { 612 /* 0xD5 Reserved */ 613 volatile uint8_t ep_ext_ctrl_d5; 614 /* 0xD6 ~ 0xDD EPN Extended Control 1/2 Registers */ 615 struct epn_ext_ctrl_regs epn_ext_ctrl[4]; 616 /* 0xDE Reserved */ 617 volatile uint8_t ep_ext_ctrl_de; 618 /* 0xDF Reserved */ 619 volatile uint8_t ep_ext_ctrl_df; 620 }; 621 622 623 /* The USB EPx FIFO Registers Definitions 624 * EP0: 60h ~ 74h 625 * EP1: 80h ~ 94h 626 * EP2: A0h ~ B4h 627 * EP3: C0h ~ D4h (D6h to DDh will be defined as marcos for usage) 628 */ 629 struct it82xx2_usb_ep_fifo_regs { 630 /* 0x60 + ep * 0x20 : EP RX FIFO Data Register */ 631 volatile uint8_t ep_rx_fifo_data; 632 /* 0x61 + ep * 0x20 : EP RX FIFO DMA Count Register */ 633 volatile uint8_t ep_rx_fifo_dma_count; 634 /* 0x62 + ep * 0x20 : EP RX FIFO Data Count MSB */ 635 volatile uint8_t ep_rx_fifo_dcnt_msb; 636 /* 0x63 + ep * 0x20 : EP RX FIFO Data Count LSB */ 637 volatile uint8_t ep_rx_fifo_dcnt_lsb; 638 /* 0x64 + ep * 0x20 : EP RX FIFO Control Register */ 639 volatile uint8_t ep_rx_fifo_ctrl; 640 /* (0x65 ~ 0x6F) + ep * 0x20 */ 641 volatile uint8_t reserved_65_6f_add_20[11]; 642 /* 0x70 + ep * 0x20 : EP TX FIFO Data Register */ 643 volatile uint8_t ep_tx_fifo_data; 644 /* (0x71 ~ 0x73) + ep * 0x20 */ 645 volatile uint8_t reserved_71_73_add_20[3]; 646 /* 0x74 + ep * 0x20 : EP TX FIFO Control Register */ 647 volatile uint8_t ep_tx_fifo_ctrl; 648 /* (0x75 ~ 0x7F) + ep * 0x20 */ 649 union { 650 struct ep_ext_regs_7x ep_res; 651 struct ep_ext_regs_9x ext_4_15; 652 struct ep_ext_regs_bx fifo_ctrl; 653 struct ep_ext_regs_dx ext_0_3; 654 }; 655 656 }; 657 658 struct usb_it82xx2_regs { 659 /* 0x00: Host TX Contrl Register */ 660 volatile uint8_t host_tx_ctrl; 661 /* 0x01: Host TX Transaction Type Register */ 662 volatile uint8_t host_tx_trans_type; 663 /* 0x02: Host TX Line Control Register */ 664 volatile uint8_t host_tx_line_ctrl; 665 /* 0x03: Host TX SOF Enable Register */ 666 volatile uint8_t host_tx_sof_enable; 667 /* 0x04: Host TX Address Register */ 668 volatile uint8_t host_tx_addr; 669 /* 0x05: Host TX EP Number Register */ 670 volatile uint8_t host_tx_endp; 671 /* 0x06: Host Frame Number MSP Register */ 672 volatile uint8_t host_frame_num_msp; 673 /* 0x07: Host Frame Number LSP Register */ 674 volatile uint8_t host_frame_num_lsp; 675 /* 0x08: Host Interrupt Status Register */ 676 volatile uint8_t host_interrupt_status; 677 /* 0x09: Host Interrupt Mask Register */ 678 volatile uint8_t host_interrupt_mask; 679 /* 0x0A: Host RX Status Register */ 680 volatile uint8_t host_rx_status; 681 /* 0x0B: Host RX PID Register */ 682 volatile uint8_t host_rx_pid; 683 /* 0x0C: MISC Control Register */ 684 volatile uint8_t misc_control; 685 /* 0x0D: MISC Status Register */ 686 volatile uint8_t misc_status; 687 /* 0x0E: Host RX Connect State Register */ 688 volatile uint8_t host_rx_connect_state; 689 /* 0x0F: Host SOF Timer MSB Register */ 690 volatile uint8_t host_sof_timer_msb; 691 /* 0x10 ~ 0x1F: Reserved Registers 10h - 1Fh */ 692 volatile uint8_t reserved_10_1f[16]; 693 /* 0x20: Host RX FIFO Data Port Register */ 694 volatile uint8_t host_rx_fifo_data; 695 /* 0x21: Host RX FIFO DMA Input Data Count Register */ 696 volatile uint8_t host_rx_fifo_dma_data_count; 697 /* 0x22: Host TX FIFO Data Count MSB Register */ 698 volatile uint8_t host_rx_fifo_data_count_msb; 699 /* 0x23: Host TX FIFO Data Count LSB Register */ 700 volatile uint8_t host_rx_fifo_data_count_lsb; 701 /* 0x24: Host RX FIFO Data Port Register */ 702 volatile uint8_t host_rx_fifo_control; 703 /* 0x25 ~ 0x2F: Reserved Registers 25h - 2Fh */ 704 volatile uint8_t reserved_25_2f[11]; 705 /* 0x30: Host TX FIFO Data Port Register */ 706 volatile uint8_t host_tx_fifo_data; 707 /* 0x31 ~ 0x3F: Reserved Registers 31h - 3Fh */ 708 volatile uint8_t reserved_31_3f[15]; 709 /* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */ 710 struct it82xx2_usb_ep_regs usb_ep_regs[4]; 711 /* 0x50: Device Controller Control Register */ 712 volatile uint8_t dc_control; 713 /* 0x51: Device Controller LINE Status Register */ 714 volatile uint8_t dc_line_status; 715 /* 0x52: Device Controller Interrupt Status Register */ 716 volatile uint8_t dc_interrupt_status; 717 /* 0x53: Device Controller Interrupt Mask Register */ 718 volatile uint8_t dc_interrupt_mask; 719 /* 0x54: Device Controller Address Register */ 720 volatile uint8_t dc_address; 721 /* 0x55: Device Controller Frame Number MSP Register */ 722 volatile uint8_t dc_frame_num_msp; 723 /* 0x56: Device Controller Frame Number LSP Register */ 724 volatile uint8_t dc_frame_num_lsp; 725 /* 0x57 ~ 0x5F: Reserved Registers 57h - 5Fh */ 726 volatile uint8_t reserved_57_5f[9]; 727 /* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */ 728 struct it82xx2_usb_ep_fifo_regs fifo_regs[4]; 729 /* 0xE0: Host/Device Control Register */ 730 volatile uint8_t host_device_control; 731 /* 0xE1 ~ 0xE3: Reserved Registers E1h - E3h */ 732 volatile uint8_t reserved_e1_e3[3]; 733 /* 0xE4: Port0 MISC Control Register */ 734 volatile uint8_t port0_misc_control; 735 /* 0xE5 ~ 0xE7: Reserved Registers E5h - E7h */ 736 volatile uint8_t reserved_e5_e7[3]; 737 /* 0xE8: Port1 MISC Control Register */ 738 volatile uint8_t port1_misc_control; 739 }; 740 #endif /* #ifndef __ASSEMBLER__ */ 741 742 /** 743 * 744 * (37xxh, 38xxh) USBPD Controller 745 * 746 */ 747 #ifndef __ASSEMBLER__ 748 struct usbpd_it8xxx2_regs { 749 /* 0x000~0x003: Reserved1 */ 750 volatile uint8_t Reserved1[4]; 751 /* 0x004: CC General Configuration */ 752 volatile uint8_t CCGCR; 753 /* 0x005: CC Channel Setting */ 754 volatile uint8_t CCCSR; 755 /* 0x006: CC Pad Setting */ 756 volatile uint8_t CCPSR; 757 }; 758 #endif /* !__ASSEMBLER__ */ 759 760 /* USBPD controller register fields */ 761 /* 0x004: CC General Configuration */ 762 #define IT8XXX2_USBPD_DISABLE_CC BIT(7) 763 #define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR BIT(6) 764 #define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1)) 765 #define IT8XXX2_USBPD_CC_SELECT_RP_DEF (BIT(3) | BIT(2)) 766 #define IT8XXX2_USBPD_CC_SELECT_RP_1A5 BIT(3) 767 #define IT8XXX2_USBPD_CC_SELECT_RP_3A0 BIT(2) 768 #define IT8XXX2_USBPD_CC1_CC2_SELECTION BIT(0) 769 /* 0x005: CC Channel Setting */ 770 #define IT8XXX2_USBPD_CC2_DISCONNECT BIT(7) 771 #define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND BIT(6) 772 #define IT8XXX2_USBPD_CC1_DISCONNECT BIT(3) 773 #define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND BIT(2) 774 #define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5)) 775 /* 0x006: CC Pad Setting */ 776 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB BIT(6) 777 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC2 BIT(5) 778 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB BIT(2) 779 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC1 BIT(1) 780 781 782 /** 783 * 784 * (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers 785 * 786 */ 787 #ifndef __ASSEMBLER__ 788 struct smfi_it8xxx2_regs { 789 volatile uint8_t reserved1[59]; 790 /* 0x3B: EC-Indirect memory address 0 */ 791 volatile uint8_t SMFI_ECINDAR0; 792 /* 0x3C: EC-Indirect memory address 1 */ 793 volatile uint8_t SMFI_ECINDAR1; 794 /* 0x3D: EC-Indirect memory address 2 */ 795 volatile uint8_t SMFI_ECINDAR2; 796 /* 0x3E: EC-Indirect memory address 3 */ 797 volatile uint8_t SMFI_ECINDAR3; 798 /* 0x3F: EC-Indirect memory data */ 799 volatile uint8_t SMFI_ECINDDR; 800 /* 0x40: Scratch SRAM 0 address low byte */ 801 volatile uint8_t SMFI_SCAR0L; 802 /* 0x41: Scratch SRAM 0 address middle byte */ 803 volatile uint8_t SMFI_SCAR0M; 804 /* 0x42: Scratch SRAM 0 address high byte */ 805 volatile uint8_t SMFI_SCAR0H; 806 volatile uint8_t reserved1_1[23]; 807 /* 0x5A: Host RAM Window Control */ 808 volatile uint8_t SMFI_HRAMWC; 809 /* 0x5B: Host RAM Window 0 Base Address [11:4] */ 810 volatile uint8_t SMFI_HRAMW0BA; 811 /* 0x5C: Host RAM Window 1 Base Address [11:4] */ 812 volatile uint8_t SMFI_HRAMW1BA; 813 /* 0x5D: Host RAM Window 0 Access Allow Size */ 814 volatile uint8_t SMFI_HRAMW0AAS; 815 /* 0x5E: Host RAM Window 1 Access Allow Size */ 816 volatile uint8_t SMFI_HRAMW1AAS; 817 volatile uint8_t reserved2[67]; 818 /* 0xA2: Flash control 6 */ 819 volatile uint8_t SMFI_FLHCTRL6R; 820 volatile uint8_t reserved3[46]; 821 }; 822 #endif /* !__ASSEMBLER__ */ 823 824 /* SMFI register fields */ 825 /* EC-Indirect read internal flash */ 826 #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) 827 /* Enable EC-indirect page program command */ 828 #define IT8XXX2_SMFI_MASK_ECINDPP BIT(3) 829 /* Scratch SRAM 0 address(BIT(19)) */ 830 #define IT8XXX2_SMFI_SC0A19 BIT(7) 831 /* Scratch SRAM enable */ 832 #define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3) 833 834 /* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */ 835 #define SMFI_H2RAMPS BIT(4) 836 /* H2RAM Window 1 Enable */ 837 #define SMFI_H2RAMW1E BIT(1) 838 /* H2RAM Window 0 Enable */ 839 #define SMFI_H2RAMW0E BIT(0) 840 841 /* Host RAM Window x Write Protect Enable (All protected) */ 842 #define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4)) 843 844 845 /** 846 * 847 * (16xxh) General Purpose I/O Port (GPIO) registers 848 * 849 */ 850 #define GPIO_IT8XXX2_REG_BASE \ 851 ((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr))) 852 853 #ifndef __ASSEMBLER__ 854 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 855 struct gpio_it8xxx2_regs { 856 /* 0x00: General Control */ 857 volatile uint8_t GPIO_GCR; 858 /* 0x01-D0: Reserved1 */ 859 volatile uint8_t reserved1[208]; 860 /* 0xD1: General Control 25 */ 861 volatile uint8_t GPIO_GCR25; 862 /* 0xD2: General Control 26 */ 863 volatile uint8_t GPIO_GCR26; 864 /* 0xD3: General Control 27 */ 865 volatile uint8_t GPIO_GCR27; 866 /* 0xD4: General Control 28 */ 867 volatile uint8_t GPIO_GCR28; 868 /* 0xD5: General Control 31 */ 869 volatile uint8_t GPIO_GCR31; 870 /* 0xD6: General Control 32 */ 871 volatile uint8_t GPIO_GCR32; 872 /* 0xD7: General Control 33 */ 873 volatile uint8_t GPIO_GCR33; 874 /* 0xD8-0xDF: Reserved2 */ 875 volatile uint8_t reserved2[8]; 876 /* 0xE0: General Control 16 */ 877 volatile uint8_t GPIO_GCR16; 878 /* 0xE1: General Control 17 */ 879 volatile uint8_t GPIO_GCR17; 880 /* 0xE2: General Control 18 */ 881 volatile uint8_t GPIO_GCR18; 882 /* 0xE3: Reserved3 */ 883 volatile uint8_t reserved3; 884 /* 0xE4: General Control 19 */ 885 volatile uint8_t GPIO_GCR19; 886 /* 0xE5: General Control 20 */ 887 volatile uint8_t GPIO_GCR20; 888 /* 0xE6: General Control 21 */ 889 volatile uint8_t GPIO_GCR21; 890 /* 0xE7: General Control 22 */ 891 volatile uint8_t GPIO_GCR22; 892 /* 0xE8: General Control 23 */ 893 volatile uint8_t GPIO_GCR23; 894 /* 0xE9: General Control 24 */ 895 volatile uint8_t GPIO_GCR24; 896 /* 0xEA-0xEC: Reserved4 */ 897 volatile uint8_t reserved4[3]; 898 /* 0xED: General Control 30 */ 899 volatile uint8_t GPIO_GCR30; 900 /* 0xEE: General Control 29 */ 901 volatile uint8_t GPIO_GCR29; 902 /* 0xEF: Reserved5 */ 903 volatile uint8_t reserved5; 904 /* 0xF0: General Control 1 */ 905 volatile uint8_t GPIO_GCR1; 906 /* 0xF1: General Control 2 */ 907 volatile uint8_t GPIO_GCR2; 908 /* 0xF2: General Control 3 */ 909 volatile uint8_t GPIO_GCR3; 910 /* 0xF3: General Control 4 */ 911 volatile uint8_t GPIO_GCR4; 912 /* 0xF4: General Control 5 */ 913 volatile uint8_t GPIO_GCR5; 914 /* 0xF5: General Control 6 */ 915 volatile uint8_t GPIO_GCR6; 916 /* 0xF6: General Control 7 */ 917 volatile uint8_t GPIO_GCR7; 918 /* 0xF7: General Control 8 */ 919 volatile uint8_t GPIO_GCR8; 920 /* 0xF8: General Control 9 */ 921 volatile uint8_t GPIO_GCR9; 922 /* 0xF9: General Control 10 */ 923 volatile uint8_t GPIO_GCR10; 924 /* 0xFA: General Control 11 */ 925 volatile uint8_t GPIO_GCR11; 926 /* 0xFB: General Control 12 */ 927 volatile uint8_t GPIO_GCR12; 928 /* 0xFC: General Control 13 */ 929 volatile uint8_t GPIO_GCR13; 930 /* 0xFD: General Control 14 */ 931 volatile uint8_t GPIO_GCR14; 932 /* 0xFE: General Control 15 */ 933 volatile uint8_t GPIO_GCR15; 934 /* 0xFF: Power Good Watch Control */ 935 volatile uint8_t GPIO_PGWCR; 936 }; 937 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 938 struct gpio_it8xxx2_regs { 939 /* 0x00: General Control */ 940 volatile uint8_t GPIO_GCR; 941 /* 0x01-0x0F: Reserved1 */ 942 volatile uint8_t reserved1[15]; 943 /* 0x10: General Control 1 */ 944 volatile uint8_t GPIO_GCR1; 945 /* 0x11: General Control 2 */ 946 volatile uint8_t GPIO_GCR2; 947 /* 0x12: General Control 3 */ 948 volatile uint8_t GPIO_GCR3; 949 /* 0x13: General Control 4 */ 950 volatile uint8_t GPIO_GCR4; 951 /* 0x14: General Control 5 */ 952 volatile uint8_t GPIO_GCR5; 953 /* 0x15: General Control 6 */ 954 volatile uint8_t GPIO_GCR6; 955 /* 0x16: General Control 7 */ 956 volatile uint8_t GPIO_GCR7; 957 /* 0x17: General Control 8 */ 958 volatile uint8_t GPIO_GCR8; 959 /* 0x18: General Control 9 */ 960 volatile uint8_t GPIO_GCR9; 961 /* 0x19: General Control 10 */ 962 volatile uint8_t GPIO_GCR10; 963 /* 0x1A: General Control 11 */ 964 volatile uint8_t GPIO_GCR11; 965 /* 0x1B: General Control 12 */ 966 volatile uint8_t GPIO_GCR12; 967 /* 0x1C: General Control 13 */ 968 volatile uint8_t GPIO_GCR13; 969 /* 0x1D: General Control 14 */ 970 volatile uint8_t GPIO_GCR14; 971 /* 0x1E: General Control 15 */ 972 volatile uint8_t GPIO_GCR15; 973 /* 0x1F: Power Good Watch Control */ 974 volatile uint8_t GPIO_PGWCR; 975 /* 0x20: General Control 16 */ 976 volatile uint8_t GPIO_GCR16; 977 /* 0x21: General Control 17 */ 978 volatile uint8_t GPIO_GCR17; 979 /* 0x22: General Control 18 */ 980 volatile uint8_t GPIO_GCR18; 981 /* 0x23: Reserved2 */ 982 volatile uint8_t reserved2; 983 /* 0x24: General Control 19 */ 984 volatile uint8_t GPIO_GCR19; 985 /* 0x25: Reserved3 */ 986 volatile uint8_t reserved3; 987 /* 0x26: General Control 21 */ 988 volatile uint8_t GPIO_GCR21; 989 /* 0x27-0x28: Reserved4 */ 990 volatile uint8_t reserved4[2]; 991 /* 0x29: General Control 24 */ 992 volatile uint8_t GPIO_GCR24; 993 /* 0x2A-0x2C: Reserved5 */ 994 volatile uint8_t reserved5[3]; 995 /* 0x2D: General Control 30 */ 996 volatile uint8_t GPIO_GCR30; 997 /* 0x2E: General Control 29 */ 998 volatile uint8_t GPIO_GCR29; 999 }; 1000 1001 /* GPIO register fields */ 1002 /* 0x16: General Control 7 */ 1003 #define IT8XXX2_GPIO_SMB2PS BIT(7) 1004 #define IT8XXX2_GPIO_SMB3PS BIT(6) 1005 #define IT8XXX2_GPIO_SMB5PS BIT(5) 1006 1007 #endif 1008 #endif /* !__ASSEMBLER__ */ 1009 1010 /* GPIO register fields */ 1011 /* 0x00: General Control */ 1012 #define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1)) 1013 #define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2 1014 #define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1 1015 #define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS) 1016 /* 0xF0: General Control 1 */ 1017 #define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2) 1018 #define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0) 1019 /* 0xE6: General Control 21 */ 1020 #define IT8XXX2_GPIO_GPH1VS BIT(1) 1021 #define IT8XXX2_GPIO_GPH2VS BIT(0) 1022 1023 #define GPCR_PORT_PIN_MODE_INPUT BIT(7) 1024 #define GPCR_PORT_PIN_MODE_OUTPUT BIT(6) 1025 #define GPCR_PORT_PIN_MODE_PULLUP BIT(2) 1026 #define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1) 1027 1028 /* 1029 * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be 1030 * configured as tri-state. 1031 */ 1032 #define GPCR_PORT_PIN_MODE_TRISTATE (GPCR_PORT_PIN_MODE_INPUT | \ 1033 GPCR_PORT_PIN_MODE_PULLUP | \ 1034 GPCR_PORT_PIN_MODE_PULLDOWN) 1035 1036 /* --- GPIO --- */ 1037 #define IT8XXX2_GPIO_BASE 0x00F01600 1038 #define IT8XXX2_GPIO2_BASE 0x00F03E00 1039 1040 #define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset)) 1041 #define IT8XXX2_GPIO_GCR25_OFFSET 0xd1 1042 #define IT8XXX2_GPIO_GCR26_OFFSET 0xd2 1043 #define IT8XXX2_GPIO_GCR27_OFFSET 0xd3 1044 #define IT8XXX2_GPIO_GCR28_OFFSET 0xd4 1045 #define IT8XXX2_GPIO_GCR31_OFFSET 0xd5 1046 #define IT8XXX2_GPIO_GCR32_OFFSET 0xd6 1047 #define IT8XXX2_GPIO_GCR33_OFFSET 0xd7 1048 #define IT8XXX2_GPIO_GCR19_OFFSET 0xe4 1049 #define IT8XXX2_GPIO_GCR20_OFFSET 0xe5 1050 #define IT8XXX2_GPIO_GCR21_OFFSET 0xe6 1051 #define IT8XXX2_GPIO_GCR22_OFFSET 0xe7 1052 #define IT8XXX2_GPIO_GCR23_OFFSET 0xe8 1053 #define IT8XXX2_GPIO_GCR24_OFFSET 0xe9 1054 #define IT8XXX2_GPIO_GCR30_OFFSET 0xed 1055 #define IT8XXX2_GPIO_GCR29_OFFSET 0xee 1056 1057 /* 1058 * TODO: use pinctrl node instead of following register declarations 1059 * to fix in tcpm\it83xx_pd.h. 1060 */ 1061 #define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18) 1062 #define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19) 1063 1064 1065 /** 1066 * 1067 * (19xxh) Analog to Digital Converter (ADC) registers 1068 * 1069 */ 1070 #ifndef __ASSEMBLER__ 1071 1072 /* Data structure to define ADC channel 13-16 control registers. */ 1073 struct adc_vchs_ctrl_t { 1074 /* 0x60: Voltage Channel Control */ 1075 volatile uint8_t VCHCTL; 1076 /* 0x61: Voltage Channel Data Buffer MSB */ 1077 volatile uint8_t VCHDATM; 1078 /* 0x62: Voltage Channel Data Buffer LSB */ 1079 volatile uint8_t VCHDATL; 1080 }; 1081 1082 struct adc_it8xxx2_regs { 1083 /* 0x00: ADC Status */ 1084 volatile uint8_t ADCSTS; 1085 /* 0x01: ADC Configuration */ 1086 volatile uint8_t ADCCFG; 1087 /* 0x02: ADC Clock Control */ 1088 volatile uint8_t ADCCTL; 1089 /* 0x03: General Control */ 1090 volatile uint8_t ADCGCR; 1091 /* 0x04: Voltage Channel 0 Control */ 1092 volatile uint8_t VCH0CTL; 1093 /* 0x05: Calibration Data Control */ 1094 volatile uint8_t KDCTL; 1095 /* 0x06-0x17: Reserved1 */ 1096 volatile uint8_t reserved1[18]; 1097 /* 0x18: Voltage Channel 0 Data Buffer LSB */ 1098 volatile uint8_t VCH0DATL; 1099 /* 0x19: Voltage Channel 0 Data Buffer MSB */ 1100 volatile uint8_t VCH0DATM; 1101 /* 0x1a-0x43: Reserved2 */ 1102 volatile uint8_t reserved2[42]; 1103 /* 0x44: ADC Data Valid Status */ 1104 volatile uint8_t ADCDVSTS; 1105 /* 0x45-0x54: Reserved2-1 */ 1106 volatile uint8_t reserved2_1[16]; 1107 /* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */ 1108 volatile uint8_t ADCIVMFSCS1; 1109 /* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */ 1110 volatile uint8_t ADCIVMFSCS2; 1111 /* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */ 1112 volatile uint8_t ADCIVMFSCS3; 1113 /* 0x58-0x5f: Reserved3 */ 1114 volatile uint8_t reserved3[8]; 1115 /* 0x60-0x6b: ADC channel 13~16 controller */ 1116 struct adc_vchs_ctrl_t adc_vchs_ctrl[4]; 1117 /* 0x6c: ADC Data Valid Status 2 */ 1118 volatile uint8_t ADCDVSTS2; 1119 }; 1120 #endif /* !__ASSEMBLER__ */ 1121 1122 /* ADC conversion time select 1 */ 1123 #define IT8XXX2_ADC_ADCCTS1 BIT(7) 1124 /* Analog accuracy initialization */ 1125 #define IT8XXX2_ADC_AINITB BIT(3) 1126 /* ADC conversion time select 0 */ 1127 #define IT8XXX2_ADC_ADCCTS0 BIT(5) 1128 /* ADC module enable */ 1129 #define IT8XXX2_ADC_ADCEN BIT(0) 1130 /* ADC data buffer keep enable */ 1131 #define IT8XXX2_ADC_DBKEN BIT(7) 1132 /* W/C data valid flag */ 1133 #define IT8XXX2_ADC_DATVAL BIT(7) 1134 /* Data valid interrupt of adc */ 1135 #define IT8XXX2_ADC_INTDVEN BIT(5) 1136 /* Voltage channel enable (Channel 4~7 and 13~16) */ 1137 #define IT8XXX2_ADC_VCHEN BIT(4) 1138 /* Automatic hardware calibration enable */ 1139 #define IT8XXX2_ADC_AHCE BIT(7) 1140 /* 0x046, 0x049, 0x04c, 0x06e, 0x071, 0x074: Voltage comparator x control */ 1141 #define IT8XXX2_VCMP_CMPEN BIT(7) 1142 #define IT8XXX2_VCMP_CMPINTEN BIT(6) 1143 #define IT8XXX2_VCMP_GREATER_THRESHOLD BIT(5) 1144 #define IT8XXX2_VCMP_EDGE_TRIGGER BIT(4) 1145 #define IT8XXX2_VCMP_GPIO_ACTIVE_LOW BIT(3) 1146 /* 0x077~0x07c: Voltage comparator x channel select MSB */ 1147 #define IT8XXX2_VCMP_VCMPXCSELM BIT(0) 1148 1149 /** 1150 * 1151 * (1Exxh) Clock and Power Management (ECPM) registers 1152 * 1153 */ 1154 #define IT8XXX2_ECPM_BASE 0x00F01E00 1155 1156 #ifndef __ASSEMBLER__ 1157 enum chip_pll_mode { 1158 CHIP_PLL_DOZE = 0, 1159 CHIP_PLL_SLEEP = 1, 1160 CHIP_PLL_DEEP_DOZE = 3, 1161 }; 1162 #endif 1163 /* 1164 * TODO: use ecpm_it8xxx2_regs instead of following register declarations 1165 * to fix in soc.c. 1166 */ 1167 #define IT8XXX2_ECPM_PLLCTRL ECREG(IT8XXX2_ECPM_BASE + 0x03) 1168 #define IT8XXX2_ECPM_AUTOCG ECREG(IT8XXX2_ECPM_BASE + 0x04) 1169 #define IT8XXX2_ECPM_CGCTRL3R ECREG(IT8XXX2_ECPM_BASE + 0x05) 1170 #define IT8XXX2_ECPM_PLLFREQR ECREG(IT8XXX2_ECPM_BASE + 0x06) 1171 #define IT8XXX2_ECPM_PLLCSS ECREG(IT8XXX2_ECPM_BASE + 0x08) 1172 #define IT8XXX2_ECPM_SCDCR0 ECREG(IT8XXX2_ECPM_BASE + 0x0c) 1173 #define IT8XXX2_ECPM_SCDCR1 ECREG(IT8XXX2_ECPM_BASE + 0x0d) 1174 #define IT8XXX2_ECPM_SCDCR2 ECREG(IT8XXX2_ECPM_BASE + 0x0e) 1175 #define IT8XXX2_ECPM_SCDCR3 ECREG(IT8XXX2_ECPM_BASE + 0x0f) 1176 #define IT8XXX2_ECPM_SCDCR4 ECREG(IT8XXX2_ECPM_BASE + 0x10) 1177 1178 /* 1179 * The count number of the counter for 25 ms register. 1180 * The 25 ms register is calculated by (count number *1.024 kHz). 1181 */ 1182 1183 #define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */ 1184 1185 /** 1186 * 1187 * (1Cxxh) SMBus Interface (SMB) registers 1188 * 1189 */ 1190 #define IT8XXX2_SMB_BASE 0x00F01C00 1191 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 1192 #define IT8XXX2_SMB_4P7USL ECREG(IT8XXX2_SMB_BASE + 0x00) 1193 #define IT8XXX2_SMB_4P0USL ECREG(IT8XXX2_SMB_BASE + 0x01) 1194 #define IT8XXX2_SMB_300NS ECREG(IT8XXX2_SMB_BASE + 0x02) 1195 #define IT8XXX2_SMB_250NS ECREG(IT8XXX2_SMB_BASE + 0x03) 1196 #define IT8XXX2_SMB_25MS ECREG(IT8XXX2_SMB_BASE + 0x04) 1197 #define IT8XXX2_SMB_45P3USL ECREG(IT8XXX2_SMB_BASE + 0x05) 1198 #define IT8XXX2_SMB_45P3USH ECREG(IT8XXX2_SMB_BASE + 0x06) 1199 #define IT8XXX2_SMB_4P7A4P0H ECREG(IT8XXX2_SMB_BASE + 0x07) 1200 #define IT8XXX2_SMB_SLVISELR ECREG(IT8XXX2_SMB_BASE + 0x08) 1201 #define IT8XXX2_SMB_SCLKTS(ch) ECREG(IT8XXX2_SMB_BASE + 0x09 + ch) 1202 #define IT8XXX2_SMB_MSTFCTRL1 ECREG(IT8XXX2_SMB_BASE + 0x0D) 1203 #define IT8XXX2_SMB_MSTFSTS1 ECREG(IT8XXX2_SMB_BASE + 0x0E) 1204 #define IT8XXX2_SMB_MSTFCTRL2 ECREG(IT8XXX2_SMB_BASE + 0x0F) 1205 #define IT8XXX2_SMB_MSTFSTS2 ECREG(IT8XXX2_SMB_BASE + 0x10) 1206 #define IT8XXX2_SMB_CHSEF ECREG(IT8XXX2_SMB_BASE + 0x11) 1207 #define IT8XXX2_SMB_I2CW2RF ECREG(IT8XXX2_SMB_BASE + 0x12) 1208 #define IT8XXX2_SMB_IWRFISTA ECREG(IT8XXX2_SMB_BASE + 0x13) 1209 #define IT8XXX2_SMB_CHSAB ECREG(IT8XXX2_SMB_BASE + 0x20) 1210 #define IT8XXX2_SMB_CHSCD ECREG(IT8XXX2_SMB_BASE + 0x21) 1211 #define IT8XXX2_SMB_SFFCTL ECREG(IT8XXX2_SMB_BASE + 0x55) 1212 #define IT8XXX2_SMB_HOSTA(base) ECREG(base + 0x00) 1213 #define IT8XXX2_SMB_HOCTL(base) ECREG(base + 0x01) 1214 #define IT8XXX2_SMB_HOCMD(base) ECREG(base + 0x02) 1215 #define IT8XXX2_SMB_TRASLA(base) ECREG(base + 0x03) 1216 #define IT8XXX2_SMB_D0REG(base) ECREG(base + 0x04) 1217 #define IT8XXX2_SMB_D1REG(base) ECREG(base + 0x05) 1218 #define IT8XXX2_SMB_HOBDB(base) ECREG(base + 0x06) 1219 #define IT8XXX2_SMB_PECERC(base) ECREG(base + 0x07) 1220 #define IT8XXX2_SMB_SMBPCTL(base) ECREG(base + 0x0A) 1221 #define IT8XXX2_SMB_HOCTL2(base) ECREG(base + 0x10) 1222 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 1223 #define IT8XXX2_SMB_SLVISEL ECREG(IT8XXX2_SMB_BASE + 0x08) 1224 #define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x09) 1225 #define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x0A) 1226 #define IT8XXX2_SMB_SMB4CHS ECREG(IT8XXX2_SMB_BASE + 0x0B) 1227 #define IT8XXX2_SMB_SCLKTS_BRGS ECREG(IT8XXX2_SMB_BASE + 0x80) 1228 #define IT8XXX2_SMB_SCLKTS_BRGM ECREG(IT8XXX2_SMB_BASE + 0x81) 1229 #define IT8XXX2_SMB_CHSBRG ECREG(IT8XXX2_SMB_BASE + 0x82) 1230 #define IT8XXX2_SMB_CHSMOT ECREG(IT8XXX2_SMB_BASE + 0x83) 1231 1232 /* SMBus register fields */ 1233 /* 0x80: SMCLK Timing Setting Register Bridge Slave */ 1234 #define IT8XXX2_SMB_PREDEN BIT(7) 1235 #endif 1236 1237 /** 1238 * Enhanced SMBus/I2C Interface 1239 * Ch_D: 0x00F03680, Ch_E: 0x00F03500, Ch_F: 0x00F03580 1240 * Ch_D: ch = 0x03, Ch_E: ch = 0x00, Ch_F: ch = 0x01 1241 */ 1242 #define IT8XXX2_I2C_DRR(base) ECREG(base + 0x00) 1243 #define IT8XXX2_I2C_PSR(base) ECREG(base + 0x01) 1244 #define IT8XXX2_I2C_HSPR(base) ECREG(base + 0x02) 1245 #define IT8XXX2_I2C_STR(base) ECREG(base + 0x03) 1246 #define IT8XXX2_I2C_DHTR(base) ECREG(base + 0x04) 1247 #define IT8XXX2_I2C_TOR(base) ECREG(base + 0x05) 1248 #define IT8XXX2_I2C_DTR(base) ECREG(base + 0x08) 1249 #define IT8XXX2_I2C_CTR(base) ECREG(base + 0x09) 1250 #define IT8XXX2_I2C_CTR1(base) ECREG(base + 0x0A) 1251 #define IT8XXX2_I2C_BYTE_CNT_H(base) ECREG(base + 0x0B) 1252 #define IT8XXX2_I2C_BYTE_CNT_L(base) ECREG(base + 0x0C) 1253 #define IT8XXX2_I2C_IRQ_ST(base) ECREG(base + 0x0D) 1254 #define IT8XXX2_I2C_IDR(base) ECREG(base + 0x06) 1255 #define IT8XXX2_I2C_TOS(base) ECREG(base + 0x07) 1256 #define IT8XXX2_I2C_SLV_NUM_H(base) ECREG(base + 0x10) 1257 #define IT8XXX2_I2C_SLV_NUM_L(base) ECREG(base + 0x11) 1258 #define IT8XXX2_I2C_STR2(base) ECREG(base + 0x12) 1259 #define IT8XXX2_I2C_NST(base) ECREG(base + 0x13) 1260 #define IT8XXX2_I2C_TO_ARB_ST(base) ECREG(base + 0x18) 1261 #define IT8XXX2_I2C_ERR_ST(base) ECREG(base + 0x19) 1262 #define IT8XXX2_I2C_FST(base) ECREG(base + 0x1B) 1263 #define IT8XXX2_I2C_EM(base) ECREG(base + 0x1C) 1264 #define IT8XXX2_I2C_MODE_SEL(base) ECREG(base + 0x1D) 1265 #define IT8XXX2_I2C_IDR2(base) ECREG(base + 0x1F) 1266 #define IT8XXX2_I2C_CTR2(base) ECREG(base + 0x20) 1267 #define IT8XXX2_I2C_RAMHA(base) ECREG(base + 0x23) 1268 #define IT8XXX2_I2C_RAMLA(base) ECREG(base + 0x24) 1269 #define IT8XXX2_I2C_RAMHA2(base) ECREG(base + 0x2C) 1270 #define IT8XXX2_I2C_RAMLA2(base) ECREG(base + 0x2D) 1271 #define IT8XXX2_I2C_CMD_ADDH(base) ECREG(base + 0x25) 1272 #define IT8XXX2_I2C_CMD_ADDL(base) ECREG(base + 0x26) 1273 #define IT8XXX2_I2C_RAMH2A(base) ECREG(base + 0x50) 1274 #define IT8XXX2_I2C_CMD_ADDH2(base) ECREG(base + 0x52) 1275 1276 /* SMBus/I2C register fields */ 1277 /* 0x09-0xB: SMCLK Timing Setting */ 1278 #define IT8XXX2_SMB_SMCLKS_1M 4 1279 #define IT8XXX2_SMB_SMCLKS_400K 3 1280 #define IT8XXX2_SMB_SMCLKS_100K 2 1281 #define IT8XXX2_SMB_SMCLKS_50K 1 1282 1283 /* 0x0E: SMBus FIFO Status 1 */ 1284 #define IT8XXX2_SMB_FIFO1_EMPTY BIT(7) 1285 #define IT8XXX2_SMB_FIFO1_FULL BIT(6) 1286 /* 0x0D: SMBus FIFO Control 1 */ 1287 /* 0x0F: SMBus FIFO Control 2 */ 1288 #define IT8XXX2_SMB_BLKDS BIT(4) 1289 #define IT8XXX2_SMB_FFEN BIT(3) 1290 #define IT8XXX2_SMB_FFCHSEL2_B 0 1291 #define IT8XXX2_SMB_FFCHSEL2_C BIT(0) 1292 /* 0x10: SMBus FIFO Status 2 */ 1293 #define IT8XXX2_SMB_FIFO2_EMPTY BIT(7) 1294 #define IT8XXX2_SMB_FIFO2_FULL BIT(6) 1295 /* 0x12: I2C Wr To Rd FIFO */ 1296 #define IT8XXX2_SMB_MAIF BIT(7) 1297 #define IT8XXX2_SMB_MBCIF BIT(6) 1298 #define IT8XXX2_SMB_MCIFI BIT(2) 1299 #define IT8XXX2_SMB_MBIFI BIT(1) 1300 #define IT8XXX2_SMB_MAIFI BIT(0) 1301 /* 0x13: I2C Wr To Rd FIFO Interrupt Status */ 1302 #define IT8XXX2_SMB_MCIFID BIT(2) 1303 #define IT8XXX2_SMB_MAIFID BIT(0) 1304 /* 0x41 0x81 0xC1: Host Control */ 1305 #define IT8XXX2_SMB_SRT BIT(6) 1306 #define IT8XXX2_SMB_LABY BIT(5) 1307 #define IT8XXX2_SMB_SMCD_EXTND BIT(4) | BIT(3) | BIT(2) 1308 #define IT8XXX2_SMB_KILL BIT(1) 1309 #define IT8XXX2_SMB_INTREN BIT(0) 1310 /* 0x43 0x83 0xC3: Transmit Slave Address */ 1311 #define IT8XXX2_SMB_DIR BIT(0) 1312 /* 0x4A 0x8A 0xCA: SMBus Pin Control */ 1313 #define IT8XXX2_SMB_SMBDCS BIT(1) 1314 #define IT8XXX2_SMB_SMBCS BIT(0) 1315 /* 0x50 0x90 0xD0: Host Control 2 */ 1316 #define IT8XXX2_SMB_SMD_TO_EN BIT(4) 1317 #define IT8XXX2_SMB_I2C_SW_EN BIT(3) 1318 #define IT8XXX2_SMB_I2C_SW_WAIT BIT(2) 1319 #define IT8XXX2_SMB_I2C_EN BIT(1) 1320 #define IT8XXX2_SMB_SMHEN BIT(0) 1321 /* 0x55: Slave A FIFO Control */ 1322 #define IT8XXX2_SMB_HSAPE BIT(1) 1323 /* 0x03: Status Register */ 1324 #define IT8XXX2_I2C_BYTE_DONE BIT(7) 1325 #define IT8XXX2_I2C_RW BIT(2) 1326 #define IT8XXX2_I2C_INT_PEND BIT(1) 1327 /* 0x04: Data Hold Time */ 1328 #define IT8XXX2_I2C_SOFT_RST BIT(7) 1329 /* 0x07: Time Out Status */ 1330 #define IT8XXX2_I2C_CLK_STRETCH BIT(7) 1331 #define IT8XXX2_I2C_SCL_IN BIT(2) 1332 #define IT8XXX2_I2C_SDA_IN BIT(0) 1333 /* 0x09: Control Register */ 1334 #define IT8XXX2_I2C_INT_EN BIT(6) 1335 #define IT8XXX2_I2C_ACK BIT(3) 1336 #define IT8XXX2_I2C_HALT BIT(0) 1337 /* 0x0A: Control 1 */ 1338 #define IT8XXX2_I2C_COMQ_EN BIT(7) 1339 #define IT8XXX2_I2C_MDL_EN BIT(1) 1340 /* 0x0C: Byte count */ 1341 #define IT8XXX2_I2C_DMA_ADDR_RELOAD BIT(5) 1342 #define IT8XXX2_I2C_BYTE_CNT_ENABLE BIT(3) 1343 /* 0x0D: Interrupt Status */ 1344 #define IT8XXX2_I2C_CNT_HOLD BIT(4) 1345 #define IT8XXX2_I2C_IDW_CLR BIT(3) 1346 #define IT8XXX2_I2C_IDR_CLR BIT(2) 1347 #define IT8XXX2_I2C_SLVDATAFLG BIT(1) 1348 #define IT8XXX2_I2C_P_CLR BIT(0) 1349 /* 0x13: Nack Status */ 1350 #define IT8XXX2_I2C_NST_CNS BIT(7) 1351 #define IT8XXX2_I2C_NST_ID_NACK BIT(3) 1352 /* 0x18: Timeout and Arbiter Status */ 1353 #define IT8XXX2_I2C_SCL_TIMEOUT_EN BIT(7) 1354 #define IT8XXX2_I2C_SDA_TIMEOUT_EN BIT(6) 1355 /* 0x19: Error Status */ 1356 #define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ BIT(0) 1357 /* 0x1B: Finish Status */ 1358 #define IT8XXX2_I2C_FST_DEV1_IRQ BIT(4) 1359 /* 0x1C: Error Mask */ 1360 #define IT8XXX2_I2C_EM_DEV1_IRQ BIT(4) 1361 1362 /* 1363 * TODO: use gctrl_it8xxx2_regs instead of following register declarations 1364 * to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c. 1365 */ 1366 /* --- General Control (GCTRL) --- */ 1367 #define IT83XX_GCTRL_BASE 0x00F02000 1368 1369 #define IT83XX_GCTRL_CHIPID1 ECREG(IT83XX_GCTRL_BASE + 0x85) 1370 #define IT83XX_GCTRL_CHIPID2 ECREG(IT83XX_GCTRL_BASE + 0x86) 1371 #define IT83XX_GCTRL_CHIPVER ECREG(IT83XX_GCTRL_BASE + 0x02) 1372 #define IT83XX_GCTRL_MCCR3 ECREG(IT83XX_GCTRL_BASE + 0x20) 1373 #define IT83XX_GCTRL_SPISLVPFE BIT(6) 1374 #define IT83XX_GCTRL_EWPR0PFH(i) ECREG(IT83XX_GCTRL_BASE + 0x60 + i) 1375 #define IT83XX_GCTRL_EWPR0PFD(i) ECREG(IT83XX_GCTRL_BASE + 0xA0 + i) 1376 #define IT83XX_GCTRL_EWPR0PFEC(i) ECREG(IT83XX_GCTRL_BASE + 0xC0 + i) 1377 1378 /* 1379 * TODO: use spisc_it8xxx2_regs instead of following register declarations 1380 * to fix in cros_shi_it8xxx2.c. 1381 */ 1382 /* Serial Peripheral Interface (SPI) */ 1383 #define IT83XX_SPI_BASE 0x00F03A00 1384 1385 #define IT83XX_SPI_SPISGCR ECREG(IT83XX_SPI_BASE + 0x00) 1386 #define IT83XX_SPI_SPISCEN BIT(0) 1387 #define IT83XX_SPI_TXRXFAR ECREG(IT83XX_SPI_BASE + 0x01) 1388 #define IT83XX_SPI_CPURXF2A BIT(4) 1389 #define IT83XX_SPI_CPURXF1A BIT(3) 1390 #define IT83XX_SPI_CPUTFA BIT(1) 1391 #define IT83XX_SPI_TXFCR ECREG(IT83XX_SPI_BASE + 0x02) 1392 #define IT83XX_SPI_TXFCMR BIT(2) 1393 #define IT83XX_SPI_TXFR BIT(1) 1394 #define IT83XX_SPI_TXFS BIT(0) 1395 #define IT83XX_SPI_GCR2 ECREG(IT83XX_SPI_BASE + 0x03) 1396 #define IT83XX_SPI_RXF2OC BIT(4) 1397 #define IT83XX_SPI_RXF1OC BIT(3) 1398 #define IT83XX_SPI_RXFAR BIT(0) 1399 #define IT83XX_SPI_IMR ECREG(IT83XX_SPI_BASE + 0x04) 1400 #define IT83XX_SPI_RX_FIFO_FULL BIT(7) 1401 #define IT83XX_SPI_RX_REACH BIT(5) 1402 #define IT83XX_SPI_EDIM BIT(2) 1403 #define IT83XX_SPI_ISR ECREG(IT83XX_SPI_BASE + 0x05) 1404 #define IT83XX_SPI_TXFSR ECREG(IT83XX_SPI_BASE + 0x06) 1405 #define IT83XX_SPI_ENDDETECTINT BIT(2) 1406 #define IT83XX_SPI_RXFSR ECREG(IT83XX_SPI_BASE + 0x07) 1407 #define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) 1408 #define IT83XX_SPI_RXF2FS BIT(2) 1409 #define IT83XX_SPI_RXF1FS BIT(1) 1410 #ifdef CHIP_VARIANT_IT83202BX 1411 #define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x08) 1412 #else 1413 #define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x0b) 1414 #endif 1415 #define IT83XX_SPI_CPUWTFDB0 ECREG_u32(IT83XX_SPI_BASE + 0x08) 1416 #define IT83XX_SPI_FCR ECREG(IT83XX_SPI_BASE + 0x09) 1417 #define IT83XX_SPI_SPISRTXF BIT(2) 1418 #define IT83XX_SPI_RXFR BIT(1) 1419 #define IT83XX_SPI_RXFCMR BIT(0) 1420 #define IT83XX_SPI_RXFRDRB0 ECREG_u32(IT83XX_SPI_BASE + 0x0C) 1421 #define IT83XX_SPI_FTCB0R ECREG(IT83XX_SPI_BASE + 0x18) 1422 #define IT83XX_SPI_FTCB1R ECREG(IT83XX_SPI_BASE + 0x19) 1423 #define IT83XX_SPI_TCCB0 ECREG(IT83XX_SPI_BASE + 0x1A) 1424 #define IT83XX_SPI_TCCB1 ECREG(IT83XX_SPI_BASE + 0x1B) 1425 #define IT83XX_SPI_HPR2 ECREG(IT83XX_SPI_BASE + 0x1E) 1426 #define IT83XX_SPI_EMMCBMR ECREG(IT83XX_SPI_BASE + 0x21) 1427 #define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */ 1428 #define IT83XX_SPI_RX_VLISMR ECREG(IT83XX_SPI_BASE + 0x26) 1429 #define IT83XX_SPI_RVLIM BIT(0) 1430 #define IT83XX_SPI_RX_VLISR ECREG(IT83XX_SPI_BASE + 0x27) 1431 #define IT83XX_SPI_RVLI BIT(0) 1432 1433 /** 1434 * 1435 * (20xxh) General Control (GCTRL) registers 1436 * 1437 */ 1438 #define GCTRL_IT8XXX2_REGS_BASE \ 1439 ((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl))) 1440 1441 #ifndef __ASSEMBLER__ 1442 struct gctrl_it8xxx2_regs { 1443 /* 0x00-0x01: Reserved_00_01 */ 1444 volatile uint8_t reserved_00_01[2]; 1445 /* 0x02: Chip Version */ 1446 volatile uint8_t GCTRL_ECHIPVER; 1447 /* 0x03-0x05: Reserved_03_05 */ 1448 volatile uint8_t reserved_03_05[3]; 1449 /* 0x06: Reset Status */ 1450 volatile uint8_t GCTRL_RSTS; 1451 /* 0x07-0x09: Reserved_07_09 */ 1452 volatile uint8_t reserved_07_09[3]; 1453 /* 0x0A: Base Address Select */ 1454 volatile uint8_t GCTRL_BADRSEL; 1455 /* 0x0B: Wait Next Clock Rising */ 1456 volatile uint8_t GCTRL_WNCKR; 1457 /* 0x0C: reserved_0c */ 1458 volatile uint8_t reserved_0c; 1459 /* 0x0D: Special Control 1 */ 1460 volatile uint8_t GCTRL_SPCTRL1; 1461 /* 0x0E-0x0F: reserved_0e_0f */ 1462 volatile uint8_t reserved_0e_0f[2]; 1463 /* 0x10: Reset Control DMM */ 1464 volatile uint8_t GCTRL_RSTDMMC; 1465 /* 0x11: Reset Control 4 */ 1466 volatile uint8_t GCTRL_RSTC4; 1467 /* 0x12-0x1B: reserved_12_1b */ 1468 volatile uint8_t reserved_12_1b[10]; 1469 /* 0x1C: Special Control 4 */ 1470 volatile uint8_t GCTRL_SPCTRL4; 1471 /* 0x1D-0x1F: reserved_1d_1f */ 1472 volatile uint8_t reserved_1d_1f[3]; 1473 /* 0x20: Memory Controller Configuration 3 */ 1474 volatile uint8_t GCTRL_MCCR3; 1475 /* 0x21: Reset Control 5 */ 1476 volatile uint8_t GCTRL_RSTC5; 1477 /* 0x22-0x2F: reserved_22_2f */ 1478 volatile uint8_t reserved_22_2f[14]; 1479 /* 0x30: Memory Controller Configuration */ 1480 volatile uint8_t GCTRL_MCCR; 1481 /* 0x31: Externel ILM/DLM Size */ 1482 volatile uint8_t GCTRL_EIDSR; 1483 /* 0x32: Reserved_32 */ 1484 volatile uint8_t reserved_32; 1485 /* 0x33: Pin Multi-function Enable 2 */ 1486 volatile uint8_t gctrl_pmer2; 1487 /* 0x34-0x36: Reserved_34_36 */ 1488 volatile uint8_t reserved_34_36[3]; 1489 /* 0x37: Eflash Protect Lock */ 1490 volatile uint8_t GCTRL_EPLR; 1491 /* 0x38-0x40: Reserved_38_40 */ 1492 volatile uint8_t reserved_38_40[9]; 1493 /* 0x41: Interrupt Vector Table Base Address */ 1494 volatile uint8_t GCTRL_IVTBAR; 1495 /* 0x42-0x43: Reserved_42_43 */ 1496 volatile uint8_t reserved_42_43[2]; 1497 /* 0x44: Memory Controller Configuration 2 */ 1498 volatile uint8_t GCTRL_MCCR2; 1499 /* 0x45: Reserved_45 */ 1500 volatile uint8_t reserved_45; 1501 /* 0x46: Pin Multi-function Enable 3 */ 1502 volatile uint8_t GCTRL_PMER3; 1503 /* 0x47-0x4A: reserved_47_4a */ 1504 volatile uint8_t reserved_47_4a[4]; 1505 /* 0x4B: ETWD and UART Control */ 1506 volatile uint8_t GCTRL_ETWDUARTCR; 1507 /* 0x4C: Wakeup MCU Control */ 1508 volatile uint8_t GCTRL_WMCR; 1509 /* 0x4D-0x4F: reserved_4d_4f */ 1510 volatile uint8_t reserved_4d_4f[3]; 1511 /* 0x50: Port 80h/81h Status Register */ 1512 volatile uint8_t GCTRL_P80H81HSR; 1513 /* 0x51: Port 80h Data Register */ 1514 volatile uint8_t GCTRL_P80HDR; 1515 /* 0x52: Port 81h Data Register */ 1516 volatile uint8_t GCTRL_P81HDR; 1517 /* 0x53: H2RAM Offset Register */ 1518 volatile uint8_t GCTRL_H2ROFSR; 1519 /* 0x54-0x5C: reserved_54_5c */ 1520 volatile uint8_t reserved_54_5c[9]; 1521 /* 0x5D: RISCV ILM Configuration 0 */ 1522 volatile uint8_t GCTRL_RVILMCR0; 1523 /* 0x5E-0x84: reserved_5e_84 */ 1524 volatile uint8_t reserved_5e_84[39]; 1525 /* 0x85: Chip ID Byte 1 */ 1526 volatile uint8_t GCTRL_ECHIPID1; 1527 /* 0x86: Chip ID Byte 2 */ 1528 volatile uint8_t GCTRL_ECHIPID2; 1529 /* 0x87: Chip ID Byte 3 */ 1530 volatile uint8_t GCTRL_ECHIPID3; 1531 }; 1532 #endif /* !__ASSEMBLER__ */ 1533 1534 /* GCTRL register fields */ 1535 /* 0x06: Reset Status */ 1536 #define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0)) 1537 #define IT8XXX2_GCTRL_IWDTR BIT(1) 1538 /* 0x10: Reset Control DMM */ 1539 #define IT8XXX2_GCTRL_UART1SD BIT(3) 1540 #define IT8XXX2_GCTRL_UART2SD BIT(2) 1541 /* 0x11: Reset Control 4 */ 1542 #define IT8XXX2_GCTRL_RPECI BIT(4) 1543 #define IT8XXX2_GCTRL_RUART2 BIT(2) 1544 #define IT8XXX2_GCTRL_RUART1 BIT(1) 1545 /* 0x1C: Special Control 4 */ 1546 #define IT8XXX2_GCTRL_LRSIWR BIT(2) 1547 #define IT8XXX2_GCTRL_LRSIPWRSWTR BIT(1) 1548 #define IT8XXX2_GCTRL_LRSIPGWR BIT(0) 1549 /* 0x20: Memory Controller Configuration 3 */ 1550 #define IT8XXX2_GCTRL_SPISLVPFE BIT(6) 1551 /* 0x30: Memory Controller Configuration */ 1552 #define IT8XXX2_GCTRL_ICACHE_RESET BIT(4) 1553 /* 0x37: Eflash Protect Lock */ 1554 #define IT8XXX2_GCTRL_EPLR_ENABLE BIT(0) 1555 /* 0x46: Pin Multi-function Enable 3 */ 1556 #define IT8XXX2_GCTRL_SMB3PSEL BIT(6) 1557 /* 0x4B: ETWD and UART Control */ 1558 #define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0) 1559 /* 0x5D: RISCV ILM Configuration 0 */ 1560 #define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0) 1561 /* Accept Port 80h Cycle */ 1562 #define IT8XXX2_GCTRL_ACP80 BIT(6) 1563 /* USB Debug Enable */ 1564 #define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7) 1565 /* USB Pad Power-On Enable */ 1566 #define IT8XXX2_GCTRL_PMER2_USB_PAD_EN BIT(7) 1567 1568 /* 1569 * VCC Detector Option. 1570 * bit[7-6] = 1: The VCC power status is treated as power-on. 1571 * The VCC supply of eSPI and related functions (EC2I, KBC, PMC and 1572 * PECI). It means VCC should be logic high before using these 1573 * functions, or firmware treats VCC logic high. 1574 */ 1575 #define IT8XXX2_GCTRL_VCCDO_MASK (BIT(6) | BIT(7)) 1576 #define IT8XXX2_GCTRL_VCCDO_VCC_ON BIT(6) 1577 /* 1578 * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH 1579 * register and WRST#. 1580 */ 1581 #define IT8XXX2_GCTRL_HGRST BIT(3) 1582 /* bit[2] = 1: Enable global reset. */ 1583 #define IT8XXX2_GCTRL_GRST BIT(2) 1584 1585 /** 1586 * 1587 * (22xxh) Battery-backed SRAM (BRAM) registers 1588 * 1589 */ 1590 #ifndef __ASSEMBLER__ 1591 /* Battery backed RAM indices. */ 1592 #define BRAM_MAGIC_FIELD_OFFSET 0xbc 1593 enum bram_indices { 1594 1595 /* This field is used to indicate BRAM is valid or not. */ 1596 BRAM_IDX_VALID_FLAGS0 = BRAM_MAGIC_FIELD_OFFSET, 1597 BRAM_IDX_VALID_FLAGS1, 1598 BRAM_IDX_VALID_FLAGS2, 1599 BRAM_IDX_VALID_FLAGS3 1600 }; 1601 #endif /* !__ASSEMBLER__ */ 1602 1603 #ifndef __ASSEMBLER__ 1604 /* 1605 * EC2I bridge registers 1606 */ 1607 struct ec2i_regs { 1608 /* 0x00: Indirect Host I/O Address Register */ 1609 volatile uint8_t IHIOA; 1610 /* 0x01: Indirect Host Data Register */ 1611 volatile uint8_t IHD; 1612 /* 0x02: Lock Super I/O Host Access Register */ 1613 volatile uint8_t LSIOHA; 1614 /* 0x03: Super I/O Access Lock Violation Register */ 1615 volatile uint8_t SIOLV; 1616 /* 0x04: EC to I-Bus Modules Access Enable Register */ 1617 volatile uint8_t IBMAE; 1618 /* 0x05: I-Bus Control Register */ 1619 volatile uint8_t IBCTL; 1620 }; 1621 1622 /* Index list of the host interface registers of PNPCFG */ 1623 enum host_pnpcfg_index { 1624 /* Logical Device Number */ 1625 HOST_INDEX_LDN = 0x07, 1626 /* Chip ID Byte 1 */ 1627 HOST_INDEX_CHIPID1 = 0x20, 1628 /* Chip ID Byte 2 */ 1629 HOST_INDEX_CHIPID2 = 0x21, 1630 /* Chip Version */ 1631 HOST_INDEX_CHIPVER = 0x22, 1632 /* Super I/O Control */ 1633 HOST_INDEX_SIOCTRL = 0x23, 1634 /* Super I/O IRQ Configuration */ 1635 HOST_INDEX_SIOIRQ = 0x25, 1636 /* Super I/O General Purpose */ 1637 HOST_INDEX_SIOGP = 0x26, 1638 /* Super I/O Power Mode */ 1639 HOST_INDEX_SIOPWR = 0x2D, 1640 /* Depth 2 I/O Address */ 1641 HOST_INDEX_D2ADR = 0x2E, 1642 /* Depth 2 I/O Data */ 1643 HOST_INDEX_D2DAT = 0x2F, 1644 /* Logical Device Activate Register */ 1645 HOST_INDEX_LDA = 0x30, 1646 /* I/O Port Base Address Bits [15:8] for Descriptor 0 */ 1647 HOST_INDEX_IOBAD0_MSB = 0x60, 1648 /* I/O Port Base Address Bits [7:0] for Descriptor 0 */ 1649 HOST_INDEX_IOBAD0_LSB = 0x61, 1650 /* I/O Port Base Address Bits [15:8] for Descriptor 1 */ 1651 HOST_INDEX_IOBAD1_MSB = 0x62, 1652 /* I/O Port Base Address Bits [7:0] for Descriptor 1 */ 1653 HOST_INDEX_IOBAD1_LSB = 0x63, 1654 /* Interrupt Request Number and Wake-Up on IRQ Enabled */ 1655 HOST_INDEX_IRQNUMX = 0x70, 1656 /* Interrupt Request Type Select */ 1657 HOST_INDEX_IRQTP = 0x71, 1658 /* DMA Channel Select 0 */ 1659 HOST_INDEX_DMAS0 = 0x74, 1660 /* DMA Channel Select 1 */ 1661 HOST_INDEX_DMAS1 = 0x75, 1662 /* Device Specific Logical Device Configuration 1 to 10 */ 1663 HOST_INDEX_DSLDC1 = 0xF0, 1664 HOST_INDEX_DSLDC2 = 0xF1, 1665 HOST_INDEX_DSLDC3 = 0xF2, 1666 HOST_INDEX_DSLDC4 = 0xF3, 1667 HOST_INDEX_DSLDC5 = 0xF4, 1668 HOST_INDEX_DSLDC6 = 0xF5, 1669 HOST_INDEX_DSLDC7 = 0xF6, 1670 HOST_INDEX_DSLDC8 = 0xF7, 1671 HOST_INDEX_DSLDC9 = 0xF8, 1672 HOST_INDEX_DSLDC10 = 0xF9, 1673 }; 1674 1675 /* List of logical device number (LDN) assignments */ 1676 enum logical_device_number { 1677 /* Serial Port 1 */ 1678 LDN_UART1 = 0x01, 1679 /* Serial Port 2 */ 1680 LDN_UART2 = 0x02, 1681 /* System Wake-Up Control */ 1682 LDN_SWUC = 0x04, 1683 /* KBC/Mouse Interface */ 1684 LDN_KBC_MOUSE = 0x05, 1685 /* KBC/Keyboard Interface */ 1686 LDN_KBC_KEYBOARD = 0x06, 1687 /* Consumer IR */ 1688 LDN_CIR = 0x0A, 1689 /* Shared Memory/Flash Interface */ 1690 LDN_SMFI = 0x0F, 1691 /* RTC-like Timer */ 1692 LDN_RTCT = 0x10, 1693 /* Power Management I/F Channel 1 */ 1694 LDN_PMC1 = 0x11, 1695 /* Power Management I/F Channel 2 */ 1696 LDN_PMC2 = 0x12, 1697 /* Serial Peripheral Interface */ 1698 LDN_SSPI = 0x13, 1699 /* Platform Environment Control Interface */ 1700 LDN_PECI = 0x14, 1701 /* Power Management I/F Channel 3 */ 1702 LDN_PMC3 = 0x17, 1703 /* Power Management I/F Channel 4 */ 1704 LDN_PMC4 = 0x18, 1705 /* Power Management I/F Channel 5 */ 1706 LDN_PMC5 = 0x19, 1707 }; 1708 1709 /* Structure for initializing PNPCFG via ec2i. */ 1710 struct ec2i_t { 1711 /* index port */ 1712 enum host_pnpcfg_index index_port; 1713 /* data port */ 1714 uint8_t data_port; 1715 }; 1716 1717 /* EC2I access index/data port */ 1718 enum ec2i_access { 1719 /* index port */ 1720 EC2I_ACCESS_INDEX = 0, 1721 /* data port */ 1722 EC2I_ACCESS_DATA = 1, 1723 }; 1724 1725 /* EC to I-Bus Access Enabled */ 1726 #define EC2I_IBCTL_CSAE BIT(0) 1727 /* EC Read from I-Bus */ 1728 #define EC2I_IBCTL_CRIB BIT(1) 1729 /* EC Write to I-Bus */ 1730 #define EC2I_IBCTL_CWIB BIT(2) 1731 #define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB) 1732 1733 /* PNPCFG Register EC Access Enable */ 1734 #define EC2I_IBMAE_CFGAE BIT(0) 1735 1736 /* 1737 * KBC registers 1738 */ 1739 struct kbc_regs { 1740 /* 0x00: KBC Host Interface Control Register */ 1741 volatile uint8_t KBHICR; 1742 /* 0x01: Reserved1 */ 1743 volatile uint8_t reserved1; 1744 /* 0x02: KBC Interrupt Control Register */ 1745 volatile uint8_t KBIRQR; 1746 /* 0x03: Reserved2 */ 1747 volatile uint8_t reserved2; 1748 /* 0x04: KBC Host Interface Keyboard/Mouse Status Register */ 1749 volatile uint8_t KBHISR; 1750 /* 0x05: Reserved3 */ 1751 volatile uint8_t reserved3; 1752 /* 0x06: KBC Host Interface Keyboard Data Output Register */ 1753 volatile uint8_t KBHIKDOR; 1754 /* 0x07: Reserved4 */ 1755 volatile uint8_t reserved4; 1756 /* 0x08: KBC Host Interface Mouse Data Output Register */ 1757 volatile uint8_t KBHIMDOR; 1758 /* 0x09: Reserved5 */ 1759 volatile uint8_t reserved5; 1760 /* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */ 1761 volatile uint8_t KBHIDIR; 1762 }; 1763 1764 /* Output Buffer Full */ 1765 #define KBC_KBHISR_OBF BIT(0) 1766 /* Input Buffer Full */ 1767 #define KBC_KBHISR_IBF BIT(1) 1768 /* A2 Address (A2) */ 1769 #define KBC_KBHISR_A2_ADDR BIT(3) 1770 #define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF \ 1771 | KBC_KBHISR_A2_ADDR) 1772 1773 /* Clear Output Buffer Full */ 1774 #define KBC_KBHICR_COBF BIT(6) 1775 /* IBF/OBF Clear Mode Enable */ 1776 #define KBC_KBHICR_IBFOBFCME BIT(5) 1777 /* Input Buffer Full CPU Interrupt Enable */ 1778 #define KBC_KBHICR_IBFCIE BIT(3) 1779 /* Output Buffer Empty CPU Interrupt Enable */ 1780 #define KBC_KBHICR_OBECIE BIT(2) 1781 /* Output Buffer Full Mouse Interrupt Enable */ 1782 #define KBC_KBHICR_OBFMIE BIT(1) 1783 /* Output Buffer Full Keyboard Interrupt Enable */ 1784 #define KBC_KBHICR_OBFKIE BIT(0) 1785 1786 /* 1787 * PMC registers 1788 */ 1789 struct pmc_regs { 1790 /* 0x00: Host Interface PM Channel 1 Status */ 1791 volatile uint8_t PM1STS; 1792 /* 0x01: Host Interface PM Channel 1 Data Out Port */ 1793 volatile uint8_t PM1DO; 1794 /* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */ 1795 volatile uint8_t PM1DOSCI; 1796 /* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */ 1797 volatile uint8_t PM1DOSMI; 1798 /* 0x04: Host Interface PM Channel 1 Data In Port */ 1799 volatile uint8_t PM1DI; 1800 /* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */ 1801 volatile uint8_t PM1DISCI; 1802 /* 0x06: Host Interface PM Channel 1 Control */ 1803 volatile uint8_t PM1CTL; 1804 /* 0x07: Host Interface PM Channel 1 Interrupt Control */ 1805 volatile uint8_t PM1IC; 1806 /* 0x08: Host Interface PM Channel 1 Interrupt Enable */ 1807 volatile uint8_t PM1IE; 1808 /* 0x09-0x0f: Reserved1 */ 1809 volatile uint8_t reserved1[7]; 1810 /* 0x10: Host Interface PM Channel 2 Status */ 1811 volatile uint8_t PM2STS; 1812 /* 0x11: Host Interface PM Channel 2 Data Out Port */ 1813 volatile uint8_t PM2DO; 1814 /* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */ 1815 volatile uint8_t PM2DOSCI; 1816 /* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */ 1817 volatile uint8_t PM2DOSMI; 1818 /* 0x14: Host Interface PM Channel 2 Data In Port */ 1819 volatile uint8_t PM2DI; 1820 /* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */ 1821 volatile uint8_t PM2DISCI; 1822 /* 0x16: Host Interface PM Channel 2 Control */ 1823 volatile uint8_t PM2CTL; 1824 /* 0x17: Host Interface PM Channel 2 Interrupt Control */ 1825 volatile uint8_t PM2IC; 1826 /* 0x18: Host Interface PM Channel 2 Interrupt Enable */ 1827 volatile uint8_t PM2IE; 1828 /* 0x19: Mailbox Control */ 1829 volatile uint8_t MBXCTRL; 1830 /* 0x1a-0x1f: Reserved2 */ 1831 volatile uint8_t reserved2[6]; 1832 /* 0x20-0xff: Reserved3 */ 1833 volatile uint8_t reserved3[0xe0]; 1834 }; 1835 1836 /* Input Buffer Full Interrupt Enable */ 1837 #define PMC_PM1CTL_IBFIE BIT(0) 1838 /* Output Buffer Full */ 1839 #define PMC_PM1STS_OBF BIT(0) 1840 /* Input Buffer Full */ 1841 #define PMC_PM1STS_IBF BIT(1) 1842 /* General Purpose Flag */ 1843 #define PMC_PM1STS_GPF BIT(2) 1844 /* A2 Address (A2) */ 1845 #define PMC_PM1STS_A2_ADDR BIT(3) 1846 1847 /* PMC2 Input Buffer Full Interrupt Enable */ 1848 #define PMC_PM2CTL_IBFIE BIT(0) 1849 /* General Purpose Flag */ 1850 #define PMC_PM2STS_GPF BIT(2) 1851 1852 /* 1853 * Dedicated Interrupt 1854 * 0b: 1855 * INT3: PMC Output Buffer Empty Int 1856 * INT25: PMC Input Buffer Full Int 1857 * 1b: 1858 * INT3: PMC1 Output Buffer Empty Int 1859 * INT25: PMC1 Input Buffer Full Int 1860 * INT26: PMC2 Output Buffer Empty Int 1861 * INT27: PMC2 Input Buffer Full Int 1862 */ 1863 #define PMC_MBXCTRL_DINT BIT(5) 1864 1865 /* 1866 * eSPI slave registers 1867 */ 1868 struct espi_slave_regs { 1869 /* 0x00-0x03: Reserved1 */ 1870 volatile uint8_t reserved1[4]; 1871 1872 /* 0x04: General Capabilities and Configuration 0 */ 1873 volatile uint8_t GCAPCFG0; 1874 /* 0x05: General Capabilities and Configuration 1 */ 1875 volatile uint8_t GCAPCFG1; 1876 /* 0x06: General Capabilities and Configuration 2 */ 1877 volatile uint8_t GCAPCFG2; 1878 /* 0x07: General Capabilities and Configuration 3 */ 1879 volatile uint8_t GCAPCFG3; 1880 1881 /* Channel 0 (Peripheral Channel) Capabilities and Configurations */ 1882 /* 0x08: Channel 0 Capabilities and Configuration 0 */ 1883 volatile uint8_t CH_PC_CAPCFG0; 1884 /* 0x09: Channel 0 Capabilities and Configuration 1 */ 1885 volatile uint8_t CH_PC_CAPCFG1; 1886 /* 0x0A: Channel 0 Capabilities and Configuration 2 */ 1887 volatile uint8_t CH_PC_CAPCFG2; 1888 /* 0x0B: Channel 0 Capabilities and Configuration 3 */ 1889 volatile uint8_t CH_PC_CAPCFG3; 1890 1891 /* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */ 1892 /* 0x0C: Channel 1 Capabilities and Configuration 0 */ 1893 volatile uint8_t CH_VW_CAPCFG0; 1894 /* 0x0D: Channel 1 Capabilities and Configuration 1 */ 1895 volatile uint8_t CH_VW_CAPCFG1; 1896 /* 0x0E: Channel 1 Capabilities and Configuration 2 */ 1897 volatile uint8_t CH_VW_CAPCFG2; 1898 /* 0x0F: Channel 1 Capabilities and Configuration 3 */ 1899 volatile uint8_t CH_VW_CAPCFG3; 1900 1901 /* Channel 2 (OOB Message Channel) Capabilities and Configurations */ 1902 /* 0x10: Channel 2 Capabilities and Configuration 0 */ 1903 volatile uint8_t CH_OOB_CAPCFG0; 1904 /* 0x11: Channel 2 Capabilities and Configuration 1 */ 1905 volatile uint8_t CH_OOB_CAPCFG1; 1906 /* 0x12: Channel 2 Capabilities and Configuration 2 */ 1907 volatile uint8_t CH_OOB_CAPCFG2; 1908 /* 0x13: Channel 2 Capabilities and Configuration 3 */ 1909 volatile uint8_t CH_OOB_CAPCFG3; 1910 1911 /* Channel 3 (Flash Access Channel) Capabilities and Configurations */ 1912 /* 0x14: Channel 3 Capabilities and Configuration 0 */ 1913 volatile uint8_t CH_FLASH_CAPCFG0; 1914 /* 0x15: Channel 3 Capabilities and Configuration 1 */ 1915 volatile uint8_t CH_FLASH_CAPCFG1; 1916 /* 0x16: Channel 3 Capabilities and Configuration 2 */ 1917 volatile uint8_t CH_FLASH_CAPCFG2; 1918 /* 0x17: Channel 3 Capabilities and Configuration 3 */ 1919 volatile uint8_t CH_FLASH_CAPCFG3; 1920 /* Channel 3 Capabilities and Configurations 2 */ 1921 /* 0x18: Channel 3 Capabilities and Configuration 2-0 */ 1922 volatile uint8_t CH_FLASH_CAPCFG2_0; 1923 /* 0x19: Channel 3 Capabilities and Configuration 2-1 */ 1924 volatile uint8_t CH_FLASH_CAPCFG2_1; 1925 /* 0x1A: Channel 3 Capabilities and Configuration 2-2 */ 1926 volatile uint8_t CH_FLASH_CAPCFG2_2; 1927 /* 0x1B: Channel 3 Capabilities and Configuration 2-3 */ 1928 volatile uint8_t CH_FLASH_CAPCFG2_3; 1929 1930 /* 0x1c-0x1f: Reserved2 */ 1931 volatile uint8_t reserved2[4]; 1932 /* 0x20-0x8f: Reserved3 */ 1933 volatile uint8_t reserved3[0x70]; 1934 1935 /* 0x90: eSPI PC Control 0 */ 1936 volatile uint8_t ESPCTRL0; 1937 /* 0x91: eSPI PC Control 1 */ 1938 volatile uint8_t ESPCTRL1; 1939 /* 0x92: eSPI PC Control 2 */ 1940 volatile uint8_t ESPCTRL2; 1941 /* 0x93: eSPI PC Control 3 */ 1942 volatile uint8_t ESPCTRL3; 1943 /* 0x94: eSPI PC Control 4 */ 1944 volatile uint8_t ESPCTRL4; 1945 /* 0x95: eSPI PC Control 5 */ 1946 volatile uint8_t ESPCTRL5; 1947 /* 0x96: eSPI PC Control 6 */ 1948 volatile uint8_t ESPCTRL6; 1949 /* 0x97: eSPI PC Control 7 */ 1950 volatile uint8_t ESPCTRL7; 1951 /* 0x98-0x9f: Reserved4 */ 1952 volatile uint8_t reserved4[8]; 1953 1954 /* 0xa0: eSPI General Control 0 */ 1955 volatile uint8_t ESGCTRL0; 1956 /* 0xa1: eSPI General Control 1 */ 1957 volatile uint8_t ESGCTRL1; 1958 /* 0xa2: eSPI General Control 2 */ 1959 volatile uint8_t ESGCTRL2; 1960 /* 0xa3: eSPI General Control 3 */ 1961 volatile uint8_t ESGCTRL3; 1962 /* 0xa4-0xaf: Reserved5 */ 1963 volatile uint8_t reserved5[12]; 1964 1965 /* 0xb0: eSPI Upstream Control 0 */ 1966 volatile uint8_t ESUCTRL0; 1967 /* 0xb1: eSPI Upstream Control 1 */ 1968 volatile uint8_t ESUCTRL1; 1969 /* 0xb2: eSPI Upstream Control 2 */ 1970 volatile uint8_t ESUCTRL2; 1971 /* 0xb3: eSPI Upstream Control 3 */ 1972 volatile uint8_t ESUCTRL3; 1973 /* 0xb4-0xb5: Reserved6 */ 1974 volatile uint8_t reserved6[2]; 1975 /* 0xb6: eSPI Upstream Control 6 */ 1976 volatile uint8_t ESUCTRL6; 1977 /* 0xb7: eSPI Upstream Control 7 */ 1978 volatile uint8_t ESUCTRL7; 1979 /* 0xb8: eSPI Upstream Control 8 */ 1980 volatile uint8_t ESUCTRL8; 1981 /* 0xb9-0xbf: Reserved7 */ 1982 volatile uint8_t reserved7[7]; 1983 1984 /* 0xc0: eSPI OOB Control 0 */ 1985 volatile uint8_t ESOCTRL0; 1986 /* 0xc1: eSPI OOB Control 1 */ 1987 volatile uint8_t ESOCTRL1; 1988 /* 0xc2-0xc3: Reserved8 */ 1989 volatile uint8_t reserved8[2]; 1990 /* 0xc4: eSPI OOB Control 4 */ 1991 volatile uint8_t ESOCTRL4; 1992 /* 0xc5-0xcf: Reserved9 */ 1993 volatile uint8_t reserved9[11]; 1994 1995 /* 0xd0: eSPI SAFS Control 0 */ 1996 volatile uint8_t ESPISAFSC0; 1997 /* 0xd1: eSPI SAFS Control 1 */ 1998 volatile uint8_t ESPISAFSC1; 1999 /* 0xd2: eSPI SAFS Control 2 */ 2000 volatile uint8_t ESPISAFSC2; 2001 /* 0xd3: eSPI SAFS Control 3 */ 2002 volatile uint8_t ESPISAFSC3; 2003 /* 0xd4: eSPI SAFS Control 4 */ 2004 volatile uint8_t ESPISAFSC4; 2005 /* 0xd5: eSPI SAFS Control 5 */ 2006 volatile uint8_t ESPISAFSC5; 2007 /* 0xd6: eSPI SAFS Control 6 */ 2008 volatile uint8_t ESPISAFSC6; 2009 /* 0xd7: eSPI SAFS Control 7 */ 2010 volatile uint8_t ESPISAFSC7; 2011 }; 2012 2013 /* 2014 * eSPI VW registers 2015 */ 2016 struct espi_vw_regs { 2017 /* 0x00-0x7f: VW index */ 2018 volatile uint8_t VW_INDEX[0x80]; 2019 /* 0x80-0x8f: Reserved1 */ 2020 volatile uint8_t reserved1[0x10]; 2021 /* 0x90: VW Contrl 0 */ 2022 volatile uint8_t VWCTRL0; 2023 /* 0x91: VW Contrl 1 */ 2024 volatile uint8_t VWCTRL1; 2025 /* 0x92: VW Contrl 2 */ 2026 volatile uint8_t VWCTRL2; 2027 /* 0x93: VW Contrl 3 */ 2028 volatile uint8_t VWCTRL3; 2029 /* 0x94: Reserved2 */ 2030 volatile uint8_t reserved2; 2031 /* 0x95: VW Contrl 5 */ 2032 volatile uint8_t VWCTRL5; 2033 /* 0x96: VW Contrl 6 */ 2034 volatile uint8_t VWCTRL6; 2035 /* 0x97: VW Contrl 7 */ 2036 volatile uint8_t VWCTRL7; 2037 /* 0x98-0x99: Reserved3 */ 2038 volatile uint8_t reserved3[2]; 2039 }; 2040 2041 #define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80 2042 /* 2043 * eSPI Queue 0 registers 2044 */ 2045 struct espi_queue0_regs { 2046 /* 0x00-0x3f: PUT_PC Data Byte 0-63 */ 2047 volatile uint8_t PUT_PC_DATA[0x40]; 2048 /* 0x40-0x7f: Reserved1 */ 2049 volatile uint8_t reserved1[0x40]; 2050 /* 0x80-0xcf: PUT_OOB Data Byte 0-79 */ 2051 volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE]; 2052 }; 2053 2054 /* 2055 * eSPI Queue 1 registers 2056 */ 2057 struct espi_queue1_regs { 2058 /* 0x00-0x4f: Upstream Data Byte 0-79 */ 2059 volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE]; 2060 /* 0x50-0x7f: Reserved1 */ 2061 volatile uint8_t reserved1[0x30]; 2062 /* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */ 2063 volatile uint8_t PUT_FLASH_NP_DATA[0x40]; 2064 }; 2065 2066 #endif /* !__ASSEMBLER__ */ 2067 2068 2069 /** 2070 * 2071 * (3Axxh) SPI Slave Controller (SPISC) registers 2072 * 2073 */ 2074 #ifndef __ASSEMBLER__ 2075 struct spisc_it8xxx2_regs { 2076 /* 0x00: SPI Slave General Control */ 2077 volatile uint8_t SPISC_SPISGCR; 2078 /* 0x01: Tx/Rx FIFO Access */ 2079 volatile uint8_t SPISC_TXRXFAR; 2080 /* 0x02: Tx FIFO Control */ 2081 volatile uint8_t SPISC_TXFCR; 2082 /* 0x03: SPI Slave General Control 2 */ 2083 volatile uint8_t SPISC_SPISGCR2; 2084 /* 0x04: Interrupt Mask */ 2085 volatile uint8_t SPISC_IMR; 2086 /* 0x05: Interrupt Status */ 2087 volatile uint8_t SPISC_ISR; 2088 /* 0x06: Tx FIFO Status */ 2089 volatile uint8_t SPISC_TXFSR; 2090 /* 0x07: Rx FIFO Status */ 2091 volatile uint8_t SPISC_RXFSR; 2092 /* 0x08: CPU Write Tx FIFO Data Byte0 */ 2093 volatile uint8_t SPISC_CPUWTXFDB0R; 2094 /* 0x09: FIFO Control / CPU Write Tx FIFO Data Byte1 */ 2095 volatile uint8_t SPISC_FCR; 2096 /* 0x0A: CPU Write Tx FIFO Data Byte2 */ 2097 volatile uint8_t SPISC_CPUWTXFDB2R; 2098 /* 0x0B: SPI Slave Response Data / CPU Write Tx FIFO Data Byte3 */ 2099 volatile uint8_t SPISC_SPISRDR; 2100 /* 0x0C: Rx FIFO Readout Data Byte0 */ 2101 volatile uint8_t SPISC_RXFRDRB0; 2102 /* 0x0D: Rx FIFO Readout Data Byte1 */ 2103 volatile uint8_t SPISC_RXFRDRB1; 2104 /* 0x0E: Rx FIFO Readout Data Byte2 */ 2105 volatile uint8_t SPISC_RXFRDRB2; 2106 /* 0x0F: Rx FIFO Readout Data Byte3 */ 2107 volatile uint8_t SPISC_RXFRDRB3; 2108 /* 0x10-0x17: Reserved1 */ 2109 volatile uint8_t reserved1[8]; 2110 /* 0x18: FIFO Target Count Byte0 */ 2111 volatile uint8_t SPISC_FTCB0R; 2112 /* 0x19: FIFO Target Count Byte1 */ 2113 volatile uint8_t SPISC_FTCB1R; 2114 /* 0x1A: Target Count Capture Byte0 */ 2115 volatile uint8_t SPISC_TCCB0; 2116 /* 0x1B: Target Count Capture Byte1 */ 2117 volatile uint8_t SPISC_TCCB1; 2118 /* 0x1C-0x1D: Reserved2 */ 2119 volatile uint8_t reserved2[2]; 2120 /* 0x1E: Hardware Parsing 2 */ 2121 volatile uint8_t SPISC_HPR2; 2122 /* 0x1F-0x25: Reserved3 */ 2123 volatile uint8_t reserved3[7]; 2124 /* 0x26: Rx Valid Length Interrupt Status Mask */ 2125 volatile uint8_t SPISC_RXVLISMR; 2126 /* 0x27: Rx Valid Length Interrupt Status */ 2127 volatile uint8_t SPISC_RXVLISR; 2128 }; 2129 #endif /* !__ASSEMBLER__ */ 2130 2131 /* SPISC register fields */ 2132 /* 0x00: SPI Slave General Control */ 2133 #define IT8XXX2_SPISC_SPISCEN BIT(0) 2134 /* 0x01: Tx/Rx FIFO Access */ 2135 #define IT8XXX2_SPISC_CPURXF1A BIT(3) 2136 #define IT8XXX2_SPISC_CPUTFA BIT(1) 2137 /* 0x02: Tx FIFO Control */ 2138 #define IT8XXX2_SPISC_TXFCMR BIT(2) 2139 #define IT8XXX2_SPISC_TXFR BIT(1) 2140 #define IT8XXX2_SPISC_TXFS BIT(0) 2141 /* 0x03: SPI Slave General Control 2 */ 2142 #define IT8XXX2_SPISC_RXF2OC BIT(4) 2143 #define IT8XXX2_SPISC_RXF1OC BIT(3) 2144 #define IT8XXX2_SPISC_RXFAR BIT(0) 2145 /* 0x04: Interrupt Mask */ 2146 #define IT8XXX2_SPISC_EDIM BIT(2) 2147 /* 0x06: Tx FIFO Status */ 2148 #define IT8XXX2_SPISC_ENDDETECTINT BIT(2) 2149 /* 0x09: FIFO Control */ 2150 #define IT8XXX2_SPISC_SPISRTXF BIT(2) 2151 #define IT8XXX2_SPISC_RXFR BIT(1) 2152 #define IT8XXX2_SPISC_RXFCMR BIT(0) 2153 /* 0x26: Rx Valid Length Interrupt Status Mask */ 2154 #define IT8XXX2_SPISC_RVLIM BIT(0) 2155 /* 0x27: Rx Valid Length Interrupt Status */ 2156 #define IT8XXX2_SPISC_RVLI BIT(0) 2157 2158 #endif /* CHIP_CHIPREGS_H */ 2159
