1 /*
2  * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef CHIP_CHIPREGS_H
7 #define CHIP_CHIPREGS_H
8 
9 #include <zephyr/sys/util.h>
10 
11 #define EC_REG_BASE_ADDR 0x00f00000
12 
13 #ifdef _ASMLANGUAGE
14 #define ECREG(x)        x
15 #else
16 
17 /*
18  * Macros for hardware registers access.
19  */
20 #define ECREG(x)		(*((volatile unsigned char *)(x)))
21 #define ECREG_u16(x)		(*((volatile unsigned short *)(x)))
22 #define ECREG_u32(x)		(*((volatile unsigned long  *)(x)))
23 
24 /*
25  * MASK operation macros
26  */
27 #define SET_MASK(reg, bit_mask)			((reg) |= (bit_mask))
28 #define CLEAR_MASK(reg, bit_mask)		((reg) &= (~(bit_mask)))
29 #define IS_MASK_SET(reg, bit_mask)		(((reg) & (bit_mask)) != 0)
30 #endif /* _ASMLANGUAGE */
31 
32 #ifndef REG_BASE_ADDR
33 #define REG_BASE_ADDR				EC_REG_BASE_ADDR
34 #endif
35 
36 /* Common definition */
37 /*
38  * EC clock frequency (PWM and tachometer driver need it to reply
39  * to api or calculate RPM)
40  */
41 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
42 #define EC_FREQ			MHZ(24)
43 #else
44 #define EC_FREQ			MHZ(8)
45 
46 #endif
47 
48 /* --- General Control (GCTRL) --- */
49 #define IT8XXX2_GCTRL_BASE      0x00F02000
50 #define IT8XXX2_GCTRL_EIDSR     ECREG(IT8XXX2_GCTRL_BASE + 0x31)
51 #define IT8XXX2_GCTRL_PMER3     ECREG(IT8XXX2_GCTRL_BASE + 0x46)
52 /* RISC-V JTAG Debug Interface Enable */
53 #define IT8XXX2_GCTRL_JTAGEN    BIT(1)
54 /* RISC-V JTAG Debug Interface Selection */
55 #define IT8XXX2_GCTRL_JTAGSEL   BIT(0)
56 #define IT8XXX2_GCTRL_JTAG      (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL)
57 
58 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
59 #define IT8XXX2_JTAG_PINS_BASE  ECREG(0xF01660)
60 #define IT8XXX2_JTAG_VOLT_SET   ECREG(0xF01648)
61 #elif CONFIG_SOC_IT8XXX2_REG_SET_V1
62 #define IT8XXX2_JTAG_PINS_BASE  ECREG(0xF01610)
63 #define IT8XXX2_JTAG_VOLT_SET   ECREG(0xF016e9)
64 #endif
65 
66 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
67 /* --- External GPIO Control (EGPIO) --- */
68 #define IT8XXX2_EGPIO_BASE      0x00F02100
69 #define IT8XXX2_EGPIO_EGCR      ECREG(IT8XXX2_EGPIO_BASE + 0x04)
70 
71 /* EGPIO register fields */
72 /*
73  * 0x04: External GPIO Control
74  * BIT(4): EXGPIO EGAD Pin Output Driving Disable
75  */
76 #define IT8XXX2_EGPIO_EEPODD    BIT(4)
77 #endif
78 
79 /**
80  *
81  * (11xxh) Interrupt controller (INTC)
82  *
83  */
84 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
85 #define ISR0			ECREG(EC_REG_BASE_ADDR + 0x3F00)
86 #define ISR1			ECREG(EC_REG_BASE_ADDR + 0x3F01)
87 #define ISR2			ECREG(EC_REG_BASE_ADDR + 0x3F02)
88 #define ISR3			ECREG(EC_REG_BASE_ADDR + 0x3F03)
89 #define ISR4			ECREG(EC_REG_BASE_ADDR + 0x3F14)
90 #define ISR5			ECREG(EC_REG_BASE_ADDR + 0x3F18)
91 #define ISR6			ECREG(EC_REG_BASE_ADDR + 0x3F1C)
92 #define ISR7			ECREG(EC_REG_BASE_ADDR + 0x3F20)
93 #define ISR8			ECREG(EC_REG_BASE_ADDR + 0x3F24)
94 #define ISR9			ECREG(EC_REG_BASE_ADDR + 0x3F28)
95 #define ISR10			ECREG(EC_REG_BASE_ADDR + 0x3F2C)
96 #define ISR11			ECREG(EC_REG_BASE_ADDR + 0x3F30)
97 #define ISR12			ECREG(EC_REG_BASE_ADDR + 0x3F34)
98 #define ISR13			ECREG(EC_REG_BASE_ADDR + 0x3F38)
99 #define ISR14			ECREG(EC_REG_BASE_ADDR + 0x3F3C)
100 #define ISR15			ECREG(EC_REG_BASE_ADDR + 0x3F40)
101 #define ISR16			ECREG(EC_REG_BASE_ADDR + 0x3F44)
102 #define ISR17			ECREG(EC_REG_BASE_ADDR + 0x3F48)
103 #define ISR18			ECREG(EC_REG_BASE_ADDR + 0x3F4C)
104 #define ISR19			ECREG(EC_REG_BASE_ADDR + 0x3F50)
105 #define ISR20			ECREG(EC_REG_BASE_ADDR + 0x3F54)
106 #define ISR21			ECREG(EC_REG_BASE_ADDR + 0x3F58)
107 #define ISR22			ECREG(EC_REG_BASE_ADDR + 0x3F5C)
108 #define ISR23			ECREG(EC_REG_BASE_ADDR + 0x3F90)
109 
110 #define IER0			ECREG(EC_REG_BASE_ADDR + 0x3F04)
111 #define IER1			ECREG(EC_REG_BASE_ADDR + 0x3F05)
112 #define IER2			ECREG(EC_REG_BASE_ADDR + 0x3F06)
113 #define IER3			ECREG(EC_REG_BASE_ADDR + 0x3F07)
114 #define IER4			ECREG(EC_REG_BASE_ADDR + 0x3F15)
115 #define IER5			ECREG(EC_REG_BASE_ADDR + 0x3F19)
116 #define IER6			ECREG(EC_REG_BASE_ADDR + 0x3F1D)
117 #define IER7			ECREG(EC_REG_BASE_ADDR + 0x3F21)
118 #define IER8			ECREG(EC_REG_BASE_ADDR + 0x3F25)
119 #define IER9			ECREG(EC_REG_BASE_ADDR + 0x3F29)
120 #define IER10			ECREG(EC_REG_BASE_ADDR + 0x3F2D)
121 #define IER11			ECREG(EC_REG_BASE_ADDR + 0x3F31)
122 #define IER12			ECREG(EC_REG_BASE_ADDR + 0x3F35)
123 #define IER13			ECREG(EC_REG_BASE_ADDR + 0x3F39)
124 #define IER14			ECREG(EC_REG_BASE_ADDR + 0x3F3D)
125 #define IER15			ECREG(EC_REG_BASE_ADDR + 0x3F41)
126 #define IER16			ECREG(EC_REG_BASE_ADDR + 0x3F45)
127 #define IER17			ECREG(EC_REG_BASE_ADDR + 0x3F49)
128 #define IER18			ECREG(EC_REG_BASE_ADDR + 0x3F4D)
129 #define IER19			ECREG(EC_REG_BASE_ADDR + 0x3F51)
130 #define IER20			ECREG(EC_REG_BASE_ADDR + 0x3F55)
131 #define IER21			ECREG(EC_REG_BASE_ADDR + 0x3F59)
132 #define IER22			ECREG(EC_REG_BASE_ADDR + 0x3F5D)
133 #define IER23			ECREG(EC_REG_BASE_ADDR + 0x3F91)
134 
135 #define IELMR0			ECREG(EC_REG_BASE_ADDR + 0x3F08)
136 #define IELMR1			ECREG(EC_REG_BASE_ADDR + 0x3F09)
137 #define IELMR2			ECREG(EC_REG_BASE_ADDR + 0x3F0A)
138 #define IELMR3			ECREG(EC_REG_BASE_ADDR + 0x3F0B)
139 #define IELMR4			ECREG(EC_REG_BASE_ADDR + 0x3F16)
140 #define IELMR5			ECREG(EC_REG_BASE_ADDR + 0x3F1A)
141 #define IELMR6			ECREG(EC_REG_BASE_ADDR + 0x3F1E)
142 #define IELMR7			ECREG(EC_REG_BASE_ADDR + 0x3F22)
143 #define IELMR8			ECREG(EC_REG_BASE_ADDR + 0x3F26)
144 #define IELMR9			ECREG(EC_REG_BASE_ADDR + 0x3F2A)
145 #define IELMR10			ECREG(EC_REG_BASE_ADDR + 0x3F2E)
146 #define IELMR11			ECREG(EC_REG_BASE_ADDR + 0x3F32)
147 #define IELMR12			ECREG(EC_REG_BASE_ADDR + 0x3F36)
148 #define IELMR13			ECREG(EC_REG_BASE_ADDR + 0x3F3A)
149 #define IELMR14			ECREG(EC_REG_BASE_ADDR + 0x3F3E)
150 #define IELMR15			ECREG(EC_REG_BASE_ADDR + 0x3F42)
151 #define IELMR16			ECREG(EC_REG_BASE_ADDR + 0x3F46)
152 #define IELMR17			ECREG(EC_REG_BASE_ADDR + 0x3F4A)
153 #define IELMR18			ECREG(EC_REG_BASE_ADDR + 0x3F4E)
154 #define IELMR19			ECREG(EC_REG_BASE_ADDR + 0x3F52)
155 #define IELMR20			ECREG(EC_REG_BASE_ADDR + 0x3F56)
156 #define IELMR21			ECREG(EC_REG_BASE_ADDR + 0x3F5A)
157 #define IELMR22			ECREG(EC_REG_BASE_ADDR + 0x3F5E)
158 #define IELMR23			ECREG(EC_REG_BASE_ADDR + 0x3F92)
159 
160 #define IPOLR0			ECREG(EC_REG_BASE_ADDR + 0x3F0C)
161 #define IPOLR1			ECREG(EC_REG_BASE_ADDR + 0x3F0D)
162 #define IPOLR2			ECREG(EC_REG_BASE_ADDR + 0x3F0E)
163 #define IPOLR3			ECREG(EC_REG_BASE_ADDR + 0x3F0F)
164 #define IPOLR4			ECREG(EC_REG_BASE_ADDR + 0x3F17)
165 #define IPOLR5			ECREG(EC_REG_BASE_ADDR + 0x3F1B)
166 #define IPOLR6			ECREG(EC_REG_BASE_ADDR + 0x3F1F)
167 #define IPOLR7			ECREG(EC_REG_BASE_ADDR + 0x3F23)
168 #define IPOLR8			ECREG(EC_REG_BASE_ADDR + 0x3F27)
169 #define IPOLR9			ECREG(EC_REG_BASE_ADDR + 0x3F2B)
170 #define IPOLR10			ECREG(EC_REG_BASE_ADDR + 0x3F2F)
171 #define IPOLR11			ECREG(EC_REG_BASE_ADDR + 0x3F33)
172 #define IPOLR12			ECREG(EC_REG_BASE_ADDR + 0x3F37)
173 #define IPOLR13			ECREG(EC_REG_BASE_ADDR + 0x3F3B)
174 #define IPOLR14			ECREG(EC_REG_BASE_ADDR + 0x3F3F)
175 #define IPOLR15			ECREG(EC_REG_BASE_ADDR + 0x3F43)
176 #define IPOLR16			ECREG(EC_REG_BASE_ADDR + 0x3F47)
177 #define IPOLR17			ECREG(EC_REG_BASE_ADDR + 0x3F4B)
178 #define IPOLR18			ECREG(EC_REG_BASE_ADDR + 0x3F4F)
179 #define IPOLR19			ECREG(EC_REG_BASE_ADDR + 0x3F53)
180 #define IPOLR20			ECREG(EC_REG_BASE_ADDR + 0x3F57)
181 #define IPOLR21			ECREG(EC_REG_BASE_ADDR + 0x3F5B)
182 #define IPOLR22			ECREG(EC_REG_BASE_ADDR + 0x3F5F)
183 #define IPOLR23			ECREG(EC_REG_BASE_ADDR + 0x3F93)
184 #endif
185 #define IVECT			ECREG(EC_REG_BASE_ADDR + 0x3F10)
186 
187 
188 /*
189  * TODO: use pinctrl node instead of following register declarations
190  *       to fix in tcpm\it83xx_pd.h.
191  */
192 /* GPIO control register */
193 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
194 #define GPCRF4			ECREG(EC_REG_BASE_ADDR + 0x163C)
195 #define GPCRF5			ECREG(EC_REG_BASE_ADDR + 0x163D)
196 #define GPCRH1			ECREG(EC_REG_BASE_ADDR + 0x1649)
197 #define GPCRH2			ECREG(EC_REG_BASE_ADDR + 0x164A)
198 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
199 #define GPCRF4			ECREG(EC_REG_BASE_ADDR + 0x168C)
200 #define GPCRF5			ECREG(EC_REG_BASE_ADDR + 0x168D)
201 #define GPCRH1			ECREG(EC_REG_BASE_ADDR + 0x1699)
202 #define GPCRH2			ECREG(EC_REG_BASE_ADDR + 0x169A)
203 #endif
204 
205 /*
206  * IT8XXX2 register structure size/offset checking macro function to mitigate
207  * the risk of unexpected compiling results.
208  */
209 #define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \
210 	BUILD_ASSERT(sizeof(struct reg_def) == size, \
211 		"Failed in size check of register structure!")
212 #define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \
213 	BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
214 		"Failed in offset check of register structure member!")
215 
216 /**
217  *
218  * (18xxh) PWM & SmartAuto Fan Control (PWM)
219  *
220  */
221 #ifndef __ASSEMBLER__
222 struct pwm_it8xxx2_regs {
223 	/* 0x000: Channel0 Clock Prescaler */
224 	volatile uint8_t C0CPRS;
225 	/* 0x001: Cycle Time0 */
226 	volatile uint8_t CTR;
227 	/* 0x002~0x00A: Reserved1 */
228 	volatile uint8_t Reserved1[9];
229 	/* 0x00B: Prescaler Clock Frequency Select */
230 	volatile uint8_t PCFSR;
231 	/* 0x00C~0x00F: Reserved2 */
232 	volatile uint8_t Reserved2[4];
233 	/* 0x010: Cycle Time1 MSB */
234 	volatile uint8_t CTR1M;
235 	/* 0x011~0x022: Reserved3 */
236 	volatile uint8_t Reserved3[18];
237 	/* 0x023: PWM Clock Control */
238 	volatile uint8_t ZTIER;
239 	/* 0x024~0x026: Reserved4 */
240 	volatile uint8_t Reserved4[3];
241 	/* 0x027: Channel4 Clock Prescaler */
242 	volatile uint8_t C4CPRS;
243 	/* 0x028: Channel4 Clock Prescaler MSB */
244 	volatile uint8_t C4MCPRS;
245 	/* 0x029~0x02A: Reserved5 */
246 	volatile uint8_t Reserved5[2];
247 	/* 0x02B: Channel6 Clock Prescaler */
248 	volatile uint8_t C6CPRS;
249 	/* 0x02C: Channel6 Clock Prescaler MSB */
250 	volatile uint8_t C6MCPRS;
251 	/* 0x02D: Channel7 Clock Prescaler */
252 	volatile uint8_t C7CPRS;
253 	/* 0x02E: Channel7 Clock Prescaler MSB */
254 	volatile uint8_t C7MCPRS;
255 	/* 0x02F~0x040: Reserved6 */
256 	volatile uint8_t reserved6[18];
257 	/* 0x041: Cycle Time1 */
258 	volatile uint8_t CTR1;
259 	/* 0x042: Cycle Time2 */
260 	volatile uint8_t CTR2;
261 	/* 0x043: Cycle Time3 */
262 	volatile uint8_t CTR3;
263 	/* 0x044~0x048: Reserved7 */
264 	volatile uint8_t reserved7[5];
265 	/* 0x049: PWM Output Open-Drain Enable */
266 	volatile uint8_t PWMODENR;
267 };
268 #endif /* !__ASSEMBLER__ */
269 
270 /* PWM register fields */
271 /* 0x023: PWM Clock Control */
272 #define IT8XXX2_PWM_PCCE		BIT(1)
273 /* 0x048: Tachometer Switch Control */
274 #define IT8XXX2_PWM_T0DVS		BIT(3)
275 #define IT8XXX2_PWM_T0CHSEL		BIT(2)
276 #define IT8XXX2_PWM_T1DVS		BIT(1)
277 #define IT8XXX2_PWM_T1CHSEL		BIT(0)
278 
279 
280 /* --- Wake-Up Control (WUC) --- */
281 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
282 #define IT8XXX2_WUC_BASE   0x00F01B00
283 
284 /* TODO: should a defined interface for configuring wake-up interrupts */
285 #define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00)
286 #define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c)
287 #define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04)
288 #define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d)
289 #define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c)
290 #define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f)
291 #endif
292 
293 /**
294  *
295  * (1Dxxh) Keyboard Matrix Scan control (KSCAN)
296  *
297  */
298 #ifndef __ASSEMBLER__
299 struct kscan_it8xxx2_regs {
300 	/* 0x000: Keyboard Scan Out */
301 	volatile uint8_t KBS_KSOL;
302 	/* 0x001: Keyboard Scan Out */
303 	volatile uint8_t KBS_KSOH1;
304 	/* 0x002: Keyboard Scan Out Control */
305 	volatile uint8_t KBS_KSOCTRL;
306 	/* 0x003: Keyboard Scan Out */
307 	volatile uint8_t KBS_KSOH2;
308 	/* 0x004: Keyboard Scan In */
309 	volatile uint8_t KBS_KSI;
310 	/* 0x005: Keyboard Scan In Control */
311 	volatile uint8_t KBS_KSICTRL;
312 	/* 0x006: Keyboard Scan In [7:0] GPIO Control */
313 	volatile uint8_t KBS_KSIGCTRL;
314 	/* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */
315 	volatile uint8_t KBS_KSIGOEN;
316 	/* 0x008: Keyboard Scan In [7:0] GPIO Data */
317 	volatile uint8_t KBS_KSIGDAT;
318 	/* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */
319 	volatile uint8_t KBS_KSIGDMRR;
320 	/* 0x00A: Keyboard Scan Out [15:8] GPIO Control */
321 	volatile uint8_t KBS_KSOHGCTRL;
322 	/* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */
323 	volatile uint8_t KBS_KSOHGOEN;
324 	/* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */
325 	volatile uint8_t KBS_KSOHGDMRR;
326 	/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
327 	volatile uint8_t KBS_KSOLGCTRL;
328 	/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
329 	volatile uint8_t KBS_KSOLGOEN;
330 };
331 #endif /* !__ASSEMBLER__ */
332 
333 /* KBS register fields */
334 /* 0x002: Keyboard Scan Out Control */
335 #define IT8XXX2_KBS_KSOPU	BIT(2)
336 #define IT8XXX2_KBS_KSOOD	BIT(0)
337 /* 0x005: Keyboard Scan In Control */
338 #define IT8XXX2_KBS_KSIPU	BIT(2)
339 /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
340 #define IT8XXX2_KBS_KSO2GCTRL	BIT(2)
341 /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
342 #define IT8XXX2_KBS_KSO2GOEN	BIT(2)
343 
344 
345 /**
346  *
347  * (1Fxxh) External Timer & External Watchdog (ETWD)
348  *
349  */
350 #ifndef __ASSEMBLER__
351 struct wdt_it8xxx2_regs {
352 	/* 0x000: Reserved1 */
353 	volatile uint8_t reserved1;
354 	/* 0x001: External Timer1/WDT Configuration */
355 	volatile uint8_t ETWCFG;
356 	/* 0x002: External Timer1 Prescaler */
357 	volatile uint8_t ET1PSR;
358 	/* 0x003: External Timer1 Counter High Byte */
359 	volatile uint8_t ET1CNTLHR;
360 	/* 0x004: External Timer1 Counter Low Byte */
361 	volatile uint8_t ET1CNTLLR;
362 	/* 0x005: External Timer1/WDT Control */
363 	volatile uint8_t ETWCTRL;
364 	/* 0x006: External WDT Counter Low Byte */
365 	volatile uint8_t EWDCNTLR;
366 	/* 0x007: External WDT Key */
367 	volatile uint8_t EWDKEYR;
368 	/* 0x008: Reserved2 */
369 	volatile uint8_t reserved2;
370 	/* 0x009: External WDT Counter High Byte */
371 	volatile uint8_t EWDCNTHR;
372 	/* 0x00A: External Timer2 Prescaler */
373 	volatile uint8_t ET2PSR;
374 	/* 0x00B: External Timer2 Counter High Byte */
375 	volatile uint8_t ET2CNTLHR;
376 	/* 0x00C: External Timer2 Counter Low Byte */
377 	volatile uint8_t ET2CNTLLR;
378 	/* 0x00D: Reserved3 */
379 	volatile uint8_t reserved3;
380 	/* 0x00E: External Timer2 Counter High Byte2 */
381 	volatile uint8_t ET2CNTLH2R;
382 };
383 #endif /* !__ASSEMBLER__ */
384 
385 /* WDT register fields */
386 /* 0x001: External Timer1/WDT Configuration */
387 #define IT8XXX2_WDT_EWDKEYEN		BIT(5)
388 #define IT8XXX2_WDT_EWDSRC		BIT(4)
389 #define IT8XXX2_WDT_LEWDCNTL		BIT(3)
390 #define IT8XXX2_WDT_LET1CNTL		BIT(2)
391 #define IT8XXX2_WDT_LET1PS		BIT(1)
392 #define IT8XXX2_WDT_LETWCFG		BIT(0)
393 /* 0x002: External Timer1 Prescaler */
394 #define IT8XXX2_WDT_ETPS_32P768_KHZ	0x00
395 #define IT8XXX2_WDT_ETPS_1P024_KHZ	0x01
396 #define IT8XXX2_WDT_ETPS_32_HZ		0x02
397 /* 0x005: External Timer1/WDT Control */
398 #define IT8XXX2_WDT_EWDSCEN		BIT(5)
399 #define IT8XXX2_WDT_EWDSCMS		BIT(4)
400 #define IT8XXX2_WDT_ET2TC		BIT(3)
401 #define IT8XXX2_WDT_ET2RST		BIT(2)
402 #define IT8XXX2_WDT_ET1TC		BIT(1)
403 #define IT8XXX2_WDT_ET1RST		BIT(0)
404 
405 /* External Timer register fields */
406 /* External Timer 3~8 control */
407 #define IT8XXX2_EXT_ETX_COMB_RST_EN	(IT8XXX2_EXT_ETXCOMB | \
408 					 IT8XXX2_EXT_ETXRST | \
409 					 IT8XXX2_EXT_ETXEN)
410 #define IT8XXX2_EXT_ETXCOMB		BIT(3)
411 #define IT8XXX2_EXT_ETXRST		BIT(1)
412 #define IT8XXX2_EXT_ETXEN		BIT(0)
413 
414 /* Control external timer3~8 */
415 #define IT8XXX2_EXT_TIMER_BASE  DT_REG_ADDR(DT_NODELABEL(timer))  /*0x00F01F10*/
416 #define IT8XXX2_EXT_CTRLX(n)    ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
417 #define IT8XXX2_EXT_PSRX(n)     ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
418 #define IT8XXX2_EXT_CNTX(n)     ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \
419 					(n << 3))
420 #define IT8XXX2_EXT_CNTOX(n)    ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \
421 					(n << 2))
422 
423 /* Free run timer configurations */
424 #define FREE_RUN_TIMER          EXT_TIMER_4
425 #define FREE_RUN_TIMER_IRQ      DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq)
426 /* Free run timer configurations */
427 #define FREE_RUN_TIMER_FLAG     DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags)
428 /* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */
429 #define FREE_RUN_TIMER_MAX_CNT  0xFFFFFFFFUL
430 
431 #ifndef __ASSEMBLER__
432 enum ext_clk_src_sel {
433 	EXT_PSR_32P768K = 0,
434 	EXT_PSR_1P024K,
435 	EXT_PSR_32,
436 	EXT_PSR_EC_CLK,
437 };
438 /*
439  * 24-bit timers: external timer 3, 5, and 7
440  * 32-bit timers: external timer 4, 6, and 8
441  */
442 enum ext_timer_idx {
443 	EXT_TIMER_3 = 0,	/* Event timer */
444 	EXT_TIMER_4,		/* Free run timer */
445 	EXT_TIMER_5,		/* Busy wait low timer */
446 	EXT_TIMER_6,		/* Busy wait high timer */
447 	EXT_TIMER_7,
448 	EXT_TIMER_8,
449 };
450 #endif
451 
452 
453 /*
454  *
455  * (2Cxxh) Platform Environment Control Interface (PECI)
456  *
457  */
458 #ifndef __ASSEMBLER__
459 struct peci_it8xxx2_regs {
460 	/* 0x00: Host Status */
461 	volatile uint8_t HOSTAR;
462 	/* 0x01: Host Control */
463 	volatile uint8_t HOCTLR;
464 	/* 0x02: Host Command */
465 	volatile uint8_t HOCMDR;
466 	/* 0x03: Host Target Address */
467 	volatile uint8_t HOTRADDR;
468 	/* 0x04: Host Write Length */
469 	volatile uint8_t HOWRLR;
470 	/* 0x05: Host Read Length */
471 	volatile uint8_t HORDLR;
472 	/* 0x06: Host Write Data */
473 	volatile uint8_t HOWRDR;
474 	/* 0x07: Host Read Data */
475 	volatile uint8_t HORDDR;
476 	/* 0x08: Host Control 2 */
477 	volatile uint8_t HOCTL2R;
478 	/* 0x09: Received Write FCS value */
479 	volatile uint8_t RWFCSV;
480 	/* 0x0A: Received Read FCS value */
481 	volatile uint8_t RRFCSV;
482 	/* 0x0B: Write FCS Value */
483 	volatile uint8_t WFCSV;
484 	/* 0x0C: Read FCS Value */
485 	volatile uint8_t RFCSV;
486 	/* 0x0D: Assured Write FCS Value */
487 	volatile uint8_t AWFCSV;
488 	/* 0x0E: Pad Control */
489 	volatile uint8_t PADCTLR;
490 };
491 #endif /* !__ASSEMBLER__ */
492 
493 /**
494  *
495  * (2Fxxh) USB Device Controller (USBDC) Registers
496  *
497  */
498 #define EP_EXT_REGS_9X        1
499 #define EP_EXT_REGS_BX        2
500 #define EP_EXT_REGS_DX        3
501 
502 #ifndef __ASSEMBLER__
503 
504 /* EP0 to EP15 Enumeration */
505 enum usb_dc_endpoints {
506 	EP0,
507 	EP1,
508 	EP2,
509 	EP3,
510 	EP4,
511 	EP5,
512 	EP6,
513 	EP7,
514 	EP8,
515 	EP9,
516 	EP10,
517 	EP11,
518 	EP12,
519 	EP13,
520 	EP14,
521 	EP15,
522 	MAX_NUM_ENDPOINTS
523 };
524 
525 union ep_ctrl_reg {
526 	volatile uint8_t value;
527 	struct {
528 		volatile uint8_t enable_bit: 1;
529 		volatile uint8_t ready_bit: 1;
530 		volatile uint8_t outdata_sequence_bit: 1;
531 		volatile uint8_t send_stall_bit: 1;
532 		volatile uint8_t iso_enable_bit: 1;
533 		volatile uint8_t direction_bit: 1;
534 		volatile uint8_t reserved: 2;
535 	} __packed fields;
536 } __packed;
537 
538 struct it82xx2_usb_ep_regs {
539 	union ep_ctrl_reg ep_ctrl;
540 	volatile uint8_t ep_status;
541 	volatile uint8_t ep_transtype_sts;
542 	volatile uint8_t ep_nak_transtype_sts;
543 };
544 
545 /* Reserved EP Extended Registers */
546 struct ep_ext_regs_7x {
547 	/* 0x75 Reserved */
548 	volatile uint8_t ep_ext_ctrl_75;
549 	/* 0x76 Reserved */
550 	volatile uint8_t ep_ext_ctrl_76;
551 	/* 0x77 Reserved */
552 	volatile uint8_t ep_ext_ctrl_77;
553 	/* 0x78 Reserved */
554 	volatile uint8_t ep_ext_ctrl_78;
555 	/* 0x79 Reserved */
556 	volatile uint8_t ep_ext_ctrl_79;
557 	/* 0x7A Reserved */
558 	volatile uint8_t ep_ext_ctrl_7a;
559 	/* 0x7B Reserved */
560 	volatile uint8_t ep_ext_ctrl_7b;
561 	/* 0x7C Reserved */
562 	volatile uint8_t ep_ext_ctrl_7c;
563 	/* 0x7D Reserved */
564 	volatile uint8_t ep_ext_ctrl_7d;
565 	/* 0x7E Reserved */
566 	volatile uint8_t ep_ext_ctrl_7e;
567 	/* 0x7F Reserved */
568 	volatile uint8_t ep_ext_ctrl_7f;
569 };
570 
571 /* From 98h to 9Dh, the EP45/67/89/1011/1213/1415 Extended Control Registers
572  * are defined, and their bits definitions are as follows:
573  *
574  * Bit    Description
575  *  7     Reserved
576  *  6     EPPOINT5_ISO_ENABLE
577  *  5     EPPOINT5_SEND_STALL
578  *  4     EPPOINT5_OUT_DATA_SEQUENCE
579  *  3     Reserved
580  *  2     EPPOINT4_ISO_ENABLE
581  *  1     EPPOINT4_SEND_STALL
582  *  0     EPPOINT4_OUT_DATA_SEQUENCE
583  *
584  * Apparently, we can tell that the EP4 and EP5 share the same register, and
585  * the EP6 and EP7 share the same one, and the rest EPs are defined in the
586  * same way.
587  */
588 union epn0n1_extend_ctrl_reg {
589 	volatile uint8_t value;
590 	struct {
591 		volatile uint8_t epn0_outdata_sequence_bit: 1;
592 		volatile uint8_t epn0_send_stall_bit: 1;
593 		volatile uint8_t epn0_iso_enable_bit: 1;
594 		volatile uint8_t reserved0: 1;
595 		volatile uint8_t epn1_outdata_sequence_bit: 1;
596 		volatile uint8_t epn1_send_stall_bit: 1;
597 		volatile uint8_t epn1_iso_enable_bit: 1;
598 		volatile uint8_t reserved1: 1;
599 	} __packed fields;
600 } __packed;
601 
602 struct ep_ext_regs_9x {
603 	/* 0x95 Reserved */
604 	volatile uint8_t ep_ext_ctrl_95;
605 	/* 0x96 Reserved */
606 	volatile uint8_t ep_ext_ctrl_96;
607 	/* 0x97 Reserved */
608 	volatile uint8_t ep_ext_ctrl_97;
609 	/* 0x98 ~ 0x9D EP45/67/89/1011/1213/1415 Extended Control Registers */
610 	union epn0n1_extend_ctrl_reg epn0n1_ext_ctrl[6];
611 	/* 0x9E Reserved */
612 	volatile uint8_t ep_ext_ctrl_9e;
613 	/* 0x9F Reserved */
614 	volatile uint8_t ep_ext_ctrl_9f;
615 };
616 
617 /* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their
618  * definitions as follows:
619  * B8h: EP_FIFO1_CONTROL0_REG
620  * B9h: EP_FIFO1_CONTROL1_REG
621  * BAh: EP_FIFO2_CONTROL0_REG
622  * BBh: EP_FIFO2_CONTROL1_REG
623  * BCh: EP_FIFO3_CONTROL0_REG
624  * BDh: EP_FIFO3_CONTROL1_REG
625  *
626  * For each one, its bits definitions are as follows:
627  * (take EP_FIFO1_CONTROL1_REG as example, which controls from EP8 to EP15)
628  *
629  * Bit  Description
630  *
631  *  7   EP15 select FIFO1 as data buffer
632  *  6   EP14 select FIFO1 as data buffer
633  *  5   EP13 select FIFO1 as data buffer
634  *  4   EP12 select FIFO1 as data buffer
635  *  3   EP11 select FIFO1 as data buffer
636  *  2   EP10 select FIFO1 as data buffer
637  *  1   EP9 select FIFO1 as data buffer
638  *  0   EP8 select FIFO1 as data buffer
639  *
640  *  1: Select
641  *  0: Not select
642  */
643 struct ep_ext_regs_bx {
644 	/* 0xB5 Reserved */
645 	volatile uint8_t ep_ext_ctrl_b5;
646 	/* 0xB6 Reserved */
647 	volatile uint8_t ep_ext_ctrl_b6;
648 	/* 0xB7 Reserved */
649 	volatile uint8_t ep_ext_ctrl_b7;
650 	/* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */
651 	volatile uint8_t ep_fifo_ctrl[6];
652 	/* 0xBE Reserved */
653 	volatile uint8_t ep_ext_ctrl_be;
654 	/* 0xBF Reserved */
655 	volatile uint8_t ep_ext_ctrl_bf;
656 };
657 
658 
659 /* From D6h to DDh are EP Extended Control Registers, and their
660  * definitions as follows:
661  * D6h: EP0_EXT_CTRL1
662  * D7h: EP0_EXT_CTRL2
663  * D8h: EP1_EXT_CTRL1
664  * D9h: EP1_EXT_CTRL2
665  * DAh: EP2_EXT_CTRL1
666  * DBh: EP2_EXT_CTRL2
667  * DCh: EP3_EXT_CTRL1
668  * DDh: EP3_EXT_CTRL2
669  *
670  * We classify them into 4 groups which each of them contains Control 1 and 2
671  * according to the EP number as follows:
672  */
673 union epn_extend_ctrl1_reg {
674 	volatile uint8_t value;
675 	struct {
676 		volatile uint8_t epn0_enable_bit: 1;
677 		volatile uint8_t epn0_direction_bit: 1;
678 		volatile uint8_t epn3_enable_bit: 1;
679 		volatile uint8_t epn3_direction_bit: 1;
680 		volatile uint8_t epn6_enable_bit: 1;
681 		volatile uint8_t epn6_direction_bit: 1;
682 		volatile uint8_t epn9_enable_bit: 1;
683 		volatile uint8_t epn9_direction_bit: 1;
684 	} __packed fields;
685 } __packed;
686 
687 struct epn_ext_ctrl_regs {
688 	/* 0xD6/0xD8/0xDA/0xDC EPN Extended Control1 Register */
689 	union epn_extend_ctrl1_reg epn_ext_ctrl1;
690 	/* 0xD7/0xD9/0xDB/0xDD EPB Extended Control2 Register */
691 	volatile uint8_t epn_ext_ctrl2;
692 };
693 
694 struct ep_ext_regs_dx {
695 	/* 0xD5 Reserved */
696 	volatile uint8_t ep_ext_ctrl_d5;
697 	/* 0xD6 ~ 0xDD EPN Extended Control 1/2 Registers */
698 	struct epn_ext_ctrl_regs epn_ext_ctrl[4];
699 	/* 0xDE Reserved */
700 	volatile uint8_t ep_ext_ctrl_de;
701 	/* 0xDF Reserved */
702 	volatile uint8_t ep_ext_ctrl_df;
703 };
704 
705 
706 /* The USB EPx FIFO Registers Definitions
707  * EP0: 60h ~ 74h
708  * EP1: 80h ~ 94h
709  * EP2: A0h ~ B4h
710  * EP3: C0h ~ D4h (D6h to DDh will be defined as marcos for usage)
711  */
712 struct it82xx2_usb_ep_fifo_regs {
713 	/* 0x60 + ep * 0x20 : EP RX FIFO Data Register  */
714 	volatile uint8_t ep_rx_fifo_data;
715 	/* 0x61 + ep * 0x20 : EP RX FIFO DMA Count Register */
716 	volatile uint8_t ep_rx_fifo_dma_count;
717 	/* 0x62 + ep * 0x20 : EP RX FIFO Data Count MSB */
718 	volatile uint8_t ep_rx_fifo_dcnt_msb;
719 	/* 0x63 + ep * 0x20 : EP RX FIFO Data Count LSB */
720 	volatile uint8_t ep_rx_fifo_dcnt_lsb;
721 	/* 0x64 + ep * 0x20  : EP RX FIFO Control Register */
722 	volatile uint8_t ep_rx_fifo_ctrl;
723 	/* (0x65 ~ 0x6F) + ep * 0x20 */
724 	volatile uint8_t reserved_65_6f_add_20[11];
725 	/* 0x70 + ep * 0x20 : EP TX FIFO Data Register  */
726 	volatile uint8_t ep_tx_fifo_data;
727 	/* (0x71 ~ 0x73) + ep * 0x20 */
728 	volatile uint8_t reserved_71_73_add_20[3];
729 	/* 0x74 + ep * 0x20 : EP TX FIFO Control Register */
730 	volatile uint8_t ep_tx_fifo_ctrl;
731 	/* (0x75 ~ 0x7F) + ep * 0x20 */
732 	union {
733 		struct ep_ext_regs_7x ep_res;
734 		struct ep_ext_regs_9x ext_4_15;
735 		struct ep_ext_regs_bx fifo_ctrl;
736 		struct ep_ext_regs_dx ext_0_3;
737 	};
738 
739 };
740 
741 /* USB Control registers */
742 #define USB_IT82XX2_REGS_BASE \
743 	((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0)))
744 
745 /* Bit definitions of the register Port0/Port1 MISC Control: 0XE4/0xE8 */
746 #define PULL_DOWN_EN	BIT(4)
747 
748 struct usb_it82xx2_regs {
749 	/* 0x00:  Host TX Contrl Register */
750 	volatile uint8_t host_tx_ctrl;
751 	/* 0x01:  Host TX Transaction Type Register */
752 	volatile uint8_t host_tx_trans_type;
753 	/* 0x02:  Host TX Line Control Register */
754 	volatile uint8_t host_tx_line_ctrl;
755 	/* 0x03:  Host TX SOF Enable Register */
756 	volatile uint8_t host_tx_sof_enable;
757 	/* 0x04:  Host TX Address Register */
758 	volatile uint8_t host_tx_addr;
759 	/* 0x05:  Host TX EP Number Register */
760 	volatile uint8_t host_tx_endp;
761 	/* 0x06:  Host Frame Number MSP Register */
762 	volatile uint8_t host_frame_num_msp;
763 	/* 0x07:  Host Frame Number LSP Register */
764 	volatile uint8_t host_frame_num_lsp;
765 	/* 0x08:  Host Interrupt Status Register */
766 	volatile uint8_t host_interrupt_status;
767 	/* 0x09:  Host Interrupt Mask Register */
768 	volatile uint8_t host_interrupt_mask;
769 	/* 0x0A:  Host RX Status Register */
770 	volatile uint8_t host_rx_status;
771 	/* 0x0B:  Host RX PID Register */
772 	volatile uint8_t host_rx_pid;
773 	/* 0x0C:  MISC Control Register */
774 	volatile uint8_t misc_control;
775 	/* 0x0D:  MISC Status Register */
776 	volatile uint8_t misc_status;
777 	/* 0x0E:  Host RX Connect State Register */
778 	volatile uint8_t host_rx_connect_state;
779 	/* 0x0F:  Host SOF Timer MSB Register */
780 	volatile uint8_t host_sof_timer_msb;
781 	/* 0x10 ~ 0x1F:  Reserved Registers 10h - 1Fh */
782 	volatile uint8_t reserved_10_1f[16];
783 	/* 0x20:  Host RX FIFO Data Port Register */
784 	volatile uint8_t host_rx_fifo_data;
785 	/* 0x21:  Host RX FIFO DMA Input Data Count Register */
786 	volatile uint8_t host_rx_fifo_dma_data_count;
787 	/* 0x22:  Host TX FIFO Data Count MSB Register */
788 	volatile uint8_t host_rx_fifo_data_count_msb;
789 	/* 0x23:  Host TX FIFO Data Count LSB Register */
790 	volatile uint8_t host_rx_fifo_data_count_lsb;
791 	/* 0x24:  Host RX FIFO Data Port Register */
792 	volatile uint8_t host_rx_fifo_control;
793 	/* 0x25 ~ 0x2F:  Reserved Registers 25h - 2Fh */
794 	volatile uint8_t reserved_25_2f[11];
795 	/* 0x30:  Host TX FIFO Data Port Register */
796 	volatile uint8_t host_tx_fifo_data;
797 	/* 0x31 ~ 0x3F:  Reserved Registers 31h - 3Fh */
798 	volatile uint8_t reserved_31_3f[15];
799 	/* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */
800 	struct it82xx2_usb_ep_regs usb_ep_regs[4];
801 	/* 0x50:  Device Controller Control Register */
802 	volatile uint8_t dc_control;
803 	/* 0x51:  Device Controller LINE Status Register */
804 	volatile uint8_t dc_line_status;
805 	/* 0x52:  Device Controller Interrupt Status Register */
806 	volatile uint8_t dc_interrupt_status;
807 	/* 0x53:  Device Controller Interrupt Mask Register */
808 	volatile uint8_t dc_interrupt_mask;
809 	/* 0x54:  Device Controller Address Register */
810 	volatile uint8_t dc_address;
811 	/* 0x55:  Device Controller Frame Number MSP Register */
812 	volatile uint8_t dc_frame_num_msp;
813 	/* 0x56:  Device Controller Frame Number LSP Register */
814 	volatile uint8_t dc_frame_num_lsp;
815 	/* 0x57 ~ 0x5F:  Reserved Registers 57h - 5Fh */
816 	volatile uint8_t reserved_57_5f[9];
817 	/* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */
818 	struct it82xx2_usb_ep_fifo_regs fifo_regs[4];
819 	/* 0xE0:  Host/Device Control Register */
820 	volatile uint8_t host_device_control;
821 	/* 0xE1 ~ 0xE3:  Reserved Registers E1h - E3h */
822 	volatile uint8_t reserved_e1_e3[3];
823 	/* 0xE4:  Port0 MISC Control Register */
824 	volatile uint8_t port0_misc_control;
825 	/* 0xE5 ~ 0xE7:  Reserved Registers E5h - E7h */
826 	volatile uint8_t reserved_e5_e7[3];
827 	/* 0xE8:  Port1 MISC Control Register */
828 	volatile uint8_t port1_misc_control;
829 };
830 #endif /* #ifndef __ASSEMBLER__ */
831 
832 /**
833  *
834  * (37xxh, 38xxh) USBPD Controller
835  *
836  */
837 #ifndef __ASSEMBLER__
838 struct usbpd_it8xxx2_regs {
839 	/* 0x000~0x003: Reserved1 */
840 	volatile uint8_t Reserved1[4];
841 	/* 0x004: CC General Configuration */
842 	volatile uint8_t CCGCR;
843 	/* 0x005: CC Channel Setting */
844 	volatile uint8_t CCCSR;
845 	/* 0x006: CC Pad Setting */
846 	volatile uint8_t CCPSR;
847 };
848 #endif /* !__ASSEMBLER__ */
849 
850 /* USBPD controller register fields */
851 /* 0x004: CC General Configuration */
852 #define IT8XXX2_USBPD_DISABLE_CC			BIT(7)
853 #define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR		BIT(6)
854 #define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED		(BIT(3) | BIT(2) | BIT(1))
855 #define IT8XXX2_USBPD_CC_SELECT_RP_DEF			(BIT(3) | BIT(2))
856 #define IT8XXX2_USBPD_CC_SELECT_RP_1A5			BIT(3)
857 #define IT8XXX2_USBPD_CC_SELECT_RP_3A0			BIT(2)
858 #define IT8XXX2_USBPD_CC1_CC2_SELECTION			BIT(0)
859 /* 0x005: CC Channel Setting */
860 #define IT8XXX2_USBPD_CC2_DISCONNECT			BIT(7)
861 #define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND	BIT(6)
862 #define IT8XXX2_USBPD_CC1_DISCONNECT			BIT(3)
863 #define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND	BIT(2)
864 #define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT		(BIT(1) | BIT(5))
865 /* 0x006: CC Pad Setting */
866 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB		BIT(6)
867 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC2		BIT(5)
868 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB		BIT(2)
869 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC1		BIT(1)
870 
871 
872 /**
873  *
874  * (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers
875  *
876  */
877 #ifndef __ASSEMBLER__
878 struct smfi_it8xxx2_regs {
879 	volatile uint8_t reserved1[59];
880 	/* 0x3B: EC-Indirect memory address 0 */
881 	volatile uint8_t SMFI_ECINDAR0;
882 	/* 0x3C: EC-Indirect memory address 1 */
883 	volatile uint8_t SMFI_ECINDAR1;
884 	/* 0x3D: EC-Indirect memory address 2 */
885 	volatile uint8_t SMFI_ECINDAR2;
886 	/* 0x3E: EC-Indirect memory address 3 */
887 	volatile uint8_t SMFI_ECINDAR3;
888 	/* 0x3F: EC-Indirect memory data */
889 	volatile uint8_t SMFI_ECINDDR;
890 	/* 0x40: Scratch SRAM 0 address low byte */
891 	volatile uint8_t SMFI_SCAR0L;
892 	/* 0x41: Scratch SRAM 0 address middle byte */
893 	volatile uint8_t SMFI_SCAR0M;
894 	/* 0x42: Scratch SRAM 0 address high byte */
895 	volatile uint8_t SMFI_SCAR0H;
896 	volatile uint8_t reserved1_1[23];
897 	/* 0x5A: Host RAM Window Control */
898 	volatile uint8_t SMFI_HRAMWC;
899 	/* 0x5B: Host RAM Window 0 Base Address [11:4] */
900 	volatile uint8_t SMFI_HRAMW0BA;
901 	/* 0x5C: Host RAM Window 1 Base Address [11:4] */
902 	volatile uint8_t SMFI_HRAMW1BA;
903 	/* 0x5D: Host RAM Window 0 Access Allow Size */
904 	volatile uint8_t SMFI_HRAMW0AAS;
905 	/* 0x5E: Host RAM Window 1 Access Allow Size */
906 	volatile uint8_t SMFI_HRAMW1AAS;
907 	volatile uint8_t reserved2[67];
908 	/* 0xA2: Flash control 6 */
909 	volatile uint8_t SMFI_FLHCTRL6R;
910 	volatile uint8_t reserved3[46];
911 };
912 #endif /* !__ASSEMBLER__ */
913 
914 /* SMFI register fields */
915 /* EC-Indirect read internal flash */
916 #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
917 /* Enable EC-indirect page program command */
918 #define IT8XXX2_SMFI_MASK_ECINDPP BIT(3)
919 /* Scratch SRAM 0 address(BIT(19)) */
920 #define IT8XXX2_SMFI_SC0A19 BIT(7)
921 /* Scratch SRAM enable */
922 #define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3)
923 
924 /* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */
925 #define SMFI_H2RAMPS           BIT(4)
926 /* H2RAM Window 1 Enable */
927 #define SMFI_H2RAMW1E          BIT(1)
928 /* H2RAM Window 0 Enable */
929 #define SMFI_H2RAMW0E          BIT(0)
930 
931 /* Host RAM Window x Write Protect Enable (All protected) */
932 #define SMFI_HRAMWXWPE_ALL     (BIT(5) | BIT(4))
933 
934 
935 /**
936  *
937  * (16xxh) General Purpose I/O Port (GPIO) registers
938  *
939  */
940 #define GPIO_IT8XXX2_REG_BASE \
941 	((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
942 
943 #ifndef __ASSEMBLER__
944 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
945 struct gpio_it8xxx2_regs {
946 	/* 0x00: General Control */
947 	volatile uint8_t GPIO_GCR;
948 	/* 0x01-D0: Reserved1 */
949 	volatile uint8_t reserved1[208];
950 	/* 0xD1: General Control 25 */
951 	volatile uint8_t GPIO_GCR25;
952 	/* 0xD2: General Control 26 */
953 	volatile uint8_t GPIO_GCR26;
954 	/* 0xD3: General Control 27 */
955 	volatile uint8_t GPIO_GCR27;
956 	/* 0xD4: General Control 28 */
957 	volatile uint8_t GPIO_GCR28;
958 	/* 0xD5: General Control 31 */
959 	volatile uint8_t GPIO_GCR31;
960 	/* 0xD6: General Control 32 */
961 	volatile uint8_t GPIO_GCR32;
962 	/* 0xD7: General Control 33 */
963 	volatile uint8_t GPIO_GCR33;
964 	/* 0xD8-0xDF: Reserved2 */
965 	volatile uint8_t reserved2[8];
966 	/* 0xE0: General Control 16 */
967 	volatile uint8_t GPIO_GCR16;
968 	/* 0xE1: General Control 17 */
969 	volatile uint8_t GPIO_GCR17;
970 	/* 0xE2: General Control 18 */
971 	volatile uint8_t GPIO_GCR18;
972 	/* 0xE3: Reserved3 */
973 	volatile uint8_t reserved3;
974 	/* 0xE4: General Control 19 */
975 	volatile uint8_t GPIO_GCR19;
976 	/* 0xE5: General Control 20 */
977 	volatile uint8_t GPIO_GCR20;
978 	/* 0xE6: General Control 21 */
979 	volatile uint8_t GPIO_GCR21;
980 	/* 0xE7: General Control 22 */
981 	volatile uint8_t GPIO_GCR22;
982 	/* 0xE8: General Control 23 */
983 	volatile uint8_t GPIO_GCR23;
984 	/* 0xE9: General Control 24 */
985 	volatile uint8_t GPIO_GCR24;
986 	/* 0xEA-0xEC: Reserved4 */
987 	volatile uint8_t reserved4[3];
988 	/* 0xED: General Control 30 */
989 	volatile uint8_t GPIO_GCR30;
990 	/* 0xEE: General Control 29 */
991 	volatile uint8_t GPIO_GCR29;
992 	/* 0xEF: Reserved5 */
993 	volatile uint8_t reserved5;
994 	/* 0xF0: General Control 1 */
995 	volatile uint8_t GPIO_GCR1;
996 	/* 0xF1: General Control 2 */
997 	volatile uint8_t GPIO_GCR2;
998 	/* 0xF2: General Control 3 */
999 	volatile uint8_t GPIO_GCR3;
1000 	/* 0xF3: General Control 4 */
1001 	volatile uint8_t GPIO_GCR4;
1002 	/* 0xF4: General Control 5 */
1003 	volatile uint8_t GPIO_GCR5;
1004 	/* 0xF5: General Control 6 */
1005 	volatile uint8_t GPIO_GCR6;
1006 	/* 0xF6: General Control 7 */
1007 	volatile uint8_t GPIO_GCR7;
1008 	/* 0xF7: General Control 8 */
1009 	volatile uint8_t GPIO_GCR8;
1010 	/* 0xF8: General Control 9 */
1011 	volatile uint8_t GPIO_GCR9;
1012 	/* 0xF9: General Control 10 */
1013 	volatile uint8_t GPIO_GCR10;
1014 	/* 0xFA: General Control 11 */
1015 	volatile uint8_t GPIO_GCR11;
1016 	/* 0xFB: General Control 12 */
1017 	volatile uint8_t GPIO_GCR12;
1018 	/* 0xFC: General Control 13 */
1019 	volatile uint8_t GPIO_GCR13;
1020 	/* 0xFD: General Control 14 */
1021 	volatile uint8_t GPIO_GCR14;
1022 	/* 0xFE: General Control 15 */
1023 	volatile uint8_t GPIO_GCR15;
1024 	/* 0xFF: Power Good Watch Control */
1025 	volatile uint8_t GPIO_PGWCR;
1026 };
1027 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
1028 struct gpio_it8xxx2_regs {
1029 	/* 0x00: General Control */
1030 	volatile uint8_t GPIO_GCR;
1031 	/* 0x01-0x0F: Reserved1 */
1032 	volatile uint8_t reserved1[15];
1033 	/* 0x10: General Control 1 */
1034 	volatile uint8_t GPIO_GCR1;
1035 	/* 0x11: General Control 2 */
1036 	volatile uint8_t GPIO_GCR2;
1037 	/* 0x12: General Control 3 */
1038 	volatile uint8_t GPIO_GCR3;
1039 	/* 0x13: General Control 4 */
1040 	volatile uint8_t GPIO_GCR4;
1041 	/* 0x14: General Control 5 */
1042 	volatile uint8_t GPIO_GCR5;
1043 	/* 0x15: General Control 6 */
1044 	volatile uint8_t GPIO_GCR6;
1045 	/* 0x16: General Control 7 */
1046 	volatile uint8_t GPIO_GCR7;
1047 	/* 0x17: General Control 8 */
1048 	volatile uint8_t GPIO_GCR8;
1049 	/* 0x18: General Control 9 */
1050 	volatile uint8_t GPIO_GCR9;
1051 	/* 0x19: General Control 10 */
1052 	volatile uint8_t GPIO_GCR10;
1053 	/* 0x1A: General Control 11 */
1054 	volatile uint8_t GPIO_GCR11;
1055 	/* 0x1B: General Control 12 */
1056 	volatile uint8_t GPIO_GCR12;
1057 	/* 0x1C: General Control 13 */
1058 	volatile uint8_t GPIO_GCR13;
1059 	/* 0x1D: General Control 14 */
1060 	volatile uint8_t GPIO_GCR14;
1061 	/* 0x1E: General Control 15 */
1062 	volatile uint8_t GPIO_GCR15;
1063 	/* 0x1F: Power Good Watch Control */
1064 	volatile uint8_t GPIO_PGWCR;
1065 	/* 0x20: General Control 16 */
1066 	volatile uint8_t GPIO_GCR16;
1067 	/* 0x21: General Control 17 */
1068 	volatile uint8_t GPIO_GCR17;
1069 	/* 0x22: General Control 18 */
1070 	volatile uint8_t GPIO_GCR18;
1071 	/* 0x23: Reserved2 */
1072 	volatile uint8_t reserved2;
1073 	/* 0x24: General Control 19 */
1074 	volatile uint8_t GPIO_GCR19;
1075 	/* 0x25: Reserved3 */
1076 	volatile uint8_t reserved3;
1077 	/* 0x26: General Control 21 */
1078 	volatile uint8_t GPIO_GCR21;
1079 	/* 0x27-0x28: Reserved4 */
1080 	volatile uint8_t reserved4[2];
1081 	/* 0x29: General Control 24 */
1082 	volatile uint8_t GPIO_GCR24;
1083 	/* 0x2A-0x2C: Reserved5 */
1084 	volatile uint8_t reserved5[3];
1085 	/* 0x2D: General Control 30 */
1086 	volatile uint8_t GPIO_GCR30;
1087 	/* 0x2E: General Control 29 */
1088 	volatile uint8_t GPIO_GCR29;
1089 };
1090 
1091 /* GPIO register fields */
1092 /* 0x16: General Control 7 */
1093 #define IT8XXX2_GPIO_SMB2PS                BIT(7)
1094 #define IT8XXX2_GPIO_SMB3PS                BIT(6)
1095 #define IT8XXX2_GPIO_SMB5PS                BIT(5)
1096 
1097 #endif
1098 #endif /* !__ASSEMBLER__ */
1099 
1100 /* GPIO register fields */
1101 /* 0x00: General Control */
1102 #define IT8XXX2_GPIO_LPCRSTEN              (BIT(2) | BIT(1))
1103 #define IT8XXX2_GPIO_GCR_ESPI_RST_D2       0x2
1104 #define IT8XXX2_GPIO_GCR_ESPI_RST_POS      1
1105 #define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK  (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS)
1106 /* 0xF0: General Control 1 */
1107 #define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN  BIT(2)
1108 #define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN  BIT(0)
1109 /* 0xE6: General Control 21 */
1110 #define IT8XXX2_GPIO_GPH1VS                BIT(1)
1111 #define IT8XXX2_GPIO_GPH2VS                BIT(0)
1112 
1113 #define KSIX_KSOX_KBS_GPIO_MODE     BIT(7)
1114 #define KSIX_KSOX_GPIO_OUTPUT       BIT(6)
1115 #define KSIX_KSOX_GPIO_PULLUP       BIT(2)
1116 #define KSIX_KSOX_GPIO_PULLDOWN     BIT(1)
1117 
1118 #define GPCR_PORT_PIN_MODE_INPUT    BIT(7)
1119 #define GPCR_PORT_PIN_MODE_OUTPUT   BIT(6)
1120 #define GPCR_PORT_PIN_MODE_PULLUP   BIT(2)
1121 #define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
1122 
1123 /*
1124  * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be
1125  * configured as tri-state.
1126  */
1127 #define GPCR_PORT_PIN_MODE_TRISTATE	(GPCR_PORT_PIN_MODE_INPUT |  \
1128 					 GPCR_PORT_PIN_MODE_PULLUP | \
1129 					 GPCR_PORT_PIN_MODE_PULLDOWN)
1130 
1131 /* --- GPIO --- */
1132 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
1133 #define IT8XXX2_GPIO_BASE  0x00F01600
1134 
1135 #define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset))
1136 #define IT8XXX2_GPIO_GCR25_OFFSET 0xd1
1137 #define IT8XXX2_GPIO_GCR26_OFFSET 0xd2
1138 #define IT8XXX2_GPIO_GCR27_OFFSET 0xd3
1139 #define IT8XXX2_GPIO_GCR28_OFFSET 0xd4
1140 #define IT8XXX2_GPIO_GCR31_OFFSET 0xd5
1141 #define IT8XXX2_GPIO_GCR32_OFFSET 0xd6
1142 #define IT8XXX2_GPIO_GCR33_OFFSET 0xd7
1143 #define IT8XXX2_GPIO_GCR19_OFFSET 0xe4
1144 #define IT8XXX2_GPIO_GCR20_OFFSET 0xe5
1145 #define IT8XXX2_GPIO_GCR21_OFFSET 0xe6
1146 #define IT8XXX2_GPIO_GCR22_OFFSET 0xe7
1147 #define IT8XXX2_GPIO_GCR23_OFFSET 0xe8
1148 #define IT8XXX2_GPIO_GCR24_OFFSET 0xe9
1149 #define IT8XXX2_GPIO_GCR30_OFFSET 0xed
1150 #define IT8XXX2_GPIO_GCR29_OFFSET 0xee
1151 #endif
1152 
1153 /*
1154  * TODO: use pinctrl node instead of following register declarations
1155  *       to fix in tcpm\it83xx_pd.h.
1156  */
1157 #define IT8XXX2_GPIO2_BASE 0x00F03E00
1158 
1159 #define IT8XXX2_GPIO_GPCRP0     ECREG(IT8XXX2_GPIO2_BASE + 0x18)
1160 #define IT8XXX2_GPIO_GPCRP1     ECREG(IT8XXX2_GPIO2_BASE + 0x19)
1161 
1162 
1163 /**
1164  *
1165  * (19xxh) Analog to Digital Converter (ADC) registers
1166  *
1167  */
1168 #ifndef __ASSEMBLER__
1169 
1170 /* Data structure to define ADC channel 13-16 control registers. */
1171 struct adc_vchs_ctrl_t {
1172 	/* 0x60: Voltage Channel Control */
1173 	volatile uint8_t VCHCTL;
1174 	/* 0x61: Voltage Channel Data Buffer MSB */
1175 	volatile uint8_t VCHDATM;
1176 	/* 0x62: Voltage Channel Data Buffer LSB */
1177 	volatile uint8_t VCHDATL;
1178 };
1179 
1180 struct adc_it8xxx2_regs {
1181 	/* 0x00: ADC Status */
1182 	volatile uint8_t ADCSTS;
1183 	/* 0x01: ADC Configuration */
1184 	volatile uint8_t ADCCFG;
1185 	/* 0x02: ADC Clock Control */
1186 	volatile uint8_t ADCCTL;
1187 	/* 0x03: General Control */
1188 	volatile uint8_t ADCGCR;
1189 	/* 0x04: Voltage Channel 0 Control */
1190 	volatile uint8_t VCH0CTL;
1191 	/* 0x05: Calibration Data Control */
1192 	volatile uint8_t KDCTL;
1193 	/* 0x06-0x17: Reserved1 */
1194 	volatile uint8_t reserved1[18];
1195 	/* 0x18: Voltage Channel 0 Data Buffer LSB */
1196 	volatile uint8_t VCH0DATL;
1197 	/* 0x19: Voltage Channel 0 Data Buffer MSB */
1198 	volatile uint8_t VCH0DATM;
1199 	/* 0x1a-0x43: Reserved2 */
1200 	volatile uint8_t reserved2[42];
1201 	/* 0x44: ADC Data Valid Status */
1202 	volatile uint8_t ADCDVSTS;
1203 	/* 0x45-0x54: Reserved2-1 */
1204 	volatile uint8_t reserved2_1[16];
1205 	/* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */
1206 	volatile uint8_t ADCIVMFSCS1;
1207 	/* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */
1208 	volatile uint8_t ADCIVMFSCS2;
1209 	/* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */
1210 	volatile uint8_t ADCIVMFSCS3;
1211 	/* 0x58-0x5f: Reserved3 */
1212 	volatile uint8_t reserved3[8];
1213 	/* 0x60-0x6b: ADC channel 13~16 controller */
1214 	struct adc_vchs_ctrl_t adc_vchs_ctrl[4];
1215 	/* 0x6c: ADC Data Valid Status 2 */
1216 	volatile uint8_t ADCDVSTS2;
1217 	/* 0x6d-0xef: Reserved4 */
1218 	volatile uint8_t reserved4[131];
1219 	/* 0xf0: ADC Clock Control Register 1 */
1220 	volatile uint8_t ADCCTL1;
1221 };
1222 #endif /* !__ASSEMBLER__ */
1223 
1224 /* ADC conversion time select 1 */
1225 #define IT8XXX2_ADC_ADCCTS1			BIT(7)
1226 /* Analog accuracy initialization */
1227 #define IT8XXX2_ADC_AINITB			BIT(3)
1228 /* ADC conversion time select 0 */
1229 #define IT8XXX2_ADC_ADCCTS0			BIT(5)
1230 /* ADC module enable */
1231 #define IT8XXX2_ADC_ADCEN			BIT(0)
1232 /* ADC data buffer keep enable */
1233 #define IT8XXX2_ADC_DBKEN			BIT(7)
1234 /* W/C data valid flag */
1235 #define IT8XXX2_ADC_DATVAL			BIT(7)
1236 /* Data valid interrupt of adc */
1237 #define IT8XXX2_ADC_INTDVEN			BIT(5)
1238 /* Voltage channel enable (Channel 4~7 and 13~16) */
1239 #define IT8XXX2_ADC_VCHEN			BIT(4)
1240 /* Automatic hardware calibration enable */
1241 #define IT8XXX2_ADC_AHCE			BIT(7)
1242 /* 0x046, 0x049, 0x04c, 0x06e, 0x071, 0x074: Voltage comparator x control */
1243 #define IT8XXX2_VCMP_CMPEN			BIT(7)
1244 #define IT8XXX2_VCMP_CMPINTEN			BIT(6)
1245 #define IT8XXX2_VCMP_GREATER_THRESHOLD		BIT(5)
1246 #define IT8XXX2_VCMP_EDGE_TRIGGER		BIT(4)
1247 #define IT8XXX2_VCMP_GPIO_ACTIVE_LOW		BIT(3)
1248 /* 0x077~0x07c: Voltage comparator x channel select MSB */
1249 #define IT8XXX2_VCMP_VCMPXCSELM			BIT(0)
1250 
1251 /**
1252  *
1253  * (1Exxh) Clock and Power Management (ECPM) registers
1254  *
1255  */
1256 #define IT8XXX2_ECPM_BASE  0x00F01E00
1257 
1258 #ifndef __ASSEMBLER__
1259 enum chip_pll_mode {
1260 	CHIP_PLL_DOZE = 0,
1261 	CHIP_PLL_SLEEP = 1,
1262 	CHIP_PLL_DEEP_DOZE = 3,
1263 };
1264 #endif
1265 /*
1266  * TODO: use ecpm_it8xxx2_regs instead of following register declarations
1267  *       to fix in soc.c.
1268  */
1269 #define IT8XXX2_ECPM_PLLCTRL    ECREG(IT8XXX2_ECPM_BASE + 0x03)
1270 #define IT8XXX2_ECPM_AUTOCG     ECREG(IT8XXX2_ECPM_BASE + 0x04)
1271 #define IT8XXX2_ECPM_CGCTRL3R   ECREG(IT8XXX2_ECPM_BASE + 0x05)
1272 #define IT8XXX2_ECPM_PLLFREQR   ECREG(IT8XXX2_ECPM_BASE + 0x06)
1273 #define IT8XXX2_ECPM_PLLCSS     ECREG(IT8XXX2_ECPM_BASE + 0x08)
1274 #define IT8XXX2_ECPM_SCDCR0     ECREG(IT8XXX2_ECPM_BASE + 0x0c)
1275 #define IT8XXX2_ECPM_SCDCR1     ECREG(IT8XXX2_ECPM_BASE + 0x0d)
1276 #define IT8XXX2_ECPM_SCDCR2     ECREG(IT8XXX2_ECPM_BASE + 0x0e)
1277 #define IT8XXX2_ECPM_SCDCR3     ECREG(IT8XXX2_ECPM_BASE + 0x0f)
1278 #define IT8XXX2_ECPM_SCDCR4     ECREG(IT8XXX2_ECPM_BASE + 0x10)
1279 
1280 /*
1281  * The count number of the counter for 25 ms register.
1282  * The 25 ms register is calculated by (count number *1.024 kHz).
1283  */
1284 
1285 #define I2C_CLK_LOW_TIMEOUT		255 /* ~=249 ms */
1286 
1287 /**
1288  *
1289  * (1Cxxh) SMBus Interface (SMB) registers
1290  *
1291  */
1292 #define IT8XXX2_SMB_BASE            0x00F01C00
1293 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
1294 #define IT8XXX2_SMB_4P7USL          ECREG(IT8XXX2_SMB_BASE + 0x00)
1295 #define IT8XXX2_SMB_4P0USL          ECREG(IT8XXX2_SMB_BASE + 0x01)
1296 #define IT8XXX2_SMB_300NS           ECREG(IT8XXX2_SMB_BASE + 0x02)
1297 #define IT8XXX2_SMB_250NS           ECREG(IT8XXX2_SMB_BASE + 0x03)
1298 #define IT8XXX2_SMB_25MS            ECREG(IT8XXX2_SMB_BASE + 0x04)
1299 #define IT8XXX2_SMB_45P3USL         ECREG(IT8XXX2_SMB_BASE + 0x05)
1300 #define IT8XXX2_SMB_45P3USH         ECREG(IT8XXX2_SMB_BASE + 0x06)
1301 #define IT8XXX2_SMB_4P7A4P0H        ECREG(IT8XXX2_SMB_BASE + 0x07)
1302 #define IT8XXX2_SMB_SLVISELR        ECREG(IT8XXX2_SMB_BASE + 0x08)
1303 #define IT8XXX2_SMB_SCLKTS(ch)      ECREG(IT8XXX2_SMB_BASE + 0x09 + ch)
1304 #define IT8XXX2_SMB_MSTFCTRL1       ECREG(IT8XXX2_SMB_BASE + 0x0D)
1305 #define IT8XXX2_SMB_MSTFSTS1        ECREG(IT8XXX2_SMB_BASE + 0x0E)
1306 #define IT8XXX2_SMB_MSTFCTRL2       ECREG(IT8XXX2_SMB_BASE + 0x0F)
1307 #define IT8XXX2_SMB_MSTFSTS2        ECREG(IT8XXX2_SMB_BASE + 0x10)
1308 #define IT8XXX2_SMB_SMB45CHS        ECREG(IT8XXX2_SMB_BASE + 0x11)
1309 #define IT8XXX2_SMB_I2CW2RF         ECREG(IT8XXX2_SMB_BASE + 0x12)
1310 #define IT8XXX2_SMB_IWRFISTA        ECREG(IT8XXX2_SMB_BASE + 0x13)
1311 #define IT8XXX2_SMB_SMB01CHS        ECREG(IT8XXX2_SMB_BASE + 0x20)
1312 #define IT8XXX2_SMB_SMB23CHS        ECREG(IT8XXX2_SMB_BASE + 0x21)
1313 #define IT8XXX2_SMB_SFFCTL          ECREG(IT8XXX2_SMB_BASE + 0x55)
1314 #define IT8XXX2_SMB_HOSTA(base)     ECREG(base + 0x00)
1315 #define IT8XXX2_SMB_HOCTL(base)     ECREG(base + 0x01)
1316 #define IT8XXX2_SMB_HOCMD(base)     ECREG(base + 0x02)
1317 #define IT8XXX2_SMB_TRASLA(base)    ECREG(base + 0x03)
1318 #define IT8XXX2_SMB_D0REG(base)     ECREG(base + 0x04)
1319 #define IT8XXX2_SMB_D1REG(base)     ECREG(base + 0x05)
1320 #define IT8XXX2_SMB_HOBDB(base)     ECREG(base + 0x06)
1321 #define IT8XXX2_SMB_PECERC(base)    ECREG(base + 0x07)
1322 #define IT8XXX2_SMB_SMBPCTL(base)   ECREG(base + 0x0A)
1323 #define IT8XXX2_SMB_HOCTL2(base)    ECREG(base + 0x10)
1324 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
1325 #define IT8XXX2_SMB_SLVISEL         ECREG(IT8XXX2_SMB_BASE + 0x08)
1326 #define IT8XXX2_SMB_SMB01CHS        ECREG(IT8XXX2_SMB_BASE + 0x09)
1327 #define IT8XXX2_SMB_SMB23CHS        ECREG(IT8XXX2_SMB_BASE + 0x0A)
1328 #define IT8XXX2_SMB_SMB45CHS        ECREG(IT8XXX2_SMB_BASE + 0x0B)
1329 #define IT8XXX2_SMB_SCLKTS_BRGS     ECREG(IT8XXX2_SMB_BASE + 0x80)
1330 #define IT8XXX2_SMB_SCLKTS_BRGM     ECREG(IT8XXX2_SMB_BASE + 0x81)
1331 #define IT8XXX2_SMB_CHSBRG          ECREG(IT8XXX2_SMB_BASE + 0x82)
1332 #define IT8XXX2_SMB_CHSMOT          ECREG(IT8XXX2_SMB_BASE + 0x83)
1333 
1334 /* SMBus register fields */
1335 /* 0x80: SMCLK Timing Setting Register Bridge Slave */
1336 #define IT8XXX2_SMB_PREDEN            BIT(7)
1337 #endif
1338 
1339 /**
1340  * Enhanced SMBus/I2C Interface
1341  * Ch_D: 0x00F03680, Ch_E: 0x00F03500, Ch_F: 0x00F03580
1342  * Ch_D: ch = 0x03, Ch_E: ch = 0x00, Ch_F: ch = 0x01
1343  */
1344 #define IT8XXX2_I2C_DRR(base)         ECREG(base + 0x00)
1345 #define IT8XXX2_I2C_PSR(base)         ECREG(base + 0x01)
1346 #define IT8XXX2_I2C_HSPR(base)        ECREG(base + 0x02)
1347 #define IT8XXX2_I2C_STR(base)         ECREG(base + 0x03)
1348 #define IT8XXX2_I2C_DHTR(base)        ECREG(base + 0x04)
1349 #define IT8XXX2_I2C_TOR(base)         ECREG(base + 0x05)
1350 #define IT8XXX2_I2C_DTR(base)         ECREG(base + 0x08)
1351 #define IT8XXX2_I2C_CTR(base)         ECREG(base + 0x09)
1352 #define IT8XXX2_I2C_CTR1(base)        ECREG(base + 0x0A)
1353 #define IT8XXX2_I2C_BYTE_CNT_H(base)  ECREG(base + 0x0B)
1354 #define IT8XXX2_I2C_BYTE_CNT_L(base)  ECREG(base + 0x0C)
1355 #define IT8XXX2_I2C_IRQ_ST(base)      ECREG(base + 0x0D)
1356 #define IT8XXX2_I2C_IDR(base)         ECREG(base + 0x06)
1357 #define IT8XXX2_I2C_TOS(base)         ECREG(base + 0x07)
1358 #define IT8XXX2_I2C_SLV_NUM_H(base)   ECREG(base + 0x10)
1359 #define IT8XXX2_I2C_SLV_NUM_L(base)   ECREG(base + 0x11)
1360 #define IT8XXX2_I2C_STR2(base)        ECREG(base + 0x12)
1361 #define IT8XXX2_I2C_NST(base)         ECREG(base + 0x13)
1362 #define IT8XXX2_I2C_TO_ARB_ST(base)   ECREG(base + 0x18)
1363 #define IT8XXX2_I2C_ERR_ST(base)      ECREG(base + 0x19)
1364 #define IT8XXX2_I2C_FST(base)         ECREG(base + 0x1B)
1365 #define IT8XXX2_I2C_EM(base)          ECREG(base + 0x1C)
1366 #define IT8XXX2_I2C_MODE_SEL(base)    ECREG(base + 0x1D)
1367 #define IT8XXX2_I2C_IDR2(base)        ECREG(base + 0x1F)
1368 #define IT8XXX2_I2C_CTR2(base)        ECREG(base + 0x20)
1369 #define IT8XXX2_I2C_RAMHA(base)       ECREG(base + 0x23)
1370 #define IT8XXX2_I2C_RAMLA(base)       ECREG(base + 0x24)
1371 #define IT8XXX2_I2C_RAMHA2(base)      ECREG(base + 0x2C)
1372 #define IT8XXX2_I2C_RAMLA2(base)      ECREG(base + 0x2D)
1373 #define IT8XXX2_I2C_CMD_ADDH(base)    ECREG(base + 0x25)
1374 #define IT8XXX2_I2C_CMD_ADDL(base)    ECREG(base + 0x26)
1375 #define IT8XXX2_I2C_RAMH2A(base)      ECREG(base + 0x50)
1376 #define IT8XXX2_I2C_CMD_ADDH2(base)   ECREG(base + 0x52)
1377 
1378 /* SMBus/I2C register fields */
1379 /* 0x09-0xB: SMCLK Timing Setting */
1380 #define IT8XXX2_SMB_SMCLKS_1M         4
1381 #define IT8XXX2_SMB_SMCLKS_400K       3
1382 #define IT8XXX2_SMB_SMCLKS_100K       2
1383 #define IT8XXX2_SMB_SMCLKS_50K        1
1384 
1385 /* 0x0E: SMBus FIFO Status 1 */
1386 #define IT8XXX2_SMB_FIFO1_EMPTY       BIT(7)
1387 #define IT8XXX2_SMB_FIFO1_FULL        BIT(6)
1388 /* 0x0D: SMBus FIFO Control 1 */
1389 /* 0x0F: SMBus FIFO Control 2 */
1390 #define IT8XXX2_SMB_BLKDS             BIT(4)
1391 #define IT8XXX2_SMB_FFEN              BIT(3)
1392 #define IT8XXX2_SMB_FFCHSEL2_B        0
1393 #define IT8XXX2_SMB_FFCHSEL2_C        BIT(0)
1394 /* 0x10: SMBus FIFO Status 2 */
1395 #define IT8XXX2_SMB_FIFO2_EMPTY       BIT(7)
1396 #define IT8XXX2_SMB_FIFO2_FULL        BIT(6)
1397 /* 0x12: I2C Wr To Rd FIFO */
1398 #define IT8XXX2_SMB_MAIF              BIT(7)
1399 #define IT8XXX2_SMB_MBCIF             BIT(6)
1400 #define IT8XXX2_SMB_MCIFI             BIT(2)
1401 #define IT8XXX2_SMB_MBIFI             BIT(1)
1402 #define IT8XXX2_SMB_MAIFI             BIT(0)
1403 /* 0x13: I2C Wr To Rd FIFO Interrupt Status */
1404 #define IT8XXX2_SMB_MCIFID            BIT(2)
1405 #define IT8XXX2_SMB_MAIFID            BIT(0)
1406 /* 0x41 0x81 0xC1: Host Control */
1407 #define IT8XXX2_SMB_SRT               BIT(6)
1408 #define IT8XXX2_SMB_LABY              BIT(5)
1409 #define IT8XXX2_SMB_SMCD_EXTND        BIT(4) | BIT(3) | BIT(2)
1410 #define IT8XXX2_SMB_KILL              BIT(1)
1411 #define IT8XXX2_SMB_INTREN            BIT(0)
1412 /* 0x43 0x83 0xC3: Transmit Slave Address */
1413 #define IT8XXX2_SMB_DIR               BIT(0)
1414 /* 0x4A 0x8A 0xCA: SMBus Pin Control */
1415 #define IT8XXX2_SMB_SMBDCS            BIT(1)
1416 #define IT8XXX2_SMB_SMBCS             BIT(0)
1417 /* 0x50 0x90 0xD0: Host Control 2 */
1418 #define IT8XXX2_SMB_SMD_TO_EN         BIT(4)
1419 #define IT8XXX2_SMB_I2C_SW_EN         BIT(3)
1420 #define IT8XXX2_SMB_I2C_SW_WAIT       BIT(2)
1421 #define IT8XXX2_SMB_I2C_EN            BIT(1)
1422 #define IT8XXX2_SMB_SMHEN             BIT(0)
1423 /* 0x55: Slave A FIFO Control */
1424 #define IT8XXX2_SMB_HSAPE             BIT(1)
1425 /* 0x03: Status Register */
1426 #define IT8XXX2_I2C_BYTE_DONE         BIT(7)
1427 #define IT8XXX2_I2C_RW                BIT(2)
1428 #define IT8XXX2_I2C_INT_PEND          BIT(1)
1429 /* 0x04: Data Hold Time */
1430 #define IT8XXX2_I2C_SOFT_RST          BIT(7)
1431 /* 0x07: Time Out Status */
1432 #define IT8XXX2_I2C_CLK_STRETCH       BIT(7)
1433 #define IT8XXX2_I2C_SCL_IN            BIT(2)
1434 #define IT8XXX2_I2C_SDA_IN            BIT(0)
1435 /* 0x09: Control Register */
1436 #define IT8XXX2_I2C_INT_EN            BIT(6)
1437 #define IT8XXX2_I2C_ACK               BIT(3)
1438 #define IT8XXX2_I2C_HALT              BIT(0)
1439 /* 0x0A: Control 1 */
1440 #define IT8XXX2_I2C_COMQ_EN           BIT(7)
1441 #define IT8XXX2_I2C_MDL_EN            BIT(1)
1442 /* 0x0C: Byte count */
1443 #define IT8XXX2_I2C_DMA_ADDR_RELOAD   BIT(5)
1444 #define IT8XXX2_I2C_BYTE_CNT_ENABLE   BIT(3)
1445 /* 0x0D: Interrupt Status */
1446 #define IT8XXX2_I2C_CNT_HOLD          BIT(4)
1447 #define IT8XXX2_I2C_IDW_CLR           BIT(3)
1448 #define IT8XXX2_I2C_IDR_CLR           BIT(2)
1449 #define IT8XXX2_I2C_SLVDATAFLG        BIT(1)
1450 #define IT8XXX2_I2C_P_CLR             BIT(0)
1451 /* 0x13: Nack Status */
1452 #define IT8XXX2_I2C_NST_CNS           BIT(7)
1453 #define IT8XXX2_I2C_NST_ID_NACK       BIT(3)
1454 /* 0x18: Timeout and Arbiter Status */
1455 #define IT8XXX2_I2C_SCL_TIMEOUT_EN    BIT(7)
1456 #define IT8XXX2_I2C_SDA_TIMEOUT_EN    BIT(6)
1457 /* 0x19: Error Status */
1458 #define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ  BIT(0)
1459 /* 0x1B: Finish Status */
1460 #define IT8XXX2_I2C_FST_DEV1_IRQ      BIT(4)
1461 /* 0x1C: Error Mask */
1462 #define IT8XXX2_I2C_EM_DEV1_IRQ       BIT(4)
1463 
1464 /*
1465  * TODO: use gctrl_it8xxx2_regs instead of following register declarations
1466  *       to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c.
1467  */
1468 /* --- General Control (GCTRL) --- */
1469 #define IT83XX_GCTRL_BASE 0x00F02000
1470 
1471 #define IT83XX_GCTRL_CHIPID1         ECREG(IT83XX_GCTRL_BASE + 0x85)
1472 #define IT83XX_GCTRL_CHIPID2         ECREG(IT83XX_GCTRL_BASE + 0x86)
1473 #define IT83XX_GCTRL_CHIPVER         ECREG(IT83XX_GCTRL_BASE + 0x02)
1474 #define IT83XX_GCTRL_MCCR3           ECREG(IT83XX_GCTRL_BASE + 0x20)
1475 #define IT83XX_GCTRL_SPISLVPFE             BIT(6)
1476 #define IT83XX_GCTRL_EWPR0PFH(i)     ECREG(IT83XX_GCTRL_BASE + 0x60 + i)
1477 #define IT83XX_GCTRL_EWPR0PFD(i)     ECREG(IT83XX_GCTRL_BASE + 0xA0 + i)
1478 #define IT83XX_GCTRL_EWPR0PFEC(i)    ECREG(IT83XX_GCTRL_BASE + 0xC0 + i)
1479 
1480 /*
1481  * TODO: use spisc_it8xxx2_regs instead of following register declarations
1482  *       to fix in cros_shi_it8xxx2.c.
1483  */
1484 /* Serial Peripheral Interface (SPI) */
1485 #define IT83XX_SPI_BASE  0x00F03A00
1486 
1487 #define IT83XX_SPI_SPISGCR           ECREG(IT83XX_SPI_BASE + 0x00)
1488 #define IT83XX_SPI_SPISCEN                 BIT(0)
1489 #define IT83XX_SPI_TXRXFAR           ECREG(IT83XX_SPI_BASE + 0x01)
1490 #define IT83XX_SPI_CPURXF2A                BIT(4)
1491 #define IT83XX_SPI_CPURXF1A                BIT(3)
1492 #define IT83XX_SPI_CPUTFA                  BIT(1)
1493 #define IT83XX_SPI_TXFCR             ECREG(IT83XX_SPI_BASE + 0x02)
1494 #define IT83XX_SPI_TXFCMR                  BIT(2)
1495 #define IT83XX_SPI_TXFR                    BIT(1)
1496 #define IT83XX_SPI_TXFS                    BIT(0)
1497 #define IT83XX_SPI_GCR2              ECREG(IT83XX_SPI_BASE + 0x03)
1498 #define IT83XX_SPI_RXF2OC                  BIT(4)
1499 #define IT83XX_SPI_RXF1OC                  BIT(3)
1500 #define IT83XX_SPI_RXFAR                   BIT(0)
1501 #define IT83XX_SPI_IMR               ECREG(IT83XX_SPI_BASE + 0x04)
1502 #define IT83XX_SPI_RX_FIFO_FULL            BIT(7)
1503 #define IT83XX_SPI_RX_REACH                BIT(5)
1504 #define IT83XX_SPI_EDIM                    BIT(2)
1505 #define IT83XX_SPI_ISR               ECREG(IT83XX_SPI_BASE + 0x05)
1506 #define IT83XX_SPI_TXFSR             ECREG(IT83XX_SPI_BASE + 0x06)
1507 #define IT83XX_SPI_ENDDETECTINT            BIT(2)
1508 #define IT83XX_SPI_RXFSR             ECREG(IT83XX_SPI_BASE + 0x07)
1509 #define IT83XX_SPI_RXFFSM                  (BIT(4) | BIT(3))
1510 #define IT83XX_SPI_RXF2FS                  BIT(2)
1511 #define IT83XX_SPI_RXF1FS                  BIT(1)
1512 #define IT83XX_SPI_SPISRDR           ECREG(IT83XX_SPI_BASE + 0x0b)
1513 #define IT83XX_SPI_CPUWTFDB0         ECREG_u32(IT83XX_SPI_BASE + 0x08)
1514 #define IT83XX_SPI_FCR               ECREG(IT83XX_SPI_BASE + 0x09)
1515 #define IT83XX_SPI_SPISRTXF                BIT(2)
1516 #define IT83XX_SPI_RXFR                    BIT(1)
1517 #define IT83XX_SPI_RXFCMR                  BIT(0)
1518 #define IT83XX_SPI_RXFRDRB0          ECREG_u32(IT83XX_SPI_BASE + 0x0C)
1519 #define IT83XX_SPI_FTCB0R            ECREG(IT83XX_SPI_BASE + 0x18)
1520 #define IT83XX_SPI_FTCB1R            ECREG(IT83XX_SPI_BASE + 0x19)
1521 #define IT83XX_SPI_TCCB0             ECREG(IT83XX_SPI_BASE + 0x1A)
1522 #define IT83XX_SPI_TCCB1             ECREG(IT83XX_SPI_BASE + 0x1B)
1523 #define IT83XX_SPI_HPR2              ECREG(IT83XX_SPI_BASE + 0x1E)
1524 #define IT83XX_SPI_EMMCBMR           ECREG(IT83XX_SPI_BASE + 0x21)
1525 #define IT83XX_SPI_EMMCABM                 BIT(1) /* eMMC Alternative Boot Mode */
1526 #define IT83XX_SPI_RX_VLISMR         ECREG(IT83XX_SPI_BASE + 0x26)
1527 #define IT83XX_SPI_RVLIM                   BIT(0)
1528 #define IT83XX_SPI_RX_VLISR          ECREG(IT83XX_SPI_BASE + 0x27)
1529 #define IT83XX_SPI_RVLI                    BIT(0)
1530 
1531 /**
1532  *
1533  * (20xxh) General Control (GCTRL) registers
1534  *
1535  */
1536 #define GCTRL_IT8XXX2_REGS_BASE \
1537 	((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
1538 
1539 #ifndef __ASSEMBLER__
1540 struct gctrl_it8xxx2_regs {
1541 	/* 0x00-0x01: Reserved_00_01 */
1542 	volatile uint8_t reserved_00_01[2];
1543 	/* 0x02: Chip Version */
1544 	volatile uint8_t GCTRL_ECHIPVER;
1545 	/* 0x03-0x05: Reserved_03_05 */
1546 	volatile uint8_t reserved_03_05[3];
1547 	/* 0x06: Reset Status */
1548 	volatile uint8_t GCTRL_RSTS;
1549 	/* 0x07-0x09: Reserved_07_09 */
1550 	volatile uint8_t reserved_07_09[3];
1551 	/* 0x0A: Base Address Select */
1552 	volatile uint8_t GCTRL_BADRSEL;
1553 	/* 0x0B: Wait Next Clock Rising */
1554 	volatile uint8_t GCTRL_WNCKR;
1555 	/* 0x0C: reserved_0c */
1556 	volatile uint8_t reserved_0c;
1557 	/* 0x0D: Special Control 1 */
1558 	volatile uint8_t GCTRL_SPCTRL1;
1559 	/* 0x0E-0x0F: reserved_0e_0f */
1560 	volatile uint8_t reserved_0e_0f[2];
1561 	/* 0x10: Reset Control DMM */
1562 	volatile uint8_t GCTRL_RSTDMMC;
1563 	/* 0x11: Reset Control 4 */
1564 	volatile uint8_t GCTRL_RSTC4;
1565 	/* 0x12-0x1B: reserved_12_1b */
1566 	volatile uint8_t reserved_12_1b[10];
1567 	/* 0x1C: Special Control 4 */
1568 	volatile uint8_t GCTRL_SPCTRL4;
1569 	/* 0x1D-0x1F: reserved_1d_1f */
1570 	volatile uint8_t reserved_1d_1f[3];
1571 	/* 0x20: Memory Controller Configuration 3 */
1572 	volatile uint8_t GCTRL_MCCR3;
1573 	/* 0x21: Reset Control 5 */
1574 	volatile uint8_t GCTRL_RSTC5;
1575 	/* 0x22-0x2F: reserved_22_2f */
1576 	volatile uint8_t reserved_22_2f[14];
1577 	/* 0x30: Memory Controller Configuration */
1578 	volatile uint8_t GCTRL_MCCR;
1579 	/* 0x31: Externel ILM/DLM Size */
1580 	volatile uint8_t GCTRL_EIDSR;
1581 	/* 0x32: Reserved_32 */
1582 	volatile uint8_t reserved_32;
1583 	/* 0x33: Pin Multi-function Enable 2 */
1584 	volatile uint8_t gctrl_pmer2;
1585 	/* 0x34-0x36: Reserved_34_36 */
1586 	volatile uint8_t reserved_34_36[3];
1587 	/* 0x37: Eflash Protect Lock */
1588 	volatile uint8_t GCTRL_EPLR;
1589 	/* 0x38-0x40: Reserved_38_40 */
1590 	volatile uint8_t reserved_38_40[9];
1591 	/* 0x41: Interrupt Vector Table Base Address */
1592 	volatile uint8_t GCTRL_IVTBAR;
1593 	/* 0x42-0x43: Reserved_42_43 */
1594 	volatile uint8_t reserved_42_43[2];
1595 	/* 0x44: Memory Controller Configuration 2 */
1596 	volatile uint8_t GCTRL_MCCR2;
1597 	/* 0x45: Reserved_45 */
1598 	volatile uint8_t reserved_45;
1599 	/* 0x46: Pin Multi-function Enable 3 */
1600 	volatile uint8_t GCTRL_PMER3;
1601 	/* 0x47-0x4A: reserved_47_4a */
1602 	volatile uint8_t reserved_47_4a[4];
1603 	/* 0x4B: ETWD and UART Control */
1604 	volatile uint8_t GCTRL_ETWDUARTCR;
1605 	/* 0x4C: Wakeup MCU Control */
1606 	volatile uint8_t GCTRL_WMCR;
1607 	/* 0x4D-0x4F: reserved_4d_4f */
1608 	volatile uint8_t reserved_4d_4f[3];
1609 	/* 0x50: Port 80h/81h Status Register */
1610 	volatile uint8_t GCTRL_P80H81HSR;
1611 	/* 0x51: Port 80h Data Register */
1612 	volatile uint8_t GCTRL_P80HDR;
1613 	/* 0x52: Port 81h Data Register */
1614 	volatile uint8_t GCTRL_P81HDR;
1615 	/* 0x53: H2RAM Offset Register */
1616 	volatile uint8_t GCTRL_H2ROFSR;
1617 	/* 0x54-0x5C: reserved_54_5c */
1618 	volatile uint8_t reserved_54_5c[9];
1619 	/* 0x5D: RISCV ILM Configuration 0 */
1620 	volatile uint8_t GCTRL_RVILMCR0;
1621 	/* 0x5E-0x84: reserved_5e_84 */
1622 	volatile uint8_t reserved_5e_84[39];
1623 	/* 0x85: Chip ID Byte 1 */
1624 	volatile uint8_t GCTRL_ECHIPID1;
1625 	/* 0x86: Chip ID Byte 2 */
1626 	volatile uint8_t GCTRL_ECHIPID2;
1627 	/* 0x87: Chip ID Byte 3 */
1628 	volatile uint8_t GCTRL_ECHIPID3;
1629 };
1630 #endif /* !__ASSEMBLER__ */
1631 
1632 /* GCTRL register fields */
1633 /* 0x06: Reset Status */
1634 #define IT8XXX2_GCTRL_LRS		(BIT(1) | BIT(0))
1635 #define IT8XXX2_GCTRL_IWDTR		BIT(1)
1636 /* 0x0B: Wait Next 65K Rising */
1637 #define IT8XXX2_GCTRL_WN65K		0x00
1638 /* 0x10: Reset Control DMM */
1639 #define IT8XXX2_GCTRL_UART1SD		BIT(3)
1640 #define IT8XXX2_GCTRL_UART2SD		BIT(2)
1641 /* 0x11: Reset Control 4 */
1642 #define IT8XXX2_GCTRL_RPECI		BIT(4)
1643 #define IT8XXX2_GCTRL_RUART2		BIT(2)
1644 #define IT8XXX2_GCTRL_RUART1		BIT(1)
1645 /* 0x1C: Special Control 4 */
1646 #define IT8XXX2_GCTRL_LRSIWR		BIT(2)
1647 #define IT8XXX2_GCTRL_LRSIPWRSWTR	BIT(1)
1648 #define IT8XXX2_GCTRL_LRSIPGWR		BIT(0)
1649 /* 0x20: Memory Controller Configuration 3 */
1650 #define IT8XXX2_GCTRL_SPISLVPFE		BIT(6)
1651 /* 0x30: Memory Controller Configuration */
1652 #define IT8XXX2_GCTRL_ICACHE_RESET	BIT(4)
1653 /* 0x37: Eflash Protect Lock */
1654 #define IT8XXX2_GCTRL_EPLR_ENABLE	BIT(0)
1655 /* 0x46: Pin Multi-function Enable 3 */
1656 #define IT8XXX2_GCTRL_SMB3PSEL		BIT(6)
1657 #define IT8XXX2_GCTRL_SRAM_CRYPTO_USED	BIT(5)
1658 /* 0x4B: ETWD and UART Control */
1659 #define IT8XXX2_GCTRL_ETWD_HW_RST_EN	BIT(0)
1660 /* 0x5D: RISCV ILM Configuration 0 */
1661 #define IT8XXX2_GCTRL_ILM0_ENABLE	BIT(0)
1662 /* Accept Port 80h Cycle */
1663 #define IT8XXX2_GCTRL_ACP80		BIT(6)
1664 /* Accept Port 81h Cycle */
1665 #define IT8XXX2_GCTRL_ACP81		BIT(3)
1666 /* USB Debug Enable */
1667 #define IT8XXX2_GCTRL_MCCR_USB_EN	BIT(7)
1668 /* USB Pad Power-On Enable */
1669 #define IT8XXX2_GCTRL_PMER2_USB_PAD_EN	BIT(7)
1670 
1671 /*
1672  * VCC Detector Option.
1673  * bit[7-6] = 1: The VCC power status is treated as power-on.
1674  * The VCC supply of eSPI and related functions (EC2I, KBC, PMC and
1675  * PECI). It means VCC should be logic high before using these
1676  * functions, or firmware treats VCC logic high.
1677  */
1678 #define IT8XXX2_GCTRL_VCCDO_MASK	(BIT(6) | BIT(7))
1679 #define IT8XXX2_GCTRL_VCCDO_VCC_ON	BIT(6)
1680 /*
1681  * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH
1682  * register and WRST#.
1683  */
1684 #define IT8XXX2_GCTRL_HGRST		BIT(3)
1685 /* bit[2] = 1: Enable global reset. */
1686 #define IT8XXX2_GCTRL_GRST		BIT(2)
1687 
1688 /**
1689  *
1690  * (22xxh) Battery-backed SRAM (BRAM) registers
1691  *
1692  */
1693 #ifndef __ASSEMBLER__
1694 /* Battery backed RAM indices. */
1695 #define BRAM_MAGIC_FIELD_OFFSET 0xbc
1696 enum bram_indices {
1697 
1698 	/* This field is used to indicate BRAM is valid or not. */
1699 	BRAM_IDX_VALID_FLAGS0 = BRAM_MAGIC_FIELD_OFFSET,
1700 	BRAM_IDX_VALID_FLAGS1,
1701 	BRAM_IDX_VALID_FLAGS2,
1702 	BRAM_IDX_VALID_FLAGS3
1703 };
1704 #endif /* !__ASSEMBLER__ */
1705 
1706 #ifndef __ASSEMBLER__
1707 /*
1708  * EC2I bridge registers
1709  */
1710 struct ec2i_regs {
1711 	/* 0x00: Indirect Host I/O Address Register */
1712 	volatile uint8_t IHIOA;
1713 	/* 0x01: Indirect Host Data Register */
1714 	volatile uint8_t IHD;
1715 	/* 0x02: Lock Super I/O Host Access Register */
1716 	volatile uint8_t LSIOHA;
1717 	/* 0x03: Super I/O Access Lock Violation Register */
1718 	volatile uint8_t SIOLV;
1719 	/* 0x04: EC to I-Bus Modules Access Enable Register */
1720 	volatile uint8_t IBMAE;
1721 	/* 0x05: I-Bus Control Register */
1722 	volatile uint8_t IBCTL;
1723 };
1724 
1725 /* Index list of the host interface registers of PNPCFG */
1726 enum host_pnpcfg_index {
1727 	/* Logical Device Number */
1728 	HOST_INDEX_LDN = 0x07,
1729 	/* Chip ID Byte 1 */
1730 	HOST_INDEX_CHIPID1 = 0x20,
1731 	/* Chip ID Byte 2 */
1732 	HOST_INDEX_CHIPID2 = 0x21,
1733 	/* Chip Version */
1734 	HOST_INDEX_CHIPVER = 0x22,
1735 	/* Super I/O Control */
1736 	HOST_INDEX_SIOCTRL = 0x23,
1737 	/* Super I/O IRQ Configuration */
1738 	HOST_INDEX_SIOIRQ = 0x25,
1739 	/* Super I/O General Purpose */
1740 	HOST_INDEX_SIOGP = 0x26,
1741 	/* Super I/O Power Mode */
1742 	HOST_INDEX_SIOPWR = 0x2D,
1743 	/* Depth 2 I/O Address */
1744 	HOST_INDEX_D2ADR = 0x2E,
1745 	/* Depth 2 I/O Data */
1746 	HOST_INDEX_D2DAT = 0x2F,
1747 	/* Logical Device Activate Register */
1748 	HOST_INDEX_LDA = 0x30,
1749 	/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
1750 	HOST_INDEX_IOBAD0_MSB = 0x60,
1751 	/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
1752 	HOST_INDEX_IOBAD0_LSB = 0x61,
1753 	/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
1754 	HOST_INDEX_IOBAD1_MSB = 0x62,
1755 	/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
1756 	HOST_INDEX_IOBAD1_LSB = 0x63,
1757 	/* Interrupt Request Number and Wake-Up on IRQ Enabled */
1758 	HOST_INDEX_IRQNUMX = 0x70,
1759 	/* Interrupt Request Type Select */
1760 	HOST_INDEX_IRQTP = 0x71,
1761 	/* DMA Channel Select 0 */
1762 	HOST_INDEX_DMAS0 = 0x74,
1763 	/* DMA Channel Select 1 */
1764 	HOST_INDEX_DMAS1 = 0x75,
1765 	/* Device Specific Logical Device Configuration 1 to 10 */
1766 	HOST_INDEX_DSLDC1 = 0xF0,
1767 	HOST_INDEX_DSLDC2 = 0xF1,
1768 	HOST_INDEX_DSLDC3 = 0xF2,
1769 	HOST_INDEX_DSLDC4 = 0xF3,
1770 	HOST_INDEX_DSLDC5 = 0xF4,
1771 	HOST_INDEX_DSLDC6 = 0xF5,
1772 	HOST_INDEX_DSLDC7 = 0xF6,
1773 	HOST_INDEX_DSLDC8 = 0xF7,
1774 	HOST_INDEX_DSLDC9 = 0xF8,
1775 	HOST_INDEX_DSLDC10 = 0xF9,
1776 };
1777 
1778 /* List of logical device number (LDN) assignments */
1779 enum logical_device_number {
1780 	/* Serial Port 1 */
1781 	LDN_UART1 = 0x01,
1782 	/* Serial Port 2 */
1783 	LDN_UART2 = 0x02,
1784 	/* System Wake-Up Control */
1785 	LDN_SWUC = 0x04,
1786 	/* KBC/Mouse Interface */
1787 	LDN_KBC_MOUSE = 0x05,
1788 	/* KBC/Keyboard Interface */
1789 	LDN_KBC_KEYBOARD = 0x06,
1790 	/* Consumer IR */
1791 	LDN_CIR = 0x0A,
1792 	/* Shared Memory/Flash Interface */
1793 	LDN_SMFI = 0x0F,
1794 	/* RTC-like Timer */
1795 	LDN_RTCT = 0x10,
1796 	/* Power Management I/F Channel 1 */
1797 	LDN_PMC1 = 0x11,
1798 	/* Power Management I/F Channel 2 */
1799 	LDN_PMC2 = 0x12,
1800 	/* Serial Peripheral Interface */
1801 	LDN_SSPI = 0x13,
1802 	/* Platform Environment Control Interface */
1803 	LDN_PECI = 0x14,
1804 	/* Power Management I/F Channel 3 */
1805 	LDN_PMC3 = 0x17,
1806 	/* Power Management I/F Channel 4 */
1807 	LDN_PMC4 = 0x18,
1808 	/* Power Management I/F Channel 5 */
1809 	LDN_PMC5 = 0x19,
1810 };
1811 
1812 /* Structure for initializing PNPCFG via ec2i. */
1813 struct ec2i_t {
1814 	/* index port */
1815 	enum host_pnpcfg_index index_port;
1816 	/* data port */
1817 	uint8_t data_port;
1818 };
1819 
1820 /* EC2I access index/data port */
1821 enum ec2i_access {
1822 	/* index port */
1823 	EC2I_ACCESS_INDEX = 0,
1824 	/* data port */
1825 	EC2I_ACCESS_DATA = 1,
1826 };
1827 
1828 /* EC to I-Bus Access Enabled */
1829 #define EC2I_IBCTL_CSAE  BIT(0)
1830 /* EC Read from I-Bus */
1831 #define EC2I_IBCTL_CRIB  BIT(1)
1832 /* EC Write to I-Bus */
1833 #define EC2I_IBCTL_CWIB  BIT(2)
1834 #define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB)
1835 
1836 /* PNPCFG Register EC Access Enable */
1837 #define EC2I_IBMAE_CFGAE BIT(0)
1838 
1839 /*
1840  * KBC registers
1841  */
1842 struct kbc_regs {
1843 	/* 0x00: KBC Host Interface Control Register */
1844 	volatile uint8_t KBHICR;
1845 	/* 0x01: Reserved1 */
1846 	volatile uint8_t reserved1;
1847 	/* 0x02: KBC Interrupt Control Register */
1848 	volatile uint8_t KBIRQR;
1849 	/* 0x03: Reserved2 */
1850 	volatile uint8_t reserved2;
1851 	/* 0x04: KBC Host Interface Keyboard/Mouse Status Register */
1852 	volatile uint8_t KBHISR;
1853 	/* 0x05: Reserved3 */
1854 	volatile uint8_t reserved3;
1855 	/* 0x06: KBC Host Interface Keyboard Data Output Register */
1856 	volatile uint8_t KBHIKDOR;
1857 	/* 0x07: Reserved4 */
1858 	volatile uint8_t reserved4;
1859 	/* 0x08: KBC Host Interface Mouse Data Output Register */
1860 	volatile uint8_t KBHIMDOR;
1861 	/* 0x09: Reserved5 */
1862 	volatile uint8_t reserved5;
1863 	/* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */
1864 	volatile uint8_t KBHIDIR;
1865 };
1866 
1867 /* Output Buffer Full */
1868 #define KBC_KBHISR_OBF      BIT(0)
1869 /* Input Buffer Full */
1870 #define KBC_KBHISR_IBF      BIT(1)
1871 /* A2 Address (A2) */
1872 #define KBC_KBHISR_A2_ADDR  BIT(3)
1873 #define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF \
1874 						| KBC_KBHISR_A2_ADDR)
1875 
1876 /* Clear Output Buffer Full */
1877 #define KBC_KBHICR_COBF      BIT(6)
1878 /* IBF/OBF Clear Mode Enable */
1879 #define KBC_KBHICR_IBFOBFCME BIT(5)
1880 /* Input Buffer Full CPU Interrupt Enable */
1881 #define KBC_KBHICR_IBFCIE    BIT(3)
1882 /* Output Buffer Empty CPU Interrupt Enable */
1883 #define KBC_KBHICR_OBECIE    BIT(2)
1884 /* Output Buffer Full Mouse Interrupt Enable */
1885 #define KBC_KBHICR_OBFMIE    BIT(1)
1886 /* Output Buffer Full Keyboard Interrupt Enable */
1887 #define KBC_KBHICR_OBFKIE    BIT(0)
1888 
1889 /*
1890  * PMC registers
1891  */
1892 struct pmc_regs {
1893 	/* 0x00: Host Interface PM Channel 1 Status */
1894 	volatile uint8_t PM1STS;
1895 	/* 0x01: Host Interface PM Channel 1 Data Out Port */
1896 	volatile uint8_t PM1DO;
1897 	/* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */
1898 	volatile uint8_t PM1DOSCI;
1899 	/* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */
1900 	volatile uint8_t PM1DOSMI;
1901 	/* 0x04: Host Interface PM Channel 1 Data In Port */
1902 	volatile uint8_t PM1DI;
1903 	/* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */
1904 	volatile uint8_t PM1DISCI;
1905 	/* 0x06: Host Interface PM Channel 1 Control */
1906 	volatile uint8_t PM1CTL;
1907 	/* 0x07: Host Interface PM Channel 1 Interrupt Control */
1908 	volatile uint8_t PM1IC;
1909 	/* 0x08: Host Interface PM Channel 1 Interrupt Enable */
1910 	volatile uint8_t PM1IE;
1911 	/* 0x09-0x0f: Reserved1 */
1912 	volatile uint8_t reserved1[7];
1913 	/* 0x10: Host Interface PM Channel 2 Status */
1914 	volatile uint8_t PM2STS;
1915 	/* 0x11: Host Interface PM Channel 2 Data Out Port */
1916 	volatile uint8_t PM2DO;
1917 	/* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */
1918 	volatile uint8_t PM2DOSCI;
1919 	/* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */
1920 	volatile uint8_t PM2DOSMI;
1921 	/* 0x14: Host Interface PM Channel 2 Data In Port */
1922 	volatile uint8_t PM2DI;
1923 	/* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */
1924 	volatile uint8_t PM2DISCI;
1925 	/* 0x16: Host Interface PM Channel 2 Control */
1926 	volatile uint8_t PM2CTL;
1927 	/* 0x17: Host Interface PM Channel 2 Interrupt Control */
1928 	volatile uint8_t PM2IC;
1929 	/* 0x18: Host Interface PM Channel 2 Interrupt Enable */
1930 	volatile uint8_t PM2IE;
1931 	/* 0x19: Mailbox Control */
1932 	volatile uint8_t MBXCTRL;
1933 	/* 0x1a-0x1f: Reserved2 */
1934 	volatile uint8_t reserved2[6];
1935 	/* 0x20-0xff: Reserved3 */
1936 	volatile uint8_t reserved3[0xe0];
1937 };
1938 
1939 /* Input Buffer Full Interrupt Enable */
1940 #define PMC_PM1CTL_IBFIE    BIT(0)
1941 /* Output Buffer Full */
1942 #define PMC_PM1STS_OBF      BIT(0)
1943 /* Input Buffer Full */
1944 #define PMC_PM1STS_IBF      BIT(1)
1945 /* General Purpose Flag */
1946 #define PMC_PM1STS_GPF      BIT(2)
1947 /* A2 Address (A2) */
1948 #define PMC_PM1STS_A2_ADDR  BIT(3)
1949 
1950 /* PMC2 Input Buffer Full Interrupt Enable */
1951 #define PMC_PM2CTL_IBFIE    BIT(0)
1952 /* General Purpose Flag */
1953 #define PMC_PM2STS_GPF      BIT(2)
1954 
1955 /*
1956  * Dedicated Interrupt
1957  * 0b:
1958  * INT3: PMC Output Buffer Empty Int
1959  * INT25: PMC Input Buffer Full Int
1960  * 1b:
1961  * INT3: PMC1 Output Buffer Empty Int
1962  * INT25: PMC1 Input Buffer Full Int
1963  * INT26: PMC2 Output Buffer Empty Int
1964  * INT27: PMC2 Input Buffer Full Int
1965  */
1966 #define PMC_MBXCTRL_DINT    BIT(5)
1967 
1968 /*
1969  * eSPI slave registers
1970  */
1971 struct espi_slave_regs {
1972 	/* 0x00-0x03: Reserved1 */
1973 	volatile uint8_t reserved1[4];
1974 
1975 	/* 0x04: General Capabilities and Configuration 0 */
1976 	volatile uint8_t GCAPCFG0;
1977 	/* 0x05: General Capabilities and Configuration 1 */
1978 	volatile uint8_t GCAPCFG1;
1979 	/* 0x06: General Capabilities and Configuration 2 */
1980 	volatile uint8_t GCAPCFG2;
1981 	/* 0x07: General Capabilities and Configuration 3 */
1982 	volatile uint8_t GCAPCFG3;
1983 
1984 	/* Channel 0 (Peripheral Channel) Capabilities and Configurations */
1985 	/* 0x08: Channel 0 Capabilities and Configuration 0 */
1986 	volatile uint8_t CH_PC_CAPCFG0;
1987 	/* 0x09: Channel 0 Capabilities and Configuration 1 */
1988 	volatile uint8_t CH_PC_CAPCFG1;
1989 	/* 0x0A: Channel 0 Capabilities and Configuration 2 */
1990 	volatile uint8_t CH_PC_CAPCFG2;
1991 	/* 0x0B: Channel 0 Capabilities and Configuration 3 */
1992 	volatile uint8_t CH_PC_CAPCFG3;
1993 
1994 	/* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */
1995 	/* 0x0C: Channel 1 Capabilities and Configuration 0 */
1996 	volatile uint8_t CH_VW_CAPCFG0;
1997 	/* 0x0D: Channel 1 Capabilities and Configuration 1 */
1998 	volatile uint8_t CH_VW_CAPCFG1;
1999 	/* 0x0E: Channel 1 Capabilities and Configuration 2 */
2000 	volatile uint8_t CH_VW_CAPCFG2;
2001 	/* 0x0F: Channel 1 Capabilities and Configuration 3 */
2002 	volatile uint8_t CH_VW_CAPCFG3;
2003 
2004 	/* Channel 2 (OOB Message Channel) Capabilities and Configurations */
2005 	/* 0x10: Channel 2 Capabilities and Configuration 0 */
2006 	volatile uint8_t CH_OOB_CAPCFG0;
2007 	/* 0x11: Channel 2 Capabilities and Configuration 1 */
2008 	volatile uint8_t CH_OOB_CAPCFG1;
2009 	/* 0x12: Channel 2 Capabilities and Configuration 2 */
2010 	volatile uint8_t CH_OOB_CAPCFG2;
2011 	/* 0x13: Channel 2 Capabilities and Configuration 3 */
2012 	volatile uint8_t CH_OOB_CAPCFG3;
2013 
2014 	/* Channel 3 (Flash Access Channel) Capabilities and Configurations */
2015 	/* 0x14: Channel 3 Capabilities and Configuration 0 */
2016 	volatile uint8_t CH_FLASH_CAPCFG0;
2017 	/* 0x15: Channel 3 Capabilities and Configuration 1 */
2018 	volatile uint8_t CH_FLASH_CAPCFG1;
2019 	/* 0x16: Channel 3 Capabilities and Configuration 2 */
2020 	volatile uint8_t CH_FLASH_CAPCFG2;
2021 	/* 0x17: Channel 3 Capabilities and Configuration 3 */
2022 	volatile uint8_t CH_FLASH_CAPCFG3;
2023 	/* Channel 3 Capabilities and Configurations 2 */
2024 	/* 0x18: Channel 3 Capabilities and Configuration 2-0 */
2025 	volatile uint8_t CH_FLASH_CAPCFG2_0;
2026 	/* 0x19: Channel 3 Capabilities and Configuration 2-1 */
2027 	volatile uint8_t CH_FLASH_CAPCFG2_1;
2028 	/* 0x1A: Channel 3 Capabilities and Configuration 2-2 */
2029 	volatile uint8_t CH_FLASH_CAPCFG2_2;
2030 	/* 0x1B: Channel 3 Capabilities and Configuration 2-3 */
2031 	volatile uint8_t CH_FLASH_CAPCFG2_3;
2032 
2033 	/* 0x1c-0x1f: Reserved2 */
2034 	volatile uint8_t reserved2[4];
2035 	/* 0x20-0x8f: Reserved3 */
2036 	volatile uint8_t reserved3[0x70];
2037 
2038 	/* 0x90: eSPI PC Control 0 */
2039 	volatile uint8_t ESPCTRL0;
2040 	/* 0x91: eSPI PC Control 1 */
2041 	volatile uint8_t ESPCTRL1;
2042 	/* 0x92: eSPI PC Control 2 */
2043 	volatile uint8_t ESPCTRL2;
2044 	/* 0x93: eSPI PC Control 3 */
2045 	volatile uint8_t ESPCTRL3;
2046 	/* 0x94: eSPI PC Control 4 */
2047 	volatile uint8_t ESPCTRL4;
2048 	/* 0x95: eSPI PC Control 5 */
2049 	volatile uint8_t ESPCTRL5;
2050 	/* 0x96: eSPI PC Control 6 */
2051 	volatile uint8_t ESPCTRL6;
2052 	/* 0x97: eSPI PC Control 7 */
2053 	volatile uint8_t ESPCTRL7;
2054 	/* 0x98-0x9f: Reserved4 */
2055 	volatile uint8_t reserved4[8];
2056 
2057 	/* 0xa0: eSPI General Control 0 */
2058 	volatile uint8_t ESGCTRL0;
2059 	/* 0xa1: eSPI General Control 1 */
2060 	volatile uint8_t ESGCTRL1;
2061 	/* 0xa2: eSPI General Control 2 */
2062 	volatile uint8_t ESGCTRL2;
2063 	/* 0xa3: eSPI General Control 3 */
2064 	volatile uint8_t ESGCTRL3;
2065 	/* 0xa4-0xaf: Reserved5 */
2066 	volatile uint8_t reserved5[12];
2067 
2068 	/* 0xb0: eSPI Upstream Control 0 */
2069 	volatile uint8_t ESUCTRL0;
2070 	/* 0xb1: eSPI Upstream Control 1 */
2071 	volatile uint8_t ESUCTRL1;
2072 	/* 0xb2: eSPI Upstream Control 2 */
2073 	volatile uint8_t ESUCTRL2;
2074 	/* 0xb3: eSPI Upstream Control 3 */
2075 	volatile uint8_t ESUCTRL3;
2076 	/* 0xb4-0xb5: Reserved6 */
2077 	volatile uint8_t reserved6[2];
2078 	/* 0xb6: eSPI Upstream Control 6 */
2079 	volatile uint8_t ESUCTRL6;
2080 	/* 0xb7: eSPI Upstream Control 7 */
2081 	volatile uint8_t ESUCTRL7;
2082 	/* 0xb8: eSPI Upstream Control 8 */
2083 	volatile uint8_t ESUCTRL8;
2084 	/* 0xb9-0xbf: Reserved7 */
2085 	volatile uint8_t reserved7[7];
2086 
2087 	/* 0xc0: eSPI OOB Control 0 */
2088 	volatile uint8_t ESOCTRL0;
2089 	/* 0xc1: eSPI OOB Control 1 */
2090 	volatile uint8_t ESOCTRL1;
2091 	/* 0xc2-0xc3: Reserved8 */
2092 	volatile uint8_t reserved8[2];
2093 	/* 0xc4: eSPI OOB Control 4 */
2094 	volatile uint8_t ESOCTRL4;
2095 	/* 0xc5-0xcf: Reserved9 */
2096 	volatile uint8_t reserved9[11];
2097 
2098 	/* 0xd0: eSPI SAFS Control 0 */
2099 	volatile uint8_t ESPISAFSC0;
2100 	/* 0xd1: eSPI SAFS Control 1 */
2101 	volatile uint8_t ESPISAFSC1;
2102 	/* 0xd2: eSPI SAFS Control 2 */
2103 	volatile uint8_t ESPISAFSC2;
2104 	/* 0xd3: eSPI SAFS Control 3 */
2105 	volatile uint8_t ESPISAFSC3;
2106 	/* 0xd4: eSPI SAFS Control 4 */
2107 	volatile uint8_t ESPISAFSC4;
2108 	/* 0xd5: eSPI SAFS Control 5 */
2109 	volatile uint8_t ESPISAFSC5;
2110 	/* 0xd6: eSPI SAFS Control 6 */
2111 	volatile uint8_t ESPISAFSC6;
2112 	/* 0xd7: eSPI SAFS Control 7 */
2113 	volatile uint8_t ESPISAFSC7;
2114 };
2115 
2116 /*
2117  * eSPI VW registers
2118  */
2119 struct espi_vw_regs {
2120 	/* 0x00-0x7f: VW index */
2121 	volatile uint8_t VW_INDEX[0x80];
2122 	/* 0x80-0x8f: Reserved1 */
2123 	volatile uint8_t reserved1[0x10];
2124 	/* 0x90: VW Contrl 0 */
2125 	volatile uint8_t VWCTRL0;
2126 	/* 0x91: VW Contrl 1 */
2127 	volatile uint8_t VWCTRL1;
2128 	/* 0x92: VW Contrl 2 */
2129 	volatile uint8_t VWCTRL2;
2130 	/* 0x93: VW Contrl 3 */
2131 	volatile uint8_t VWCTRL3;
2132 	/* 0x94: Reserved2 */
2133 	volatile uint8_t reserved2;
2134 	/* 0x95: VW Contrl 5 */
2135 	volatile uint8_t VWCTRL5;
2136 	/* 0x96: VW Contrl 6 */
2137 	volatile uint8_t VWCTRL6;
2138 	/* 0x97: VW Contrl 7 */
2139 	volatile uint8_t VWCTRL7;
2140 	/* 0x98-0x99: Reserved3 */
2141 	volatile uint8_t reserved3[2];
2142 };
2143 
2144 #define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80
2145 /*
2146  * eSPI Queue 0 registers
2147  */
2148 struct espi_queue0_regs {
2149 	/* 0x00-0x3f: PUT_PC Data Byte 0-63 */
2150 	volatile uint8_t PUT_PC_DATA[0x40];
2151 	/* 0x40-0x7f: Reserved1 */
2152 	volatile uint8_t reserved1[0x40];
2153 	/* 0x80-0xcf: PUT_OOB Data Byte 0-79 */
2154 	volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
2155 };
2156 
2157 /*
2158  * eSPI Queue 1 registers
2159  */
2160 struct espi_queue1_regs {
2161 	/* 0x00-0x4f: Upstream Data Byte 0-79 */
2162 	volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
2163 	/* 0x50-0x7f: Reserved1 */
2164 	volatile uint8_t reserved1[0x30];
2165 	/* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */
2166 	volatile uint8_t PUT_FLASH_NP_DATA[0x40];
2167 };
2168 
2169 #endif /* !__ASSEMBLER__ */
2170 
2171 
2172 /**
2173  *
2174  * (3Axxh) SPI Slave Controller (SPISC) registers
2175  *
2176  */
2177 #ifndef __ASSEMBLER__
2178 struct spisc_it8xxx2_regs {
2179 	/* 0x00: SPI Slave General Control */
2180 	volatile uint8_t SPISC_SPISGCR;
2181 	/* 0x01: Tx/Rx FIFO Access */
2182 	volatile uint8_t SPISC_TXRXFAR;
2183 	/* 0x02: Tx FIFO Control */
2184 	volatile uint8_t SPISC_TXFCR;
2185 	/* 0x03: SPI Slave General Control 2 */
2186 	volatile uint8_t SPISC_SPISGCR2;
2187 	/* 0x04: Interrupt Mask */
2188 	volatile uint8_t SPISC_IMR;
2189 	/* 0x05: Interrupt Status */
2190 	volatile uint8_t SPISC_ISR;
2191 	/* 0x06: Tx FIFO Status */
2192 	volatile uint8_t SPISC_TXFSR;
2193 	/* 0x07: Rx FIFO Status */
2194 	volatile uint8_t SPISC_RXFSR;
2195 	/* 0x08: CPU Write Tx FIFO Data Byte0 */
2196 	volatile uint8_t SPISC_CPUWTXFDB0R;
2197 	/* 0x09: FIFO Control / CPU Write Tx FIFO Data Byte1 */
2198 	volatile uint8_t SPISC_FCR;
2199 	/* 0x0A: CPU Write Tx FIFO Data Byte2 */
2200 	volatile uint8_t SPISC_CPUWTXFDB2R;
2201 	/* 0x0B: SPI Slave Response Data / CPU Write Tx FIFO Data Byte3 */
2202 	volatile uint8_t SPISC_SPISRDR;
2203 	/* 0x0C: Rx FIFO Readout Data Byte0 */
2204 	volatile uint8_t SPISC_RXFRDRB0;
2205 	/* 0x0D: Rx FIFO Readout Data Byte1 */
2206 	volatile uint8_t SPISC_RXFRDRB1;
2207 	/* 0x0E: Rx FIFO Readout Data Byte2 */
2208 	volatile uint8_t SPISC_RXFRDRB2;
2209 	/* 0x0F: Rx FIFO Readout Data Byte3 */
2210 	volatile uint8_t SPISC_RXFRDRB3;
2211 	/* 0x10-0x17: Reserved1 */
2212 	volatile uint8_t reserved1[8];
2213 	/* 0x18: FIFO Target Count Byte0 */
2214 	volatile uint8_t SPISC_FTCB0R;
2215 	/* 0x19: FIFO Target Count Byte1 */
2216 	volatile uint8_t SPISC_FTCB1R;
2217 	/* 0x1A: Target Count Capture Byte0 */
2218 	volatile uint8_t SPISC_TCCB0;
2219 	/* 0x1B: Target Count Capture Byte1 */
2220 	volatile uint8_t SPISC_TCCB1;
2221 	/* 0x1C-0x1D: Reserved2 */
2222 	volatile uint8_t reserved2[2];
2223 	/* 0x1E: Hardware Parsing 2 */
2224 	volatile uint8_t SPISC_HPR2;
2225 	/* 0x1F-0x25: Reserved3 */
2226 	volatile uint8_t reserved3[7];
2227 	/* 0x26: Rx Valid Length Interrupt Status Mask */
2228 	volatile uint8_t SPISC_RXVLISMR;
2229 	/* 0x27: Rx Valid Length Interrupt Status */
2230 	volatile uint8_t SPISC_RXVLISR;
2231 };
2232 #endif /* !__ASSEMBLER__ */
2233 
2234 /* SPISC register fields */
2235 /* 0x00: SPI Slave General Control */
2236 #define IT8XXX2_SPISC_SPISCEN		BIT(0)
2237 /* 0x01: Tx/Rx FIFO Access */
2238 #define IT8XXX2_SPISC_CPURXF1A		BIT(3)
2239 #define IT8XXX2_SPISC_CPUTFA		BIT(1)
2240 /* 0x02: Tx FIFO Control */
2241 #define IT8XXX2_SPISC_TXFCMR		BIT(2)
2242 #define IT8XXX2_SPISC_TXFR		BIT(1)
2243 #define IT8XXX2_SPISC_TXFS		BIT(0)
2244 /* 0x03: SPI Slave General Control 2 */
2245 #define IT8XXX2_SPISC_RXF2OC		BIT(4)
2246 #define IT8XXX2_SPISC_RXF1OC		BIT(3)
2247 #define IT8XXX2_SPISC_RXFAR		BIT(0)
2248 /* 0x04: Interrupt Mask */
2249 #define IT8XXX2_SPISC_EDIM		BIT(2)
2250 /* 0x06: Tx FIFO Status */
2251 #define IT8XXX2_SPISC_ENDDETECTINT	BIT(2)
2252 /* 0x09: FIFO Control */
2253 #define IT8XXX2_SPISC_SPISRTXF		BIT(2)
2254 #define IT8XXX2_SPISC_RXFR		BIT(1)
2255 #define IT8XXX2_SPISC_RXFCMR		BIT(0)
2256 /* 0x26: Rx Valid Length Interrupt Status Mask */
2257 #define IT8XXX2_SPISC_RVLIM		BIT(0)
2258 /* 0x27: Rx Valid Length Interrupt Status */
2259 #define IT8XXX2_SPISC_RVLI		BIT(0)
2260 
2261 #endif /* CHIP_CHIPREGS_H */
2262