1 /* 2 * Copyright (c) 2024 ITE Corporation. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_ITE_IT8801_H_ 8 #define ZEPHYR_INCLUDE_DRIVERS_MFD_ITE_IT8801_H_ 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /* 15 * IC clock and power management controller register fields 16 */ 17 /* 0xf9: Gather interrupt status register */ 18 #define IT8801_REG_GISR 0xf9 19 #define IT8801_REG_MASK_GISR_GKSIIS BIT(6) 20 /* 0xfb: Gather interrupt enable control register */ 21 #define IT8801_REG_GIECR 0xfb 22 #define IT8801_REG_MASK_GKSIIE BIT(3) 23 #define IT8801_REG_MASK_GGPIOIE BIT(2) 24 25 /* 26 * General control register fields 27 */ 28 #define IT8801_REG_LBVIDR 0xfe 29 #define IT8801_REG_HBVIDR 0xff 30 31 struct it8801_vendor_id_t { 32 uint8_t chip_id; 33 uint8_t reg; 34 }; 35 36 static const struct it8801_vendor_id_t it8801_id_verify[] = { 37 {0x12, IT8801_REG_HBVIDR}, 38 {0x83, IT8801_REG_LBVIDR}, 39 }; 40 41 /* 42 * SMbus interface register fields 43 */ 44 /* 0xfa: SMBus control register */ 45 #define IT8801_REG_SMBCR 0xfa 46 #define IT8801_REG_MASK_ARE BIT(4) 47 48 /* 49 * GPIO register fields 50 */ 51 #define IT8801_GPIOAFS_FUN1 0x0 52 #define IT8801_GPIOAFS_FUN2 0x01 53 #define IT8801_GPIOAFS_FUN3 0x02 54 /* GPIO control register */ 55 /* GPIO direction */ 56 #define IT8801_GPIODIR BIT(5) 57 /* GPIO input and output type */ 58 #define IT8801_GPIOIOT_OD BIT(4) 59 #define IT8801_GPIOIOT_INT_FALL BIT(4) 60 #define IT8801_GPIOIOT_INT_RISE BIT(3) 61 /* GPIO polarity */ 62 #define IT8801_GPIOPOL BIT(2) 63 /* GPIO pull-down enable */ 64 #define IT8801_GPIOPDE BIT(1) 65 /* GPIO pull-up enable */ 66 #define IT8801_GPIOPUE BIT(0) 67 68 /* 69 * Keyboard matrix scan controller register fields 70 */ 71 /* 0x40: Keyboard scan out mode control register */ 72 #define IT8801_REG_MASK_KSOSDIC BIT(7) 73 #define IT8801_REG_MASK_KSE BIT(6) 74 #define IT8801_REG_MASK_AKSOSC BIT(5) 75 76 /* 77 * PWM register fields 78 */ 79 #define PWM_IT8801_FREQ 32895 80 /* Control push-pull flag */ 81 #define PWM_IT8801_PUSH_PULL BIT(8) 82 /* 0x5f: PWM output open-drain disable register */ 83 #define IT8801_REG_PWMODDSR 0x5f 84 /* PWM mode control register */ 85 #define IT8801_PWMMCR_MCR_MASK GENMASK(1, 0) 86 #define IT8801_PWMMCR_MCR_OFF 0 87 #define IT8801_PWMMCR_MCR_BLINKING 1 88 #define IT8801_PWMMCR_MCR_BREATHING 2 89 #define IT8801_PWMMCR_MCR_ON 3 90 91 /* 92 * For IT8801 MFD alternate function controller 93 */ 94 #define IT8801_DT_INST_MFDCTRL(inst, idx) DT_INST_PHANDLE_BY_IDX(inst, mfdctrl, idx) 95 96 #define IT8801_DT_INST_MFDCTRL_LEN(inst) DT_INST_PROP_LEN_OR(inst, mfdctrl, 0) 97 98 #define IT8801_DEV_MFD(idx, inst) \ 99 DEVICE_DT_GET(DT_PHANDLE(IT8801_DT_INST_MFDCTRL(inst, idx), altctrls)) 100 #define IT8801_DEV_MFD_PIN(idx, inst) DT_PHA(IT8801_DT_INST_MFDCTRL(inst, idx), altctrls, pin) 101 #define IT8801_DEV_MFD_FUNC(idx, inst) DT_PHA(IT8801_DT_INST_MFDCTRL(inst, idx), altctrls, alt_func) 102 103 #define IT8801_DT_MFD_ITEMS_FUNC(idx, inst) \ 104 { \ 105 .gpiocr = IT8801_DEV_MFD(idx, inst), \ 106 .pin = IT8801_DEV_MFD_PIN(idx, inst), \ 107 .alt_func = IT8801_DEV_MFD_FUNC(idx, inst), \ 108 } 109 110 #define IT8801_DT_MFD_ITEMS_LIST(inst) \ 111 {LISTIFY(IT8801_DT_INST_MFDCTRL_LEN(inst), \ 112 IT8801_DT_MFD_ITEMS_FUNC, (,), \ 113 inst) } 114 115 /* 116 * Configure alternate function pin 117 */ 118 int mfd_it8801_configure_pins(const struct i2c_dt_spec *i2c_dev, const struct device *dev, 119 uint8_t pin, uint8_t func); 120 121 /* Define the IT8801 MFD interrupt callback function handler */ 122 typedef void (*it8801_callback_handler_t)(const struct device *dev); 123 124 struct it8801_mfd_callback { 125 sys_snode_t node; 126 it8801_callback_handler_t cb; 127 const struct device *dev; 128 }; 129 /* Register the interrupt of IT8801 MFD callback function */ 130 void mfd_it8801_register_interrupt_callback(const struct device *mfd, 131 struct it8801_mfd_callback *callback); 132 133 #ifdef __cplusplus 134 } 135 #endif 136 137 #endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_ITE_IT8801_H_ */ 138
