1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_xspi.h 4 * @author MCD Application Team 5 * @brief Header file of XSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_XSPI_H 21 #define STM32H5xx_HAL_XSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 #include "stm32h5xx_ll_dlyb.h" 30 31 #if defined(HSPI) || defined(HSPI1) || defined(HSPI2)|| defined(OCTOSPI) || defined(OCTOSPI1)|| defined(OCTOSPI2) 32 33 /** @addtogroup STM32H5xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup XSPI 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup XSPI_Exported_Types XSPI Exported Types 43 * @{ 44 */ 45 #define HAL_XSPI_DLYB_CfgTypeDef LL_DLYB_CfgTypeDef 46 47 /** 48 * @brief XSPI Init structure definition 49 */ 50 typedef struct 51 { 52 uint32_t FifoThresholdByte; /*!< This is the threshold used by the Peripheral to generate the interrupt 53 indicating that data are available in reception or free place 54 is available in transmission. 55 For OCTOSPI, this parameter can be a value between 1 and 32 */ 56 uint32_t MemoryMode; /*!< It Specifies the memory mode. 57 This parameter can be a value of @ref XSPI_MemoryMode */ 58 uint32_t MemoryType; /*!< It indicates the external device type connected to the XSPI. 59 This parameter can be a value of @ref XSPI_MemoryType */ 60 uint32_t MemorySize; /*!< It defines the size of the external device connected to the XSPI, 61 it corresponds to the number of address bits required to access 62 the external device. 63 This parameter can be a value of @ref XSPI_MemorySize*/ 64 uint32_t ChipSelectHighTimeCycle; /*!< It defines the minimum number of clocks which the chip select 65 must remain high between commands. 66 This parameter can be a value between 1 and 64U */ 67 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 68 This parameter can be a value of @ref XSPI_FreeRunningClock */ 69 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 70 This parameter can be a value of @ref XSPI_ClockMode */ 71 uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. 72 This parameter can be a value of @ref XSPI_WrapSize */ 73 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 74 the external clock based on the AHB clock. 75 This parameter can be a value between 0 and 255U */ 76 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 77 to take in account external signal delays. 78 This parameter can be a value of @ref XSPI_SampleShifting */ 79 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 80 This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */ 81 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 82 defines the boundary of bytes to release the chip select. 83 This parameter can be a value of @ref XSPI_ChipSelectBoundary */ 84 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 85 by the delay block. 86 This parameter can be a value of @ref XSPI_DelayBlockBypass */ 87 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 88 Refresh+1 clock cycles. 89 This parameter can be a value between 0 and 0xFFFFFFFF */ 90 } XSPI_InitTypeDef; 91 92 /** 93 * @brief HAL XSPI Handle Structure definition 94 */ 95 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 96 typedef struct __XSPI_HandleTypeDef 97 #else 98 typedef struct 99 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 100 { 101 XSPI_TypeDef *Instance; /*!< XSPI registers base address */ 102 XSPI_InitTypeDef Init; /*!< XSPI initialization parameters */ 103 uint8_t *pBuffPtr; /*!< Address of the XSPI buffer for transfer */ 104 __IO uint32_t XferSize; /*!< Number of data to transfer */ 105 __IO uint32_t XferCount; /*!< Counter of data transferred */ 106 DMA_HandleTypeDef *hdmatx; /*!< Handle of the DMA channel used for transmit */ 107 DMA_HandleTypeDef *hdmarx; /*!< Handle of the DMA channel used for receive */ 108 __IO uint32_t State; /*!< Internal state of the XSPI HAL driver */ 109 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 110 uint32_t Timeout; /*!< Timeout used for the XSPI external device access */ 111 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 112 void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi); 113 void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 114 void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi); 115 void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 116 void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 117 void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 118 void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 119 void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 120 void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi); 121 void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi); 122 123 void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi); 124 void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi); 125 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 126 } XSPI_HandleTypeDef; 127 128 /** 129 * @brief HAL XSPI Regular Command Structure definition 130 */ 131 typedef struct 132 { 133 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 134 to the registers for the write operation (these registers are only 135 used for memory-mapped mode). 136 This parameter can be a value of @ref XSPI_OperationType */ 137 uint32_t IOSelect; /*!< It indicates the IOs used to exchange data with external memory. 138 This parameter can be a value of @ref XSPI_IOSelect */ 139 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 140 This parameter can be a value between 0 and 0xFFFFFFFFU */ 141 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 142 This parameter can be a value of @ref XSPI_InstructionMode */ 143 uint32_t InstructionWidth; /*!< It indicates the width of the instruction. 144 This parameter can be a value of @ref XSPI_InstructionWidth */ 145 uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase. 146 This parameter can be a value of @ref XSPI_InstructionDTRMode */ 147 uint32_t Address; /*!< It contains the address to be sent to the device. 148 This parameter can be a value between 0 and 0xFFFFFFFF */ 149 uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises number of lines 150 for address (except no address). 151 This parameter can be a value of @ref XSPI_AddressMode */ 152 uint32_t AddressWidth; /*!< It indicates the width of the address. 153 This parameter can be a value of @ref XSPI_AddressWidth */ 154 uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase. 155 This parameter can be a value of @ref XSPI_AddressDTRMode */ 156 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 157 This parameter can be a value between 0 and 0xFFFFFFFF */ 158 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 159 This parameter can be a value of @ref XSPI_AlternateBytesMode */ 160 uint32_t AlternateBytesWidth; /*!< It indicates the width of the alternate bytes. 161 This parameter can be a value of @ref XSPI_AlternateBytesWidth */ 162 uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 163 This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */ 164 uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines 165 for data exchange (except no data). 166 This parameter can be a value of @ref XSPI_DataMode */ 167 uint32_t DataLength; /*!< It indicates the number of data transferred with this command. 168 This field is only used for indirect mode. 169 This parameter can be a value between 1 and 0xFFFFFFFFU */ 170 uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase. 171 This parameter can be a value of @ref XSPI_DataDTRMode */ 172 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 173 This parameter can be a value between 0 and 31U */ 174 uint32_t DQSMode; /*!< It enables or not the data strobe management. 175 This parameter can be a value of @ref XSPI_DQSMode */ 176 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. When SIOO mode enabled, 177 instruction will be sent only once. 178 This parameter can be a value of @ref XSPI_SIOOMode */ 179 } XSPI_RegularCmdTypeDef; 180 /** 181 * @brief HAL XSPI Hyperbus Configuration Structure definition 182 */ 183 typedef struct 184 { 185 uint32_t RWRecoveryTimeCycle; /*!< It indicates the number of cycles for the device read write recovery time. 186 This parameter can be a value between 0 and 255U */ 187 uint32_t AccessTimeCycle; /*!< It indicates the number of cycles for the device access time. 188 This parameter can be a value between 0 and 255U */ 189 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 190 This parameter can be a value of @ref XSPI_WriteZeroLatency */ 191 uint32_t LatencyMode; /*!< It configures the latency mode. 192 This parameter can be a value of @ref XSPI_LatencyMode */ 193 } XSPI_HyperbusCfgTypeDef; 194 195 /** 196 * @brief HAL XSPI Hyperbus Command Structure definition 197 */ 198 typedef struct 199 { 200 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 201 This parameter can be a value of @ref XSPI_AddressSpace */ 202 uint32_t Address; /*!< It contains the address to be sent to the device. 203 This parameter can be a value between 0 and 0xFFFFFFFF */ 204 uint32_t AddressWidth; /*!< It indicates the width of the address. 205 This parameter can be a value of @ref XSPI_AddressWidth */ 206 uint32_t DataLength; /*!< It indicates the number of data transferred with this command. 207 This field is only used for indirect mode. 208 This parameter can be a value between 1 and 0xFFFFFFFF 209 In case of autopolling mode, this parameter can be 210 any value between 1 and 4 */ 211 uint32_t DQSMode; /*!< It enables or not the data strobe management. 212 This parameter can be a value of @ref XSPI_DQSMode */ 213 } XSPI_HyperbusCmdTypeDef; 214 215 /** 216 * @brief HAL XSPI Auto Polling mode configuration structure definition 217 */ 218 typedef struct 219 { 220 uint32_t MatchValue; /*!< Specifies the value to be compared with the masked status register to get 221 a match. 222 This parameter can be any value between 0 and 0xFFFFFFFFU */ 223 uint32_t MatchMask; /*!< Specifies the mask to be applied to the status bytes received. 224 This parameter can be any value between 0 and 0xFFFFFFFFU */ 225 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 226 This parameter can be a value of @ref XSPI_MatchMode */ 227 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 228 This parameter can be a value of @ref XSPI_AutomaticStop */ 229 uint32_t IntervalTime; /*!< Specifies the number of clock cycles between two read during automatic 230 polling phases. 231 This parameter can be any value between 0 and 0xFFFFU */ 232 } XSPI_AutoPollingTypeDef; 233 234 /** 235 * @brief HAL XSPI Memory Mapped mode configuration structure definition 236 */ 237 typedef struct 238 { 239 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 240 This parameter can be a value of @ref XSPI_TimeOutActivation */ 241 uint32_t TimeoutPeriodClock; /*!< Specifies the number of clock to wait when the FIFO is full before to 242 release the chip select. 243 This parameter can be any value between 0 and 0xFFFFU */ 244 } XSPI_MemoryMappedTypeDef; 245 246 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 247 /** 248 * @brief HAL XSPI Callback ID enumeration definition 249 */ 250 typedef enum 251 { 252 HAL_XSPI_ERROR_CB_ID = 0x00U, /*!< XSPI Error Callback ID */ 253 HAL_XSPI_ABORT_CB_ID = 0x01U, /*!< XSPI Abort Callback ID */ 254 HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< XSPI FIFO Threshold Callback ID */ 255 HAL_XSPI_CMD_CPLT_CB_ID = 0x03U, /*!< XSPI Command Complete Callback ID */ 256 HAL_XSPI_RX_CPLT_CB_ID = 0x04U, /*!< XSPI Rx Complete Callback ID */ 257 HAL_XSPI_TX_CPLT_CB_ID = 0x05U, /*!< XSPI Tx Complete Callback ID */ 258 HAL_XSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< XSPI Rx Half Complete Callback ID */ 259 HAL_XSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< XSPI Tx Half Complete Callback ID */ 260 HAL_XSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< XSPI Status Match Callback ID */ 261 HAL_XSPI_TIMEOUT_CB_ID = 0x09U, /*!< XSPI Timeout Callback ID */ 262 HAL_XSPI_MSP_INIT_CB_ID = 0x0AU, /*!< XSPI MspInit Callback ID */ 263 HAL_XSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< XSPI MspDeInit Callback ID */ 264 } HAL_XSPI_CallbackIDTypeDef; 265 266 /** 267 * @brief HAL XSPI Callback pointer definition 268 */ 269 typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); 270 271 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 272 /** 273 * @} 274 */ 275 276 /* Exported constants --------------------------------------------------------*/ 277 /** @defgroup XSPI_Exported_Constants XSPI Exported Constants 278 * @{ 279 */ 280 281 /** @defgroup XSPI_State XSPI State 282 * @{ 283 */ 284 #define HAL_XSPI_STATE_RESET (0x00000000U) /*!< Initial state */ 285 #define HAL_XSPI_STATE_READY (0x00000002U) /*!< Driver ready to be used */ 286 #define HAL_XSPI_STATE_HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 287 #define HAL_XSPI_STATE_CMD_CFG (0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 288 #define HAL_XSPI_STATE_READ_CMD_CFG (0x00000014U) /*!< Read command configuration done, not the write command configuration */ 289 #define HAL_XSPI_STATE_WRITE_CMD_CFG (0x00000024U) /*!< Write command configuration done, not the read command configuration */ 290 #define HAL_XSPI_STATE_BUSY_CMD (0x00000008U) /*!< Command without data on-going */ 291 #define HAL_XSPI_STATE_BUSY_TX (0x00000018U) /*!< Indirect Tx on-going */ 292 #define HAL_XSPI_STATE_BUSY_RX (0x00000028U) /*!< Indirect Rx on-going */ 293 #define HAL_XSPI_STATE_BUSY_AUTO_POLLING (0x00000048U) /*!< Auto-polling on-going */ 294 #define HAL_XSPI_STATE_BUSY_MEM_MAPPED (0x00000088U) /*!< Memory-mapped on-going */ 295 #define HAL_XSPI_STATE_ABORT (0x00000100U) /*!< Abort on-going */ 296 #define HAL_XSPI_STATE_ERROR (0x00000200U) /*!< Blocking error, driver should be re-initialized */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup XSPI_ErrorCode XSPI Error Code 302 * @{ 303 */ 304 #define HAL_XSPI_ERROR_NONE (0x00000000U) /*!< No error */ 305 #define HAL_XSPI_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ 306 #define HAL_XSPI_ERROR_TRANSFER (0x00000002U) /*!< Transfer error */ 307 #define HAL_XSPI_ERROR_DMA (0x00000004U) /*!< DMA transfer error */ 308 #define HAL_XSPI_ERROR_INVALID_PARAM (0x00000008U) /*!< Invalid parameters error */ 309 #define HAL_XSPI_ERROR_INVALID_SEQUENCE (0x00000010U) /*!< Sequence is incorrect */ 310 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 311 #define HAL_XSPI_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid callback error */ 312 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup XSPI_MemoryMode XSPI Memory Mode 318 * @{ 319 */ 320 #define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */ 321 #define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */ 322 323 /** 324 * @} 325 */ 326 327 /** @defgroup XSPI_MemoryType XSPI Memory Type 328 * @{ 329 */ 330 #define HAL_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */ 331 #define HAL_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */ 332 #define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 333 #define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/ 334 #define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 335 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */ 336 337 /** 338 * @} 339 */ 340 341 /** @defgroup XSPI_MemorySize XSPI Memory Size 342 * @{ 343 */ 344 #define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ 345 #define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ 346 #define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ 347 #define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ 348 #define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ 349 #define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ 350 #define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ 351 #define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ 352 #define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ 353 #define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ 354 #define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ 355 #define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ 356 #define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ 357 #define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ 358 #define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ 359 #define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ 360 #define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ 361 #define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ 362 #define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ 363 #define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ 364 #define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ 365 #define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ 366 #define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ 367 #define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ 368 #define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ 369 #define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ 370 #define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ 371 #define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ 372 #define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ 373 #define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ 374 #define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ 375 #define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ 376 /** 377 * @} 378 */ 379 380 /** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock 381 * @{ 382 */ 383 #define HAL_XSPI_FREERUNCLK_DISABLE (0x00000000U) /*!< CLK is not free running */ 384 #define HAL_XSPI_FREERUNCLK_ENABLE ((uint32_t)XSPI_DCR1_FRCK) /*!< CLK is always provided (running) */ 385 /** 386 * @} 387 */ 388 389 /** @defgroup XSPI_ClockMode XSPI Clock Mode 390 * @{ 391 */ 392 #define HAL_XSPI_CLOCK_MODE_0 (0x00000000U) /*!< CLK must stay low while nCS is high */ 393 #define HAL_XSPI_CLOCK_MODE_3 ((uint32_t)XSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 394 /** 395 * @} 396 */ 397 398 /** @defgroup XSPI_WrapSize XSPI Wrap-Size 399 * @{ 400 */ 401 #define HAL_XSPI_WRAP_NOT_SUPPORTED (0x00000000U) /*!< wrapped reads are not supported by the memory */ 402 #define HAL_XSPI_WRAP_16_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 403 #define HAL_XSPI_WRAP_32_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 404 #define HAL_XSPI_WRAP_64_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 405 #define HAL_XSPI_WRAP_128_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 406 /** 407 * @} 408 */ 409 410 /** @defgroup XSPI_SampleShifting XSPI Sample Shifting 411 * @{ 412 */ 413 #define HAL_XSPI_SAMPLE_SHIFT_NONE (0x00000000U) /*!< No shift */ 414 #define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE ((uint32_t)XSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 415 /** 416 * @} 417 */ 418 419 /** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle 420 * @{ 421 */ 422 #define HAL_XSPI_DHQC_DISABLE (0x00000000U) /*!< No Delay */ 423 #define HAL_XSPI_DHQC_ENABLE ((uint32_t)XSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 424 /** 425 * @} 426 */ 427 428 /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary 429 * @{ 430 */ 431 #define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ 432 #define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ 433 #define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ 434 #define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ 435 #define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ 436 #define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ 437 #define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ 438 #define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ 439 #define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ 440 #define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ 441 #define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ 442 #define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ 443 #define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ 444 #define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ 445 #define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ 446 #define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ 447 #define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ 448 #define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ 449 #define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ 450 #define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ 451 #define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ 452 #define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ 453 #define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ 454 #define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ 455 #define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ 456 #define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ 457 #define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ 458 #define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ 459 #define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ 460 #define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ 461 #define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ 462 #define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup XSPI_DelayBlockBypass XSPI Delay Block Bypaas 468 * @{ 469 */ 470 #define HAL_XSPI_DELAY_BLOCK_ON (0x00000000U) /*!< Sampling clock is delayed by the delay block */ 471 #define HAL_XSPI_DELAY_BLOCK_BYPASS ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 472 /** 473 * @} 474 */ 475 476 /** @defgroup XSPI_OperationType XSPI Operation Type 477 * @{ 478 */ 479 #define HAL_XSPI_OPTYPE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 480 #define HAL_XSPI_OPTYPE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */ 481 #define HAL_XSPI_OPTYPE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */ 482 #define HAL_XSPI_OPTYPE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ 483 484 /** 485 * @} 486 */ 487 488 /** @defgroup XSPI_IOSelect XSPI IO Select 489 * @{ 490 */ 491 #define HAL_XSPI_SELECT_IO_3_0 (0x00000000U) /*!< Data exchanged over IO[3:0] */ 492 #define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[7:4] */ 493 #define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */ 494 /** 495 * @} 496 */ 497 498 /** @defgroup XSPI_InstructionMode XSPI Instruction Mode 499 * @{ 500 */ 501 #define HAL_XSPI_INSTRUCTION_NONE (0x00000000U) /*!< No instruction */ 502 #define HAL_XSPI_INSTRUCTION_1_LINE ((uint32_t)XSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 503 #define HAL_XSPI_INSTRUCTION_2_LINES ((uint32_t)XSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 504 #define HAL_XSPI_INSTRUCTION_4_LINES ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 505 #define HAL_XSPI_INSTRUCTION_8_LINES ((uint32_t)XSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 506 /** 507 * @} 508 */ 509 510 /** @defgroup XSPI_InstructionWidth XSPI Instruction Width 511 * @{ 512 */ 513 #define HAL_XSPI_INSTRUCTION_8_BITS (0x00000000U) /*!< 8-bit instruction */ 514 #define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 515 #define HAL_XSPI_INSTRUCTION_24_BITS ((uint32_t)XSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 516 #define HAL_XSPI_INSTRUCTION_32_BITS ((uint32_t)XSPI_CCR_ISIZE) /*!< 32-bit instruction */ 517 /** 518 * @} 519 */ 520 521 /** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode 522 * @{ 523 */ 524 #define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for instruction phase */ 525 #define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 526 /** 527 * @} 528 */ 529 530 /** @defgroup XSPI_AddressMode XSPI Address Mode 531 * @{ 532 */ 533 #define HAL_XSPI_ADDRESS_NONE (0x00000000U) /*!< No address */ 534 #define HAL_XSPI_ADDRESS_1_LINE ((uint32_t)XSPI_CCR_ADMODE_0) /*!< Address on a single line */ 535 #define HAL_XSPI_ADDRESS_2_LINES ((uint32_t)XSPI_CCR_ADMODE_1) /*!< Address on two lines */ 536 #define HAL_XSPI_ADDRESS_4_LINES ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 537 #define HAL_XSPI_ADDRESS_8_LINES ((uint32_t)XSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 538 /** 539 * @} 540 */ 541 542 /** @defgroup XSPI_AddressWidth XSPI Address width 543 * @{ 544 */ 545 #define HAL_XSPI_ADDRESS_8_BITS (0x00000000U) /*!< 8-bit address */ 546 #define HAL_XSPI_ADDRESS_16_BITS ((uint32_t)XSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 547 #define HAL_XSPI_ADDRESS_24_BITS ((uint32_t)XSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 548 #define HAL_XSPI_ADDRESS_32_BITS ((uint32_t)XSPI_CCR_ADSIZE) /*!< 32-bit address */ 549 /** 550 * @} 551 */ 552 553 /** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode 554 * @{ 555 */ 556 #define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for address phase */ 557 #define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 558 /** 559 * @} 560 */ 561 562 /** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode 563 * @{ 564 */ 565 #define HAL_XSPI_ALT_BYTES_NONE (0x00000000U) /*!< No alternate bytes */ 566 #define HAL_XSPI_ALT_BYTES_1_LINE ((uint32_t)XSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 567 #define HAL_XSPI_ALT_BYTES_2_LINES ((uint32_t)XSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 568 #define HAL_XSPI_ALT_BYTES_4_LINES ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 569 #define HAL_XSPI_ALT_BYTES_8_LINES ((uint32_t)XSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width 575 * @{ 576 */ 577 #define HAL_XSPI_ALT_BYTES_8_BITS (0x00000000U) /*!< 8-bit alternate bytes */ 578 #define HAL_XSPI_ALT_BYTES_16_BITS ((uint32_t)XSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 579 #define HAL_XSPI_ALT_BYTES_24_BITS ((uint32_t)XSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 580 #define HAL_XSPI_ALT_BYTES_32_BITS ((uint32_t)XSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 581 /** 582 * @} 583 */ 584 585 /** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode 586 * @{ 587 */ 588 #define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 589 #define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup XSPI_DataMode XSPI Data Mode 595 * @{ 596 */ 597 #define HAL_XSPI_DATA_NONE (0x00000000U) /*!< No data */ 598 #define HAL_XSPI_DATA_1_LINE ((uint32_t)XSPI_CCR_DMODE_0) /*!< Data on a single line */ 599 #define HAL_XSPI_DATA_2_LINES ((uint32_t)XSPI_CCR_DMODE_1) /*!< Data on two lines */ 600 #define HAL_XSPI_DATA_4_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1)) /*!< Data on four lines */ 601 #define HAL_XSPI_DATA_8_LINES ((uint32_t)XSPI_CCR_DMODE_2) /*!< Data on eight lines */ 602 /** 603 * @} 604 */ 605 606 /** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode 607 * @{ 608 */ 609 #define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for data phase */ 610 #define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 611 /** 612 * @} 613 */ 614 615 /** @defgroup XSPI_DQSMode XSPI DQS Mode 616 * @{ 617 */ 618 #define HAL_XSPI_DQS_DISABLE (0x00000000U) /*!< DQS disabled */ 619 #define HAL_XSPI_DQS_ENABLE ((uint32_t)XSPI_CCR_DQSE) /*!< DQS enabled */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup XSPI_SIOOMode XSPI SIOO Mode 625 * @{ 626 */ 627 #define HAL_XSPI_SIOO_INST_EVERY_CMD (0x00000000U) /*!< Send instruction on every transaction */ 628 #define HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)XSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 629 /** 630 * @} 631 */ 632 633 /** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation 634 * @{ 635 */ 636 #define HAL_XSPI_LATENCY_ON_WRITE (0x00000000U) /*!< Latency on write accesses */ 637 #define HAL_XSPI_NO_LATENCY_ON_WRITE ((uint32_t)XSPI_HLCR_WZL) /*!< No latency on write accesses */ 638 /** 639 * @} 640 */ 641 642 /** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode 643 * @{ 644 */ 645 #define HAL_XSPI_VARIABLE_LATENCY (0x00000000U) /*!< Variable initial latency */ 646 #define HAL_XSPI_FIXED_LATENCY ((uint32_t)XSPI_HLCR_LM) /*!< Fixed latency */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space 652 * @{ 653 */ 654 #define HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */ 655 #define HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup XSPI_MatchMode XSPI Match Mode 661 * @{ 662 */ 663 #define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between unmasked bits */ 664 #define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 665 /** 666 * @} 667 */ 668 669 /** @defgroup XSPI_AutomaticStop XSPI Automatic Stop 670 * @{ 671 */ 672 #define HAL_XSPI_AUTOMATIC_STOP_DISABLE (0x00000000U) /*!< AutoPolling stops only with abort or XSPI disabling */ 673 #define HAL_XSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)XSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 674 /** 675 * @} 676 */ 677 678 /** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation 679 * @{ 680 */ 681 #define HAL_XSPI_TIMEOUT_COUNTER_DISABLE (0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 682 #define HAL_XSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)XSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 683 /** 684 * @} 685 */ 686 687 /** @defgroup XSPI_Flags XSPI Flags 688 * @{ 689 */ 690 #define HAL_XSPI_FLAG_BUSY XSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 691 #define HAL_XSPI_FLAG_TO XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 692 #define HAL_XSPI_FLAG_SM XSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 693 #define HAL_XSPI_FLAG_FT XSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 694 #define HAL_XSPI_FLAG_TC XSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 695 #define HAL_XSPI_FLAG_TE XSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 696 /** 697 * @} 698 */ 699 700 /** @defgroup XSPI_Interrupts XSPI Interrupts 701 * @{ 702 */ 703 #define HAL_XSPI_IT_TO XSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 704 #define HAL_XSPI_IT_SM XSPI_CR_SMIE /*!< Interrupt on the status match flag */ 705 #define HAL_XSPI_IT_FT XSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 706 #define HAL_XSPI_IT_TC XSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 707 #define HAL_XSPI_IT_TE XSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 708 /** 709 * @} 710 */ 711 712 /** @defgroup XSPI_Timeout_definition XSPI Timeout definition 713 * @{ 714 */ 715 #define HAL_XSPI_TIMEOUT_DEFAULT_VALUE (5000U) /* 5 s */ 716 /** 717 * @} 718 */ 719 720 /** 721 * @} 722 */ 723 724 /* Exported macros -----------------------------------------------------------*/ 725 /** @defgroup XSPI_Exported_Macros XSPI Exported Macros 726 * @{ 727 */ 728 /** @brief Reset XSPI handle state. 729 * @param __HANDLE__ specifies the XSPI Handle. 730 * @retval None 731 */ 732 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 733 #define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 734 (__HANDLE__)->State = HAL_XSPI_STATE_RESET; \ 735 (__HANDLE__)->MspInitCallback = NULL; \ 736 (__HANDLE__)->MspDeInitCallback = NULL; \ 737 } while(0) 738 #else 739 #define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_XSPI_STATE_RESET) 740 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 741 742 /** @brief Enable the XSPI peripheral. 743 * @param __HANDLE__ specifies the XSPI Handle. 744 * @retval None 745 */ 746 #define HAL_XSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) 747 748 /** @brief Disable the XSPI peripheral. 749 * @param __HANDLE__ specifies the XSPI Handle. 750 * @retval None 751 */ 752 #define HAL_XSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) 753 754 /** @brief Enable the specified XSPI interrupt. 755 * @param __HANDLE__ specifies the XSPI Handle. 756 * @param __INTERRUPT__ specifies the XSPI interrupt source to enable. 757 * This parameter can be one of the following values: 758 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 759 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 760 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 761 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 762 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 763 * @retval None 764 */ 765 #define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 766 767 /** @brief Disable the specified XSPI interrupt. 768 * @param __HANDLE__ specifies the XSPI Handle. 769 * @param __INTERRUPT__ specifies the XSPI interrupt source to disable. 770 * This parameter can be one of the following values: 771 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 772 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 773 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 774 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 775 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 776 * @retval None 777 */ 778 #define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 779 780 /** @brief Check whether the specified XSPI interrupt source is enabled or not. 781 * @param __HANDLE__ specifies the XSPI Handle. 782 * @param __INTERRUPT__ specifies the XSPI interrupt source to check. 783 * This parameter can be one of the following values: 784 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 785 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 786 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 787 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 788 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 789 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 790 */ 791 #define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ 792 == (__INTERRUPT__)) 793 794 /** 795 * @brief Check whether the selected XSPI flag is set or not. 796 * @param __HANDLE__ specifies the XSPI Handle. 797 * @param __FLAG__ specifies the XSPI flag to check. 798 * This parameter can be one of the following values: 799 * @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag 800 * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag 801 * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag 802 * @arg HAL_XSPI_FLAG_FT: XSPI FIFO threshold flag 803 * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag 804 * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag 805 * @retval None 806 */ 807 #define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 808 != 0U) ? SET : RESET) 809 810 /** @brief Clears the specified XSPI's flag status. 811 * @param __HANDLE__ specifies the XSPI Handle. 812 * @param __FLAG__ specifies the XSPI clear register flag that needs to be set 813 * This parameter can be one of the following values: 814 * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag 815 * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag 816 * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag 817 * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag 818 * @retval None 819 */ 820 #define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 821 822 /** 823 * @} 824 */ 825 826 /* Exported functions --------------------------------------------------------*/ 827 /** @addtogroup XSPI_Exported_Functions 828 * @{ 829 */ 830 831 /* Initialization/de-initialization functions ********************************/ 832 /** @addtogroup XSPI_Exported_Functions_Group1 833 * @{ 834 */ 835 HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi); 836 void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi); 837 HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi); 838 void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); 839 840 /** 841 * @} 842 */ 843 844 /* IO operation functions *****************************************************/ 845 /** @addtogroup XSPI_Exported_Functions_Group2 846 * @{ 847 */ 848 /* XSPI IRQ handler function */ 849 void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi); 850 851 /* XSPI command configuration functions */ 852 HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, 853 uint32_t Timeout); 854 HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); 855 HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, 856 uint32_t Timeout); 857 HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, 858 uint32_t Timeout); 859 860 /* XSPI indirect mode functions */ 861 HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); 862 HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); 863 HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 864 HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 865 HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 866 HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 867 868 /* XSPI status flag polling mode functions */ 869 HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, 870 uint32_t Timeout); 871 HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg); 872 873 /* XSPI memory-mapped mode functions */ 874 HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg); 875 876 /* Callback functions in non-blocking modes ***********************************/ 877 void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi); 878 void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi); 879 void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi); 880 881 /* XSPI indirect mode Callback functions */ 882 void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi); 883 void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi); 884 void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi); 885 void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); 886 void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); 887 888 /* XSPI status flag polling mode functions */ 889 void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi); 890 891 /* XSPI memory-mapped mode functions */ 892 void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi); 893 894 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 895 /* XSPI callback registering/unregistering */ 896 HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, 897 pXSPI_CallbackTypeDef pCallback); 898 HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID); 899 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 900 901 /** 902 * @} 903 */ 904 905 /* Peripheral Control and State functions ************************************/ 906 /** @addtogroup XSPI_Exported_Functions_Group3 907 * @{ 908 */ 909 HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi); 910 HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi); 911 HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold); 912 uint32_t HAL_XSPI_GetFifoThreshold(XSPI_HandleTypeDef *hxspi); 913 HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type); 914 HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size); 915 HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler); 916 HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout); 917 uint32_t HAL_XSPI_GetError(XSPI_HandleTypeDef *hxspi); 918 uint32_t HAL_XSPI_GetState(XSPI_HandleTypeDef *hxspi); 919 920 /** 921 * @} 922 */ 923 924 /* XSPI Delay Block functions ************************************/ 925 /** @addtogroup XSPI_Exported_Functions_Group4 926 * @{ 927 */ 928 929 HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); 930 HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); 931 HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, 932 HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); 933 934 /** 935 * @} 936 */ 937 938 /** 939 * @} 940 */ 941 /* End of exported functions -------------------------------------------------*/ 942 943 /* Private macros ------------------------------------------------------------*/ 944 /** 945 @cond 0 946 */ 947 #define IS_XSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\ 948 ((THRESHOLD) <= ((XSPI_CR_FTHRES >> XSPI_CR_FTHRES_Pos)+1U))) 949 #define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ 950 ((MODE) == HAL_XSPI_DUAL_MEM)) 951 952 #define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ 953 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \ 954 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \ 955 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \ 956 ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \ 957 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS)) 958 959 #define IS_XSPI_MEMORY_SIZE(SIZE) (((SIZE) == HAL_XSPI_SIZE_16B) || \ 960 ((SIZE) == HAL_XSPI_SIZE_32B) || \ 961 ((SIZE) == HAL_XSPI_SIZE_64B) || \ 962 ((SIZE) == HAL_XSPI_SIZE_128B) || \ 963 ((SIZE) == HAL_XSPI_SIZE_256B) || \ 964 ((SIZE) == HAL_XSPI_SIZE_512B) || \ 965 ((SIZE) == HAL_XSPI_SIZE_1KB) || \ 966 ((SIZE) == HAL_XSPI_SIZE_2KB) || \ 967 ((SIZE) == HAL_XSPI_SIZE_4KB) || \ 968 ((SIZE) == HAL_XSPI_SIZE_8KB) || \ 969 ((SIZE) == HAL_XSPI_SIZE_16KB) || \ 970 ((SIZE) == HAL_XSPI_SIZE_32KB) || \ 971 ((SIZE) == HAL_XSPI_SIZE_64KB) || \ 972 ((SIZE) == HAL_XSPI_SIZE_128KB) || \ 973 ((SIZE) == HAL_XSPI_SIZE_256KB) || \ 974 ((SIZE) == HAL_XSPI_SIZE_512KB) || \ 975 ((SIZE) == HAL_XSPI_SIZE_1MB) || \ 976 ((SIZE) == HAL_XSPI_SIZE_2MB) || \ 977 ((SIZE) == HAL_XSPI_SIZE_4MB) || \ 978 ((SIZE) == HAL_XSPI_SIZE_8MB) || \ 979 ((SIZE) == HAL_XSPI_SIZE_16MB) || \ 980 ((SIZE) == HAL_XSPI_SIZE_32MB) || \ 981 ((SIZE) == HAL_XSPI_SIZE_64MB) || \ 982 ((SIZE) == HAL_XSPI_SIZE_128MB) || \ 983 ((SIZE) == HAL_XSPI_SIZE_256MB) || \ 984 ((SIZE) == HAL_XSPI_SIZE_512MB) || \ 985 ((SIZE) == HAL_XSPI_SIZE_1GB) || \ 986 ((SIZE) == HAL_XSPI_SIZE_2GB) || \ 987 ((SIZE) == HAL_XSPI_SIZE_4GB) || \ 988 ((SIZE) == HAL_XSPI_SIZE_8GB) || \ 989 ((SIZE) == HAL_XSPI_SIZE_16GB) || \ 990 ((SIZE) == HAL_XSPI_SIZE_32GB)) 991 992 #define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) 993 994 #define IS_XSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \ 995 ((CLK) == HAL_XSPI_FREERUNCLK_ENABLE)) 996 997 #define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ 998 ((MODE) == HAL_XSPI_CLOCK_MODE_3)) 999 1000 #define IS_XSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \ 1001 ((SIZE) == HAL_XSPI_WRAP_16_BYTES) || \ 1002 ((SIZE) == HAL_XSPI_WRAP_32_BYTES) || \ 1003 ((SIZE) == HAL_XSPI_WRAP_64_BYTES) || \ 1004 ((SIZE) == HAL_XSPI_WRAP_128_BYTES)) 1005 1006 #define IS_XSPI_CLK_PRESCALER(PRESCALER) ((PRESCALER) <= 255U) 1007 1008 #define IS_XSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE) || \ 1009 ((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)) 1010 1011 #define IS_XSPI_DHQC(CYCLE) (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \ 1012 ((CYCLE) == HAL_XSPI_DHQC_ENABLE)) 1013 1014 #define IS_XSPI_CS_BOUND(SIZE) (((SIZE) == HAL_XSPI_BONDARYOF_NONE) || \ 1015 ((SIZE) == HAL_XSPI_BONDARYOF_16B) || \ 1016 ((SIZE) == HAL_XSPI_BONDARYOF_32B) || \ 1017 ((SIZE) == HAL_XSPI_BONDARYOF_64B) || \ 1018 ((SIZE) == HAL_XSPI_BONDARYOF_128B) || \ 1019 ((SIZE) == HAL_XSPI_BONDARYOF_256B) || \ 1020 ((SIZE) == HAL_XSPI_BONDARYOF_512B) || \ 1021 ((SIZE) == HAL_XSPI_BONDARYOF_1KB) || \ 1022 ((SIZE) == HAL_XSPI_BONDARYOF_2KB) || \ 1023 ((SIZE) == HAL_XSPI_BONDARYOF_4KB) || \ 1024 ((SIZE) == HAL_XSPI_BONDARYOF_8KB) || \ 1025 ((SIZE) == HAL_XSPI_BONDARYOF_16KB) || \ 1026 ((SIZE) == HAL_XSPI_BONDARYOF_32KB) || \ 1027 ((SIZE) == HAL_XSPI_BONDARYOF_64KB) || \ 1028 ((SIZE) == HAL_XSPI_BONDARYOF_128KB) || \ 1029 ((SIZE) == HAL_XSPI_BONDARYOF_256KB) || \ 1030 ((SIZE) == HAL_XSPI_BONDARYOF_512KB) || \ 1031 ((SIZE) == HAL_XSPI_BONDARYOF_1MB) || \ 1032 ((SIZE) == HAL_XSPI_BONDARYOF_2MB) || \ 1033 ((SIZE) == HAL_XSPI_BONDARYOF_4MB) || \ 1034 ((SIZE) == HAL_XSPI_BONDARYOF_8MB) || \ 1035 ((SIZE) == HAL_XSPI_BONDARYOF_16MB) || \ 1036 ((SIZE) == HAL_XSPI_BONDARYOF_32MB) || \ 1037 ((SIZE) == HAL_XSPI_BONDARYOF_64MB) || \ 1038 ((SIZE) == HAL_XSPI_BONDARYOF_128MB) || \ 1039 ((SIZE) == HAL_XSPI_BONDARYOF_256MB) || \ 1040 ((SIZE) == HAL_XSPI_BONDARYOF_512MB) || \ 1041 ((SIZE) == HAL_XSPI_BONDARYOF_1GB) || \ 1042 ((SIZE) == HAL_XSPI_BONDARYOF_2GB) || \ 1043 ((SIZE) == HAL_XSPI_BONDARYOF_4GB) || \ 1044 ((SIZE) == HAL_XSPI_BONDARYOF_8GB) || \ 1045 ((SIZE) == HAL_XSPI_BONDARYOF_16GB)) 1046 1047 #define IS_XSPI_DLYB_BYPASS(DLYB) (((DLYB) == HAL_XSPI_DELAY_BLOCK_ON) || \ 1048 ((DLYB) == HAL_XSPI_DELAY_BLOCK_BYPASS)) 1049 1050 1051 1052 #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ 1053 ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \ 1054 ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \ 1055 ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG)) 1056 1057 #define IS_XSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \ 1058 ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \ 1059 ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0)) 1060 1061 #define IS_XSPI_INSTRUCTION(OPCODE) ((OPCODE) <= 0xFFFFFFFFU) 1062 1063 #define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ 1064 ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \ 1065 ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \ 1066 ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \ 1067 ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES)) 1068 1069 #define IS_XSPI_INSTRUCTION_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS) || \ 1070 ((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \ 1071 ((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \ 1072 ((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS)) 1073 1074 #define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ 1075 ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) 1076 1077 #define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ 1078 ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \ 1079 ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \ 1080 ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \ 1081 ((MODE) == HAL_XSPI_ADDRESS_8_LINES)) 1082 1083 #define IS_XSPI_ADDRESS_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS) || \ 1084 ((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \ 1085 ((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \ 1086 ((WIDTH) == HAL_XSPI_ADDRESS_32_BITS)) 1087 1088 #define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ 1089 ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE)) 1090 1091 #define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ 1092 ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \ 1093 ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \ 1094 ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \ 1095 ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES)) 1096 1097 #define IS_XSPI_ALT_BYTES_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS) || \ 1098 ((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \ 1099 ((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \ 1100 ((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS)) 1101 1102 #define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ 1103 ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE)) 1104 1105 #define IS_XSPI_DATA_MODE(MODE) (((MODE) == HAL_XSPI_DATA_NONE) || \ 1106 ((MODE) == HAL_XSPI_DATA_1_LINE) || \ 1107 ((MODE) == HAL_XSPI_DATA_2_LINES) || \ 1108 ((MODE) == HAL_XSPI_DATA_4_LINES) || \ 1109 ((MODE) == HAL_XSPI_DATA_8_LINES)) 1110 1111 #define IS_XSPI_DATA_LENGTH(NUMBER) ((NUMBER) >= 1U) 1112 1113 #define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ 1114 ((MODE) == HAL_XSPI_DATA_DTR_ENABLE)) 1115 1116 #define IS_XSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 1117 1118 #define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ 1119 ((MODE) == HAL_XSPI_DQS_ENABLE)) 1120 1121 #define IS_XSPI_SIOO_MODE(MODE) (((MODE) == HAL_XSPI_SIOO_INST_EVERY_CMD) || \ 1122 ((MODE) == HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD)) 1123 1124 #define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) 1125 1126 #define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) 1127 1128 #define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ 1129 ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE)) 1130 1131 #define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ 1132 ((MODE) == HAL_XSPI_FIXED_LATENCY)) 1133 1134 #define IS_XSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \ 1135 ((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE)) 1136 1137 #define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ 1138 ((MODE) == HAL_XSPI_MATCH_MODE_OR)) 1139 1140 #define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ 1141 ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE)) 1142 1143 #define IS_XSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 1144 1145 #define IS_XSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 1146 1147 #define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ 1148 ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE)) 1149 1150 #define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 1151 1152 /** 1153 @endcond 1154 */ 1155 1156 /* End of private macros -----------------------------------------------------*/ 1157 1158 /** 1159 * @} 1160 */ 1161 1162 /** 1163 * @} 1164 */ 1165 1166 #endif /* HSPI || HSPI1 || HSPI2 || OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 1167 1168 #ifdef __cplusplus 1169 } 1170 #endif 1171 1172 #endif /* STM32U5xx_HAL_XSPI_H */ 1173
