1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_xspi.h 4 * @author MCD Application Team 5 * @brief Header file of XSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_XSPI_H 21 #define STM32N6xx_HAL_XSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 #if defined(XSPI) || defined(XSPI1) || defined(XSPI2) || defined(XSPI3) 31 32 /** @addtogroup STM32N6xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup XSPI 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup XSPI_Exported_Types XSPI Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief XSPI Init structure definition 47 */ 48 typedef struct 49 { 50 uint32_t FifoThresholdByte; /*!< This is the threshold used by the Peripheral to generate the interrupt 51 indicating that data are available in reception or free place 52 is available in transmission. 53 For XSPI, this parameter can be a value between 1 and 64 */ 54 uint32_t MemoryMode; /*!< It Specifies the memory mode. 55 This parameter can be a value of @ref XSPI_MemoryMode */ 56 uint32_t MemoryType; /*!< It indicates the external device type connected to the XSPI. 57 This parameter can be a value of @ref XSPI_MemoryType */ 58 uint32_t MemorySize; /*!< It defines the size of the external device connected to the XSPI, 59 it corresponds to the number of address bits required to access 60 the external device. 61 This parameter can be a value of @ref XSPI_MemorySize*/ 62 uint32_t ChipSelectHighTimeCycle; /*!< It defines the minimum number of clocks which the chip select 63 must remain high between commands. 64 This parameter can be a value between 1 and 64U */ 65 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 66 This parameter can be a value of @ref XSPI_FreeRunningClock */ 67 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 68 This parameter can be a value of @ref XSPI_ClockMode */ 69 uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. 70 This parameter can be a value of @ref XSPI_WrapSize */ 71 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 72 the external clock based on the AHB clock. 73 This parameter can be a value between 0 and 255U */ 74 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 75 to take in account external signal delays. 76 This parameter can be a value of @ref XSPI_SampleShifting */ 77 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 78 This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */ 79 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 80 defines the boundary of bytes to release the chip select. 81 This parameter can be a value of @ref XSPI_ChipSelectBoundary */ 82 uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is 83 released every MaxTran+1 bytes when the other XSPI request the access 84 to the bus. 85 This parameter can be a value between 0 and 255U */ 86 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 87 Refresh+1 clock cycles. 88 This parameter can be a value between 0 and 0xFFFFFFFF */ 89 uint32_t MemorySelect; /*!< It indicates if the output of nCS. 90 This parameter can be a value of @ref XSPI_MemorySelect */ 91 uint32_t MemoryExtended; /*!< If available, It indicates if NCS1 and NCS2 are software or hardware controlled when one 92 XSPI drives two same size external memories located in contiguous places 93 in the memory map. 94 This parameter can be a value of @ref XSPI_MemoryExtended */ 95 } XSPI_InitTypeDef; 96 97 /** 98 * @brief HAL XSPI Handle Structure definition 99 */ 100 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 101 typedef struct __XSPI_HandleTypeDef 102 #else 103 typedef struct 104 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 105 { 106 XSPI_TypeDef *Instance; /*!< XSPI registers base address */ 107 XSPI_InitTypeDef Init; /*!< XSPI initialization parameters */ 108 uint8_t *pBuffPtr; /*!< Address of the XSPI buffer for transfer */ 109 __IO uint32_t XferSize; /*!< Number of data to transfer */ 110 __IO uint32_t XferCount; /*!< Counter of data transferred */ 111 DMA_HandleTypeDef *hdmatx; /*!< Handle of the DMA channel used for transmit */ 112 DMA_HandleTypeDef *hdmarx; /*!< Handle of the DMA channel used for receive */ 113 __IO uint32_t State; /*!< Internal state of the XSPI HAL driver */ 114 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 115 uint32_t Timeout; /*!< Timeout used for the XSPI external device access */ 116 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 117 void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi); 118 void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 119 void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi); 120 void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 121 void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 122 void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 123 void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 124 void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 125 void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi); 126 void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi); 127 128 void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi); 129 void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi); 130 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 131 } XSPI_HandleTypeDef; 132 133 /** 134 * @brief HAL XSPI Regular Command Structure definition 135 */ 136 typedef struct 137 { 138 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 139 to the registers for the write operation (these registers are only 140 used for memory-mapped mode). 141 This parameter can be a value of @ref XSPI_OperationType */ 142 uint32_t IOSelect; /*!< It indicates the IOs used to exchange data with external memory. 143 This parameter can be a value of @ref XSPI_IOSelect */ 144 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 145 This parameter can be a value between 0 and 0xFFFFFFFFU */ 146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 147 This parameter can be a value of @ref XSPI_InstructionMode */ 148 uint32_t InstructionWidth; /*!< It indicates the width of the instruction. 149 This parameter can be a value of @ref XSPI_InstructionWidth */ 150 uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase. 151 This parameter can be a value of @ref XSPI_InstructionDTRMode */ 152 uint32_t Address; /*!< It contains the address to be sent to the device. 153 This parameter can be a value between 0 and 0xFFFFFFFFU */ 154 uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises number of lines 155 for address (except no address). 156 This parameter can be a value of @ref XSPI_AddressMode */ 157 uint32_t AddressWidth; /*!< It indicates the width of the address. 158 This parameter can be a value of @ref XSPI_AddressWidth */ 159 uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase. 160 This parameter can be a value of @ref XSPI_AddressDTRMode */ 161 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 162 This parameter can be a value between 0 and 0xFFFFFFFFU */ 163 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 164 This parameter can be a value of @ref XSPI_AlternateBytesMode */ 165 uint32_t AlternateBytesWidth; /*!< It indicates the width of the alternate bytes. 166 This parameter can be a value of @ref XSPI_AlternateBytesWidth */ 167 uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 168 This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */ 169 uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines 170 for data exchange (except no data). 171 This parameter can be a value of @ref XSPI_DataMode */ 172 uint32_t DataLength; /*!< It indicates the number of data transferred with this command. 173 This field is only used for indirect mode. 174 This parameter can be a value between 1 and 0xFFFFFFFFU */ 175 uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase. 176 This parameter can be a value of @ref XSPI_DataDTRMode */ 177 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 178 This parameter can be a value between 0 and 31U */ 179 uint32_t DQSMode; /*!< It enables or not the data strobe management. 180 This parameter can be a value of @ref XSPI_DQSMode */ 181 } XSPI_RegularCmdTypeDef; 182 /** 183 * @brief HAL XSPI Hyperbus Configuration Structure definition 184 */ 185 typedef struct 186 { 187 uint32_t RWRecoveryTimeCycle; /*!< It indicates the number of cycles for the device read write recovery time. 188 This parameter can be a value between 0 and 255U */ 189 uint32_t AccessTimeCycle; /*!< It indicates the number of cycles for the device access time. 190 This parameter can be a value between 0 and 255U */ 191 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 192 This parameter can be a value of @ref XSPI_WriteZeroLatency */ 193 uint32_t LatencyMode; /*!< It configures the latency mode. 194 This parameter can be a value of @ref XSPI_LatencyMode */ 195 } XSPI_HyperbusCfgTypeDef; 196 197 /** 198 * @brief HAL XSPI Hyperbus Command Structure definition 199 */ 200 typedef struct 201 { 202 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 203 This parameter can be a value of @ref XSPI_AddressSpace */ 204 uint32_t Address; /*!< It contains the address to be sent to the device. 205 This parameter can be a value between 0 and 0xFFFFFFFFU */ 206 uint32_t AddressWidth; /*!< It indicates the width of the address. 207 This parameter can be a value of @ref XSPI_AddressWidth */ 208 uint32_t DataLength; /*!< It indicates the number of data transferred with this command. 209 This field is only used for indirect mode. 210 This parameter can be a value between 1 and 0xFFFFFFFF 211 In case of autopolling mode, this parameter can be 212 any value between 1 and 4 */ 213 uint32_t DQSMode; /*!< It enables or not the data strobe management. 214 This parameter can be a value of @ref XSPI_DQSMode */ 215 uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines 216 for data exchange (except no data). 217 This parameter can be a value of @ref XSPI_DataMode */ 218 } XSPI_HyperbusCmdTypeDef; 219 220 /** 221 * @brief HAL XSPI Auto Polling mode configuration structure definition 222 */ 223 typedef struct 224 { 225 uint32_t MatchValue; /*!< Specifies the value to be compared with the masked status register to get 226 a match. 227 This parameter can be any value between 0 and 0xFFFFFFFFU */ 228 uint32_t MatchMask; /*!< Specifies the mask to be applied to the status bytes received. 229 This parameter can be any value between 0 and 0xFFFFFFFFU */ 230 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 231 This parameter can be a value of @ref XSPI_MatchMode */ 232 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 233 This parameter can be a value of @ref XSPI_AutomaticStop */ 234 uint32_t IntervalTime; /*!< Specifies the number of clock cycles between two read during automatic 235 polling phases. 236 This parameter can be any value between 0 and 0xFFFFU */ 237 } XSPI_AutoPollingTypeDef; 238 239 /** 240 * @brief HAL XSPI Memory Mapped mode configuration structure definition 241 */ 242 typedef struct 243 { 244 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 245 This parameter can be a value of @ref XSPI_TimeOutActivation */ 246 uint32_t TimeoutPeriodClock; /*!< Specifies the number of clock to wait when the FIFO is full before to 247 release the chip select. 248 This parameter can be any value between 0 and 0xFFFFU */ 249 uint32_t NoPrefetchData; /*!< Specifies if the automatic prefetch in the external memory is enabled or not. 250 This parameter can be a value of @ref XSPI_NoPrefetchData */ 251 uint32_t NoPrefetchAXI; /*!< Specifies if the automatic prefetch in the external memory when the corresponding AXI 252 transaction is signaled as not-prefetchable, is enabled or not. 253 This parameter can be a value of @ref XSPI_NoPrefetchAXI */ 254 } XSPI_MemoryMappedTypeDef; 255 256 /** 257 * @brief HAL XSPI IO Manager Configuration structure definition 258 */ 259 typedef struct 260 { 261 uint32_t nCSOverride; /*!< It indicates Chip select selector override setting for XSPI. 262 This parameter can be a value @ref XSPIM_MemorySelect_Override */ 263 uint32_t IOPort; /*!< It indicates which port of the XSPI IO Manager is used for the instance. 264 This parameter can be a value of @ref XSPI_IO_Manger_IOPort */ 265 uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) 266 expected if some signals are multiplexed in the XSPI IO Manager with the 267 other XSPI. 268 This parameter can be a value between 1 and 256 */ 269 } XSPIM_CfgTypeDef; 270 271 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 272 /** 273 * @brief HAL XSPI Callback ID enumeration definition 274 */ 275 typedef enum 276 { 277 HAL_XSPI_ERROR_CB_ID = 0x00U, /*!< XSPI Error Callback ID */ 278 HAL_XSPI_ABORT_CB_ID = 0x01U, /*!< XSPI Abort Callback ID */ 279 HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< XSPI FIFO Threshold Callback ID */ 280 HAL_XSPI_CMD_CPLT_CB_ID = 0x03U, /*!< XSPI Command Complete Callback ID */ 281 HAL_XSPI_RX_CPLT_CB_ID = 0x04U, /*!< XSPI Rx Complete Callback ID */ 282 HAL_XSPI_TX_CPLT_CB_ID = 0x05U, /*!< XSPI Tx Complete Callback ID */ 283 HAL_XSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< XSPI Rx Half Complete Callback ID */ 284 HAL_XSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< XSPI Tx Half Complete Callback ID */ 285 HAL_XSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< XSPI Status Match Callback ID */ 286 HAL_XSPI_TIMEOUT_CB_ID = 0x09U, /*!< XSPI Timeout Callback ID */ 287 HAL_XSPI_MSP_INIT_CB_ID = 0x0AU, /*!< XSPI MspInit Callback ID */ 288 HAL_XSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< XSPI MspDeInit Callback ID */ 289 } HAL_XSPI_CallbackIDTypeDef; 290 291 /** 292 * @brief HAL XSPI Callback pointer definition 293 */ 294 typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); 295 296 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 297 /** 298 * @brief HAL XSPI High-speed interface calibration structure definition 299 */ 300 typedef struct 301 { 302 uint32_t DelayValueType; /*!< It indicates which calibration is concerned by the configuration. 303 This parameter can be a value of @ref XSPI_DelayType */ 304 uint32_t FineCalibrationUnit; /*!< It indicates the fine calibration value of the delay. 305 This parameter can be a value between 0 and 0x7FU */ 306 uint32_t CoarseCalibrationUnit; /*!< It indicates the coarse calibration value of the delay. 307 This parameter can be a value between 0 and 0x1FU */ 308 uint32_t MaxCalibration; /*!< It indicates that the calibration is outside the range of DLL master. 309 It applies only when the DelayValueType is HAL_XSPI_CAL_FULL_CYCLE_DELAY. 310 This parameter can be a value of @ref XSPI_MaxCal */ 311 } XSPI_HSCalTypeDef; 312 313 /** 314 * @} 315 */ 316 317 /* Exported constants --------------------------------------------------------*/ 318 /** @defgroup XSPI_Exported_Constants XSPI Exported Constants 319 * @{ 320 */ 321 322 /** @defgroup XSPI_State XSPI State 323 * @{ 324 */ 325 #define HAL_XSPI_STATE_RESET (0x00000000U) /*!< Initial state */ 326 #define HAL_XSPI_STATE_READY (0x00000002U) /*!< Driver ready to be used */ 327 #define HAL_XSPI_STATE_HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 328 #define HAL_XSPI_STATE_CMD_CFG (0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 329 #define HAL_XSPI_STATE_READ_CMD_CFG (0x00000014U) /*!< Read command configuration done, not the write command configuration */ 330 #define HAL_XSPI_STATE_WRITE_CMD_CFG (0x00000024U) /*!< Write command configuration done, not the read command configuration */ 331 #define HAL_XSPI_STATE_BUSY_CMD (0x00000008U) /*!< Command without data on-going */ 332 #define HAL_XSPI_STATE_BUSY_TX (0x00000018U) /*!< Indirect Tx on-going */ 333 #define HAL_XSPI_STATE_BUSY_RX (0x00000028U) /*!< Indirect Rx on-going */ 334 #define HAL_XSPI_STATE_BUSY_AUTO_POLLING (0x00000048U) /*!< Auto-polling on-going */ 335 #define HAL_XSPI_STATE_BUSY_MEM_MAPPED (0x00000088U) /*!< Memory-mapped on-going */ 336 #define HAL_XSPI_STATE_ABORT (0x00000100U) /*!< Abort on-going */ 337 #define HAL_XSPI_STATE_ERROR (0x00000200U) /*!< Blocking error, driver should be re-initialized */ 338 /** 339 * @} 340 */ 341 342 /** @defgroup XSPI_ErrorCode XSPI Error Code 343 * @{ 344 */ 345 #define HAL_XSPI_ERROR_NONE (0x00000000U) /*!< No error */ 346 #define HAL_XSPI_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ 347 #define HAL_XSPI_ERROR_TRANSFER (0x00000002U) /*!< Transfer error */ 348 #define HAL_XSPI_ERROR_DMA (0x00000004U) /*!< DMA transfer error */ 349 #define HAL_XSPI_ERROR_INVALID_PARAM (0x00000008U) /*!< Invalid parameters error */ 350 #define HAL_XSPI_ERROR_INVALID_SEQUENCE (0x00000010U) /*!< Sequence is incorrect */ 351 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 352 #define HAL_XSPI_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid callback error */ 353 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup XSPI_MemoryMode XSPI Memory Mode 359 * @{ 360 */ 361 #define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */ 362 #define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */ 363 364 /** 365 * @} 366 */ 367 368 /** @defgroup XSPI_MemoryType XSPI Memory Type 369 * @{ 370 */ 371 #define HAL_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */ 372 #define HAL_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */ 373 #define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 374 #define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/ 375 #define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 376 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */ 377 378 /** 379 * @} 380 */ 381 382 /** @defgroup XSPI_MemorySize XSPI Memory Size 383 * @{ 384 */ 385 #define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Bytes = 2^( 0+1)) */ 386 #define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Bytes = 2^( 1+1)) */ 387 #define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Bytes = 2^( 2+1)) */ 388 #define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Bytes = 2^( 3+1)) */ 389 #define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Bytes = 2^( 4+1)) */ 390 #define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Bytes = 2^( 5+1)) */ 391 #define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Bytes = 2^( 6+1)) */ 392 #define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Bytes = 2^( 7+1)) */ 393 #define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Bytes = 2^( 8+1)) */ 394 #define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KBytes = 2^( 9+1)) */ 395 #define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KBytes = 2^(10+1)) */ 396 #define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KBytes = 2^(11+1)) */ 397 #define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KBytes = 2^(12+1)) */ 398 #define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */ 399 #define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */ 400 #define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */ 401 #define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KBytes = 2^(16+1)) */ 402 #define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KBytes = 2^(17+1)) */ 403 #define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KBytes = 2^(18+1)) */ 404 #define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MBytes = 2^(19+1)) */ 405 #define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MBytes = 2^(20+1)) */ 406 #define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MBytes = 2^(21+1)) */ 407 #define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MBytes = 2^(22+1)) */ 408 #define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */ 409 #define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */ 410 #define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */ 411 #define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MBytes = 2^(26+1)) */ 412 #define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MBytes = 2^(27+1)) */ 413 #define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (512 MBytes = 2^(28+1)) */ 414 #define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits ( 1 GBytes = 2^(29+1)) */ 415 #define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits ( 2 GBytes = 2^(30+1)) */ 416 #define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits ( 4 GBytes = 2^(31+1)) */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock 422 * @{ 423 */ 424 #define HAL_XSPI_FREERUNCLK_DISABLE (0x00000000U) /*!< CLK is not free running */ 425 #define HAL_XSPI_FREERUNCLK_ENABLE ((uint32_t)XSPI_DCR1_FRCK) /*!< CLK is always provided (running) */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup XSPI_ClockMode XSPI Clock Mode 431 * @{ 432 */ 433 #define HAL_XSPI_CLOCK_MODE_0 (0x00000000U) /*!< CLK must stay low while nCS is high */ 434 #define HAL_XSPI_CLOCK_MODE_3 ((uint32_t)XSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 435 /** 436 * @} 437 */ 438 439 /** @defgroup XSPI_WrapSize XSPI Wrap-Size 440 * @{ 441 */ 442 #define HAL_XSPI_WRAP_NOT_SUPPORTED (0x00000000U) /*!< wrapped reads are not supported by the memory */ 443 #define HAL_XSPI_WRAP_16_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 444 #define HAL_XSPI_WRAP_32_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 445 #define HAL_XSPI_WRAP_64_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 446 #define HAL_XSPI_WRAP_128_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 447 /** 448 * @} 449 */ 450 451 /** @defgroup XSPI_SampleShifting XSPI Sample Shifting 452 * @{ 453 */ 454 #define HAL_XSPI_SAMPLE_SHIFT_NONE (0x00000000U) /*!< No shift */ 455 #define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE ((uint32_t)XSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 456 /** 457 * @} 458 */ 459 460 /** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle 461 * @{ 462 */ 463 #define HAL_XSPI_DHQC_DISABLE (0x00000000U) /*!< No Delay */ 464 #define HAL_XSPI_DHQC_ENABLE ((uint32_t)XSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 465 /** 466 * @} 467 */ 468 469 /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary 470 * @{ 471 */ 472 #define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ 473 #define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Bytes = 2^(1)) */ 474 #define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Bytes = 2^(2)) */ 475 #define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Bytes = 2^(3)) */ 476 #define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Bytes = 2^(4)) */ 477 #define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Bytes = 2^(5)) */ 478 #define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Bytes = 2^(6)) */ 479 #define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Bytes = 2^(7)) */ 480 #define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Bytes = 2^(8)) */ 481 #define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Bytes = 2^(9)) */ 482 #define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KBytes = 2^(10)) */ 483 #define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KBytes = 2^(11)) */ 484 #define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KBytes = 2^(12)) */ 485 #define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KBytes = 2^(13)) */ 486 #define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KBytes = 2^(14)) */ 487 #define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KBytes = 2^(15)) */ 488 #define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KBytes = 2^(16)) */ 489 #define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KBytes = 2^(17)) */ 490 #define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KBytes = 2^(18)) */ 491 #define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KBytes = 2^(19)) */ 492 #define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MBytes = 2^(20)) */ 493 #define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MBytes = 2^(21)) */ 494 #define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MBytes = 2^(22)) */ 495 #define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MBytes = 2^(23)) */ 496 #define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MBytes = 2^(24)) */ 497 #define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MBytes = 2^(25)) */ 498 #define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MBytes = 2^(26)) */ 499 #define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MBytes = 2^(27)) */ 500 #define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MBytes = 2^(28)) */ 501 #define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MBytes = 2^(29)) */ 502 #define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GBytes = 2^(30)) */ 503 #define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GBytes = 2^(31)) */ 504 /** 505 * @} 506 */ 507 508 /** @defgroup XSPI_MemorySelect XSPI Memory Select 509 * @{ 510 */ 511 #define HAL_XSPI_CSSEL_NCS1 (0x00000000U) /*!< The output of nCS is nCS1 */ 512 #define HAL_XSPI_CSSEL_NCS2 ((uint32_t)XSPI_CR_CSSEL) /*!< The output of nCS is nCS2 */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup XSPI_MemoryExtended XSPI Memory Extended 518 * @{ 519 */ 520 #define HAL_XSPI_CSSEL_SW (0x00000000U) /*!< NCS1 and NCS2 are software controlled. */ 521 #define HAL_XSPI_CSSEL_HW ((uint32_t)XSPI_DCR1_EXTENDMEM) /*!< NCS1 and NCS2 are hardware controlled. */ 522 /** 523 * @} 524 */ 525 526 /** @defgroup XSPI_OperationType XSPI Operation Type 527 * @{ 528 */ 529 #define HAL_XSPI_OPTYPE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 530 #define HAL_XSPI_OPTYPE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */ 531 #define HAL_XSPI_OPTYPE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */ 532 #define HAL_XSPI_OPTYPE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ 533 534 /** 535 * @} 536 */ 537 538 /** @defgroup XSPI_IOSelect XSPI IO Select 539 * @{ 540 */ 541 #define HAL_XSPI_SELECT_IO_3_0 (0x00000000U) /*!< Data exchanged over IO[3:0] */ 542 #define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)XSPI_CR_MSEL_0) /*!< Data exchanged over IO[7:4] */ 543 #define HAL_XSPI_SELECT_IO_11_8 ((uint32_t)XSPI_CR_MSEL_1) /*!< Data exchanged over IO[11:8] */ 544 #define HAL_XSPI_SELECT_IO_15_12 ((uint32_t)XSPI_CR_MSEL ) /*!< Data exchanged over IO[15:12] */ 545 #define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */ 546 #define HAL_XSPI_SELECT_IO_15_8 ((uint32_t)XSPI_CR_MSEL_1) /*!< Data exchanged over IO[15:8] */ 547 /** 548 * @} 549 */ 550 551 /** @defgroup XSPI_InstructionMode XSPI Instruction Mode 552 * @{ 553 */ 554 #define HAL_XSPI_INSTRUCTION_NONE (0x00000000U) /*!< No instruction */ 555 #define HAL_XSPI_INSTRUCTION_1_LINE ((uint32_t)XSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 556 #define HAL_XSPI_INSTRUCTION_2_LINES ((uint32_t)XSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 557 #define HAL_XSPI_INSTRUCTION_4_LINES ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 558 #define HAL_XSPI_INSTRUCTION_8_LINES ((uint32_t)XSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup XSPI_InstructionWidth XSPI Instruction Width 564 * @{ 565 */ 566 #define HAL_XSPI_INSTRUCTION_8_BITS (0x00000000U) /*!< 8-bit instruction */ 567 #define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 568 #define HAL_XSPI_INSTRUCTION_24_BITS ((uint32_t)XSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 569 #define HAL_XSPI_INSTRUCTION_32_BITS ((uint32_t)XSPI_CCR_ISIZE) /*!< 32-bit instruction */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode 575 * @{ 576 */ 577 #define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for instruction phase */ 578 #define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 579 /** 580 * @} 581 */ 582 583 /** @defgroup XSPI_AddressMode XSPI Address Mode 584 * @{ 585 */ 586 #define HAL_XSPI_ADDRESS_NONE (0x00000000U) /*!< No address */ 587 #define HAL_XSPI_ADDRESS_1_LINE ((uint32_t)XSPI_CCR_ADMODE_0) /*!< Address on a single line */ 588 #define HAL_XSPI_ADDRESS_2_LINES ((uint32_t)XSPI_CCR_ADMODE_1) /*!< Address on two lines */ 589 #define HAL_XSPI_ADDRESS_4_LINES ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 590 #define HAL_XSPI_ADDRESS_8_LINES ((uint32_t)XSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 591 /** 592 * @} 593 */ 594 595 /** @defgroup XSPI_AddressWidth XSPI Address width 596 * @{ 597 */ 598 #define HAL_XSPI_ADDRESS_8_BITS (0x00000000U) /*!< 8-bit address */ 599 #define HAL_XSPI_ADDRESS_16_BITS ((uint32_t)XSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 600 #define HAL_XSPI_ADDRESS_24_BITS ((uint32_t)XSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 601 #define HAL_XSPI_ADDRESS_32_BITS ((uint32_t)XSPI_CCR_ADSIZE) /*!< 32-bit address */ 602 /** 603 * @} 604 */ 605 606 /** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode 607 * @{ 608 */ 609 #define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for address phase */ 610 #define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 611 /** 612 * @} 613 */ 614 615 /** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode 616 * @{ 617 */ 618 #define HAL_XSPI_ALT_BYTES_NONE (0x00000000U) /*!< No alternate bytes */ 619 #define HAL_XSPI_ALT_BYTES_1_LINE ((uint32_t)XSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 620 #define HAL_XSPI_ALT_BYTES_2_LINES ((uint32_t)XSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 621 #define HAL_XSPI_ALT_BYTES_4_LINES ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 622 #define HAL_XSPI_ALT_BYTES_8_LINES ((uint32_t)XSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 623 /** 624 * @} 625 */ 626 627 /** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width 628 * @{ 629 */ 630 #define HAL_XSPI_ALT_BYTES_8_BITS (0x00000000U) /*!< 8-bit alternate bytes */ 631 #define HAL_XSPI_ALT_BYTES_16_BITS ((uint32_t)XSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 632 #define HAL_XSPI_ALT_BYTES_24_BITS ((uint32_t)XSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 633 #define HAL_XSPI_ALT_BYTES_32_BITS ((uint32_t)XSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 634 /** 635 * @} 636 */ 637 638 /** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode 639 * @{ 640 */ 641 #define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 642 #define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 643 /** 644 * @} 645 */ 646 647 /** @defgroup XSPI_DataMode XSPI Data Mode 648 * @{ 649 */ 650 #define HAL_XSPI_DATA_NONE (0x00000000U) /*!< No data */ 651 #define HAL_XSPI_DATA_1_LINE ((uint32_t)XSPI_CCR_DMODE_0) /*!< Data on a single line */ 652 #define HAL_XSPI_DATA_2_LINES ((uint32_t)XSPI_CCR_DMODE_1) /*!< Data on two lines */ 653 #define HAL_XSPI_DATA_4_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1)) /*!< Data on four lines */ 654 #define HAL_XSPI_DATA_8_LINES ((uint32_t)XSPI_CCR_DMODE_2) /*!< Data on eight lines */ 655 #define HAL_XSPI_DATA_16_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_2)) /*!< Data on sixteen lines valid for HSPI only */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode 661 * @{ 662 */ 663 #define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for data phase */ 664 #define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 665 /** 666 * @} 667 */ 668 669 /** @defgroup XSPI_DQSMode XSPI DQS Mode 670 * @{ 671 */ 672 #define HAL_XSPI_DQS_DISABLE (0x00000000U) /*!< DQS disabled */ 673 #define HAL_XSPI_DQS_ENABLE ((uint32_t)XSPI_CCR_DQSE) /*!< DQS enabled */ 674 /** 675 * @} 676 */ 677 678 /** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation 679 * @{ 680 */ 681 #define HAL_XSPI_LATENCY_ON_WRITE (0x00000000U) /*!< Latency on write accesses */ 682 #define HAL_XSPI_NO_LATENCY_ON_WRITE ((uint32_t)XSPI_HLCR_WZL) /*!< No latency on write accesses */ 683 /** 684 * @} 685 */ 686 687 /** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode 688 * @{ 689 */ 690 #define HAL_XSPI_VARIABLE_LATENCY (0x00000000U) /*!< Variable initial latency */ 691 #define HAL_XSPI_FIXED_LATENCY ((uint32_t)XSPI_HLCR_LM) /*!< Fixed latency */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space 697 * @{ 698 */ 699 #define HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */ 700 #define HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 701 /** 702 * @} 703 */ 704 705 /** @defgroup XSPI_MatchMode XSPI Match Mode 706 * @{ 707 */ 708 #define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between unmasked bits */ 709 #define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 710 /** 711 * @} 712 */ 713 714 /** @defgroup XSPI_AutomaticStop XSPI Automatic Stop 715 * @{ 716 */ 717 #define HAL_XSPI_AUTOMATIC_STOP_DISABLE (0x00000000U) /*!< AutoPolling stops only with abort or XSPI disabling */ 718 #define HAL_XSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)XSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 719 /** 720 * @} 721 */ 722 723 /** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation 724 * @{ 725 */ 726 #define HAL_XSPI_TIMEOUT_COUNTER_DISABLE (0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 727 #define HAL_XSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)XSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 728 /** 729 * @} 730 */ 731 732 /** @defgroup XSPI_NoPrefetchAXI XSPI No Prefetch AXI 733 * @{ 734 */ 735 #define HAL_XSPI_AXI_PREFETCH_ENABLE (0x00000000U) /*!< Prefetch is enabled for AXI signaled transactions */ 736 #define HAL_XSPI_AXI_PREFETCH_DISABLE ((uint32_t)XSPI_CR_NOPREF_AXI) /*!< Prefetch is disable for AXI signaled transactions */ 737 /** 738 * @} 739 */ 740 741 /** @defgroup XSPI_NoPrefetchData XSPI No Prefetch Data 742 * @{ 743 */ 744 #define HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE (0x00000000U) /*!< Automatic prefetch enabled */ 745 #define HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE ((uint32_t)XSPI_CR_NOPREF) /*!< Automatic prefetch disabled */ 746 /** 747 * @} 748 */ 749 750 /** @defgroup XSPI_Flags XSPI Flags 751 * @{ 752 */ 753 #define HAL_XSPI_FLAG_BUSY XSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 754 #define HAL_XSPI_FLAG_TO XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 755 #define HAL_XSPI_FLAG_SM XSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 756 #define HAL_XSPI_FLAG_FT XSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 757 #define HAL_XSPI_FLAG_TC XSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 758 #define HAL_XSPI_FLAG_TE XSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 759 /** 760 * @} 761 */ 762 763 /** @defgroup XSPI_Interrupts XSPI Interrupts 764 * @{ 765 */ 766 #define HAL_XSPI_IT_TO XSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 767 #define HAL_XSPI_IT_SM XSPI_CR_SMIE /*!< Interrupt on the status match flag */ 768 #define HAL_XSPI_IT_FT XSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 769 #define HAL_XSPI_IT_TC XSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 770 #define HAL_XSPI_IT_TE XSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 771 /** 772 * @} 773 */ 774 775 /** @defgroup XSPI_Timeout_definition XSPI Timeout definition 776 * @{ 777 */ 778 #define HAL_XSPI_TIMEOUT_DEFAULT_VALUE (5000U) /* 5 s */ 779 /** 780 * @} 781 */ 782 783 /** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port 784 * @{ 785 */ 786 #define HAL_XSPIM_IOPORT_1 (0x00000000U) /*!< Port 1 */ 787 #define HAL_XSPIM_IOPORT_2 (0x00000001U) /*!< Port 2 */ 788 /** 789 * @} 790 */ 791 792 793 /** @defgroup XSPI_DelayType XSPI Calibration Delay Type 794 * @{ 795 */ 796 #define HAL_XSPI_CAL_FULL_CYCLE_DELAY (0x00000000U) /*!< Delay value equivalent to full memory-clock cycle */ 797 #define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY (0x00000001U) /*!< Delay value for the feedback clock when reading without DQS */ 798 #define HAL_XSPI_CAL_DATA_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operations */ 799 #define HAL_XSPI_CAL_DQS_INPUT_DELAY (0x00000003U) /*!< Delay value for DQS input when sampling data for read operations */ 800 /** 801 * @} 802 */ 803 804 /** @defgroup XSPIM_MemorySelect_Override XSPIM Memory Select Override 805 * @{ 806 */ 807 #define HAL_XSPI_CSSEL_OVR_DISABLED (0x00000000U) 808 #define HAL_XSPI_CSSEL_OVR_NCS1 (0x00000010U) /*!< The chip select signal from XSPI is sent to NCS1 */ 809 #define HAL_XSPI_CSSEL_OVR_NCS2 (0x00000070U) /*!< The chip select signal from XSPI is sent to NCS2 */ 810 /** 811 * @} 812 */ 813 814 /** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value 815 * @{ 816 */ 817 #define HAL_XSPI_MAXCAL_NOT_REACHED (0x00000000U) /*!< Memory-clock perido inside the range of DLL master */ 818 #define HAL_XSPI_MAXCAL_REACHED ((uint32_t)XSPI_CALFCR_CALMAX) /*!< Memory-clock period outside the range of DLL master (max delay values used) */ 819 /** 820 * @} 821 */ 822 823 /** 824 * @} 825 */ 826 827 /* Exported macros -----------------------------------------------------------*/ 828 /** @defgroup XSPI_Exported_Macros XSPI Exported Macros 829 * @{ 830 */ 831 /** @brief Reset XSPI handle state. 832 * @param __HANDLE__ specifies the XSPI Handle. 833 * @retval None 834 */ 835 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 836 #define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 837 (__HANDLE__)->State = HAL_XSPI_STATE_RESET; \ 838 (__HANDLE__)->MspInitCallback = NULL; \ 839 (__HANDLE__)->MspDeInitCallback = NULL; \ 840 } while(0) 841 #else 842 #define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_XSPI_STATE_RESET) 843 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 844 845 /** @brief Enable the XSPI peripheral. 846 * @param __HANDLE__ specifies the XSPI Handle. 847 * @retval None 848 */ 849 #define HAL_XSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) 850 851 /** @brief Disable the XSPI peripheral. 852 * @param __HANDLE__ specifies the XSPI Handle. 853 * @retval None 854 */ 855 #define HAL_XSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) 856 857 /** @brief Enable the specified XSPI interrupt. 858 * @param __HANDLE__ specifies the XSPI Handle. 859 * @param __INTERRUPT__ specifies the XSPI interrupt source to enable. 860 * This parameter can be one of the following values: 861 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 862 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 863 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 864 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 865 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 866 * @retval None 867 */ 868 #define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 869 870 /** @brief Disable the specified XSPI interrupt. 871 * @param __HANDLE__ specifies the XSPI Handle. 872 * @param __INTERRUPT__ specifies the XSPI interrupt source to disable. 873 * This parameter can be one of the following values: 874 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 875 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 876 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 877 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 878 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 879 * @retval None 880 */ 881 #define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 882 883 /** @brief Check whether the specified XSPI interrupt source is enabled or not. 884 * @param __HANDLE__ specifies the XSPI Handle. 885 * @param __INTERRUPT__ specifies the XSPI interrupt source to check. 886 * This parameter can be one of the following values: 887 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 888 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 889 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 890 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 891 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 892 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 893 */ 894 #define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ 895 == (__INTERRUPT__)) 896 897 /** 898 * @brief Check whether the selected XSPI flag is set or not. 899 * @param __HANDLE__ specifies the XSPI Handle. 900 * @param __FLAG__ specifies the XSPI flag to check. 901 * This parameter can be one of the following values: 902 * @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag 903 * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag 904 * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag 905 * @arg HAL_XSPI_FLAG_FT: XSPI FIFO threshold flag 906 * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag 907 * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag 908 * @retval None 909 */ 910 #define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 911 != 0U) ? SET : RESET) 912 913 /** @brief Clears the specified XSPI's flag status. 914 * @param __HANDLE__ specifies the XSPI Handle. 915 * @param __FLAG__ specifies the XSPI clear register flag that needs to be set 916 * This parameter can be one of the following values: 917 * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag 918 * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag 919 * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag 920 * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag 921 * @retval None 922 */ 923 #define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 924 925 /** 926 * @} 927 */ 928 929 /* Exported functions --------------------------------------------------------*/ 930 /** @addtogroup XSPI_Exported_Functions XSPI Exported Functions 931 * @{ 932 */ 933 934 /* Initialization/de-initialization functions ********************************/ 935 /** @addtogroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions 936 * @{ 937 */ 938 HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi); 939 void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi); 940 HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi); 941 void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); 942 943 /** 944 * @} 945 */ 946 947 /* IO operation functions *****************************************************/ 948 /** @addtogroup XSPI_Exported_Functions_Group2 Input and Output operation functions 949 * @{ 950 */ 951 /* XSPI IRQ handler function */ 952 void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi); 953 954 /* XSPI command configuration functions */ 955 HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, 956 uint32_t Timeout); 957 HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); 958 HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, 959 uint32_t Timeout); 960 HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, 961 uint32_t Timeout); 962 963 /* XSPI indirect mode functions */ 964 HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); 965 HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); 966 HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); 967 HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 968 HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); 969 HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 970 971 /* XSPI status flag polling mode functions */ 972 HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, 973 uint32_t Timeout); 974 HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg); 975 976 /* XSPI memory-mapped mode functions */ 977 HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg); 978 979 /* Callback functions in non-blocking modes ***********************************/ 980 void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi); 981 void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi); 982 void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi); 983 984 /* XSPI indirect mode Callback functions */ 985 void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi); 986 void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi); 987 void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi); 988 void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); 989 void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); 990 991 /* XSPI status flag polling mode functions */ 992 void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi); 993 994 /* XSPI memory-mapped mode functions */ 995 void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi); 996 997 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 998 /* XSPI callback registering/unregistering */ 999 HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, 1000 pXSPI_CallbackTypeDef pCallback); 1001 HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID); 1002 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 1003 1004 /** 1005 * @} 1006 */ 1007 1008 /* Peripheral Control and State functions ************************************/ 1009 /** @addtogroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions 1010 * @{ 1011 */ 1012 HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi); 1013 HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi); 1014 HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold); 1015 uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi); 1016 HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type); 1017 HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size); 1018 HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler); 1019 HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout); 1020 uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi); 1021 uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi); 1022 1023 /** 1024 * @} 1025 */ 1026 1027 /* XSPI IO Manager configuration function ************************************/ 1028 /** @addtogroup XSPI_Exported_Functions_Group4 IO Manager configuration function 1029 * @{ 1030 */ 1031 HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout); 1032 1033 /** 1034 * @} 1035 */ 1036 1037 /* XSPI high-speed interface and calibration functions ***********************/ 1038 /** @addtogroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions 1039 * @{ 1040 */ 1041 HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); 1042 HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); 1043 1044 /** 1045 * @} 1046 */ 1047 1048 /** 1049 * @} 1050 */ 1051 /* End of exported functions -------------------------------------------------*/ 1052 1053 /* Private macros ------------------------------------------------------------*/ 1054 /** 1055 @cond 0 1056 */ 1057 #define IS_XSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\ 1058 ((THRESHOLD) <= ((XSPI_CR_FTHRES >> XSPI_CR_FTHRES_Pos)+1U))) 1059 #define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ 1060 ((MODE) == HAL_XSPI_DUAL_MEM)) 1061 1062 #define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ 1063 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \ 1064 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \ 1065 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \ 1066 ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \ 1067 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS)) 1068 1069 #define IS_XSPI_MEMORY_SIZE(SIZE) (((SIZE) == HAL_XSPI_SIZE_16B) || \ 1070 ((SIZE) == HAL_XSPI_SIZE_32B) || \ 1071 ((SIZE) == HAL_XSPI_SIZE_64B) || \ 1072 ((SIZE) == HAL_XSPI_SIZE_128B) || \ 1073 ((SIZE) == HAL_XSPI_SIZE_256B) || \ 1074 ((SIZE) == HAL_XSPI_SIZE_512B) || \ 1075 ((SIZE) == HAL_XSPI_SIZE_1KB) || \ 1076 ((SIZE) == HAL_XSPI_SIZE_2KB) || \ 1077 ((SIZE) == HAL_XSPI_SIZE_4KB) || \ 1078 ((SIZE) == HAL_XSPI_SIZE_8KB) || \ 1079 ((SIZE) == HAL_XSPI_SIZE_16KB) || \ 1080 ((SIZE) == HAL_XSPI_SIZE_32KB) || \ 1081 ((SIZE) == HAL_XSPI_SIZE_64KB) || \ 1082 ((SIZE) == HAL_XSPI_SIZE_128KB) || \ 1083 ((SIZE) == HAL_XSPI_SIZE_256KB) || \ 1084 ((SIZE) == HAL_XSPI_SIZE_512KB) || \ 1085 ((SIZE) == HAL_XSPI_SIZE_1MB) || \ 1086 ((SIZE) == HAL_XSPI_SIZE_2MB) || \ 1087 ((SIZE) == HAL_XSPI_SIZE_4MB) || \ 1088 ((SIZE) == HAL_XSPI_SIZE_8MB) || \ 1089 ((SIZE) == HAL_XSPI_SIZE_16MB) || \ 1090 ((SIZE) == HAL_XSPI_SIZE_32MB) || \ 1091 ((SIZE) == HAL_XSPI_SIZE_64MB) || \ 1092 ((SIZE) == HAL_XSPI_SIZE_128MB) || \ 1093 ((SIZE) == HAL_XSPI_SIZE_256MB) || \ 1094 ((SIZE) == HAL_XSPI_SIZE_512MB) || \ 1095 ((SIZE) == HAL_XSPI_SIZE_1GB) || \ 1096 ((SIZE) == HAL_XSPI_SIZE_2GB) || \ 1097 ((SIZE) == HAL_XSPI_SIZE_4GB) || \ 1098 ((SIZE) == HAL_XSPI_SIZE_8GB) || \ 1099 ((SIZE) == HAL_XSPI_SIZE_16GB) || \ 1100 ((SIZE) == HAL_XSPI_SIZE_32GB)) 1101 1102 #define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) 1103 1104 #define IS_XSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \ 1105 ((CLK) == HAL_XSPI_FREERUNCLK_ENABLE)) 1106 1107 #define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ 1108 ((MODE) == HAL_XSPI_CLOCK_MODE_3)) 1109 1110 #define IS_XSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \ 1111 ((SIZE) == HAL_XSPI_WRAP_16_BYTES) || \ 1112 ((SIZE) == HAL_XSPI_WRAP_32_BYTES) || \ 1113 ((SIZE) == HAL_XSPI_WRAP_64_BYTES) || \ 1114 ((SIZE) == HAL_XSPI_WRAP_128_BYTES)) 1115 1116 #define IS_XSPI_CLK_PRESCALER(PRESCALER) ((PRESCALER) <= 255U) 1117 1118 #define IS_XSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE) || \ 1119 ((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)) 1120 1121 #define IS_XSPI_DHQC(CYCLE) (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \ 1122 ((CYCLE) == HAL_XSPI_DHQC_ENABLE)) 1123 1124 #define IS_XSPI_CS_BOUND(SIZE) (((SIZE) == HAL_XSPI_BONDARYOF_NONE) || \ 1125 ((SIZE) == HAL_XSPI_BONDARYOF_16B) || \ 1126 ((SIZE) == HAL_XSPI_BONDARYOF_32B) || \ 1127 ((SIZE) == HAL_XSPI_BONDARYOF_64B) || \ 1128 ((SIZE) == HAL_XSPI_BONDARYOF_128B) || \ 1129 ((SIZE) == HAL_XSPI_BONDARYOF_256B) || \ 1130 ((SIZE) == HAL_XSPI_BONDARYOF_512B) || \ 1131 ((SIZE) == HAL_XSPI_BONDARYOF_1KB) || \ 1132 ((SIZE) == HAL_XSPI_BONDARYOF_2KB) || \ 1133 ((SIZE) == HAL_XSPI_BONDARYOF_4KB) || \ 1134 ((SIZE) == HAL_XSPI_BONDARYOF_8KB) || \ 1135 ((SIZE) == HAL_XSPI_BONDARYOF_16KB) || \ 1136 ((SIZE) == HAL_XSPI_BONDARYOF_32KB) || \ 1137 ((SIZE) == HAL_XSPI_BONDARYOF_64KB) || \ 1138 ((SIZE) == HAL_XSPI_BONDARYOF_128KB) || \ 1139 ((SIZE) == HAL_XSPI_BONDARYOF_256KB) || \ 1140 ((SIZE) == HAL_XSPI_BONDARYOF_512KB) || \ 1141 ((SIZE) == HAL_XSPI_BONDARYOF_1MB) || \ 1142 ((SIZE) == HAL_XSPI_BONDARYOF_2MB) || \ 1143 ((SIZE) == HAL_XSPI_BONDARYOF_4MB) || \ 1144 ((SIZE) == HAL_XSPI_BONDARYOF_8MB) || \ 1145 ((SIZE) == HAL_XSPI_BONDARYOF_16MB) || \ 1146 ((SIZE) == HAL_XSPI_BONDARYOF_32MB) || \ 1147 ((SIZE) == HAL_XSPI_BONDARYOF_64MB) || \ 1148 ((SIZE) == HAL_XSPI_BONDARYOF_128MB) || \ 1149 ((SIZE) == HAL_XSPI_BONDARYOF_256MB) || \ 1150 ((SIZE) == HAL_XSPI_BONDARYOF_512MB) || \ 1151 ((SIZE) == HAL_XSPI_BONDARYOF_1GB) || \ 1152 ((SIZE) == HAL_XSPI_BONDARYOF_2GB) || \ 1153 ((SIZE) == HAL_XSPI_BONDARYOF_4GB) || \ 1154 ((SIZE) == HAL_XSPI_BONDARYOF_8GB) || \ 1155 ((SIZE) == HAL_XSPI_BONDARYOF_16GB)) 1156 1157 1158 #define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) 1159 1160 #define IS_XSPI_CSSEL(CSSEL) (((CSSEL) == HAL_XSPI_CSSEL_NCS1) || \ 1161 ((CSSEL) == HAL_XSPI_CSSEL_NCS2)) 1162 1163 #define IS_XSPI_EXTENDMEM(EXTENDMEM) (((EXTENDMEM) == HAL_XSPI_CSSEL_SW) || \ 1164 ((EXTENDMEM) == HAL_XSPI_CSSEL_HW)) 1165 1166 #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ 1167 ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \ 1168 ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \ 1169 ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG)) 1170 1171 #define IS_XSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \ 1172 ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \ 1173 ((MEMSEL) == HAL_XSPI_SELECT_IO_11_8) || \ 1174 ((MEMSEL) == HAL_XSPI_SELECT_IO_15_12) || \ 1175 ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0) || \ 1176 ((MEMSEL) == HAL_XSPI_SELECT_IO_15_8)) 1177 1178 #define IS_XSPI_INSTRUCTION(OPCODE) ((OPCODE) <= 0xFFFFFFFFU) 1179 1180 #define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ 1181 ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \ 1182 ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \ 1183 ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \ 1184 ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES)) 1185 1186 #define IS_XSPI_INSTRUCTION_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS) || \ 1187 ((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \ 1188 ((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \ 1189 ((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS)) 1190 1191 #define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ 1192 ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) 1193 1194 #define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ 1195 ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \ 1196 ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \ 1197 ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \ 1198 ((MODE) == HAL_XSPI_ADDRESS_8_LINES)) 1199 1200 #define IS_XSPI_ADDRESS_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS) || \ 1201 ((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \ 1202 ((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \ 1203 ((WIDTH) == HAL_XSPI_ADDRESS_32_BITS)) 1204 1205 #define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ 1206 ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE)) 1207 1208 #define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ 1209 ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \ 1210 ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \ 1211 ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \ 1212 ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES)) 1213 1214 #define IS_XSPI_ALT_BYTES_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS) || \ 1215 ((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \ 1216 ((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \ 1217 ((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS)) 1218 1219 #define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ 1220 ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE)) 1221 1222 #define IS_XSPI_DATA_MODE(TYPE,MODE) (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \ 1223 (((MODE) == HAL_XSPI_DATA_NONE) || \ 1224 ((MODE) == HAL_XSPI_DATA_8_LINES) || \ 1225 ((MODE) == HAL_XSPI_DATA_16_LINES)): \ 1226 (((MODE) == HAL_XSPI_DATA_NONE) || \ 1227 ((MODE) == HAL_XSPI_DATA_1_LINE) || \ 1228 ((MODE) == HAL_XSPI_DATA_2_LINES) || \ 1229 ((MODE) == HAL_XSPI_DATA_4_LINES) || \ 1230 ((MODE) == HAL_XSPI_DATA_8_LINES) || \ 1231 ((MODE) == HAL_XSPI_DATA_16_LINES))) 1232 #define IS_XSPI_DATA_LENGTH(NUMBER) ((NUMBER) >= 1U) 1233 1234 #define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ 1235 ((MODE) == HAL_XSPI_DATA_DTR_ENABLE)) 1236 1237 #define IS_XSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 1238 1239 #define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ 1240 ((MODE) == HAL_XSPI_DQS_ENABLE)) 1241 1242 #define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) 1243 1244 #define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) 1245 1246 #define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ 1247 ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE)) 1248 1249 #define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ 1250 ((MODE) == HAL_XSPI_FIXED_LATENCY)) 1251 1252 #define IS_XSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \ 1253 ((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE)) 1254 1255 #define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ 1256 ((MODE) == HAL_XSPI_MATCH_MODE_OR)) 1257 1258 #define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ 1259 ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE)) 1260 1261 #define IS_XSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 1262 1263 #define IS_XSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 1264 1265 #define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ 1266 ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE)) 1267 #define IS_XSPI_NO_PREFETCH_DATA(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE) || \ 1268 ((MODE) == HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE)) 1269 1270 #define IS_XSPI_NO_PREFETCH_AXI(MODE) (((MODE) == HAL_XSPI_AXI_PREFETCH_ENABLE) || \ 1271 ((MODE) == HAL_XSPI_AXI_PREFETCH_DISABLE)) 1272 1273 #define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 1274 1275 #define IS_XSPIM_IO_PORT(PORT) (((PORT) == HAL_XSPIM_IOPORT_1) || \ 1276 ((PORT) == HAL_XSPIM_IOPORT_2)) 1277 1278 #define IS_XSPIM_NCS_OVR(PORT) (((PORT) == HAL_XSPI_CSSEL_OVR_DISABLED) || \ 1279 ((PORT) == HAL_XSPI_CSSEL_OVR_NCS1) || \ 1280 ((PORT) == HAL_XSPI_CSSEL_OVR_NCS2)) 1281 1282 #define IS_XSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) 1283 1284 #define IS_XSPI_DELAY_TYPE(TYPE) (((TYPE) == HAL_XSPI_CAL_FULL_CYCLE_DELAY) || \ 1285 ((TYPE) == HAL_XSPI_CAL_FEEDBACK_CLK_DELAY) || \ 1286 ((TYPE) == HAL_XSPI_CAL_DATA_OUTPUT_DELAY) || \ 1287 ((TYPE) == HAL_XSPI_CAL_DQS_INPUT_DELAY)) 1288 1289 #define IS_XSPI_FINECAL_VALUE(VALUE) ((VALUE) <= 0x7FU) 1290 1291 #define IS_XSPI_COARSECAL_VALUE(VALUE) ((VALUE) <= 0x1FU) 1292 1293 /** 1294 @endcond 1295 */ 1296 1297 /* End of private macros -----------------------------------------------------*/ 1298 1299 /** 1300 * @} 1301 */ 1302 1303 /** 1304 * @} 1305 */ 1306 1307 #endif /* XSPI || XSPI1 || XSPI2 || XSPI3 */ 1308 1309 #ifdef __cplusplus 1310 } 1311 #endif 1312 1313 #endif /* STM32N6xx_HAL_XSPI_H */ 1314
