1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_xspi.h 4 * @author MCD Application Team 5 * @brief Header file of XSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_XSPI_H 21 #define STM32U5xx_HAL_XSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 #include "stm32u5xx_ll_dlyb.h" 30 31 #if defined(HSPI) || defined(HSPI1) || defined(HSPI2)|| defined(OCTOSPI) || defined(OCTOSPI1)|| defined(OCTOSPI2) 32 33 /** @addtogroup STM32U5xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup XSPI 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup XSPI_Exported_Types XSPI Exported Types 43 * @{ 44 */ 45 #define HAL_XSPI_DLYB_CfgTypeDef LL_DLYB_CfgTypeDef 46 47 /** 48 * @brief XSPI Init structure definition 49 */ 50 typedef struct 51 { 52 uint32_t FifoThresholdByte; /*!< This is the threshold used by the Peripheral to generate the interrupt 53 indicating that data are available in reception or free place 54 is available in transmission. 55 For OCTOSPI, this parameter can be a value between 1 and 32. 56 For HSPI, this parameter can be a value between 1 and 64 */ 57 uint32_t MemoryMode; /*!< It Specifies the memory mode. 58 This parameter can be a value of @ref XSPI_MemoryMode */ 59 uint32_t MemoryType; /*!< It indicates the external device type connected to the XSPI. 60 This parameter can be a value of @ref XSPI_MemoryType */ 61 uint32_t MemorySize; /*!< It defines the size of the external device connected to the XSPI, 62 it corresponds to the number of address bits required to access 63 the external device. 64 This parameter can be a value of @ref XSPI_MemorySize*/ 65 uint32_t ChipSelectHighTimeCycle; /*!< It defines the minimum number of clocks which the chip select 66 must remain high between commands. 67 This parameter can be a value between 1 and 64U */ 68 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 69 This parameter can be a value of @ref XSPI_FreeRunningClock */ 70 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 71 This parameter can be a value of @ref XSPI_ClockMode */ 72 uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. 73 This parameter can be a value of @ref XSPI_WrapSize */ 74 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 75 the external clock based on the AHB clock. 76 This parameter can be a value between 0 and 255U */ 77 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 78 to take in account external signal delays. 79 This parameter can be a value of @ref XSPI_SampleShifting */ 80 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 81 This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */ 82 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 83 defines the boundary of bytes to release the chip select. 84 This parameter can be a value of @ref XSPI_ChipSelectBoundary */ 85 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 86 by the delay block. 87 This parameter can be a value of @ref XSPI_DelayBlockBypass */ 88 uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is 89 released every MaxTran+1 bytes when the other XSPI request the access 90 to the bus. 91 This parameter can be a value between 0 and 255U */ 92 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 93 Refresh+1 clock cycles. 94 This parameter can be a value between 0 and 0xFFFFFFFF */ 95 } XSPI_InitTypeDef; 96 97 /** 98 * @brief HAL XSPI Handle Structure definition 99 */ 100 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 101 typedef struct __XSPI_HandleTypeDef 102 #else 103 typedef struct 104 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 105 { 106 XSPI_TypeDef *Instance; /*!< XSPI registers base address */ 107 XSPI_InitTypeDef Init; /*!< XSPI initialization parameters */ 108 uint8_t *pBuffPtr; /*!< Address of the XSPI buffer for transfer */ 109 __IO uint32_t XferSize; /*!< Number of data to transfer */ 110 __IO uint32_t XferCount; /*!< Counter of data transferred */ 111 DMA_HandleTypeDef *hdmatx; /*!< Handle of the DMA channel used for transmit */ 112 DMA_HandleTypeDef *hdmarx; /*!< Handle of the DMA channel used for receive */ 113 __IO uint32_t State; /*!< Internal state of the XSPI HAL driver */ 114 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 115 uint32_t Timeout; /*!< Timeout used for the XSPI external device access */ 116 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 117 void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi); 118 void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 119 void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi); 120 void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 121 void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 122 void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 123 void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 124 void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); 125 void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi); 126 void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi); 127 128 void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi); 129 void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi); 130 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 131 } XSPI_HandleTypeDef; 132 133 /** 134 * @brief HAL XSPI Regular Command Structure definition 135 */ 136 typedef struct 137 { 138 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 139 to the registers for the write operation (these registers are only 140 used for memory-mapped mode). 141 This parameter can be a value of @ref XSPI_OperationType */ 142 uint32_t IOSelect; /*!< It indicates the IOs used to exchange data with external memory. 143 This parameter can be a value of @ref XSPI_IOSelect */ 144 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 145 This parameter can be a value between 0 and 0xFFFFFFFFU */ 146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 147 This parameter can be a value of @ref XSPI_InstructionMode */ 148 uint32_t InstructionWidth; /*!< It indicates the width of the instruction. 149 This parameter can be a value of @ref XSPI_InstructionWidth */ 150 uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase. 151 This parameter can be a value of @ref XSPI_InstructionDTRMode */ 152 uint32_t Address; /*!< It contains the address to be sent to the device. 153 This parameter can be a value between 0 and 0xFFFFFFFF */ 154 uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises number of lines 155 for address (except no address). 156 This parameter can be a value of @ref XSPI_AddressMode */ 157 uint32_t AddressWidth; /*!< It indicates the width of the address. 158 This parameter can be a value of @ref XSPI_AddressWidth */ 159 uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase. 160 This parameter can be a value of @ref XSPI_AddressDTRMode */ 161 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 162 This parameter can be a value between 0 and 0xFFFFFFFF */ 163 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 164 This parameter can be a value of @ref XSPI_AlternateBytesMode */ 165 uint32_t AlternateBytesWidth; /*!< It indicates the width of the alternate bytes. 166 This parameter can be a value of @ref XSPI_AlternateBytesWidth */ 167 uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 168 This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */ 169 uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines 170 for data exchange (except no data). 171 This parameter can be a value of @ref XSPI_DataMode */ 172 uint32_t DataLength; /*!< It indicates the number of data transferred with this command. 173 This field is only used for indirect mode. 174 This parameter can be a value between 1 and 0xFFFFFFFFU */ 175 uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase. 176 This parameter can be a value of @ref XSPI_DataDTRMode */ 177 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 178 This parameter can be a value between 0 and 31U */ 179 uint32_t DQSMode; /*!< It enables or not the data strobe management. 180 This parameter can be a value of @ref XSPI_DQSMode */ 181 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. When SIOO mode enabled, 182 instruction will be sent only once. 183 This parameter can be a value of @ref XSPI_SIOOMode */ 184 } XSPI_RegularCmdTypeDef; 185 /** 186 * @brief HAL XSPI Hyperbus Configuration Structure definition 187 */ 188 typedef struct 189 { 190 uint32_t RWRecoveryTimeCycle; /*!< It indicates the number of cycles for the device read write recovery time. 191 This parameter can be a value between 0 and 255U */ 192 uint32_t AccessTimeCycle; /*!< It indicates the number of cycles for the device access time. 193 This parameter can be a value between 0 and 255U */ 194 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 195 This parameter can be a value of @ref XSPI_WriteZeroLatency */ 196 uint32_t LatencyMode; /*!< It configures the latency mode. 197 This parameter can be a value of @ref XSPI_LatencyMode */ 198 } XSPI_HyperbusCfgTypeDef; 199 200 /** 201 * @brief HAL XSPI Hyperbus Command Structure definition 202 */ 203 typedef struct 204 { 205 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 206 This parameter can be a value of @ref XSPI_AddressSpace */ 207 uint32_t Address; /*!< It contains the address to be sent to the device. 208 This parameter can be a value between 0 and 0xFFFFFFFF */ 209 uint32_t AddressWidth; /*!< It indicates the width of the address. 210 This parameter can be a value of @ref XSPI_AddressWidth */ 211 uint32_t DataLength; /*!< It indicates the number of data transferred with this command. 212 This field is only used for indirect mode. 213 This parameter can be a value between 1 and 0xFFFFFFFF 214 In case of autopolling mode, this parameter can be 215 any value between 1 and 4 */ 216 uint32_t DQSMode; /*!< It enables or not the data strobe management. 217 This parameter can be a value of @ref XSPI_DQSMode */ 218 #if defined(HSPI1) 219 uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines 220 for data exchange (except no data). 221 This parameter can be a value of @ref XSPI_DataMode */ 222 #endif /* HSPI1 */ 223 } XSPI_HyperbusCmdTypeDef; 224 225 /** 226 * @brief HAL XSPI Auto Polling mode configuration structure definition 227 */ 228 typedef struct 229 { 230 uint32_t MatchValue; /*!< Specifies the value to be compared with the masked status register to get 231 a match. 232 This parameter can be any value between 0 and 0xFFFFFFFFU */ 233 uint32_t MatchMask; /*!< Specifies the mask to be applied to the status bytes received. 234 This parameter can be any value between 0 and 0xFFFFFFFFU */ 235 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 236 This parameter can be a value of @ref XSPI_MatchMode */ 237 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 238 This parameter can be a value of @ref XSPI_AutomaticStop */ 239 uint32_t IntervalTime; /*!< Specifies the number of clock cycles between two read during automatic 240 polling phases. 241 This parameter can be any value between 0 and 0xFFFFU */ 242 } XSPI_AutoPollingTypeDef; 243 244 /** 245 * @brief HAL XSPI Memory Mapped mode configuration structure definition 246 */ 247 typedef struct 248 { 249 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 250 This parameter can be a value of @ref XSPI_TimeOutActivation */ 251 uint32_t TimeoutPeriodClock; /*!< Specifies the number of clock to wait when the FIFO is full before to 252 release the chip select. 253 This parameter can be any value between 0 and 0xFFFFU */ 254 } XSPI_MemoryMappedTypeDef; 255 256 #if defined(OCTOSPIM) 257 /** 258 * @brief HAL XSPI IO Manager Configuration structure definition 259 */ 260 typedef struct 261 { 262 uint32_t ClkPort; /*!< It indicates which port of the XSPI IO Manager is used for the CLK pins. 263 This parameter can be a value between 1 and 8 */ 264 uint32_t DQSPort; /*!< It indicates which port of the XSPI IO Manager is used for the DQS pin. 265 This parameter can be a value between 1 and 8, 266 0 means that signal not used */ 267 uint32_t NCSPort; /*!< It indicates which port of the XSPI IO Manager is used for the NCS pin. 268 This parameter can be a value between 1 and 8 */ 269 uint32_t IOLowPort; /*!< It indicates which port of the XSPI IO Manager is used for the IO[3:0] pins. 270 This parameter can be a value of @ref XSPIM_IOPort */ 271 uint32_t IOHighPort; /*!< It indicates which port of the XSPI IO Manager is used for the IO[7:4] pins. 272 This parameter can be a value of @ref XSPIM_IOPort */ 273 uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) 274 expected if some signals are multiplexed in the XSPI IO Manager with the 275 other XSPI. 276 This parameter can be a value between 1 and 256 */ 277 } XSPIM_CfgTypeDef; 278 279 #endif /* OCTOSPIM */ 280 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 281 /** 282 * @brief HAL XSPI Callback ID enumeration definition 283 */ 284 typedef enum 285 { 286 HAL_XSPI_ERROR_CB_ID = 0x00U, /*!< XSPI Error Callback ID */ 287 HAL_XSPI_ABORT_CB_ID = 0x01U, /*!< XSPI Abort Callback ID */ 288 HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< XSPI FIFO Threshold Callback ID */ 289 HAL_XSPI_CMD_CPLT_CB_ID = 0x03U, /*!< XSPI Command Complete Callback ID */ 290 HAL_XSPI_RX_CPLT_CB_ID = 0x04U, /*!< XSPI Rx Complete Callback ID */ 291 HAL_XSPI_TX_CPLT_CB_ID = 0x05U, /*!< XSPI Tx Complete Callback ID */ 292 HAL_XSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< XSPI Rx Half Complete Callback ID */ 293 HAL_XSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< XSPI Tx Half Complete Callback ID */ 294 HAL_XSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< XSPI Status Match Callback ID */ 295 HAL_XSPI_TIMEOUT_CB_ID = 0x09U, /*!< XSPI Timeout Callback ID */ 296 HAL_XSPI_MSP_INIT_CB_ID = 0x0AU, /*!< XSPI MspInit Callback ID */ 297 HAL_XSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< XSPI MspDeInit Callback ID */ 298 } HAL_XSPI_CallbackIDTypeDef; 299 300 /** 301 * @brief HAL XSPI Callback pointer definition 302 */ 303 typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); 304 305 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 306 #if defined(HSPI_CALFCR_FINE) 307 /** 308 * @brief HAL XSPI High-speed interface calibration structure definition 309 */ 310 typedef struct 311 { 312 uint32_t DelayValueType; /*!< It indicates which calibration is concerned by the configuration. 313 This parameter can be a value of @ref XSPI_DelayType */ 314 uint32_t FineCalibrationUnit; /*!< It indicates the fine calibration value of the delay. 315 This parameter can be a value between 0 and 0x7FU */ 316 uint32_t CoarseCalibrationUnit; /*!< It indicates the coarse calibration value of the delay. 317 This parameter can be a value between 0 and 0x1FU */ 318 uint32_t MaxCalibration; /*!< It indicates that the calibration is outside the range of DLL master. 319 It applies only when the DelayValueType is HAL_XSPI_CAL_FULL_CYCLE_DELAY. 320 This parameter can be a value of @ref XSPI_MaxCal */ 321 } XSPI_HSCalTypeDef; 322 323 #endif /* HSPI_CALFCR_FINE */ 324 /** 325 * @} 326 */ 327 328 /* Exported constants --------------------------------------------------------*/ 329 /** @defgroup XSPI_Exported_Constants XSPI Exported Constants 330 * @{ 331 */ 332 333 /** @defgroup XSPI_State XSPI State 334 * @{ 335 */ 336 #define HAL_XSPI_STATE_RESET (0x00000000U) /*!< Initial state */ 337 #define HAL_XSPI_STATE_READY (0x00000002U) /*!< Driver ready to be used */ 338 #define HAL_XSPI_STATE_HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 339 #define HAL_XSPI_STATE_CMD_CFG (0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 340 #define HAL_XSPI_STATE_READ_CMD_CFG (0x00000014U) /*!< Read command configuration done, not the write command configuration */ 341 #define HAL_XSPI_STATE_WRITE_CMD_CFG (0x00000024U) /*!< Write command configuration done, not the read command configuration */ 342 #define HAL_XSPI_STATE_BUSY_CMD (0x00000008U) /*!< Command without data on-going */ 343 #define HAL_XSPI_STATE_BUSY_TX (0x00000018U) /*!< Indirect Tx on-going */ 344 #define HAL_XSPI_STATE_BUSY_RX (0x00000028U) /*!< Indirect Rx on-going */ 345 #define HAL_XSPI_STATE_BUSY_AUTO_POLLING (0x00000048U) /*!< Auto-polling on-going */ 346 #define HAL_XSPI_STATE_BUSY_MEM_MAPPED (0x00000088U) /*!< Memory-mapped on-going */ 347 #define HAL_XSPI_STATE_ABORT (0x00000100U) /*!< Abort on-going */ 348 #define HAL_XSPI_STATE_ERROR (0x00000200U) /*!< Blocking error, driver should be re-initialized */ 349 /** 350 * @} 351 */ 352 353 /** @defgroup XSPI_ErrorCode XSPI Error Code 354 * @{ 355 */ 356 #define HAL_XSPI_ERROR_NONE (0x00000000U) /*!< No error */ 357 #define HAL_XSPI_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ 358 #define HAL_XSPI_ERROR_TRANSFER (0x00000002U) /*!< Transfer error */ 359 #define HAL_XSPI_ERROR_DMA (0x00000004U) /*!< DMA transfer error */ 360 #define HAL_XSPI_ERROR_INVALID_PARAM (0x00000008U) /*!< Invalid parameters error */ 361 #define HAL_XSPI_ERROR_INVALID_SEQUENCE (0x00000010U) /*!< Sequence is incorrect */ 362 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 363 #define HAL_XSPI_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid callback error */ 364 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 365 /** 366 * @} 367 */ 368 369 /** @defgroup XSPI_MemoryMode XSPI Memory Mode 370 * @{ 371 */ 372 #define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */ 373 #define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */ 374 375 /** 376 * @} 377 */ 378 379 /** @defgroup XSPI_MemoryType XSPI Memory Type 380 * @{ 381 */ 382 #define HAL_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */ 383 #define HAL_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */ 384 #define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 385 #define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/ 386 #define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 387 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */ 388 389 /** 390 * @} 391 */ 392 393 /** @defgroup XSPI_MemorySize XSPI Memory Size 394 * @{ 395 */ 396 #define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ 397 #define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ 398 #define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ 399 #define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ 400 #define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ 401 #define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ 402 #define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ 403 #define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ 404 #define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ 405 #define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ 406 #define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ 407 #define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ 408 #define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ 409 #define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ 410 #define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ 411 #define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ 412 #define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ 413 #define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ 414 #define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ 415 #define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ 416 #define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ 417 #define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ 418 #define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ 419 #define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ 420 #define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ 421 #define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ 422 #define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ 423 #define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ 424 #define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ 425 #define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ 426 #define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ 427 #define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock 433 * @{ 434 */ 435 #define HAL_XSPI_FREERUNCLK_DISABLE (0x00000000U) /*!< CLK is not free running */ 436 #define HAL_XSPI_FREERUNCLK_ENABLE ((uint32_t)XSPI_DCR1_FRCK) /*!< CLK is always provided (running) */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup XSPI_ClockMode XSPI Clock Mode 442 * @{ 443 */ 444 #define HAL_XSPI_CLOCK_MODE_0 (0x00000000U) /*!< CLK must stay low while nCS is high */ 445 #define HAL_XSPI_CLOCK_MODE_3 ((uint32_t)XSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 446 /** 447 * @} 448 */ 449 450 /** @defgroup XSPI_WrapSize XSPI Wrap-Size 451 * @{ 452 */ 453 #define HAL_XSPI_WRAP_NOT_SUPPORTED (0x00000000U) /*!< wrapped reads are not supported by the memory */ 454 #define HAL_XSPI_WRAP_16_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 455 #define HAL_XSPI_WRAP_32_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 456 #define HAL_XSPI_WRAP_64_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 457 #define HAL_XSPI_WRAP_128_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 458 /** 459 * @} 460 */ 461 462 /** @defgroup XSPI_SampleShifting XSPI Sample Shifting 463 * @{ 464 */ 465 #define HAL_XSPI_SAMPLE_SHIFT_NONE (0x00000000U) /*!< No shift */ 466 #define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE ((uint32_t)XSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 467 /** 468 * @} 469 */ 470 471 /** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle 472 * @{ 473 */ 474 #define HAL_XSPI_DHQC_DISABLE (0x00000000U) /*!< No Delay */ 475 #define HAL_XSPI_DHQC_ENABLE ((uint32_t)XSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary 481 * @{ 482 */ 483 #define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ 484 #define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ 485 #define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ 486 #define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ 487 #define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ 488 #define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ 489 #define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ 490 #define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ 491 #define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ 492 #define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ 493 #define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ 494 #define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ 495 #define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ 496 #define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ 497 #define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ 498 #define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ 499 #define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ 500 #define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ 501 #define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ 502 #define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ 503 #define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ 504 #define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ 505 #define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ 506 #define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ 507 #define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ 508 #define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ 509 #define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ 510 #define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ 511 #define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ 512 #define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ 513 #define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ 514 #define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup XSPI_DelayBlockBypass XSPI Delay Block Bypaas 520 * @{ 521 */ 522 #define HAL_XSPI_DELAY_BLOCK_ON (0x00000000U) /*!< Sampling clock is delayed by the delay block */ 523 #define HAL_XSPI_DELAY_BLOCK_BYPASS ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup XSPI_OperationType XSPI Operation Type 529 * @{ 530 */ 531 #define HAL_XSPI_OPTYPE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 532 #define HAL_XSPI_OPTYPE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */ 533 #define HAL_XSPI_OPTYPE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */ 534 #define HAL_XSPI_OPTYPE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ 535 536 /** 537 * @} 538 */ 539 540 /** @defgroup XSPI_IOSelect XSPI IO Select 541 * @{ 542 */ 543 #define HAL_XSPI_SELECT_IO_3_0 (0x00000000U) /*!< Data exchanged over IO[3:0] */ 544 #if defined(HSPI_CR_MSEL) 545 #define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)HSPI_CR_MSEL_0 | OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[7:4] */ 546 #define HAL_XSPI_SELECT_IO_11_8 ((uint32_t)HSPI_CR_MSEL_1) /*!< Data exchanged over IO[11:8] */ 547 #define HAL_XSPI_SELECT_IO_15_12 ((uint32_t)HSPI_CR_MSEL | OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[15:12] */ 548 #define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */ 549 #define HAL_XSPI_SELECT_IO_15_8 ((uint32_t)HSPI_CR_MSEL_1) /*!< Data exchanged over IO[15:8] */ 550 #else 551 #define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[7:4] */ 552 #define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */ 553 #endif /* HSPI_CR_MSEL */ 554 /** 555 * @} 556 */ 557 558 /** @defgroup XSPI_InstructionMode XSPI Instruction Mode 559 * @{ 560 */ 561 #define HAL_XSPI_INSTRUCTION_NONE (0x00000000U) /*!< No instruction */ 562 #define HAL_XSPI_INSTRUCTION_1_LINE ((uint32_t)XSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 563 #define HAL_XSPI_INSTRUCTION_2_LINES ((uint32_t)XSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 564 #define HAL_XSPI_INSTRUCTION_4_LINES ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 565 #define HAL_XSPI_INSTRUCTION_8_LINES ((uint32_t)XSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 566 /** 567 * @} 568 */ 569 570 /** @defgroup XSPI_InstructionWidth XSPI Instruction Width 571 * @{ 572 */ 573 #define HAL_XSPI_INSTRUCTION_8_BITS (0x00000000U) /*!< 8-bit instruction */ 574 #define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 575 #define HAL_XSPI_INSTRUCTION_24_BITS ((uint32_t)XSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 576 #define HAL_XSPI_INSTRUCTION_32_BITS ((uint32_t)XSPI_CCR_ISIZE) /*!< 32-bit instruction */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode 582 * @{ 583 */ 584 #define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for instruction phase */ 585 #define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 586 /** 587 * @} 588 */ 589 590 /** @defgroup XSPI_AddressMode XSPI Address Mode 591 * @{ 592 */ 593 #define HAL_XSPI_ADDRESS_NONE (0x00000000U) /*!< No address */ 594 #define HAL_XSPI_ADDRESS_1_LINE ((uint32_t)XSPI_CCR_ADMODE_0) /*!< Address on a single line */ 595 #define HAL_XSPI_ADDRESS_2_LINES ((uint32_t)XSPI_CCR_ADMODE_1) /*!< Address on two lines */ 596 #define HAL_XSPI_ADDRESS_4_LINES ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 597 #define HAL_XSPI_ADDRESS_8_LINES ((uint32_t)XSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 598 /** 599 * @} 600 */ 601 602 /** @defgroup XSPI_AddressWidth XSPI Address width 603 * @{ 604 */ 605 #define HAL_XSPI_ADDRESS_8_BITS (0x00000000U) /*!< 8-bit address */ 606 #define HAL_XSPI_ADDRESS_16_BITS ((uint32_t)XSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 607 #define HAL_XSPI_ADDRESS_24_BITS ((uint32_t)XSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 608 #define HAL_XSPI_ADDRESS_32_BITS ((uint32_t)XSPI_CCR_ADSIZE) /*!< 32-bit address */ 609 /** 610 * @} 611 */ 612 613 /** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode 614 * @{ 615 */ 616 #define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for address phase */ 617 #define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 618 /** 619 * @} 620 */ 621 622 /** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode 623 * @{ 624 */ 625 #define HAL_XSPI_ALT_BYTES_NONE (0x00000000U) /*!< No alternate bytes */ 626 #define HAL_XSPI_ALT_BYTES_1_LINE ((uint32_t)XSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 627 #define HAL_XSPI_ALT_BYTES_2_LINES ((uint32_t)XSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 628 #define HAL_XSPI_ALT_BYTES_4_LINES ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 629 #define HAL_XSPI_ALT_BYTES_8_LINES ((uint32_t)XSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 630 /** 631 * @} 632 */ 633 634 /** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width 635 * @{ 636 */ 637 #define HAL_XSPI_ALT_BYTES_8_BITS (0x00000000U) /*!< 8-bit alternate bytes */ 638 #define HAL_XSPI_ALT_BYTES_16_BITS ((uint32_t)XSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 639 #define HAL_XSPI_ALT_BYTES_24_BITS ((uint32_t)XSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 640 #define HAL_XSPI_ALT_BYTES_32_BITS ((uint32_t)XSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 641 /** 642 * @} 643 */ 644 645 /** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode 646 * @{ 647 */ 648 #define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 649 #define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 650 /** 651 * @} 652 */ 653 654 /** @defgroup XSPI_DataMode XSPI Data Mode 655 * @{ 656 */ 657 #define HAL_XSPI_DATA_NONE (0x00000000U) /*!< No data */ 658 #define HAL_XSPI_DATA_1_LINE ((uint32_t)XSPI_CCR_DMODE_0) /*!< Data on a single line */ 659 #define HAL_XSPI_DATA_2_LINES ((uint32_t)XSPI_CCR_DMODE_1) /*!< Data on two lines */ 660 #define HAL_XSPI_DATA_4_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1)) /*!< Data on four lines */ 661 #define HAL_XSPI_DATA_8_LINES ((uint32_t)XSPI_CCR_DMODE_2) /*!< Data on eight lines */ 662 #if defined(HSPI_CR_MSEL) 663 #define HAL_XSPI_DATA_16_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_2)) /*!< Data on sixteen lines valid for HSPI only */ 664 #endif /* 16BITS_AVAILABILITY */ 665 /** 666 * @} 667 */ 668 669 /** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode 670 * @{ 671 */ 672 #define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for data phase */ 673 #define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 674 /** 675 * @} 676 */ 677 678 /** @defgroup XSPI_DQSMode XSPI DQS Mode 679 * @{ 680 */ 681 #define HAL_XSPI_DQS_DISABLE (0x00000000U) /*!< DQS disabled */ 682 #define HAL_XSPI_DQS_ENABLE ((uint32_t)XSPI_CCR_DQSE) /*!< DQS enabled */ 683 /** 684 * @} 685 */ 686 687 /** @defgroup XSPI_SIOOMode XSPI SIOO Mode 688 * @{ 689 */ 690 #define HAL_XSPI_SIOO_INST_EVERY_CMD (0x00000000U) /*!< Send instruction on every transaction */ 691 #define HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)XSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation 697 * @{ 698 */ 699 #define HAL_XSPI_LATENCY_ON_WRITE (0x00000000U) /*!< Latency on write accesses */ 700 #define HAL_XSPI_NO_LATENCY_ON_WRITE ((uint32_t)XSPI_HLCR_WZL) /*!< No latency on write accesses */ 701 /** 702 * @} 703 */ 704 705 /** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode 706 * @{ 707 */ 708 #define HAL_XSPI_VARIABLE_LATENCY (0x00000000U) /*!< Variable initial latency */ 709 #define HAL_XSPI_FIXED_LATENCY ((uint32_t)XSPI_HLCR_LM) /*!< Fixed latency */ 710 /** 711 * @} 712 */ 713 714 /** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space 715 * @{ 716 */ 717 #define HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */ 718 #define HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 719 /** 720 * @} 721 */ 722 723 /** @defgroup XSPI_MatchMode XSPI Match Mode 724 * @{ 725 */ 726 #define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between unmasked bits */ 727 #define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 728 /** 729 * @} 730 */ 731 732 /** @defgroup XSPI_AutomaticStop XSPI Automatic Stop 733 * @{ 734 */ 735 #define HAL_XSPI_AUTOMATIC_STOP_DISABLE (0x00000000U) /*!< AutoPolling stops only with abort or XSPI disabling */ 736 #define HAL_XSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)XSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 737 /** 738 * @} 739 */ 740 741 /** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation 742 * @{ 743 */ 744 #define HAL_XSPI_TIMEOUT_COUNTER_DISABLE (0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 745 #define HAL_XSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)XSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 746 /** 747 * @} 748 */ 749 750 /** @defgroup XSPI_Flags XSPI Flags 751 * @{ 752 */ 753 #define HAL_XSPI_FLAG_BUSY XSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 754 #define HAL_XSPI_FLAG_TO XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 755 #define HAL_XSPI_FLAG_SM XSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 756 #define HAL_XSPI_FLAG_FT XSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 757 #define HAL_XSPI_FLAG_TC XSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 758 #define HAL_XSPI_FLAG_TE XSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 759 /** 760 * @} 761 */ 762 763 /** @defgroup XSPI_Interrupts XSPI Interrupts 764 * @{ 765 */ 766 #define HAL_XSPI_IT_TO XSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 767 #define HAL_XSPI_IT_SM XSPI_CR_SMIE /*!< Interrupt on the status match flag */ 768 #define HAL_XSPI_IT_FT XSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 769 #define HAL_XSPI_IT_TC XSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 770 #define HAL_XSPI_IT_TE XSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 771 /** 772 * @} 773 */ 774 775 /** @defgroup XSPI_Timeout_definition XSPI Timeout definition 776 * @{ 777 */ 778 #define HAL_XSPI_TIMEOUT_DEFAULT_VALUE (5000U) /* 5 s */ 779 /** 780 * @} 781 */ 782 783 #if defined(OCTOSPIM) 784 /** @defgroup XSPIM_IOPort XSPI IO Manager IO Port 785 * @{ 786 */ 787 #define HAL_XSPIM_IOPORT_NONE (0x00000000U) /*!< IOs not used */ 788 #define HAL_XSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ 789 #define HAL_XSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ 790 #define HAL_XSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ 791 #define HAL_XSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ 792 #define HAL_XSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U)) /*!< Port 3 - IO[3:0] */ 793 #define HAL_XSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U)) /*!< Port 3 - IO[7:4] */ 794 #define HAL_XSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U)) /*!< Port 4 - IO[3:0] */ 795 #define HAL_XSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U)) /*!< Port 4 - IO[7:4] */ 796 #define HAL_XSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U)) /*!< Port 5 - IO[3:0] */ 797 #define HAL_XSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U)) /*!< Port 5 - IO[7:4] */ 798 #define HAL_XSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U)) /*!< Port 6 - IO[3:0] */ 799 #define HAL_XSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U)) /*!< Port 6 - IO[7:4] */ 800 #define HAL_XSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U)) /*!< Port 7 - IO[3:0] */ 801 #define HAL_XSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U)) /*!< Port 7 - IO[7:4] */ 802 #define HAL_XSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U)) /*!< Port 8 - IO[3:0] */ 803 #define HAL_XSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U)) /*!< Port 8 - IO[7:4] */ 804 /** 805 * @} 806 */ 807 808 #endif /* OCTOSPIM */ 809 #if defined(HSPI_CALFCR_FINE) 810 811 /** @defgroup XSPI_DelayType XSPI Calibration Delay Type 812 * @{ 813 */ 814 #define HAL_XSPI_CAL_FULL_CYCLE_DELAY (0x00000000U) /*!< Delay value equivalent to full memory-clock cycle */ 815 #define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY (0x00000001U) /*!< Delay value for the feedback clock when reading without DQS */ 816 #define HAL_XSPI_CAL_DATA_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operations */ 817 #define HAL_XSPI_CAL_DQS_INPUT_DELAY (0x00000003U) /*!< Delay value for DQS input when sampling data for read operations */ 818 /** 819 * @} 820 */ 821 822 /** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value 823 * @{ 824 */ 825 #define HAL_XSPI_MAXCAL_NOT_REACHED (0x00000000U) /*!< Memory-clock perido inside the range of DLL master */ 826 #define HAL_XSPI_MAXCAL_REACHED ((uint32_t)HSPI_CALFCR_CALMAX) /*!< Memory-clock period outside the range of DLL master (max delay values used) */ 827 /** 828 * @} 829 */ 830 831 #endif /* HSPI_CALFCR_FINE */ 832 /** 833 * @} 834 */ 835 836 /* Exported macros -----------------------------------------------------------*/ 837 /** @defgroup XSPI_Exported_Macros XSPI Exported Macros 838 * @{ 839 */ 840 /** @brief Reset XSPI handle state. 841 * @param __HANDLE__ specifies the XSPI Handle. 842 * @retval None 843 */ 844 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 845 #define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 846 (__HANDLE__)->State = HAL_XSPI_STATE_RESET; \ 847 (__HANDLE__)->MspInitCallback = NULL; \ 848 (__HANDLE__)->MspDeInitCallback = NULL; \ 849 } while(0) 850 #else 851 #define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_XSPI_STATE_RESET) 852 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 853 854 /** @brief Enable the XSPI peripheral. 855 * @param __HANDLE__ specifies the XSPI Handle. 856 * @retval None 857 */ 858 #define HAL_XSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) 859 860 /** @brief Disable the XSPI peripheral. 861 * @param __HANDLE__ specifies the XSPI Handle. 862 * @retval None 863 */ 864 #define HAL_XSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) 865 866 /** @brief Enable the specified XSPI interrupt. 867 * @param __HANDLE__ specifies the XSPI Handle. 868 * @param __INTERRUPT__ specifies the XSPI interrupt source to enable. 869 * This parameter can be one of the following values: 870 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 871 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 872 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 873 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 874 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 875 * @retval None 876 */ 877 #define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 878 879 /** @brief Disable the specified XSPI interrupt. 880 * @param __HANDLE__ specifies the XSPI Handle. 881 * @param __INTERRUPT__ specifies the XSPI interrupt source to disable. 882 * This parameter can be one of the following values: 883 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 884 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 885 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 886 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 887 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 888 * @retval None 889 */ 890 #define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 891 892 /** @brief Check whether the specified XSPI interrupt source is enabled or not. 893 * @param __HANDLE__ specifies the XSPI Handle. 894 * @param __INTERRUPT__ specifies the XSPI interrupt source to check. 895 * This parameter can be one of the following values: 896 * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt 897 * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt 898 * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt 899 * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt 900 * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt 901 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 902 */ 903 #define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ 904 == (__INTERRUPT__)) 905 906 /** 907 * @brief Check whether the selected XSPI flag is set or not. 908 * @param __HANDLE__ specifies the XSPI Handle. 909 * @param __FLAG__ specifies the XSPI flag to check. 910 * This parameter can be one of the following values: 911 * @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag 912 * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag 913 * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag 914 * @arg HAL_XSPI_FLAG_FT: XSPI FIFO threshold flag 915 * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag 916 * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag 917 * @retval None 918 */ 919 #define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 920 != 0U) ? SET : RESET) 921 922 /** @brief Clears the specified XSPI's flag status. 923 * @param __HANDLE__ specifies the XSPI Handle. 924 * @param __FLAG__ specifies the XSPI clear register flag that needs to be set 925 * This parameter can be one of the following values: 926 * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag 927 * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag 928 * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag 929 * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag 930 * @retval None 931 */ 932 #define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 933 934 /** 935 * @} 936 */ 937 938 /* Exported functions --------------------------------------------------------*/ 939 /** @addtogroup XSPI_Exported_Functions 940 * @{ 941 */ 942 943 /* Initialization/de-initialization functions ********************************/ 944 /** @addtogroup XSPI_Exported_Functions_Group1 945 * @{ 946 */ 947 HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi); 948 void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi); 949 HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi); 950 void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); 951 952 /** 953 * @} 954 */ 955 956 /* IO operation functions *****************************************************/ 957 /** @addtogroup XSPI_Exported_Functions_Group2 958 * @{ 959 */ 960 /* XSPI IRQ handler function */ 961 void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi); 962 963 /* XSPI command configuration functions */ 964 HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, 965 uint32_t Timeout); 966 HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); 967 HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, 968 uint32_t Timeout); 969 HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, 970 uint32_t Timeout); 971 972 /* XSPI indirect mode functions */ 973 HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); 974 HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); 975 HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 976 HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 977 HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 978 HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); 979 980 /* XSPI status flag polling mode functions */ 981 HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, 982 uint32_t Timeout); 983 HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg); 984 985 /* XSPI memory-mapped mode functions */ 986 HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg); 987 988 /* Callback functions in non-blocking modes ***********************************/ 989 void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi); 990 void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi); 991 void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi); 992 993 /* XSPI indirect mode Callback functions */ 994 void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi); 995 void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi); 996 void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi); 997 void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); 998 void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); 999 1000 /* XSPI status flag polling mode functions */ 1001 void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi); 1002 1003 /* XSPI memory-mapped mode functions */ 1004 void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi); 1005 1006 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) 1007 /* XSPI callback registering/unregistering */ 1008 HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, 1009 pXSPI_CallbackTypeDef pCallback); 1010 HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID); 1011 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ 1012 1013 /** 1014 * @} 1015 */ 1016 1017 /* Peripheral Control and State functions ************************************/ 1018 /** @addtogroup XSPI_Exported_Functions_Group3 1019 * @{ 1020 */ 1021 HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi); 1022 HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi); 1023 HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold); 1024 uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi); 1025 HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type); 1026 HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size); 1027 HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler); 1028 HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout); 1029 uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi); 1030 uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi); 1031 1032 /** 1033 * @} 1034 */ 1035 1036 #if defined(OCTOSPIM) 1037 /* XSPI IO Manager configuration function ************************************/ 1038 /** @addtogroup XSPI_Exported_Functions_Group4 1039 * @{ 1040 */ 1041 HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout); 1042 1043 /** 1044 * @} 1045 */ 1046 1047 #endif /* OCTOSPIM */ 1048 /* XSPI Delay Block functions ************************************/ 1049 #if defined(OCTOSPIM) 1050 /** @addtogroup XSPI_Exported_Functions_Group5 Delay Block function 1051 * @{ 1052 */ 1053 #endif /* OCTOSPIM */ 1054 1055 HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); 1056 HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); 1057 HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, 1058 HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); 1059 1060 /** 1061 * @} 1062 */ 1063 1064 #if defined(HSPI_CALFCR_FINE) 1065 /* XSPI high-speed interface and calibration functions ***********************/ 1066 /** @addtogroup XSPI_Exported_Functions_Group6 1067 * @{ 1068 */ 1069 HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); 1070 HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); 1071 1072 /** 1073 * @} 1074 */ 1075 1076 #endif /* HSPI_CALFCR_FINE */ 1077 /** 1078 * @} 1079 */ 1080 /* End of exported functions -------------------------------------------------*/ 1081 1082 /* Private macros ------------------------------------------------------------*/ 1083 /** 1084 @cond 0 1085 */ 1086 #define IS_OCTOSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\ 1087 ((THRESHOLD) <= ((OCTOSPI_CR_FTHRES >> OCTOSPI_CR_FTHRES_Pos)+1U))) 1088 1089 1090 #if defined(HSPI1) 1091 #define IS_HSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\ 1092 ((THRESHOLD) <= ((HSPI_CR_FTHRES >> HSPI_CR_FTHRES_Pos)+1U))) 1093 #endif /* HSPI1 */ 1094 #define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ 1095 ((MODE) == HAL_XSPI_DUAL_MEM)) 1096 1097 #define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ 1098 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \ 1099 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \ 1100 ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \ 1101 ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \ 1102 ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS)) 1103 1104 #define IS_XSPI_MEMORY_SIZE(SIZE) (((SIZE) == HAL_XSPI_SIZE_16B) || \ 1105 ((SIZE) == HAL_XSPI_SIZE_32B) || \ 1106 ((SIZE) == HAL_XSPI_SIZE_64B) || \ 1107 ((SIZE) == HAL_XSPI_SIZE_128B) || \ 1108 ((SIZE) == HAL_XSPI_SIZE_256B) || \ 1109 ((SIZE) == HAL_XSPI_SIZE_512B) || \ 1110 ((SIZE) == HAL_XSPI_SIZE_1KB) || \ 1111 ((SIZE) == HAL_XSPI_SIZE_2KB) || \ 1112 ((SIZE) == HAL_XSPI_SIZE_4KB) || \ 1113 ((SIZE) == HAL_XSPI_SIZE_8KB) || \ 1114 ((SIZE) == HAL_XSPI_SIZE_16KB) || \ 1115 ((SIZE) == HAL_XSPI_SIZE_32KB) || \ 1116 ((SIZE) == HAL_XSPI_SIZE_64KB) || \ 1117 ((SIZE) == HAL_XSPI_SIZE_128KB) || \ 1118 ((SIZE) == HAL_XSPI_SIZE_256KB) || \ 1119 ((SIZE) == HAL_XSPI_SIZE_512KB) || \ 1120 ((SIZE) == HAL_XSPI_SIZE_1MB) || \ 1121 ((SIZE) == HAL_XSPI_SIZE_2MB) || \ 1122 ((SIZE) == HAL_XSPI_SIZE_4MB) || \ 1123 ((SIZE) == HAL_XSPI_SIZE_8MB) || \ 1124 ((SIZE) == HAL_XSPI_SIZE_16MB) || \ 1125 ((SIZE) == HAL_XSPI_SIZE_32MB) || \ 1126 ((SIZE) == HAL_XSPI_SIZE_64MB) || \ 1127 ((SIZE) == HAL_XSPI_SIZE_128MB) || \ 1128 ((SIZE) == HAL_XSPI_SIZE_256MB) || \ 1129 ((SIZE) == HAL_XSPI_SIZE_512MB) || \ 1130 ((SIZE) == HAL_XSPI_SIZE_1GB) || \ 1131 ((SIZE) == HAL_XSPI_SIZE_2GB) || \ 1132 ((SIZE) == HAL_XSPI_SIZE_4GB) || \ 1133 ((SIZE) == HAL_XSPI_SIZE_8GB) || \ 1134 ((SIZE) == HAL_XSPI_SIZE_16GB) || \ 1135 ((SIZE) == HAL_XSPI_SIZE_32GB)) 1136 1137 #define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) 1138 1139 #define IS_XSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \ 1140 ((CLK) == HAL_XSPI_FREERUNCLK_ENABLE)) 1141 1142 #define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ 1143 ((MODE) == HAL_XSPI_CLOCK_MODE_3)) 1144 1145 #define IS_XSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \ 1146 ((SIZE) == HAL_XSPI_WRAP_16_BYTES) || \ 1147 ((SIZE) == HAL_XSPI_WRAP_32_BYTES) || \ 1148 ((SIZE) == HAL_XSPI_WRAP_64_BYTES) || \ 1149 ((SIZE) == HAL_XSPI_WRAP_128_BYTES)) 1150 1151 #define IS_XSPI_CLK_PRESCALER(PRESCALER) ((PRESCALER) <= 255U) 1152 1153 #define IS_XSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE) || \ 1154 ((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)) 1155 1156 #define IS_XSPI_DHQC(CYCLE) (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \ 1157 ((CYCLE) == HAL_XSPI_DHQC_ENABLE)) 1158 1159 #define IS_XSPI_CS_BOUND(SIZE) (((SIZE) == HAL_XSPI_BONDARYOF_NONE) || \ 1160 ((SIZE) == HAL_XSPI_BONDARYOF_16B) || \ 1161 ((SIZE) == HAL_XSPI_BONDARYOF_32B) || \ 1162 ((SIZE) == HAL_XSPI_BONDARYOF_64B) || \ 1163 ((SIZE) == HAL_XSPI_BONDARYOF_128B) || \ 1164 ((SIZE) == HAL_XSPI_BONDARYOF_256B) || \ 1165 ((SIZE) == HAL_XSPI_BONDARYOF_512B) || \ 1166 ((SIZE) == HAL_XSPI_BONDARYOF_1KB) || \ 1167 ((SIZE) == HAL_XSPI_BONDARYOF_2KB) || \ 1168 ((SIZE) == HAL_XSPI_BONDARYOF_4KB) || \ 1169 ((SIZE) == HAL_XSPI_BONDARYOF_8KB) || \ 1170 ((SIZE) == HAL_XSPI_BONDARYOF_16KB) || \ 1171 ((SIZE) == HAL_XSPI_BONDARYOF_32KB) || \ 1172 ((SIZE) == HAL_XSPI_BONDARYOF_64KB) || \ 1173 ((SIZE) == HAL_XSPI_BONDARYOF_128KB) || \ 1174 ((SIZE) == HAL_XSPI_BONDARYOF_256KB) || \ 1175 ((SIZE) == HAL_XSPI_BONDARYOF_512KB) || \ 1176 ((SIZE) == HAL_XSPI_BONDARYOF_1MB) || \ 1177 ((SIZE) == HAL_XSPI_BONDARYOF_2MB) || \ 1178 ((SIZE) == HAL_XSPI_BONDARYOF_4MB) || \ 1179 ((SIZE) == HAL_XSPI_BONDARYOF_8MB) || \ 1180 ((SIZE) == HAL_XSPI_BONDARYOF_16MB) || \ 1181 ((SIZE) == HAL_XSPI_BONDARYOF_32MB) || \ 1182 ((SIZE) == HAL_XSPI_BONDARYOF_64MB) || \ 1183 ((SIZE) == HAL_XSPI_BONDARYOF_128MB) || \ 1184 ((SIZE) == HAL_XSPI_BONDARYOF_256MB) || \ 1185 ((SIZE) == HAL_XSPI_BONDARYOF_512MB) || \ 1186 ((SIZE) == HAL_XSPI_BONDARYOF_1GB) || \ 1187 ((SIZE) == HAL_XSPI_BONDARYOF_2GB) || \ 1188 ((SIZE) == HAL_XSPI_BONDARYOF_4GB) || \ 1189 ((SIZE) == HAL_XSPI_BONDARYOF_8GB) || \ 1190 ((SIZE) == HAL_XSPI_BONDARYOF_16GB)) 1191 1192 #define IS_XSPI_DLYB_BYPASS(DLYB) (((DLYB) == HAL_XSPI_DELAY_BLOCK_ON) || \ 1193 ((DLYB) == HAL_XSPI_DELAY_BLOCK_BYPASS)) 1194 1195 1196 #define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) 1197 1198 #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ 1199 ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \ 1200 ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \ 1201 ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG)) 1202 1203 #define IS_OCTOSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \ 1204 ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \ 1205 ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0)) 1206 1207 #if defined(HSPI1) 1208 #define IS_HSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \ 1209 ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \ 1210 ((MEMSEL) == HAL_XSPI_SELECT_IO_11_8) || \ 1211 ((MEMSEL) == HAL_XSPI_SELECT_IO_15_12) || \ 1212 ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0) || \ 1213 ((MEMSEL) == HAL_XSPI_SELECT_IO_15_8)) 1214 1215 #endif /* HSPI1 */ 1216 #define IS_XSPI_INSTRUCTION(OPCODE) ((OPCODE) <= 0xFFFFFFFFU) 1217 1218 #define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ 1219 ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \ 1220 ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \ 1221 ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \ 1222 ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES)) 1223 1224 #define IS_XSPI_INSTRUCTION_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS) || \ 1225 ((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \ 1226 ((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \ 1227 ((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS)) 1228 1229 #define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ 1230 ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) 1231 1232 #define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ 1233 ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \ 1234 ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \ 1235 ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \ 1236 ((MODE) == HAL_XSPI_ADDRESS_8_LINES)) 1237 1238 #define IS_XSPI_ADDRESS_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS) || \ 1239 ((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \ 1240 ((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \ 1241 ((WIDTH) == HAL_XSPI_ADDRESS_32_BITS)) 1242 1243 #define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ 1244 ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE)) 1245 1246 #define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ 1247 ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \ 1248 ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \ 1249 ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \ 1250 ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES)) 1251 1252 #define IS_XSPI_ALT_BYTES_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS) || \ 1253 ((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \ 1254 ((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \ 1255 ((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS)) 1256 1257 #define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ 1258 ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE)) 1259 1260 #define IS_OCTOSPI_DATA_MODE(MODE) (((MODE) == HAL_XSPI_DATA_NONE) || \ 1261 ((MODE) == HAL_XSPI_DATA_1_LINE) || \ 1262 ((MODE) == HAL_XSPI_DATA_2_LINES) || \ 1263 ((MODE) == HAL_XSPI_DATA_4_LINES) || \ 1264 ((MODE) == HAL_XSPI_DATA_8_LINES)) 1265 1266 #if defined(HSPI1) 1267 #define IS_HSPI_DATA_MODE(TYPE,MODE) (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \ 1268 (((MODE) == HAL_XSPI_DATA_NONE) || \ 1269 ((MODE) == HAL_XSPI_DATA_8_LINES) || \ 1270 ((MODE) == HAL_XSPI_DATA_16_LINES)): \ 1271 (((MODE) == HAL_XSPI_DATA_NONE) || \ 1272 ((MODE) == HAL_XSPI_DATA_1_LINE) || \ 1273 ((MODE) == HAL_XSPI_DATA_2_LINES) || \ 1274 ((MODE) == HAL_XSPI_DATA_4_LINES) || \ 1275 ((MODE) == HAL_XSPI_DATA_8_LINES) || \ 1276 ((MODE) == HAL_XSPI_DATA_16_LINES))) 1277 1278 #endif /* HSPI1 */ 1279 #define IS_XSPI_DATA_LENGTH(NUMBER) ((NUMBER) >= 1U) 1280 1281 #define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ 1282 ((MODE) == HAL_XSPI_DATA_DTR_ENABLE)) 1283 1284 #define IS_XSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 1285 1286 #define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ 1287 ((MODE) == HAL_XSPI_DQS_ENABLE)) 1288 1289 #define IS_XSPI_SIOO_MODE(MODE) (((MODE) == HAL_XSPI_SIOO_INST_EVERY_CMD) || \ 1290 ((MODE) == HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD)) 1291 1292 #define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) 1293 1294 #define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) 1295 1296 #define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ 1297 ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE)) 1298 1299 #define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ 1300 ((MODE) == HAL_XSPI_FIXED_LATENCY)) 1301 1302 #define IS_XSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \ 1303 ((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE)) 1304 1305 #define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ 1306 ((MODE) == HAL_XSPI_MATCH_MODE_OR)) 1307 1308 #define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ 1309 ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE)) 1310 1311 #define IS_XSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 1312 1313 #define IS_XSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 1314 1315 #define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ 1316 ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE)) 1317 1318 #define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 1319 1320 #if defined(OCTOSPIM) 1321 #define IS_XSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 1322 1323 #define IS_XSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U) 1324 1325 #define IS_XSPIM_IO_PORT(PORT) (((PORT) == HAL_XSPIM_IOPORT_1_LOW) || \ 1326 ((PORT) == HAL_XSPIM_IOPORT_1_HIGH) || \ 1327 ((PORT) == HAL_XSPIM_IOPORT_2_LOW) || \ 1328 ((PORT) == HAL_XSPIM_IOPORT_2_HIGH) || \ 1329 ((PORT) == HAL_XSPIM_IOPORT_3_LOW) || \ 1330 ((PORT) == HAL_XSPIM_IOPORT_3_HIGH) || \ 1331 ((PORT) == HAL_XSPIM_IOPORT_4_LOW) || \ 1332 ((PORT) == HAL_XSPIM_IOPORT_4_HIGH) || \ 1333 ((PORT) == HAL_XSPIM_IOPORT_5_LOW) || \ 1334 ((PORT) == HAL_XSPIM_IOPORT_5_HIGH) || \ 1335 ((PORT) == HAL_XSPIM_IOPORT_6_LOW) || \ 1336 ((PORT) == HAL_XSPIM_IOPORT_6_HIGH) || \ 1337 ((PORT) == HAL_XSPIM_IOPORT_7_LOW) || \ 1338 ((PORT) == HAL_XSPIM_IOPORT_7_HIGH) || \ 1339 ((PORT) == HAL_XSPIM_IOPORT_8_LOW) || \ 1340 ((PORT) == HAL_XSPIM_IOPORT_8_HIGH)) 1341 1342 #define IS_XSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) 1343 1344 #endif /* OCTOSPIM */ 1345 #define IS_XSPI_DELAY_TYPE(TYPE) (((TYPE) == HAL_XSPI_CAL_FULL_CYCLE_DELAY) || \ 1346 ((TYPE) == HAL_XSPI_CAL_FEEDBACK_CLK_DELAY) || \ 1347 ((TYPE) == HAL_XSPI_CAL_DATA_OUTPUT_DELAY) || \ 1348 ((TYPE) == HAL_XSPI_CAL_DQS_INPUT_DELAY)) 1349 1350 #define IS_XSPI_FINECAL_VALUE(VALUE) ((VALUE) <= 0x7FU) 1351 1352 #define IS_XSPI_COARSECAL_VALUE(VALUE) ((VALUE) <= 0x1FU) 1353 1354 /** 1355 @endcond 1356 */ 1357 1358 /* End of private macros -----------------------------------------------------*/ 1359 1360 /** 1361 * @} 1362 */ 1363 1364 /** 1365 * @} 1366 */ 1367 1368 #endif /* HSPI || HSPI1 || HSPI2 || OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 1369 1370 #ifdef __cplusplus 1371 } 1372 #endif 1373 1374 #endif /* STM32U5xx_HAL_XSPI_H */ 1375
