1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32WBAxx_HAL_H 22 #define __STM32WBAxx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbaxx_hal_conf.h" 30 31 /** @addtogroup STM32WBAxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported variables --------------------------------------------------------*/ 63 /** @defgroup HAL_Exported_Variables HAL Exported Variables 64 * @{ 65 */ 66 extern __IO uint32_t uwTick; 67 extern uint32_t uwTickPrio; 68 extern HAL_TickFreqTypeDef uwTickFreq; 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup HAL_Exported_Constants HAL Exported Constants 75 * @{ 76 */ 77 78 /** 79 * @brief STM32WBAxx HAL Driver version number 80 */ 81 #define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 82 #define __STM32WBAxx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ 83 #define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ 84 #define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 85 #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ 86 |(__STM32WBAxx_HAL_VERSION_SUB1 << 16U)\ 87 |(__STM32WBAxx_HAL_VERSION_SUB2 << 8U )\ 88 |(__STM32WBAxx_HAL_VERSION_RC)) 89 90 /** 91 * @} 92 */ 93 94 /** @defgroup REV_ID device revision ID 95 * @{ 96 */ 97 #define REV_ID_A 0x1000U /*!< STM32WBA_2 rev.A */ 98 #define REV_ID_B 0x2000U /*!< STM32WBA_2 rev.B */ 99 /** 100 * @} 101 */ 102 103 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 104 * @{ 105 */ 106 107 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 108 * @{ 109 */ 110 #define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 111 #define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 112 #define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 113 #define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 114 #define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 115 #define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 116 #define SYSCFG_IT_FPU_ALL (SYSCFG_IT_FPU_IOC|SYSCFG_IT_FPU_DZC|SYSCFG_IT_FPU_UFC|SYSCFG_IT_FPU_OFC|SYSCFG_IT_FPU_IDC|SYSCFG_IT_FPU_IXC) /*!< All */ 117 118 /** 119 * @} 120 */ 121 122 /** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection 123 * @{ 124 */ 125 #define SYSCFG_IO_CELL SYSCFG_CCCSR_EN1 /*!< Compensation cell for the VDD I/O power rail */ 126 #ifdef SYSCFG_CCCSR_EN2 127 #define SYSCFG_IO2_CELL SYSCFG_CCCSR_EN2 /*!< Compensation cell for the VDDIO2 I/O power rail */ 128 #endif /* SYSCFG_CCCSR_EN2 */ 129 /** 130 * @} 131 */ 132 133 /** @defgroup SYSCFG_Compensation_Cell_Ready_Selection Compensation Cell Ready Selection 134 * @{ 135 */ 136 #define SYSCFG_IO_CELL_READY SYSCFG_CCCSR_RDY1 /*!< Ready flag of compensation cell for the VDD I/O power rail */ 137 #ifdef SYSCFG_CCCSR_EN2 138 #define SYSCFG_IO2_CELL_READY SYSCFG_CCCSR_RDY2 /*!< Ready flag of compensation cell for the VDDIO2 I/O power rail */ 139 #endif /* SYSCFG_CCCSR_EN2 */ 140 /** 141 * @} 142 */ 143 144 /** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config 145 * @{ 146 */ 147 #define SYSCFG_IO_CELL_CODE 0UL /*!< Code from the cell */ 148 #define SYSCFG_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */ 149 /** 150 * @} 151 */ 152 153 154 /** @defgroup SYSCFG_Flags_Definition Flags 155 * @{ 156 */ 157 158 #define SYSCFG_FLAG_MCLR SYSCFG_MESR_MCLR /*!< Device memories erase status */ 159 #define SYSCFG_FLAG_IPMEE SYSCFG_MESR_IPMEE /*!< ICACHE and PKA SRAM erase status */ 160 161 /** 162 * @} 163 */ 164 165 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 166 * @{ 167 */ 168 169 /** @brief Fast-mode Plus driving capability on a specific GPIO 170 */ 171 #define SYSCFG_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast-mode Plus on PA6 */ 172 #define SYSCFG_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast-mode Plus on PA7 */ 173 #define SYSCFG_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast-mode Plus on PA15 */ 174 #define SYSCFG_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast-mode Plus on PB3 */ 175 #define SYSCFG_FASTMODEPLUS_ALL (SYSCFG_FASTMODEPLUS_PA6|SYSCFG_FASTMODEPLUS_PA7|SYSCFG_FASTMODEPLUS_PA15|SYSCFG_FASTMODEPLUS_PB3) /*!< All */ 176 177 /** 178 * @} 179 */ 180 181 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items 182 * @brief SYSCFG items to set lock on 183 * @{ 184 */ 185 #define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ 186 #define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ 187 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 188 #define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 189 #define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ 190 #define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ 191 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ 192 #else 193 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 194 #endif /* __ARM_FEATURE_CMSE */ 195 /** 196 * @} 197 */ 198 199 #if defined (SYSCFG_SECCFGR_SYSCFGSEC) 200 /** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items 201 * @brief SYSCFG items to configure secure or non-secure attributes on 202 * @{ 203 */ 204 #define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ 205 #define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ 206 #define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ 207 #define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ 208 /** 209 * @} 210 */ 211 #endif /* SYSCFG_SECCFGR_SYSCFGSEC */ 212 213 /** @defgroup SYSCFG_attributes SYSCFG attributes 214 * @brief SYSCFG secure or non-secure attributes 215 * @{ 216 */ 217 #define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ 218 #define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ 219 /** 220 * @} 221 */ 222 223 #ifdef SYSCFG_OTGHSPHYCR_EN 224 /** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection 225 * @{ 226 */ 227 228 /** @brief OTG HS PHY reference clock frequency selection 229 */ 230 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ 231 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ 232 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ 233 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ 234 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ 235 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down 241 * @{ 242 */ 243 244 /** @brief OTG HS PHY Power Down config 245 */ 246 #define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ 247 #define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ 248 /** 249 * @} 250 */ 251 252 /** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable 253 * @{ 254 */ 255 #define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ 256 #define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ 257 /** 258 * @} 259 */ 260 261 /** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current 262 * @{ 263 */ 264 265 /** @brief High-speed (HS) transmitter preemphasis current control 266 */ 267 #define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ 268 #define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ 269 #define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ 270 #define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ 271 /** 272 * @} 273 */ 274 275 /** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold 276 * @{ 277 */ 278 279 /** @brief Squelch threshold adjustment 280 */ 281 #define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ 282 #define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ 283 /** 284 * @} 285 */ 286 287 /** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold 288 * @{ 289 */ 290 291 /** @brief Disconnect threshold adjustment 292 */ 293 #define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ 294 #define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ 295 /** 296 * @} 297 */ 298 #endif /* SYSCFG_OTGHSPHYCR_EN */ 299 300 /** 301 * @} 302 */ 303 304 /* Exported macros -----------------------------------------------------------*/ 305 306 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 307 * @{ 308 */ 309 310 /** @brief Freeze/Unfreeze Peripherals in Debug mode 311 */ 312 #if defined(DBGMCU_APB1LFZR_DBG_TIM2_STOP) 313 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM2_STOP) 314 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM2_STOP) 315 #endif /* DBGMCU_APB1LFZR_DBG_TIM2_STOP */ 316 317 #if defined(DBGMCU_APB1LFZR_DBG_TIM3_STOP) 318 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM3_STOP) 319 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM3_STOP) 320 #endif /* DBGMCU_APB1LFZR_DBG_TIM3_STOP */ 321 322 #if defined(DBGMCU_APB1LFZR_DBG_WWDG_STOP) 323 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_WWDG_STOP) 324 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_WWDG_STOP) 325 #endif /* DBGMCU_APB1LFZR_DBG_WWDG_STOP */ 326 327 #if defined(DBGMCU_APB1LFZR_DBG_IWDG_STOP) 328 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_IWDG_STOP) 329 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_IWDG_STOP) 330 #endif /* DBGMCU_APB1LFZR_DBG_IWDG_STOP */ 331 332 #if defined(DBGMCU_APB1LFZR_DBG_I2C1_STOP) 333 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_I2C1_STOP) 334 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_I2C1_STOP) 335 #endif /* DBGMCU_APB1LFZR_DBG_I2C1_STOP */ 336 337 #if defined(DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) 338 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1HFZR, DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) 339 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1HFZR, DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) 340 #endif /* DBGMCU_APB1HFZR_DBG_LPTIM2_STOP */ 341 342 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 343 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 344 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 345 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 346 347 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 348 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 349 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 350 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 351 352 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 353 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 354 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 355 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 356 357 #if defined(DBGMCU_APB7FZR_DBG_I2C3_STOP) 358 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_I2C3_STOP) 359 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_I2C3_STOP) 360 #endif /* DBGMCU_APB7FZR_DBG_I2C3_STOP */ 361 362 #if defined(DBGMCU_APB7FZR_DBG_LPTIM1_STOP) 363 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_LPTIM1_STOP) 364 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_LPTIM1_STOP) 365 #endif /* DBGMCU_APB7FZR_DBG_LPTIM1_STOP */ 366 367 #if defined(DBGMCU_APB7FZR_DBG_RTC_STOP) 368 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_RTC_STOP) 369 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_RTC_STOP) 370 #endif /* DBGMCU_APB7FZR_DBG_RTC_STOP */ 371 372 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 373 #define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 374 #define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 375 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */ 376 377 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 378 #define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 379 #define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 380 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */ 381 382 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 383 #define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 384 #define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 385 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */ 386 387 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 388 #define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 389 #define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 390 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */ 391 392 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 393 #define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 394 #define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 395 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */ 396 397 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 398 #define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 399 #define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 400 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */ 401 402 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 403 #define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 404 #define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 405 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */ 406 407 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 408 #define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 409 #define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 410 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */ 411 412 /** 413 * @} 414 */ 415 416 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 417 * @{ 418 */ 419 420 /** @brief Floating Point Unit interrupt enable/disable macros 421 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 422 */ 423 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 424 SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 425 }while(0) 426 427 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 428 CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 429 }while(0) 430 431 /** @brief SYSCFG Break ECC lock. 432 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 433 * @note The selected configuration is locked and can be unlocked only by system reset. 434 */ 435 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 436 437 /** @brief SYSCFG Break Cortex-M33 Lockup lock. 438 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 439 * @note The selected configuration is locked and can be unlocked only by system reset. 440 */ 441 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 442 443 /** @brief SYSCFG Break PVD lock. 444 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in 445 * the PWR_CR2 register. 446 * @note The selected configuration is locked and can be unlocked only by system reset. 447 */ 448 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 449 450 /** @brief SYSCFG Break SRAM2 parity lock. 451 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 452 * @note The selected configuration is locked and can be unlocked by system reset. 453 */ 454 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 455 456 /** @brief Check SYSCFG flag is set or not. 457 * @param __FLAG__ specifies the flag to check. 458 * This parameter can be one of the following values: 459 * @arg @ref SYSCFG_FLAG_MCLR Device memories erase status flag 460 * @arg @ref SYSCFG_FLAG_IPMEE ICACHE and PKA SRAM erase status flag 461 * @retval The new state of __FLAG__ (TRUE or FALSE). 462 */ 463 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (READ_BIT(SYSCFG->MESR, (__FLAG__)) == (__FLAG__)) 464 465 /** @brief Clear SYSCFG flag. 466 * @param __FLAG__ specifies the flag(s) to clear. 467 * This parameter can be any combination of the following values: 468 * @arg @ref SYSCFG_FLAG_MCLR Device memories erase status flag 469 * @arg @ref SYSCFG_FLAG_IPMEE ICACHE and PKA SRAM erase status flag 470 */ 471 #define __HAL_SYSCFG_CLEAR_FLAG(__FLAG__) SET_BIT(SYSCFG->MESR, (__FLAG__)) 472 473 /** @brief Fast-mode Plus driving capability enable/disable macros 474 * @param __FASTMODEPLUS__: This parameter can be a value of : 475 * @arg @ref SYSCFG_FASTMODEPLUS_PA6 Fast-mode Plus driving capability activation on PA6 476 * @arg @ref SYSCFG_FASTMODEPLUS_PA7 Fast-mode Plus driving capability activation on PA7 477 * @arg @ref SYSCFG_FASTMODEPLUS_PA15 Fast-mode Plus driving capability activation on PA15 478 * @arg @ref SYSCFG_FASTMODEPLUS_PB3 Fast-mode Plus driving capability activation on PB3 479 */ 480 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 481 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 482 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 483 }while(0) 484 485 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 486 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 487 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 488 }while(0) 489 490 /** 491 * @} 492 */ 493 494 /* Private macros ------------------------------------------------------------*/ 495 496 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 497 * @{ 498 */ 499 500 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \ 501 (((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U)) 502 503 #ifdef SYSCFG_CCCSR_EN2 504 #define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_CELL) || \ 505 ((__CELL__) == SYSCFG_IO2_CELL)) 506 507 #define IS_SYSCFG_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_READY) || \ 508 ((__CELL__) == SYSCFG_IO2_CELL_READY)) 509 #else 510 #define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_CELL)) 511 512 #define IS_SYSCFG_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_READY)) 513 #endif /* SYSCFG_CCCSR_EN2 */ 514 515 #define IS_SYSCFG_COMPENSATION_CELL_CODE(__VALUE__) (((__VALUE__) == SYSCFG_IO_CELL_CODE) || \ 516 ((__VALUE__) == SYSCFG_IO_REGISTER_CODE)) 517 518 #define IS_SYSCFG_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) 519 520 #define IS_SYSCFG_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) 521 522 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 523 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 524 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 525 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 526 527 528 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \ 529 (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U)) 530 531 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 532 533 #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ 534 ((__ATTRIBUTES__) == SYSCFG_NSEC)) 535 536 #define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_ALL) != 0x00U) && \ 537 (((__ITEM__) & ~SYSCFG_ALL) == 0x00U)) 538 539 #endif /* __ARM_FEATURE_CMSE */ 540 541 #if defined (SYSCFG_SECCFGR_SYSCFGSEC) 542 #define IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(__ITEM__) (((__ITEM__) == (SYSCFG_CLK)) || \ 543 ((__ITEM__) == (SYSCFG_CLASSB)) || \ 544 ((__ITEM__) == (SYSCFG_FPU))) 545 #endif /* SYSCFG_SECCFGR_SYSCFGSEC */ 546 547 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \ 548 (((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U)) 549 550 #ifdef SYSCFG_OTGHSPHYCR_EN 551 #define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ 552 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ 553 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ 554 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ 555 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ 556 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) 557 558 #define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ 559 ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) 560 561 #define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ 562 ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) 563 564 #define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ 565 ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) 566 567 #define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ 568 ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) 569 570 #define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ 571 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ 572 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ 573 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) 574 #endif /* SYSCFG_OTGHSPHYCR_EN */ 575 576 /** 577 * @} 578 */ 579 580 /* Exported functions --------------------------------------------------------*/ 581 582 /** @addtogroup HAL_Exported_Functions 583 * @{ 584 */ 585 586 /** @addtogroup HAL_Exported_Functions_Group1 587 * @{ 588 */ 589 590 /* Initialization and de-initialization functions ******************************/ 591 HAL_StatusTypeDef HAL_Init(void); 592 HAL_StatusTypeDef HAL_DeInit(void); 593 void HAL_MspInit(void); 594 void HAL_MspDeInit(void); 595 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 596 597 /** 598 * @} 599 */ 600 601 /** @addtogroup HAL_Exported_Functions_Group2 602 * @{ 603 */ 604 605 /* Peripheral Control functions ************************************************/ 606 void HAL_IncTick(void); 607 void HAL_Delay(uint32_t Delay); 608 uint32_t HAL_GetTick(void); 609 uint32_t HAL_GetTickPrio(void); 610 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 611 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 612 void HAL_SuspendTick(void); 613 void HAL_ResumeTick(void); 614 uint32_t HAL_GetHalVersion(void); 615 uint32_t HAL_GetREVID(void); 616 uint32_t HAL_GetDEVID(void); 617 uint32_t HAL_GetUIDw0(void); 618 uint32_t HAL_GetUIDw1(void); 619 uint32_t HAL_GetUIDw2(void); 620 621 /** 622 * @} 623 */ 624 625 /** @addtogroup HAL_Exported_Functions_Group3 626 * @{ 627 */ 628 629 /* DBGMCU Peripheral Control functions *****************************************/ 630 void HAL_DBGMCU_EnableDBGStopMode(void); 631 void HAL_DBGMCU_DisableDBGStopMode(void); 632 void HAL_DBGMCU_EnableDBGStandbyMode(void); 633 void HAL_DBGMCU_DisableDBGStandbyMode(void); 634 635 /** 636 * @} 637 */ 638 639 /** @addtogroup HAL_Exported_Functions_Group4 640 * @{ 641 */ 642 643 /* SYSCFG Control functions ****************************************************/ 644 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 645 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 646 void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void); 647 void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void); 648 649 650 #ifdef SYSCFG_OTGHSPHYCR_EN 651 void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection); 652 void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); 653 void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); 654 void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); 655 void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); 656 void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); 657 #endif /* SYSCFG_OTGHSPHYCR_EN */ 658 659 void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection); 660 void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection); 661 uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection); 662 void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, 663 uint32_t PmosValue); 664 HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue, 665 uint32_t *pPmosValue); 666 /** 667 * @} 668 */ 669 670 /** @addtogroup HAL_Exported_Functions_Group5 671 * @{ 672 */ 673 674 /* SYSCFG Lock functions ********************************************/ 675 void HAL_SYSCFG_Lock(uint32_t Item); 676 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); 677 678 /** 679 * @} 680 */ 681 682 /** @addtogroup HAL_Exported_Functions_Group6 683 * @{ 684 */ 685 686 #if defined (SYSCFG_SECCFGR_SYSCFGSEC) 687 /* SYSCFG Attributes functions ********************************************/ 688 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 689 void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); 690 #endif /* __ARM_FEATURE_CMSE */ 691 HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 692 #endif /* SYSCFG_SECCFGR_SYSCFGSEC */ 693 694 /** 695 * @} 696 */ 697 698 /** 699 * @} 700 */ 701 702 /** 703 * @} 704 */ 705 706 /** 707 * @} 708 */ 709 710 #ifdef __cplusplus 711 } 712 #endif 713 714 #endif /* __STM32WBAxx_HAL_H */ 715
