1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32U5xx_HAL_H 22 #define __STM32U5xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_conf.h" 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported variables --------------------------------------------------------*/ 63 /** @defgroup HAL_Exported_Variables HAL Exported Variables 64 * @{ 65 */ 66 extern __IO uint32_t uwTick; 67 extern uint32_t uwTickPrio; 68 extern HAL_TickFreqTypeDef uwTickFreq; 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup REV_ID device revision ID 75 * @{ 76 */ 77 #define REV_ID_A 0x1000U /*!< STM32U5 rev.A */ 78 #define REV_ID_B 0x2000U /*!< STM32U5 rev.B */ 79 /** 80 * @} 81 */ 82 83 84 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 85 * @{ 86 */ 87 88 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 89 * @{ 90 */ 91 #define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 92 #define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 93 #define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 94 #define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 95 #define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 96 #define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 103 * @{ 104 */ 105 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 106 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ 107 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ 108 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ 109 110 /** 111 * @} 112 */ 113 114 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 115 * @{ 116 */ 117 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to 118 Voltage reference buffer output */ 119 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 120 121 /** 122 * @} 123 */ 124 125 /** @defgroup SYSCFG_flags_definition Flags 126 * @{ 127 */ 128 129 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 130 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 131 132 /** 133 * @} 134 */ 135 136 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 137 * @{ 138 */ 139 140 /** @brief Fast-mode Plus driving capability on a specific GPIO 141 */ 142 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 143 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 144 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 145 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 146 /** 147 * @} 148 */ 149 150 #if defined(SYSCFG_CFGR1_ENDCAP) 151 /** @defgroup SYSCFG_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE 152 * @{ 153 */ 154 #define SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ 155 #define SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ 156 #define SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ 157 #define SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ 158 /** 159 * @} 160 */ 161 #endif /* SYSCFG_CFGR1_ENDCAP */ 162 163 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items 164 * @brief SYSCFG items to set lock on 165 * @{ 166 */ 167 #define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ 168 #define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ 169 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 170 #define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 171 #define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ 172 #define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ 173 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ 174 #else 175 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 176 #endif /* __ARM_FEATURE_CMSE */ 177 /** 178 * @} 179 */ 180 181 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 182 183 /** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items 184 * @brief SYSCFG items to configure secure or non-secure attributes on 185 * @{ 186 */ 187 #define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ 188 #define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ 189 #define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ 190 #define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ 191 /** 192 * @} 193 */ 194 195 /** @defgroup SYSCFG_attributes SYSCFG attributes 196 * @brief SYSCFG secure or non-secure attributes 197 * @{ 198 */ 199 #define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ 200 #define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ 201 /** 202 * @} 203 */ 204 205 #endif /* __ARM_FEATURE_CMSE */ 206 207 #ifdef SYSCFG_OTGHSPHYCR_EN 208 /** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection 209 * @{ 210 */ 211 212 /** @brief OTG HS PHY reference clock frequency selection 213 */ 214 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ 215 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ 216 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ 217 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ 218 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ 219 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ 220 /** 221 * @} 222 */ 223 224 /** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down 225 * @{ 226 */ 227 228 /** @brief OTG HS PHY Power Down config 229 */ 230 231 #define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ 232 #define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ 233 234 /** 235 * @} 236 */ 237 238 /** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable 239 * @{ 240 */ 241 242 #define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ 243 #define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ 244 245 /** 246 * @} 247 */ 248 249 /** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current 250 * @{ 251 */ 252 253 /** @brief High-speed (HS) transmitter preemphasis current control 254 */ 255 #define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ 256 #define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ 257 #define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ 258 #define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ 259 260 /** 261 * @} 262 */ 263 264 /** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold 265 * @{ 266 */ 267 268 /** @brief Squelch threshold adjustment 269 */ 270 #define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ 271 #define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ 272 273 /** 274 * @} 275 */ 276 277 /** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold 278 * @{ 279 */ 280 281 /** @brief Disconnect threshold adjustment 282 */ 283 #define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ 284 #define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ 285 286 /** 287 * @} 288 */ 289 290 #endif /* SYSCFG_OTGHSPHYCR_EN */ 291 /** 292 * @} 293 */ 294 295 /* Exported macros -----------------------------------------------------------*/ 296 297 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 298 * @{ 299 */ 300 301 /** @brief Freeze/Unfreeze Peripherals in Debug mode 302 */ 303 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 304 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 305 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 306 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ 307 308 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 309 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 310 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 311 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ 312 313 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 314 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 315 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 316 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 317 318 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 319 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 320 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 321 #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ 322 323 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 324 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 325 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 326 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ 327 328 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 329 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 330 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 331 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ 332 333 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 334 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 335 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 336 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ 337 338 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 339 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 340 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 341 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ 342 343 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 344 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 345 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 346 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ 347 348 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 349 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 350 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 351 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ 352 353 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 354 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 355 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 356 #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ 357 358 #if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP) 359 #define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) 360 #define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) 361 #endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */ 362 363 #if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP) 364 #define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) 365 #define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) 366 #endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */ 367 368 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 369 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 370 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 371 #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ 372 373 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 374 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 375 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 376 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 377 378 #if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) 379 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 380 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 381 #endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ 382 383 #if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) 384 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 385 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 386 #endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ 387 388 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 389 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 390 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 391 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 392 393 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 394 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 395 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 396 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 397 398 #if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) 399 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 400 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 401 #endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ 402 403 #if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 404 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 405 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 406 #endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ 407 408 #if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 409 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 410 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 411 #endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ 412 413 #if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 414 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 415 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 416 #endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ 417 418 #if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) 419 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 420 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 421 #endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ 422 423 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 424 #define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 425 #define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 426 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */ 427 428 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 429 #define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 430 #define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 431 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */ 432 433 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 434 #define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 435 #define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 436 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */ 437 438 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 439 #define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 440 #define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 441 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */ 442 443 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 444 #define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 445 #define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 446 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */ 447 448 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 449 #define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 450 #define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 451 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */ 452 453 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 454 #define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 455 #define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 456 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */ 457 458 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 459 #define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 460 #define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 461 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */ 462 463 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 464 #define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 465 #define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 466 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */ 467 468 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 469 #define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 470 #define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 471 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */ 472 473 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 474 #define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 475 #define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 476 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */ 477 478 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 479 #define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 480 #define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 481 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */ 482 483 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 484 #define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 485 #define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 486 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA12_STOP */ 487 488 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 489 #define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 490 #define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 491 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA13_STOP */ 492 493 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 494 #define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 495 #define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 496 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA14_STOP */ 497 498 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 499 #define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 500 #define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 501 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA15_STOP */ 502 503 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 504 #define __HAL_DBGMCU_FREEZE_LPDMA0() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 505 #define __HAL_DBGMCU_UNFREEZE_LPDMA0() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 506 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA0_STOP */ 507 508 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 509 #define __HAL_DBGMCU_FREEZE_LPDMA1() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 510 #define __HAL_DBGMCU_UNFREEZE_LPDMA1() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 511 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA1_STOP */ 512 513 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 514 #define __HAL_DBGMCU_FREEZE_LPDMA2() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 515 #define __HAL_DBGMCU_UNFREEZE_LPDMA2() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 516 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA2_STOP */ 517 518 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 519 #define __HAL_DBGMCU_FREEZE_LPDMA3() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 520 #define __HAL_DBGMCU_UNFREEZE_LPDMA3() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 521 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA3_STOP */ 522 523 /** 524 * @} 525 */ 526 527 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 528 * @{ 529 */ 530 531 /** @brief Floating Point Unit interrupt enable/disable macros 532 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 533 */ 534 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 535 SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 536 }while(0) 537 538 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 539 CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 540 }while(0) 541 542 /** @brief SYSCFG Break ECC lock. 543 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 544 * @note The selected configuration is locked and can be unlocked only by system reset. 545 */ 546 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 547 548 /** @brief SYSCFG Break Cortex-M33 Lockup lock. 549 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 550 * @note The selected configuration is locked and can be unlocked only by system reset. 551 */ 552 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 553 554 /** @brief SYSCFG Break PVD lock. 555 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in 556 * the PWR_CR2 register. 557 * @note The selected configuration is locked and can be unlocked only by system reset. 558 */ 559 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 560 561 /** @brief SYSCFG Break SRAM2 parity lock. 562 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 563 * @note The selected configuration is locked and can be unlocked by system reset. 564 */ 565 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 566 567 /** @brief Check SYSCFG flag is set or not. 568 * @param __FLAG__: specifies the flag to check. 569 * This parameter can be one of the following values: 570 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 571 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 572 * @retval The new state of __FLAG__ (TRUE or FALSE). 573 */ 574 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ 575 & (__FLAG__))!= 0) ? 1 : 0) 576 577 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 578 */ 579 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 580 581 /** @brief Fast-mode Plus driving capability enable/disable macros 582 * @param __FASTMODEPLUS__: This parameter can be a value of : 583 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 584 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 585 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 586 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 587 */ 588 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 589 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 590 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 591 }while(0) 592 593 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 594 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 595 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 596 }while(0) 597 598 /** 599 * @} 600 */ 601 602 /* Private macros ------------------------------------------------------------*/ 603 604 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 605 * @{ 606 */ 607 608 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 609 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 610 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 611 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 612 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 613 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 614 615 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 616 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 617 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 618 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 619 620 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 621 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ 622 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ 623 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) 624 625 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 626 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 627 628 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 629 630 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 631 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 632 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 633 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 634 635 #if defined(SYSCFG_CFGR1_ENDCAP) 636 #define IS_SYSCFG_DECOUPLING_CAPACITANCE(__CAPA__) (((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_OFF) || \ 637 ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_1_DIV_3) || \ 638 ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_2_DIV_3) || \ 639 ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_FULL)) 640 #endif /* SYSCFG_CFGR1_ENDCAP */ 641 642 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 643 #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ 644 ((__ATTRIBUTES__) == SYSCFG_NSEC)) 645 646 #define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \ 647 (((__ITEM__) & SYSCFG_CLASSB) == SYSCFG_CLASSB) || \ 648 (((__ITEM__) & SYSCFG_FPU) == SYSCFG_FPU) || \ 649 (((__ITEM__) & ~(SYSCFG_ALL)) == 0U)) 650 651 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 652 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 653 (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ 654 (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ 655 (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \ 656 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 657 658 #else 659 660 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 661 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 662 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 663 #endif /* __ARM_FEATURE_CMSE */ 664 665 #if defined SYSCFG_OTGHSPHYCR_EN 666 #define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ 667 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ 668 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ 669 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ 670 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ 671 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) 672 673 #define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ 674 ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) 675 676 #define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ 677 ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) 678 679 #define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ 680 ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) 681 682 #define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ 683 ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) 684 685 #define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ 686 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ 687 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ 688 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) 689 #endif /* SYSCFG_OTGHSPHYCR_EN */ 690 691 /** 692 * @} 693 */ 694 695 /** @defgroup HAL_Private_Macros HAL Private Macros 696 * @{ 697 */ 698 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 699 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 700 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 701 /** 702 * @} 703 */ 704 705 /* Exported functions --------------------------------------------------------*/ 706 707 /** @addtogroup HAL_Exported_Functions HAL Exported Functions 708 * @{ 709 */ 710 711 /** @addtogroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions 712 * @{ 713 */ 714 715 /* Initialization and de-initialization functions ******************************/ 716 HAL_StatusTypeDef HAL_Init(void); 717 HAL_StatusTypeDef HAL_DeInit(void); 718 void HAL_MspInit(void); 719 void HAL_MspDeInit(void); 720 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 721 722 /** 723 * @} 724 */ 725 726 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions 727 * @{ 728 */ 729 730 /* Peripheral Control functions ************************************************/ 731 void HAL_IncTick(void); 732 void HAL_Delay(uint32_t Delay); 733 uint32_t HAL_GetTick(void); 734 uint32_t HAL_GetTickPrio(void); 735 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 736 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 737 void HAL_SuspendTick(void); 738 void HAL_ResumeTick(void); 739 uint32_t HAL_GetHalVersion(void); 740 uint32_t HAL_GetREVID(void); 741 uint32_t HAL_GetDEVID(void); 742 uint32_t HAL_GetUIDw0(void); 743 uint32_t HAL_GetUIDw1(void); 744 uint32_t HAL_GetUIDw2(void); 745 746 /** 747 * @} 748 */ 749 750 /** @addtogroup HAL_Exported_Functions_Group3 HAL Debug functions 751 * @{ 752 */ 753 754 /* DBGMCU Peripheral Control functions *****************************************/ 755 void HAL_DBGMCU_EnableDBGStopMode(void); 756 void HAL_DBGMCU_DisableDBGStopMode(void); 757 void HAL_DBGMCU_EnableDBGStandbyMode(void); 758 void HAL_DBGMCU_DisableDBGStandbyMode(void); 759 760 /** 761 * @} 762 */ 763 764 /** @addtogroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions 765 * @{ 766 */ 767 768 /* SYSCFG Control functions ****************************************************/ 769 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 770 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 771 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 772 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 773 void HAL_SYSCFG_DisableVREFBUF(void); 774 #ifdef SYSCFG_OTGHSPHYCR_EN 775 void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection); 776 void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); 777 void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); 778 void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); 779 void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); 780 void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); 781 #endif /* SYSCFG_OTGHSPHYCR_EN */ 782 void HAL_SYSCFG_EnableIOAnalogBooster(void); 783 void HAL_SYSCFG_DisableIOAnalogBooster(void); 784 void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void); 785 void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void); 786 #if defined(SYSCFG_CFGR1_ENDCAP) 787 void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance); 788 uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void); 789 #endif /* SYSCFG_CFGR1_ENDCAP */ 790 void HAL_SYSCFG_EnableSRAMCached(void); 791 void HAL_SYSCFG_DisableSRAMCached(void); 792 void HAL_SYSCFG_EnableVddCompensationCell(void); 793 void HAL_SYSCFG_EnableVddIO2CompensationCell(void); 794 #if defined(SYSCFG_CCCSR_EN3) 795 void HAL_SYSCFG_EnableVddHSPICompensationCell(void); 796 #endif /* SYSCFG_CCCSR_EN3 */ 797 void HAL_SYSCFG_DisableVddCompensationCell(void); 798 void HAL_SYSCFG_DisableVddIO2CompensationCell(void); 799 #if defined(SYSCFG_CCCSR_EN3) 800 void HAL_SYSCFG_DisableVddHSPICompensationCell(void); 801 #endif /* SYSCFG_CCCSR_EN3 */ 802 /** 803 * @} 804 */ 805 806 /** @addtogroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions 807 * @{ 808 */ 809 810 /* SYSCFG Lock functions ********************************************/ 811 void HAL_SYSCFG_Lock(uint32_t Item); 812 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); 813 814 /** 815 * @} 816 */ 817 818 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 819 820 /** @addtogroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions 821 * @{ 822 */ 823 824 /* SYSCFG Attributes functions ********************************************/ 825 void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); 826 HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 827 828 /** 829 * @} 830 */ 831 832 #endif /* __ARM_FEATURE_CMSE */ 833 834 /** 835 * @} 836 */ 837 838 /** 839 * @} 840 */ 841 842 /** 843 * @} 844 */ 845 846 #ifdef __cplusplus 847 } 848 #endif 849 850 #endif /* __STM32U5xx_HAL_H */ 851
