1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32H5xx_HAL_H 22 #define __STM32H5xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_conf.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported variables --------------------------------------------------------*/ 63 /** @defgroup HAL_Exported_Variables HAL Exported Variables 64 * @{ 65 */ 66 extern __IO uint32_t uwTick; 67 extern uint32_t uwTickPrio; 68 extern HAL_TickFreqTypeDef uwTickFreq; 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup SBS_Exported_Constants SBS Exported Constants 75 * @{ 76 */ 77 78 /** @defgroup SBS_FPU_Interrupts FPU Interrupts 79 * @{ 80 */ 81 #define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 82 #define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 83 #define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 84 #define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 85 #define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 86 #define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 87 88 /** 89 * @} 90 */ 91 92 /** @defgroup SBS_BREAK_CONFIG SBS Break Config 93 * @{ 94 */ 95 #define SBS_BREAK_FLASH_ECC SBS_CFGR2_ECCL /*!< Enable and lock the FLASH ECC double error with TIM1/8/15/16/17 96 Break inputs.*/ 97 #define SBS_BREAK_PVD SBS_CFGR2_PVDL /*!< Enable and lock the PVD connection with TIM1/8/15/16/17 98 Break inputs. */ 99 #define SBS_BREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enable and lock the SRAM ECC double error signal with 100 TIM1/8/15/16/17 Break inputs.*/ 101 #define SBS_BREAK_LOCKUP SBS_CFGR2_CLL /*!< Enable and lock the connection of Cortex-M33 LOCKUP (hardfault) 102 output to TIM1/8/15/16/17 Break inputs.*/ 103 104 /** 105 * @} 106 */ 107 108 /** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale 109 * @{ 110 */ 111 #define VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 112 #define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ 113 #define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ 114 #define VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ 115 116 /** 117 * @} 118 */ 119 120 /** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance 121 * @{ 122 */ 123 #define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to 124 Voltage reference buffer output */ 125 #define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 126 127 /** 128 * @} 129 */ 130 131 /** @defgroup SBS_FastModePlus_GPIO Fast-mode Plus on GPIO 132 * @{ 133 */ 134 135 /** @brief Fast-mode Plus driving capability on a specific GPIO 136 */ 137 #define SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 138 #define SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 139 #define SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 140 #if defined(SBS_PMCR_PB9_FMP) 141 #define SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 142 #endif /* SBS_PMCR_PB9_FMP */ 143 144 /** 145 * @} 146 */ 147 148 #if defined(SBS_PMCR_ETH_SEL_PHY) 149 /** @defgroup SBS_Ethernet_Config Ethernet Config 150 * @{ 151 */ 152 #define SBS_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface (MII) or GMII */ 153 #define SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */ 154 155 #define IS_SBS_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SBS_ETH_MII) || \ 156 ((CONFIG) == SBS_ETH_RMII)) 157 158 /** 159 * @} 160 */ 161 #endif /* SBS_PMCR_ETH_SEL_PHY */ 162 163 /** @defgroup SBS_Boostvddsel_Selection Boost VDD Selection 164 * @{ 165 */ 166 #define SBS_BOOSTVDDSEL_VDDA ((uint32_t)0x00000000) /*!< Select VDDA as analog switch supply voltage 167 (when BOOSTEN bit is cleared) */ 168 #define SBS_BOOSTVDDSEL_VDD SBS_PMCR_BOOSTVDDSEL /*!< Select VDD as analog switch supply voltage 169 (regardless of BOOSTEN bit) */ 170 171 #define IS_SBS_BOOSTVDD_SELECTION(BOOSTVDDSEL) (((BOOSTVDDSEL) == SBS_BOOSTVDDSEL_VDDA) || \ 172 ((BOOSTVDDSEL) == SBS_BOOSTVDDSEL_VDD)) 173 174 /** 175 * @} 176 */ 177 178 179 /** @defgroup SBS_Memories_Erase_Flag_Status Memory Erase Flags Status 180 * @{ 181 */ 182 #define SBS_MEMORIES_ERASE_FLAG_IPMEE SBS_MESR_IPMEE /*!< Select the Status of End Of Erase for ICACHE 183 and PKA RAMs */ 184 #define SBS_MEMORIES_ERASE_FLAG_MCLR SBS_MESR_MCLR /*!< Select the Status of Erase after Power-on Reset 185 (SRAM2, BKPRAM, ICACHE, DCACHE, PKA rams) */ 186 187 #define IS_SBS_MEMORIES_ERASE_FLAG(FLAG) (((FLAG) == SBS_MEMORIES_ERASE_FLAG_IPMEE) || \ 188 ((FLAG) == SBS_MEMORIES_ERASE_FLAG_MCLR)) 189 190 /** 191 * @} 192 */ 193 194 /** @defgroup SBS_IOCompenstionCell_Config IOCompenstionCell Config 195 * @{ 196 */ 197 #define SBS_VDD_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ 198 #define SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< Code from the SBS compensation cell code register */ 199 200 #define IS_SBS_VDD_CODE_SELECT(SELECT) (((SELECT) == SBS_VDD_CELL_CODE)|| \ 201 ((SELECT) == SBS_VDD_REGISTER_CODE)) 202 203 #define SBS_VDDIO_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ 204 #define SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< Code from the SBS compensation cell code register */ 205 206 #define IS_SBS_VDDIO_CODE_SELECT(SELECT) (((SELECT) == SBS_VDDIO_CELL_CODE)|| \ 207 ((SELECT) == SBS_VDDIO_REGISTER_CODE)) 208 209 #define IS_SBS_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) 210 211 /** 212 * @} 213 */ 214 215 #if defined(SBS_EPOCHSELCR_EPOCH_SEL) 216 /** @defgroup SBS_EPOCH_Selection EPOCH Selection 217 * @{ 218 */ 219 #define SBS_EPOCH_SEL_SECURE 0x0UL /*!< EPOCH secure selected */ 220 #define SBS_EPOCH_SEL_NONSECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH non secure selected */ 221 #define SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */ 222 223 #define IS_SBS_EPOCH_SELECTION(SELECT) (((SELECT) == SBS_EPOCH_SEL_SECURE) || \ 224 ((SELECT) == SBS_EPOCH_SEL_NONSECURE) || \ 225 ((SELECT) == SBS_EPOCH_SEL_PUFCHECK)) 226 /** 227 * @} 228 */ 229 #endif /* SBS_EPOCHSELCR_EPOCH_SEL */ 230 231 #if defined(SBS_NEXTHDPLCR_NEXTHDPL) 232 /** @defgroup SBS_NextHDPL_Selection Next HDPL Selection 233 * @{ 234 */ 235 #define SBS_OBKHDPL_INCR_0 0x00U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ 236 #define SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ 237 #define SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ 238 #define SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ 239 /** 240 * @} 241 */ 242 #endif /* SBS_NEXTHDPLCR_NEXTHDPL */ 243 244 /** @defgroup SBS_HDPL_Value HDPL Value 245 * @{ 246 */ 247 #define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ 248 #define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 0 */ 249 #define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 0 */ 250 #define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 0 */ 251 /** 252 * @} 253 */ 254 255 #if defined(SBS_DBGCR_DBG_AUTH_SEC) 256 /** @defgroup SBS_DEBUG_SEC_Value Debug sec Value 257 * @{ 258 */ 259 #define SBS_DEBUG_SEC_NSEC 0x000000B4U /*!< Debug opening for secure and non-secure */ 260 #define SBS_DEBUG_NSEC 0x0000003CU /*!< Debug opening for non-secure only */ 261 /** 262 * @} 263 */ 264 #endif /* SBS_DBGCR_DBG_AUTH_SEC */ 265 266 /** @defgroup SBS_Lock_items SBS Lock items 267 * @brief SBS items to set lock on 268 * @{ 269 */ 270 #define SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or 271 non-secure only) */ 272 #define SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or 273 non-secure only) */ 274 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 275 #define SBS_SAU (SBS_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 276 #define SBS_MPU_SEC (SBS_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) 277 */ 278 #define SBS_VTOR_AIRCR_SEC (SBS_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure 279 code only) */ 280 #define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC|SBS_SAU|SBS_MPU_SEC|SBS_VTOR_AIRCR_SEC) /*!< All */ 281 #else 282 #define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 283 #endif /* __ARM_FEATURE_CMSE */ 284 /** 285 * @} 286 */ 287 288 /** @defgroup SBS_Attributes_items SBS Attributes items 289 * @brief SBS items to configure secure or non-secure attributes on 290 * @{ 291 */ 292 #define SBS_CLK SBS_SECCFGR_SBSSEC /*!< SBS clock control */ 293 #define SBS_CLASSB SBS_SECCFGR_CLASSBSEC /*!< Class B */ 294 #define SBS_FPU SBS_SECCFGR_FPUSEC /*!< FPU */ 295 #define SBS_SMPS SBS_SECCFGR_SDCE_SEC_EN /*!< SMPS */ 296 #define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU | SBS_SMPS) /*!< All */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup SBS_attributes SBS attributes 302 * @brief SBS secure or non-secure attributes 303 * @{ 304 */ 305 #define SBS_SEC 0x00000001U /*!< Secure attribute */ 306 #define SBS_NSEC 0x00000000U /*!< Non-secure attribute */ 307 /** 308 * @} 309 */ 310 311 /** 312 * @} 313 */ 314 315 /* Exported macros -----------------------------------------------------------*/ 316 317 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 318 * @{ 319 */ 320 321 /** @brief Freeze/Unfreeze Peripherals in Debug mode 322 */ 323 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 324 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 325 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 326 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ 327 328 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 329 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 330 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 331 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ 332 333 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 334 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 335 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 336 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 337 338 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 339 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 340 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 341 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 342 343 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 344 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 345 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 346 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ 347 348 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 349 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 350 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 351 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ 352 353 #if defined(DBGMCU_APB1FZR1_DBG_TIM12_STOP) 354 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP) 355 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP) 356 #endif /* DBGMCU_APB1FZR1_DBG_TIM12_STOP */ 357 358 #if defined(DBGMCU_APB1FZR1_DBG_TIM13_STOP) 359 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP) 360 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP) 361 #endif /* DBGMCU_APB1FZR1_DBG_TIM13_STOP */ 362 363 #if defined(DBGMCU_APB1FZR1_DBG_TIM14_STOP) 364 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP) 365 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP) 366 #endif /* DBGMCU_APB1FZR1_DBG_TIM14_STOP */ 367 368 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 369 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 370 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 371 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ 372 373 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 374 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 375 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 376 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ 377 378 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 379 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 380 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 381 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ 382 383 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 384 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 385 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 386 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ 387 388 #if defined(DBGMCU_APB1FZR1_DBG_I3C1_STOP) 389 #define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP) 390 #define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP) 391 #endif /* DBGMCU_APB1FZR1_DBG_I3C1_STOP */ 392 393 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 394 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 395 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 396 #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ 397 398 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 399 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 400 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 401 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 402 403 #if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) 404 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 405 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 406 #endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ 407 408 #if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) 409 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 410 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 411 #endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ 412 413 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 414 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 415 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 416 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 417 418 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 419 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 420 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 421 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 422 423 #if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) 424 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 425 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 426 #endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ 427 428 #if defined(DBGMCU_APB3FZR_DBG_I2C4_STOP) 429 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP) 430 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP) 431 #endif /* DBGMCU_APB3FZR_DBG_I2C4_STOP */ 432 433 #if defined(DBGMCU_APB3FZR_DBG_I3C2_STOP) 434 #define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP) 435 #define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP) 436 #endif /* DBGMCU_APB3FZR_DBG_I3C2_STOP */ 437 438 #if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 439 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 440 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 441 #endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ 442 443 #if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 444 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 445 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 446 #endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ 447 448 #if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 449 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 450 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 451 #endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ 452 453 #if defined(DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 454 #define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 455 #define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 456 #endif /* DBGMCU_APB3FZR_DBG_LPTIM5_STOP */ 457 458 #if defined(DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 459 #define __HAL_DBGMCU_FREEZE_LPTIM6() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 460 #define __HAL_DBGMCU_UNFREEZE_LPTIM6() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 461 #endif /* DBGMCU_APB3FZR_DBG_LPTIM6_STOP */ 462 463 #if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) 464 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 465 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 466 #endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ 467 468 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 469 #define __HAL_DBGMCU_FREEZE_GPDMA1_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 470 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 471 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */ 472 473 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 474 #define __HAL_DBGMCU_FREEZE_GPDMA1_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 475 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 476 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */ 477 478 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 479 #define __HAL_DBGMCU_FREEZE_GPDMA1_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 480 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 481 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */ 482 483 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 484 #define __HAL_DBGMCU_FREEZE_GPDMA1_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 485 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 486 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */ 487 488 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 489 #define __HAL_DBGMCU_FREEZE_GPDMA1_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 490 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 491 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */ 492 493 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 494 #define __HAL_DBGMCU_FREEZE_GPDMA1_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 495 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 496 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */ 497 498 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 499 #define __HAL_DBGMCU_FREEZE_GPDMA1_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 500 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 501 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */ 502 503 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 504 #define __HAL_DBGMCU_FREEZE_GPDMA1_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 505 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 506 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */ 507 508 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 509 #define __HAL_DBGMCU_FREEZE_GPDMA2_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 510 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 511 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP */ 512 513 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 514 #define __HAL_DBGMCU_FREEZE_GPDMA2_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 515 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 516 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP */ 517 518 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 519 #define __HAL_DBGMCU_FREEZE_GPDMA2_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 520 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 521 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP */ 522 523 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 524 #define __HAL_DBGMCU_FREEZE_GPDMA2_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 525 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 526 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP */ 527 528 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 529 #define __HAL_DBGMCU_FREEZE_GPDMA2_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 530 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 531 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP */ 532 533 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 534 #define __HAL_DBGMCU_FREEZE_GPDMA2_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 535 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 536 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP */ 537 538 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 539 #define __HAL_DBGMCU_FREEZE_GPDMA2_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 540 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 541 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP */ 542 543 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 544 #define __HAL_DBGMCU_FREEZE_GPDMA2_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 545 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 546 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP */ 547 548 /** 549 * @} 550 */ 551 552 /** @defgroup SBS_Exported_Macros SBS Exported Macros 553 * @{ 554 */ 555 556 /** @brief Floating Point Unit interrupt enable/disable macros 557 * @param __INTERRUPT__: This parameter can be a value of @ref SBS_FPU_Interrupts 558 */ 559 #define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\ 560 SET_BIT(SBS->FPUIMR, (__INTERRUPT__));\ 561 }while(0) 562 563 #define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\ 564 CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__));\ 565 }while(0) 566 567 /** @brief SBS Break ECC lock. 568 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 569 * @note The selected configuration is locked and can be unlocked only by system reset. 570 */ 571 #define __HAL_SBS_BREAK_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_ECCL) 572 573 /** @brief SBS Break Cortex-M33 Lockup lock. 574 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 575 * @note The selected configuration is locked and can be unlocked only by system reset. 576 */ 577 #define __HAL_SBS_BREAK_LOCKUP_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_CLL) 578 579 /** @brief SBS Break PVD lock. 580 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] 581 * in the PWR_CR2 register. 582 * @note The selected configuration is locked and can be unlocked only by system reset. 583 */ 584 #define __HAL_SBS_BREAK_PVD_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_PVDL) 585 586 /** @brief SBS Break SRAM double ECC lock. 587 * Enable and lock the connection of SRAM double ECC error to TIM1/8/15/16/17 Break input. 588 * @note The selected configuration is locked and can be unlocked only by system reset. 589 */ 590 #define __HAL_SBS_BREAK_SRAM_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_SEL) 591 592 /** @brief Fast-mode Plus driving capability enable/disable macros 593 * @param __FASTMODEPLUS__: This parameter can be a value of : 594 * @arg @ref SBS_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 595 * @arg @ref SBS_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 596 * @arg @ref SBS_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 597 * @arg @ref SBS_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 598 */ 599 #define __HAL_SBS_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\ 600 SET_BIT(SBS->PMCR, (__FASTMODEPLUS__));\ 601 }while(0) 602 603 #define __HAL_SBS_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\ 604 CLEAR_BIT(SBS->PMCR, (__FASTMODEPLUS__));\ 605 }while(0) 606 607 /** @brief Check SBS Memories Erase Status Flags. 608 * @param __FLAG__: specifies the flag to check. 609 * This parameter can be one of the following values: 610 * @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs 611 * @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM, 612 * ICACHE, DCACHE, PKA RAMs) 613 * @retval The new state of __FLAG__ (TRUE or FALSE). 614 */ 615 #define __HAL_SBS_GET_MEMORIES_ERASE_STATUS(__FLAG__) ((((SBS->MESR) & (__FLAG__))!= 0) ? 1 : 0) 616 617 /** @brief Clear SBS Memories Erase Status Flags. 618 * @param __FLAG__: specifies the flag to clear. 619 * This parameter can be one of the following values: 620 * @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs 621 * @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM, 622 * ICACHE, DCACHE, PKA RAMs) 623 */ 624 #define __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS(__FLAG__) do {assert_param(IS_SBS_MEMORIES_ERASE_FLAG((__FLAG__)));\ 625 WRITE_REG(SBS->MESR, (__FLAG__));\ 626 }while(0) 627 628 /** 629 * @} 630 */ 631 632 /* Private macros ------------------------------------------------------------*/ 633 634 /** @defgroup SBS_Private_Macros SBS Private Macros 635 * @{ 636 */ 637 638 #define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \ 639 (((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \ 640 (((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \ 641 (((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \ 642 (((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \ 643 (((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC)) 644 645 #define IS_SBS_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SBS_BREAK_FLASH_ECC) || \ 646 ((__CONFIG__) == SBS_BREAK_PVD) || \ 647 ((__CONFIG__) == SBS_BREAK_SRAM_ECC) || \ 648 ((__CONFIG__) == SBS_BREAK_LOCKUP)) 649 650 #define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \ 651 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \ 652 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \ 653 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE3)) 654 655 #define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 656 ((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE)) 657 658 #define IS_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 659 660 #if defined(SBS_FASTMODEPLUS_PB9) 661 #define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \ 662 (((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \ 663 (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8) || \ 664 (((__PIN__) & SBS_FASTMODEPLUS_PB9) == SBS_FASTMODEPLUS_PB9)) 665 #else 666 #define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \ 667 (((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \ 668 (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8)) 669 #endif /* SBS_FASTMODEPLUS_PB9 */ 670 671 #define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || ((__LEVEL__) == SBS_HDPL_VALUE_1) || \ 672 ((__LEVEL__) == SBS_HDPL_VALUE_2) || ((__LEVEL__) == SBS_HDPL_VALUE_3)) 673 674 #define IS_SBS_OBKHDPL_SELECTION(__SELECT__) (((__SELECT__) == SBS_OBKHDPL_INCR_0) || \ 675 ((__SELECT__) == SBS_OBKHDPL_INCR_1) || \ 676 ((__SELECT__) == SBS_OBKHDPL_INCR_2) || \ 677 ((__SELECT__) == SBS_OBKHDPL_INCR_3)) 678 679 #define IS_SBS_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SBS_CLK) == SBS_CLK) || \ 680 (((__ITEM__) & SBS_CLASSB) == SBS_CLASSB) || \ 681 (((__ITEM__) & SBS_FPU) == SBS_FPU) || \ 682 (((__ITEM__) & SBS_SMPS) == SBS_SMPS) || \ 683 (((__ITEM__) & ~(SBS_ALL)) == 0U)) 684 685 #define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\ 686 ((__ATTRIBUTES__) == SBS_NSEC)) 687 688 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 689 690 #define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \ 691 (((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \ 692 (((__ITEM__) & SBS_SAU) == SBS_SAU) || \ 693 (((__ITEM__) & SBS_MPU_SEC) == SBS_MPU_SEC) || \ 694 (((__ITEM__) & SBS_VTOR_AIRCR_SEC) == SBS_VTOR_AIRCR_SEC) || \ 695 (((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U)) 696 697 #else 698 699 #define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \ 700 (((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \ 701 (((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U)) 702 703 704 #endif /* __ARM_FEATURE_CMSE */ 705 /** 706 * @} 707 */ 708 709 /** @defgroup HAL_Private_Macros HAL Private Macros 710 * @{ 711 */ 712 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 713 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 714 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 715 /** 716 * @} 717 */ 718 /* Exported functions --------------------------------------------------------*/ 719 720 /** @addtogroup HAL_Exported_Functions 721 * @{ 722 */ 723 724 /** @addtogroup HAL_Exported_Functions_Group1 725 * @{ 726 */ 727 728 /* Initialization and de-initialization functions ******************************/ 729 HAL_StatusTypeDef HAL_Init(void); 730 HAL_StatusTypeDef HAL_DeInit(void); 731 void HAL_MspInit(void); 732 void HAL_MspDeInit(void); 733 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 734 735 /** 736 * @} 737 */ 738 739 /** @addtogroup HAL_Exported_Functions_Group2 740 * @{ 741 */ 742 743 /* Peripheral Control functions ************************************************/ 744 void HAL_IncTick(void); 745 void HAL_Delay(uint32_t Delay); 746 uint32_t HAL_GetTick(void); 747 uint32_t HAL_GetTickPrio(void); 748 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 749 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 750 void HAL_SuspendTick(void); 751 void HAL_ResumeTick(void); 752 uint32_t HAL_GetHalVersion(void); 753 uint32_t HAL_GetREVID(void); 754 uint32_t HAL_GetDEVID(void); 755 uint32_t HAL_GetUIDw0(void); 756 uint32_t HAL_GetUIDw1(void); 757 uint32_t HAL_GetUIDw2(void); 758 759 /** 760 * @} 761 */ 762 763 /** @addtogroup HAL_Exported_Functions_Group3 764 * @{ 765 */ 766 767 /* DBGMCU Peripheral Control functions *****************************************/ 768 void HAL_DBGMCU_EnableDBGStopMode(void); 769 void HAL_DBGMCU_DisableDBGStopMode(void); 770 void HAL_DBGMCU_EnableDBGStandbyMode(void); 771 void HAL_DBGMCU_DisableDBGStandbyMode(void); 772 773 /** 774 * @} 775 */ 776 777 /** @addtogroup HAL_Exported_Functions_Group4 778 * @{ 779 */ 780 781 /* VREFBUF Control functions ****************************************************/ 782 #if defined(VREFBUF) 783 void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 784 void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode); 785 void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 786 HAL_StatusTypeDef HAL_EnableVREFBUF(void); 787 void HAL_DisableVREFBUF(void); 788 #endif /* VREFBUF */ 789 790 /** 791 * @} 792 */ 793 794 /** @addtogroup HAL_Exported_Functions_Group5 795 * @{ 796 */ 797 798 /* SBS System Configuration functions *******************************************/ 799 void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface); 800 void HAL_SBS_EnableVddIO1CompensationCell(void); 801 void HAL_SBS_DisableVddIO1CompensationCell(void); 802 void HAL_SBS_EnableVddIO2CompensationCell(void); 803 void HAL_SBS_DisableVddIO2CompensationCell(void); 804 void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode); 805 void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode); 806 uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void); 807 uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void); 808 void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); 809 void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); 810 uint32_t HAL_SBS_GetNMOSVddCompensationValue(void); 811 uint32_t HAL_SBS_GetPMOSVddCompensationValue(void); 812 uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void); 813 uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void); 814 void HAL_SBS_FLASH_EnableECCNMI(void); 815 void HAL_SBS_FLASH_DisableECCNMI(void); 816 uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void); 817 818 /** 819 * @} 820 */ 821 822 /** @addtogroup HAL_Exported_Functions_Group6 823 * @{ 824 */ 825 826 /* SBS Boot control functions ***************************************************/ 827 void HAL_SBS_IncrementHDPLValue(void); 828 uint32_t HAL_SBS_GetHDPLValue(void); 829 830 /** 831 * @} 832 */ 833 834 /** @addtogroup HAL_Exported_Functions_Group7 835 * @{ 836 */ 837 838 /* SBS Hardware secure storage control functions ********************************/ 839 void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection); 840 uint32_t HAL_SBS_GetEPOCHSelection(void); 841 void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value); 842 uint32_t HAL_SBS_GetOBKHDPL(void); 843 844 /** 845 * @} 846 */ 847 848 /** @addtogroup HAL_Exported_Functions_Group8 849 * @{ 850 */ 851 852 /* SBS Debug control functions ***************************************************/ 853 void HAL_SBS_OpenAccessPort(void); 854 void HAL_SBS_OpenDebug(void); 855 HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level); 856 uint32_t HAL_SBS_GetDebugLevel(void); 857 void HAL_SBS_LockDebugConfig(void); 858 void HAL_SBS_ConfigDebugSecurity(uint32_t Security); 859 uint32_t HAL_SBS_GetDebugSecurity(void); 860 861 /** 862 * @} 863 */ 864 865 866 /** @addtogroup HAL_Exported_Functions_Group9 867 * @{ 868 */ 869 870 /* SBS Lock functions ********************************************/ 871 void HAL_SBS_Lock(uint32_t Item); 872 HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem); 873 874 /** 875 * @} 876 */ 877 878 /** @addtogroup HAL_Exported_Functions_Group10 879 * @{ 880 */ 881 882 /* SBS Attributes functions ********************************************/ 883 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 884 void HAL_SBS_ConfigAttributes(uint32_t Item, uint32_t Attributes); 885 HAL_StatusTypeDef HAL_SBS_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 886 #endif /* __ARM_FEATURE_CMSE */ 887 888 /** 889 * @} 890 */ 891 892 /** 893 * @} 894 */ 895 896 /** 897 * @} 898 */ 899 900 /** 901 * @} 902 */ 903 904 #ifdef __cplusplus 905 } 906 #endif /* __cplusplus */ 907 908 #endif /* __STM32H5xx_HAL_H */ 909
