1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32MP1xx_HAL_RCC_EX_H 21 #define __STM32MP1xx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 /** 43 * @brief RCC extended clocks structure definition 44 */ 45 typedef struct 46 { 47 uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. 48 This parameter can be a value of @ref 49 RCCEx_Periph_Clock_Selection */ 50 51 RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters. 52 This parameter will be used only when 53 PLL2 is selected as Clock Source */ 54 55 RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters. 56 This parameter will be used only when 57 PLL3 is selected as Clock Source */ 58 59 RCC_PLLInitTypeDef PLL4; /*!< PLL4 structure parameters. 60 This parameter will be used only when 61 PLL3 is selected as Clock Source */ 62 63 uint32_t I2c12ClockSelection; /*!< Specifies I2C12 clock source 64 This parameter can be a value of 65 @ref RCCEx_I2C12_Clock_Source */ 66 67 uint32_t I2c35ClockSelection; /*!< Specifies I2C35 clock source 68 This parameter can be a value of 69 @ref RCCEx_I2C35_Clock_Source */ 70 71 uint32_t I2c46ClockSelection; /*!< Specifies I2C46 clock source 72 This parameter can be a value of 73 @ref RCCEx_I2C46_Clock_Source */ 74 75 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source 76 This parameter can be a value of @ref 77 RCCEx_SAI1_Clock_Source */ 78 79 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source 80 This parameter can be a value of @ref 81 RCCEx_SAI2_Clock_Source */ 82 83 uint32_t Sai3ClockSelection; /*!< Specifies SAI3 clock source 84 This parameter can be a value of @ref 85 RCCEx_SAI3_Clock_Source */ 86 87 uint32_t Sai4ClockSelection; /*!< Specifies SAI4 clock source 88 This parameter can be a value of @ref 89 RCCEx_SAI4_Clock_Source */ 90 91 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source 92 This parameter can be a value of @ref 93 RCCEx_SPI1_Clock_Source */ 94 95 uint32_t Spi23ClockSelection; /*!< Specifies SPI23 clock source 96 This parameter can be a value of @ref 97 RCCEx_SPI23_Clock_Source */ 98 99 uint32_t Spi45ClockSelection; /*!< Specifies SPI45 clock source 100 This parameter can be a value of @ref 101 RCCEx_SPI45_Clock_Source */ 102 103 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source 104 This parameter can be a value of @ref 105 RCCEx_SPI6_Clock_Source */ 106 107 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source 108 This parameter can be a value of @ref 109 RCCEx_USART1_Clock_Source */ 110 111 uint32_t Uart24ClockSelection; /*!< Specifies UART24 clock source 112 This parameter can be a value of @ref 113 RCCEx_UART24_Clock_Source */ 114 115 uint32_t Uart35ClockSelection; /*!< Specifies UART35 clock source 116 This parameter can be a value of @ref 117 RCCEx_UART35_Clock_Source */ 118 119 uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source 120 This parameter can be a value of @ref 121 RCCEx_USART6_Clock_Source */ 122 123 uint32_t Uart78ClockSelection; /*!< Specifies UART78 clock source 124 This parameter can be a value of @ref 125 RCCEx_UART78_Clock_Source */ 126 127 uint32_t Sdmmc12ClockSelection; /*!< Specifies SDMMC12 clock source 128 This parameter can be a value of @ref 129 RCCEx_SDMMC12_Clock_Source */ 130 131 uint32_t Sdmmc3ClockSelection; /*!< Specifies SDMMC3 clock source 132 This parameter can be a value of @ref 133 RCCEx_SDMMC3_Clock_Source */ 134 135 uint32_t EthClockSelection; /*!< Specifies ETH clock source 136 This parameter can be a value of @ref 137 RCCEx_ETH_Clock_Source */ 138 139 uint32_t FmcClockSelection; /*!< Specifies FMC clock source 140 This parameter can be a value of @ref 141 RCCEx_FMC_Clock_Source */ 142 143 uint32_t QspiClockSelection; /*!< Specifies QSPI clock source 144 This parameter can be a value of @ref 145 RCCEx_QSPI_Clock_Source */ 146 147 uint32_t DsiClockSelection; /*!< Specifies DSI clock source 148 This parameter can be a value of @ref 149 RCCEx_DSI_Clock_Source */ 150 151 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 152 This parameter can be a value of @ref 153 RCCEx_CKPER_Clock_Source */ 154 155 uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source 156 This parameter can be a value of @ref 157 RCCEx_SPDIFRX_Clock_Source */ 158 159 uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source 160 This parameter can be a value of @ref 161 RCCEx_FDCAN_Clock_Source */ 162 163 uint32_t Rng1ClockSelection; /*!< Specifies RNG1 clock source 164 This parameter can be a value of @ref 165 RCCEx_RNG1_Clock_Source */ 166 167 uint32_t Rng2ClockSelection; /*!< Specifies RNG2 clock source 168 This parameter can be a value of @ref 169 RCCEx_RNG2_Clock_Source */ 170 171 uint32_t StgenClockSelection; /*!< Specifies STGEN clock source 172 This parameter can be a value of @ref 173 RCCEx_STGEN_Clock_Source */ 174 175 uint32_t UsbphyClockSelection; /*!< Specifies USB PHY clock source 176 This parameter can be a value of @ref 177 RCCEx_USBPHY_Clock_Source */ 178 179 uint32_t UsboClockSelection; /*!< Specifies USB OTG clock source 180 This parameter can be a value of @ref 181 RCCEx_USBO_Clock_Source */ 182 183 uint32_t CecClockSelection; /*!< Specifies CEC clock source 184 This parameter can be a value of @ref 185 RCCEx_CEC_Clock_Source */ 186 187 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 188 This parameter can be a value of @ref 189 RCCEx_LPTIM1_Clock_Source */ 190 191 uint32_t Lptim23ClockSelection; /*!< Specifies LPTIM23 clock source 192 This parameter can be a value of @ref 193 RCCEx_LPTIM23_Clock_Source */ 194 195 uint32_t Lptim45ClockSelection; /*!< Specifies LPTIM45 clock source 196 This parameter can be a value of @ref 197 RCCEx_LPTIM45_Clock_Source */ 198 199 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 200 This parameter can be a value of @ref 201 RCCEx_ADC_Clock_Source */ 202 203 uint32_t RTCClockSelection; /*!< Specifies RTC clock source 204 This parameter can be a value of @ref 205 RCC_RTC_Clock_Source */ 206 207 uint32_t TIMG1PresSelection; /*!< Specifies TIM Group 1 Clock Prescalers 208 Selection. 209 This parameter can be a value of @ref 210 RCCEx_TIMG1_Prescaler_Selection */ 211 212 uint32_t TIMG2PresSelection; /*!< Specifies TIM Group 2 Clock Prescalers 213 Selection. 214 This parameter can be a value of @ref 215 RCCEx_TIMG2_Prescaler_Selection */ 216 } RCC_PeriphCLKInitTypeDef; 217 /** 218 * @} 219 */ 220 221 /* Exported constants --------------------------------------------------------*/ 222 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 223 * @{ 224 */ 225 226 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx_Periph_Clock_Selection 227 * @{ 228 */ 229 #define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001) 230 #define RCC_PERIPHCLK_UART24 ((uint64_t)0x00000002) 231 #define RCC_PERIPHCLK_UART35 ((uint64_t)0x00000004) 232 #define RCC_PERIPHCLK_ADC ((uint64_t)0x00000008) 233 #define RCC_PERIPHCLK_I2C12 ((uint64_t)0x00000010) 234 #define RCC_PERIPHCLK_I2C35 ((uint64_t)0x00000020) 235 #define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00000040) 236 #define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00000080) 237 #define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00000100) 238 #define RCC_PERIPHCLK_USBPHY ((uint64_t)0x00000200) 239 #define RCC_PERIPHCLK_TIMG1 ((uint64_t)0x00000400) 240 #define RCC_PERIPHCLK_TIMG2 ((uint64_t)0x00000800) 241 #define RCC_PERIPHCLK_RTC ((uint64_t)0x00001000) 242 #define RCC_PERIPHCLK_CEC ((uint64_t)0x00002000) 243 #define RCC_PERIPHCLK_USART6 ((uint64_t)0x00004000) 244 #define RCC_PERIPHCLK_UART78 ((uint64_t)0x00008000) 245 #define RCC_PERIPHCLK_LPTIM23 ((uint64_t)0x00010000) 246 #define RCC_PERIPHCLK_LPTIM45 ((uint64_t)0x00020000) 247 #define RCC_PERIPHCLK_SAI3 ((uint64_t)0x00040000) 248 #define RCC_PERIPHCLK_USBO ((uint64_t)0x00080000) 249 #define RCC_PERIPHCLK_FMC ((uint64_t)0x00100000) 250 #define RCC_PERIPHCLK_QSPI ((uint64_t)0x00200000) 251 #define RCC_PERIPHCLK_DSI ((uint64_t)0x00400000) 252 #define RCC_PERIPHCLK_CKPER ((uint64_t)0x00800000) 253 #define RCC_PERIPHCLK_SPDIFRX ((uint64_t)0x01000000) 254 #define RCC_PERIPHCLK_FDCAN ((uint64_t)0x02000000) 255 #define RCC_PERIPHCLK_SPI1 ((uint64_t)0x04000000) 256 #define RCC_PERIPHCLK_SPI23 ((uint64_t)0x08000000) 257 #define RCC_PERIPHCLK_SPI45 ((uint64_t)0x10000000) 258 #define RCC_PERIPHCLK_SPI6 ((uint64_t)0x20000000) 259 #define RCC_PERIPHCLK_SAI4 ((uint64_t)0x40000000) 260 #define RCC_PERIPHCLK_SDMMC12 ((uint64_t)0x80000000) 261 #define RCC_PERIPHCLK_SDMMC3 ((uint64_t)0x100000000) 262 #define RCC_PERIPHCLK_ETH ((uint64_t)0x200000000) 263 #define RCC_PERIPHCLK_RNG1 ((uint64_t)0x400000000) 264 #define RCC_PERIPHCLK_RNG2 ((uint64_t)0x800000000) 265 #define RCC_PERIPHCLK_STGEN ((uint64_t)0x1000000000) 266 #define RCC_PERIPHCLK_I2C46 ((uint64_t)0x2000000000) 267 268 #define IS_RCC_PERIPHCLOCK(SELECTION) \ 269 ((((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 270 (((SELECTION) & RCC_PERIPHCLK_UART24) == RCC_PERIPHCLK_UART24) || \ 271 (((SELECTION) & RCC_PERIPHCLK_UART35) == RCC_PERIPHCLK_UART35) || \ 272 (((SELECTION) & RCC_PERIPHCLK_I2C12) == RCC_PERIPHCLK_I2C12) || \ 273 (((SELECTION) & RCC_PERIPHCLK_I2C35) == RCC_PERIPHCLK_I2C35) || \ 274 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 275 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 276 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 277 (((SELECTION) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY) || \ 278 (((SELECTION) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 279 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 280 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 281 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ 282 (((SELECTION) & RCC_PERIPHCLK_UART78) == RCC_PERIPHCLK_UART78) || \ 283 (((SELECTION) & RCC_PERIPHCLK_I2C46) == RCC_PERIPHCLK_I2C46) || \ 284 (((SELECTION) & RCC_PERIPHCLK_LPTIM23) == RCC_PERIPHCLK_LPTIM23) || \ 285 (((SELECTION) & RCC_PERIPHCLK_LPTIM45) == RCC_PERIPHCLK_LPTIM45) || \ 286 (((SELECTION) & RCC_PERIPHCLK_SAI3) == RCC_PERIPHCLK_SAI3) || \ 287 (((SELECTION) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) || \ 288 (((SELECTION) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 289 (((SELECTION) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) || \ 290 (((SELECTION) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) || \ 291 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ 292 (((SELECTION) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 293 (((SELECTION) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) || \ 294 (((SELECTION) & RCC_PERIPHCLK_SPI23) == RCC_PERIPHCLK_SPI23) || \ 295 (((SELECTION) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) || \ 296 (((SELECTION) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) || \ 297 (((SELECTION) & RCC_PERIPHCLK_SAI4) == RCC_PERIPHCLK_SAI4) || \ 298 (((SELECTION) & RCC_PERIPHCLK_SDMMC12) == RCC_PERIPHCLK_SDMMC12) || \ 299 (((SELECTION) & RCC_PERIPHCLK_SDMMC3) == RCC_PERIPHCLK_SDMMC3) || \ 300 (((SELECTION) & RCC_PERIPHCLK_ETH) == RCC_PERIPHCLK_ETH) || \ 301 (((SELECTION) & RCC_PERIPHCLK_RNG1) == RCC_PERIPHCLK_RNG1) || \ 302 (((SELECTION) & RCC_PERIPHCLK_RNG2) == RCC_PERIPHCLK_RNG2) || \ 303 (((SELECTION) & RCC_PERIPHCLK_USBO) == RCC_PERIPHCLK_USBO) || \ 304 (((SELECTION) & RCC_PERIPHCLK_STGEN) == RCC_PERIPHCLK_STGEN) || \ 305 (((SELECTION) & RCC_PERIPHCLK_TIMG1) == RCC_PERIPHCLK_TIMG1) || \ 306 (((SELECTION) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2)) 307 /** 308 * @} 309 */ 310 311 /** @defgroup RCCEx_Periph_One_Clock RCCEx_Periph_One_Clock 312 * @{ 313 */ 314 #define RCC_PERIPHCLK_DAC ((uint64_t)0x4000000000) 315 #define RCC_PERIPHCLK_LTDC ((uint64_t)0x8000000000) 316 #define RCC_PERIPHCLK_DFSDM1 ((uint64_t)0x10000000000) 317 #define RCC_PERIPHCLK_TEMP ((uint64_t)0x20000000000) 318 #define RCC_PERIPHCLK_IWDG1 ((uint64_t)0x40000000000) 319 #define RCC_PERIPHCLK_DDRPHYC ((uint64_t)0x80000000000) 320 #define RCC_PERIPHCLK_IWDG2 ((uint64_t)0x100000000000) 321 #define RCC_PERIPHCLK_GPU ((uint64_t)0x200000000000) 322 #define RCC_PERIPHCLK_WWDG ((uint64_t)0x400000000000) 323 #define RCC_PERIPHCLK_TIM2 RCC_PERIPHCLK_TIMG1 324 #define RCC_PERIPHCLK_TIM3 RCC_PERIPHCLK_TIMG1 325 #define RCC_PERIPHCLK_TIM4 RCC_PERIPHCLK_TIMG1 326 #define RCC_PERIPHCLK_TIM5 RCC_PERIPHCLK_TIMG1 327 #define RCC_PERIPHCLK_TIM6 RCC_PERIPHCLK_TIMG1 328 #define RCC_PERIPHCLK_TIM7 RCC_PERIPHCLK_TIMG1 329 #define RCC_PERIPHCLK_TIM12 RCC_PERIPHCLK_TIMG1 330 #define RCC_PERIPHCLK_TIM13 RCC_PERIPHCLK_TIMG1 331 #define RCC_PERIPHCLK_TIM14 RCC_PERIPHCLK_TIMG1 332 #define RCC_PERIPHCLK_TIM1 RCC_PERIPHCLK_TIMG2 333 #define RCC_PERIPHCLK_TIM8 RCC_PERIPHCLK_TIMG2 334 #define RCC_PERIPHCLK_TIM15 RCC_PERIPHCLK_TIMG2 335 #define RCC_PERIPHCLK_TIM16 RCC_PERIPHCLK_TIMG2 336 #define RCC_PERIPHCLK_TIM17 RCC_PERIPHCLK_TIMG2 337 338 #define IS_RCC_PERIPHONECLOCK(PERIPH) \ 339 ((((PERIPH) & RCC_PERIPHCLK_DAC) == RCC_PERIPHCLK_DAC) || \ 340 (((PERIPH) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ 341 (((PERIPH) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 342 (((PERIPH) & RCC_PERIPHCLK_TEMP) == RCC_PERIPHCLK_TEMP) || \ 343 (((PERIPH) & RCC_PERIPHCLK_IWDG1) == RCC_PERIPHCLK_IWDG1) || \ 344 (((PERIPH) & RCC_PERIPHCLK_IWDG2) == RCC_PERIPHCLK_IWDG2) || \ 345 (((PERIPH) & RCC_PERIPHCLK_WWDG) == RCC_PERIPHCLK_WWDG) || \ 346 (((PERIPH) & RCC_PERIPHCLK_DDRPHYC) == RCC_PERIPHCLK_DDRPHYC) || \ 347 (((PERIPH) & RCC_PERIPHCLK_GPU) == RCC_PERIPHCLK_GPU) || \ 348 (((PERIPH) & RCC_PERIPHCLK_TIMG1) == RCC_PERIPHCLK_TIMG1) || \ 349 (((PERIPH) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2)) 350 /** 351 * @} 352 */ 353 354 /** @defgroup RCCEx_I2C12_Clock_Source I2C12 Clock Source 355 * @{ 356 */ 357 #define RCC_I2C12CLKSOURCE_PCLK1 0U 358 #define RCC_I2C12CLKSOURCE_PLL4 RCC_I2C12CKSELR_I2C12SRC_0 359 #define RCC_I2C12CLKSOURCE_HSI RCC_I2C12CKSELR_I2C12SRC_1 360 #define RCC_I2C12CLKSOURCE_CSI (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0) 361 362 #define IS_RCC_I2C12CLKSOURCE(SOURCE) \ 363 (((SOURCE) == RCC_I2C12CLKSOURCE_PCLK1) || \ 364 ((SOURCE) == RCC_I2C12CLKSOURCE_PLL4) || \ 365 ((SOURCE) == RCC_I2C12CLKSOURCE_HSI) || \ 366 ((SOURCE) == RCC_I2C12CLKSOURCE_CSI)) 367 /** 368 * @} 369 */ 370 371 /** @defgroup RCCEx_I2C35_Clock_Source I2C35 Clock Source 372 * @{ 373 */ 374 #define RCC_I2C35CLKSOURCE_PCLK1 0U 375 #define RCC_I2C35CLKSOURCE_PLL4 RCC_I2C35CKSELR_I2C35SRC_0 376 #define RCC_I2C35CLKSOURCE_HSI RCC_I2C35CKSELR_I2C35SRC_1 377 #define RCC_I2C35CLKSOURCE_CSI (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0) 378 379 #define IS_RCC_I2C35CLKSOURCE(SOURCE) \ 380 (((SOURCE) == RCC_I2C35CLKSOURCE_PCLK1) || \ 381 ((SOURCE) == RCC_I2C35CLKSOURCE_PLL4) || \ 382 ((SOURCE) == RCC_I2C35CLKSOURCE_HSI) || \ 383 ((SOURCE) == RCC_I2C35CLKSOURCE_CSI)) 384 /** 385 * @} 386 */ 387 388 389 /** @defgroup RCCEx_I2C46_Clock_Source I2C46 Clock Source 390 * @{ 391 */ 392 #define RCC_I2C46CLKSOURCE_PCLK5 0U 393 #define RCC_I2C46CLKSOURCE_PLL3 RCC_I2C46CKSELR_I2C46SRC_0 394 #define RCC_I2C46CLKSOURCE_HSI RCC_I2C46CKSELR_I2C46SRC_1 395 #define RCC_I2C46CLKSOURCE_CSI (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0) 396 397 #define IS_RCC_I2C46CLKSOURCE(SOURCE) \ 398 (((SOURCE) == RCC_I2C46CLKSOURCE_PCLK5) || \ 399 ((SOURCE) == RCC_I2C46CLKSOURCE_PLL3) || \ 400 ((SOURCE) == RCC_I2C46CLKSOURCE_HSI) || \ 401 ((SOURCE) == RCC_I2C46CLKSOURCE_CSI)) 402 /** 403 * @} 404 */ 405 406 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 407 * @{ 408 */ 409 #define RCC_SAI1CLKSOURCE_PLL4 0U 410 #define RCC_SAI1CLKSOURCE_PLL3_Q RCC_SAI1CKSELR_SAI1SRC_0 411 #define RCC_SAI1CLKSOURCE_I2SCKIN RCC_SAI1CKSELR_SAI1SRC_1 412 #define RCC_SAI1CLKSOURCE_PER (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0) 413 #define RCC_SAI1CLKSOURCE_PLL3_R RCC_SAI1CKSELR_SAI1SRC_2 414 415 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ 416 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL4) || \ 417 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3_Q) || \ 418 ((__SOURCE__) == RCC_SAI1CLKSOURCE_I2SCKIN) || \ 419 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PER) || \ 420 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3_R)) 421 /** 422 * @} 423 */ 424 425 426 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 427 * @{ 428 */ 429 #define RCC_SAI2CLKSOURCE_PLL4 0U 430 #define RCC_SAI2CLKSOURCE_PLL3_Q RCC_SAI2CKSELR_SAI2SRC_0 431 #define RCC_SAI2CLKSOURCE_I2SCKIN RCC_SAI2CKSELR_SAI2SRC_1 432 #define RCC_SAI2CLKSOURCE_PER (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0) 433 #define RCC_SAI2CLKSOURCE_SPDIF RCC_SAI2CKSELR_SAI2SRC_2 434 #define RCC_SAI2CLKSOURCE_PLL3_R (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0) 435 436 437 #define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \ 438 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL4) || \ 439 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3_Q) || \ 440 ((__SOURCE__) == RCC_SAI2CLKSOURCE_I2SCKIN) || \ 441 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PER) || \ 442 ((__SOURCE__) == RCC_SAI2CLKSOURCE_SPDIF) || \ 443 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3_R)) 444 /** 445 * @} 446 */ 447 448 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source 449 * @{ 450 */ 451 #define RCC_SAI3CLKSOURCE_PLL4 0U 452 #define RCC_SAI3CLKSOURCE_PLL3_Q RCC_SAI3CKSELR_SAI3SRC_0 453 #define RCC_SAI3CLKSOURCE_I2SCKIN RCC_SAI3CKSELR_SAI3SRC_1 454 #define RCC_SAI3CLKSOURCE_PER (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0) 455 #define RCC_SAI3CLKSOURCE_PLL3_R RCC_SAI3CKSELR_SAI3SRC_2 456 457 #define IS_RCC_SAI3CLKSOURCE(__SOURCE__) \ 458 (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL4) || \ 459 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3_Q) || \ 460 ((__SOURCE__) == RCC_SAI3CLKSOURCE_I2SCKIN) || \ 461 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PER) || \ 462 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3_R)) 463 /** 464 * @} 465 */ 466 467 468 /** @defgroup RCCEx_SAI4_Clock_Source SAI4 Clock Source 469 * @{ 470 */ 471 #define RCC_SAI4CLKSOURCE_PLL4 0U 472 #define RCC_SAI4CLKSOURCE_PLL3_Q RCC_SAI4CKSELR_SAI4SRC_0 473 #define RCC_SAI4CLKSOURCE_I2SCKIN RCC_SAI4CKSELR_SAI4SRC_1 474 #define RCC_SAI4CLKSOURCE_PER (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0) 475 #define RCC_SAI4CLKSOURCE_PLL3_R RCC_SAI4CKSELR_SAI4SRC_2 476 477 #define IS_RCC_SAI4CLKSOURCE(__SOURCE__) \ 478 (((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL4) || \ 479 ((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL3_Q) || \ 480 ((__SOURCE__) == RCC_SAI4CLKSOURCE_I2SCKIN) || \ 481 ((__SOURCE__) == RCC_SAI4CLKSOURCE_PER) || \ 482 ((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL3_R)) 483 /** 484 * @} 485 */ 486 487 488 /** @defgroup RCCEx_SPI1_Clock_Source SPI/I2S1 Clock Source 489 * @{ 490 */ 491 #define RCC_SPI1CLKSOURCE_PLL4 0U 492 #define RCC_SPI1CLKSOURCE_PLL3_Q RCC_SPI2S1CKSELR_SPI1SRC_0 493 #define RCC_SPI1CLKSOURCE_I2SCKIN RCC_SPI2S1CKSELR_SPI1SRC_1 494 #define RCC_SPI1CLKSOURCE_PER (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0) 495 #define RCC_SPI1CLKSOURCE_PLL3_R RCC_SPI2S1CKSELR_SPI1SRC_2 496 497 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 498 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL4) || \ 499 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3_Q) || \ 500 ((__SOURCE__) == RCC_SPI1CLKSOURCE_I2SCKIN) || \ 501 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PER) || \ 502 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3_R)) 503 /** 504 * @} 505 */ 506 507 /** @defgroup RCCEx_SPI23_Clock_Source SPI/I2S2,3 Clock Source 508 * @{ 509 */ 510 #define RCC_SPI23CLKSOURCE_PLL4 0U 511 #define RCC_SPI23CLKSOURCE_PLL3_Q RCC_SPI2S23CKSELR_SPI23SRC_0 512 #define RCC_SPI23CLKSOURCE_I2SCKIN RCC_SPI2S23CKSELR_SPI23SRC_1 513 #define RCC_SPI23CLKSOURCE_PER (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0) 514 #define RCC_SPI23CLKSOURCE_PLL3_R RCC_SPI2S23CKSELR_SPI23SRC_2 515 516 #define IS_RCC_SPI23CLKSOURCE(__SOURCE__) \ 517 (((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL4) || \ 518 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL3_Q) || \ 519 ((__SOURCE__) == RCC_SPI23CLKSOURCE_I2SCKIN) || \ 520 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PER) || \ 521 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL3_R)) 522 /** 523 * @} 524 */ 525 526 /** @defgroup RCCEx_SPI45_Clock_Source SPI45 Clock Source 527 * @{ 528 */ 529 #define RCC_SPI45CLKSOURCE_PCLK2 0U 530 #define RCC_SPI45CLKSOURCE_PLL4 RCC_SPI45CKSELR_SPI45SRC_0 531 #define RCC_SPI45CLKSOURCE_HSI RCC_SPI45CKSELR_SPI45SRC_1 532 #define RCC_SPI45CLKSOURCE_CSI (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0) 533 #define RCC_SPI45CLKSOURCE_HSE RCC_SPI45CKSELR_SPI45SRC_2 534 535 #define IS_RCC_SPI45CLKSOURCE(__SOURCE__) \ 536 (((__SOURCE__) == RCC_SPI45CLKSOURCE_PCLK2) || \ 537 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL4) || \ 538 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ 539 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ 540 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) 541 /** 542 * @} 543 */ 544 545 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 546 * @{ 547 */ 548 #define RCC_SPI6CLKSOURCE_PCLK5 0U 549 #define RCC_SPI6CLKSOURCE_PLL4 RCC_SPI6CKSELR_SPI6SRC_0 550 #define RCC_SPI6CLKSOURCE_HSI RCC_SPI6CKSELR_SPI6SRC_1 551 #define RCC_SPI6CLKSOURCE_CSI (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0) 552 #define RCC_SPI6CLKSOURCE_HSE RCC_SPI6CKSELR_SPI6SRC_2 553 #define RCC_SPI6CLKSOURCE_PLL3 (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0) 554 555 #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ 556 (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK5) || \ 557 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL4) || \ 558 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 559 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 560 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ 561 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)) 562 /** 563 * @} 564 */ 565 566 567 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 568 * @{ 569 */ 570 #define RCC_USART1CLKSOURCE_PCLK5 0U 571 #define RCC_USART1CLKSOURCE_PLL3 RCC_UART1CKSELR_UART1SRC_0 572 #define RCC_USART1CLKSOURCE_HSI RCC_UART1CKSELR_UART1SRC_1 573 #define RCC_USART1CLKSOURCE_CSI (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0) 574 #define RCC_USART1CLKSOURCE_PLL4 RCC_UART1CKSELR_UART1SRC_2 575 #define RCC_USART1CLKSOURCE_HSE (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0) 576 577 #define IS_RCC_USART1CLKSOURCE(SOURCE) \ 578 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK5) || \ 579 ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ 580 ((SOURCE) == RCC_USART1CLKSOURCE_HSI) || \ 581 ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ 582 ((SOURCE) == RCC_USART1CLKSOURCE_PLL4) || \ 583 ((SOURCE) == RCC_USART1CLKSOURCE_HSE)) 584 /** 585 * @} 586 */ 587 588 /** @defgroup RCCEx_UART24_Clock_Source UART24 Clock Source 589 * @{ 590 */ 591 #define RCC_UART24CLKSOURCE_PCLK1 0U 592 #define RCC_UART24CLKSOURCE_PLL4 RCC_UART24CKSELR_UART24SRC_0 593 #define RCC_UART24CLKSOURCE_HSI RCC_UART24CKSELR_UART24SRC_1 594 #define RCC_UART24CLKSOURCE_CSI (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0) 595 #define RCC_UART24CLKSOURCE_HSE RCC_UART24CKSELR_UART24SRC_2 596 597 #define IS_RCC_UART24CLKSOURCE(SOURCE) \ 598 (((SOURCE) == RCC_UART24CLKSOURCE_PCLK1) || \ 599 ((SOURCE) == RCC_UART24CLKSOURCE_PLL4) || \ 600 ((SOURCE) == RCC_UART24CLKSOURCE_HSI) || \ 601 ((SOURCE) == RCC_UART24CLKSOURCE_CSI) || \ 602 ((SOURCE) == RCC_UART24CLKSOURCE_HSE)) 603 /** 604 * @} 605 */ 606 607 /** @defgroup RCCEx_UART35_Clock_Source UART35 Clock Source 608 * @{ 609 */ 610 #define RCC_UART35CLKSOURCE_PCLK1 0U 611 #define RCC_UART35CLKSOURCE_PLL4 RCC_UART35CKSELR_UART35SRC_0 612 #define RCC_UART35CLKSOURCE_HSI RCC_UART35CKSELR_UART35SRC_1 613 #define RCC_UART35CLKSOURCE_CSI (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0) 614 #define RCC_UART35CLKSOURCE_HSE RCC_UART35CKSELR_UART35SRC_2 615 616 #define IS_RCC_UART35CLKSOURCE(SOURCE) \ 617 (((SOURCE) == RCC_UART35CLKSOURCE_PCLK1) || \ 618 ((SOURCE) == RCC_UART35CLKSOURCE_PLL4) || \ 619 ((SOURCE) == RCC_UART35CLKSOURCE_HSI) || \ 620 ((SOURCE) == RCC_UART35CLKSOURCE_CSI) || \ 621 ((SOURCE) == RCC_UART35CLKSOURCE_HSE)) 622 /** 623 * @} 624 */ 625 626 /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source 627 * @{ 628 */ 629 #define RCC_USART6CLKSOURCE_PCLK2 0U 630 #define RCC_USART6CLKSOURCE_PLL4 RCC_UART6CKSELR_UART6SRC_0 631 #define RCC_USART6CLKSOURCE_HSI RCC_UART6CKSELR_UART6SRC_1 632 #define RCC_USART6CLKSOURCE_CSI (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0) 633 #define RCC_USART6CLKSOURCE_HSE RCC_UART6CKSELR_UART6SRC_2 634 635 #define IS_RCC_USART6CLKSOURCE(SOURCE) \ 636 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ 637 ((SOURCE) == RCC_USART6CLKSOURCE_PLL4) || \ 638 ((SOURCE) == RCC_USART6CLKSOURCE_HSI) || \ 639 ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ 640 ((SOURCE) == RCC_USART6CLKSOURCE_HSE)) 641 /** 642 * @} 643 */ 644 645 /** @defgroup RCCEx_UART78_Clock_Source UART78 Clock Source 646 * @{ 647 */ 648 #define RCC_UART78CLKSOURCE_PCLK1 0U 649 #define RCC_UART78CLKSOURCE_PLL4 RCC_UART78CKSELR_UART78SRC_0 650 #define RCC_UART78CLKSOURCE_HSI RCC_UART78CKSELR_UART78SRC_1 651 #define RCC_UART78CLKSOURCE_CSI (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0) 652 #define RCC_UART78CLKSOURCE_HSE RCC_UART78CKSELR_UART78SRC_2 653 654 #define IS_RCC_UART78CLKSOURCE(SOURCE) \ 655 (((SOURCE) == RCC_UART78CLKSOURCE_PCLK1) || \ 656 ((SOURCE) == RCC_UART78CLKSOURCE_PLL4) || \ 657 ((SOURCE) == RCC_UART78CLKSOURCE_HSI) || \ 658 ((SOURCE) == RCC_UART78CLKSOURCE_CSI) || \ 659 ((SOURCE) == RCC_UART78CLKSOURCE_HSE)) 660 /** 661 * @} 662 */ 663 664 /** @defgroup RCCEx_SDMMC12_Clock_Source SDMMC12 Clock Source 665 * @{ 666 */ 667 #define RCC_SDMMC12CLKSOURCE_HCLK6 0U 668 #define RCC_SDMMC12CLKSOURCE_PLL3 RCC_SDMMC12CKSELR_SDMMC12SRC_0 669 #define RCC_SDMMC12CLKSOURCE_PLL4 RCC_SDMMC12CKSELR_SDMMC12SRC_1 670 #define RCC_SDMMC12CLKSOURCE_HSI (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0) 671 672 #define IS_RCC_SDMMC12CLKSOURCE(SOURCE) \ 673 (((SOURCE) == RCC_SDMMC12CLKSOURCE_HCLK6) || \ 674 ((SOURCE) == RCC_SDMMC12CLKSOURCE_PLL3) || \ 675 ((SOURCE) == RCC_SDMMC12CLKSOURCE_PLL4) || \ 676 ((SOURCE) == RCC_SDMMC12CLKSOURCE_HSI)) 677 /** 678 * @} 679 */ 680 681 /** @defgroup RCCEx_SDMMC3_Clock_Source SDMMC3 Clock Source 682 * @{ 683 */ 684 #define RCC_SDMMC3CLKSOURCE_HCLK2 0U 685 #define RCC_SDMMC3CLKSOURCE_PLL3 RCC_SDMMC3CKSELR_SDMMC3SRC_0 686 #define RCC_SDMMC3CLKSOURCE_PLL4 RCC_SDMMC3CKSELR_SDMMC3SRC_1 687 #define RCC_SDMMC3CLKSOURCE_HSI (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0) 688 689 #define IS_RCC_SDMMC3CLKSOURCE(SOURCE) \ 690 (((SOURCE) == RCC_SDMMC3CLKSOURCE_HCLK2) || \ 691 ((SOURCE) == RCC_SDMMC3CLKSOURCE_PLL3) || \ 692 ((SOURCE) == RCC_SDMMC3CLKSOURCE_PLL4) || \ 693 ((SOURCE) == RCC_SDMMC3CLKSOURCE_HSI)) 694 /** 695 * @} 696 */ 697 698 /** @defgroup RCCEx_ETH_Clock_Source ETH Clock Source 699 * @{ 700 */ 701 #define RCC_ETHCLKSOURCE_PLL4 0U 702 #define RCC_ETHCLKSOURCE_PLL3 RCC_ETHCKSELR_ETHSRC_0 703 #define RCC_ETHCLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_1 704 705 706 #define IS_RCC_ETHCLKSOURCE(SOURCE) (((SOURCE) == RCC_ETHCLKSOURCE_PLL4) || \ 707 ((SOURCE) == RCC_ETHCLKSOURCE_PLL3) || \ 708 ((SOURCE) == RCC_ETHCLKSOURCE_OFF)) 709 /** 710 * @} 711 */ 712 713 714 /** @defgroup RCCEx_ETH_PrecisionTimeProtocol_Divider ETH PrecisionTimeProtocol Divider 715 * @{ 716 */ 717 #define RCC_ETHPTPDIV_1 0U /*Bypass (default after reset*/ 718 #define RCC_ETHPTPDIV_2 RCC_ETHCKSELR_ETHPTPDIV_0 /*Division by 2*/ 719 #define RCC_ETHPTPDIV_3 RCC_ETHCKSELR_ETHPTPDIV_1 /*Division by 3*/ 720 #define RCC_ETHPTPDIV_4 (RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 4*/ 721 #define RCC_ETHPTPDIV_5 RCC_ETHCKSELR_ETHPTPDIV_2 /*Division by 5*/ 722 #define RCC_ETHPTPDIV_6 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 6*/ 723 #define RCC_ETHPTPDIV_7 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 7*/ 724 #define RCC_ETHPTPDIV_8 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 8*/ 725 #define RCC_ETHPTPDIV_9 RCC_ETHCKSELR_ETHPTPDIV_3 /*Division by 9*/ 726 #define RCC_ETHPTPDIV_10 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 10*/ 727 #define RCC_ETHPTPDIV_11 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 11*/ 728 #define RCC_ETHPTPDIV_12 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 12*/ 729 #define RCC_ETHPTPDIV_13 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2) /*Division by 13*/ 730 #define RCC_ETHPTPDIV_14 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 14*/ 731 #define RCC_ETHPTPDIV_15 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 15*/ 732 #define RCC_ETHPTPDIV_16 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 16*/ 733 734 735 #define IS_RCC_ETHPTPDIV(SOURCE) (((SOURCE) == RCC_ETHPTPDIV_1) || \ 736 ((SOURCE) == RCC_ETHPTPDIV_2) || \ 737 ((SOURCE) == RCC_ETHPTPDIV_3) || \ 738 ((SOURCE) == RCC_ETHPTPDIV_4) || \ 739 ((SOURCE) == RCC_ETHPTPDIV_5) || \ 740 ((SOURCE) == RCC_ETHPTPDIV_6) || \ 741 ((SOURCE) == RCC_ETHPTPDIV_7) || \ 742 ((SOURCE) == RCC_ETHPTPDIV_8) || \ 743 ((SOURCE) == RCC_ETHPTPDIV_9) || \ 744 ((SOURCE) == RCC_ETHPTPDIV_10) || \ 745 ((SOURCE) == RCC_ETHPTPDIV_11) || \ 746 ((SOURCE) == RCC_ETHPTPDIV_12) || \ 747 ((SOURCE) == RCC_ETHPTPDIV_13) || \ 748 ((SOURCE) == RCC_ETHPTPDIV_14) || \ 749 ((SOURCE) == RCC_ETHPTPDIV_15) || \ 750 ((SOURCE) == RCC_ETHPTPDIV_16)) 751 /** 752 * @} 753 */ 754 755 756 /** @defgroup RCCEx_QSPI_Clock_Source QSPI Clock Source 757 * @{ 758 */ 759 #define RCC_QSPICLKSOURCE_ACLK 0U 760 #define RCC_QSPICLKSOURCE_PLL3 RCC_QSPICKSELR_QSPISRC_0 761 #define RCC_QSPICLKSOURCE_PLL4 RCC_QSPICKSELR_QSPISRC_1 762 #define RCC_QSPICLKSOURCE_PER (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0) 763 764 #define IS_RCC_QSPICLKSOURCE(SOURCE) \ 765 (((SOURCE) == RCC_QSPICLKSOURCE_ACLK) || \ 766 ((SOURCE) == RCC_QSPICLKSOURCE_PLL3) || \ 767 ((SOURCE) == RCC_QSPICLKSOURCE_PLL4) || \ 768 ((SOURCE) == RCC_QSPICLKSOURCE_PER)) 769 /** 770 * @} 771 */ 772 773 /** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source 774 * @{ 775 */ 776 #define RCC_FMCCLKSOURCE_ACLK 0U 777 #define RCC_FMCCLKSOURCE_PLL3 RCC_FMCCKSELR_FMCSRC_0 778 #define RCC_FMCCLKSOURCE_PLL4 RCC_FMCCKSELR_FMCSRC_1 779 #define RCC_FMCCLKSOURCE_PER (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0) 780 781 #define IS_RCC_FMCCLKSOURCE(SOURCE) (((SOURCE) == RCC_FMCCLKSOURCE_ACLK) || \ 782 ((SOURCE) == RCC_FMCCLKSOURCE_PLL3) || \ 783 ((SOURCE) == RCC_FMCCLKSOURCE_PLL4) || \ 784 ((SOURCE) == RCC_FMCCLKSOURCE_PER)) 785 /** 786 * @} 787 */ 788 789 #if defined(FDCAN1) 790 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source 791 * @{ 792 */ 793 #define RCC_FDCANCLKSOURCE_HSE 0U 794 #define RCC_FDCANCLKSOURCE_PLL3 RCC_FDCANCKSELR_FDCANSRC_0 795 #define RCC_FDCANCLKSOURCE_PLL4_Q RCC_FDCANCKSELR_FDCANSRC_1 796 #define RCC_FDCANCLKSOURCE_PLL4_R (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0) 797 798 799 800 #define IS_RCC_FDCANCLKSOURCE(SOURCE) \ 801 (((SOURCE) == RCC_FDCANCLKSOURCE_HSE) || \ 802 ((SOURCE) == RCC_FDCANCLKSOURCE_PLL3) || \ 803 ((SOURCE) == RCC_FDCANCLKSOURCE_PLL4_Q) || \ 804 ((SOURCE) == RCC_FDCANCLKSOURCE_PLL4_R)) 805 /** 806 * @} 807 */ 808 #endif /*FDCAN1*/ 809 810 /** @defgroup RCCEx_SPDIFRX_Clock_Source SPDIFRX Clock Source 811 * @{ 812 */ 813 #define RCC_SPDIFRXCLKSOURCE_PLL4 0U 814 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_SPDIFCKSELR_SPDIFSRC_0 815 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_1 816 817 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) \ 818 (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL4) || \ 819 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ 820 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) 821 /** 822 * @} 823 */ 824 825 /** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source 826 * @{ 827 */ 828 #define RCC_CECCLKSOURCE_LSE 0U 829 #define RCC_CECCLKSOURCE_LSI RCC_CECCKSELR_CECSRC_0 830 #define RCC_CECCLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_1 831 832 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ 833 ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ 834 ((SOURCE) == RCC_CECCLKSOURCE_CSI122)) 835 /** 836 * @} 837 */ 838 839 /** @defgroup RCCEx_USBPHY_Clock_Source USBPHY Clock Source 840 * @{ 841 */ 842 #define RCC_USBPHYCLKSOURCE_HSE 0U 843 #define RCC_USBPHYCLKSOURCE_PLL4 RCC_USBCKSELR_USBPHYSRC_0 844 #define RCC_USBPHYCLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_1 845 846 #define IS_RCC_USBPHYCLKSOURCE(SOURCE) \ 847 (((SOURCE) == RCC_USBPHYCLKSOURCE_HSE) || \ 848 ((SOURCE) ==RCC_USBPHYCLKSOURCE_PLL4) || \ 849 ((SOURCE) ==RCC_USBPHYCLKSOURCE_HSE2)) 850 /** 851 * @} 852 */ 853 854 /** @defgroup RCCEx_USBO_Clock_Source USBO Clock Source 855 * @{ 856 */ 857 #define RCC_USBOCLKSOURCE_PLL4 0U 858 #define RCC_USBOCLKSOURCE_PHY RCC_USBCKSELR_USBOSRC 859 860 #define IS_RCC_USBOCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBOCLKSOURCE_PLL4) || \ 861 ((SOURCE) == RCC_USBOCLKSOURCE_PHY)) 862 /** 863 * @} 864 */ 865 866 867 /** @defgroup RCCEx_RNG1_Clock_Source RNG1 Clock Source 868 * @{ 869 */ 870 #define RCC_RNG1CLKSOURCE_CSI 0U 871 #define RCC_RNG1CLKSOURCE_PLL4 RCC_RNG1CKSELR_RNG1SRC_0 872 #define RCC_RNG1CLKSOURCE_LSE RCC_RNG1CKSELR_RNG1SRC_1 873 #define RCC_RNG1CLKSOURCE_LSI (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0) 874 875 #define IS_RCC_RNG1CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG1CLKSOURCE_CSI) || \ 876 ((SOURCE) == RCC_RNG1CLKSOURCE_PLL4) || \ 877 ((SOURCE) == RCC_RNG1CLKSOURCE_LSE) || \ 878 ((SOURCE) == RCC_RNG1CLKSOURCE_LSI)) 879 880 /** 881 * @} 882 */ 883 884 885 /** @defgroup RCCEx_RNG2_Clock_Source RNG2 Clock Source 886 * @{ 887 */ 888 #define RCC_RNG2CLKSOURCE_CSI 0U 889 #define RCC_RNG2CLKSOURCE_PLL4 RCC_RNG2CKSELR_RNG2SRC_0 890 #define RCC_RNG2CLKSOURCE_LSE RCC_RNG2CKSELR_RNG2SRC_1 891 #define RCC_RNG2CLKSOURCE_LSI (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0) 892 893 #define IS_RCC_RNG2CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG2CLKSOURCE_CSI) || \ 894 ((SOURCE) == RCC_RNG2CLKSOURCE_PLL4) || \ 895 ((SOURCE) == RCC_RNG2CLKSOURCE_LSE) || \ 896 ((SOURCE) == RCC_RNG2CLKSOURCE_LSI)) 897 898 /** 899 * @} 900 */ 901 902 903 /** @defgroup RCCEx_CKPER_Clock_Source CKPER Clock Source 904 * @{ 905 */ 906 #define RCC_CKPERCLKSOURCE_HSI 0U 907 #define RCC_CKPERCLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_0 908 #define RCC_CKPERCLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_1 909 #define RCC_CKPERCLKSOURCE_OFF (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/ 910 911 #define IS_RCC_CKPERCLKSOURCE(SOURCE) (((SOURCE) == RCC_CKPERCLKSOURCE_HSI) || \ 912 ((SOURCE) == RCC_CKPERCLKSOURCE_CSI) || \ 913 ((SOURCE) == RCC_CKPERCLKSOURCE_HSE) || \ 914 ((SOURCE) == RCC_CKPERCLKSOURCE_OFF)) 915 /** 916 * @} 917 */ 918 919 920 /** @defgroup RCCEx_STGEN_Clock_Source STGEN Clock Source 921 * @{ 922 */ 923 #define RCC_STGENCLKSOURCE_HSI 0U 924 #define RCC_STGENCLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_0 925 #define RCC_STGENCLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_1 926 927 #define IS_RCC_STGENCLKSOURCE(SOURCE) \ 928 (((SOURCE) == RCC_STGENCLKSOURCE_HSI) || \ 929 ((SOURCE) == RCC_STGENCLKSOURCE_HSE) || \ 930 ((SOURCE) == RCC_STGENCLKSOURCE_OFF)) 931 /** 932 * @} 933 */ 934 935 #if defined(DSI) 936 /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source 937 * @{ 938 */ 939 #define RCC_DSICLKSOURCE_PHY 0U 940 #define RCC_DSICLKSOURCE_PLL4 RCC_DSICKSELR_DSISRC 941 942 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \ 943 (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ 944 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL4)) 945 /** 946 * @} 947 */ 948 #endif /*DSI*/ 949 950 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 951 * @{ 952 */ 953 #define RCC_ADCCLKSOURCE_PLL4 0U 954 #define RCC_ADCCLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_0 955 #define RCC_ADCCLKSOURCE_PLL3 RCC_ADCCKSELR_ADCSRC_1 956 957 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL4) || \ 958 ((SOURCE) == RCC_ADCCLKSOURCE_PER) || \ 959 ((SOURCE) == RCC_ADCCLKSOURCE_PLL3)) 960 /** 961 * @} 962 */ 963 964 965 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 966 * @{ 967 */ 968 #define RCC_LPTIM1CLKSOURCE_PCLK1 0U 969 #define RCC_LPTIM1CLKSOURCE_PLL4 RCC_LPTIM1CKSELR_LPTIM1SRC_0 970 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_LPTIM1CKSELR_LPTIM1SRC_1 971 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0) 972 #define RCC_LPTIM1CLKSOURCE_LSI RCC_LPTIM1CKSELR_LPTIM1SRC_2 973 #define RCC_LPTIM1CLKSOURCE_PER (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0) 974 #define RCC_LPTIM1CLKSOURCE_OFF (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1) 975 976 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) \ 977 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 978 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL4) || \ 979 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ 980 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ 981 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ 982 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PER) || \ 983 ((SOURCE) == RCC_LPTIM1CLKSOURCE_OFF)) 984 /** 985 * @} 986 */ 987 988 /** @defgroup RCCEx_LPTIM23_Clock_Source LPTIM23 Clock Source 989 * @{ 990 */ 991 #define RCC_LPTIM23CLKSOURCE_PCLK3 0U 992 #define RCC_LPTIM23CLKSOURCE_PLL4 RCC_LPTIM23CKSELR_LPTIM23SRC_0 993 #define RCC_LPTIM23CLKSOURCE_PER RCC_LPTIM23CKSELR_LPTIM23SRC_1 994 #define RCC_LPTIM23CLKSOURCE_LSE (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0) 995 #define RCC_LPTIM23CLKSOURCE_LSI RCC_LPTIM23CKSELR_LPTIM23SRC_2 996 #define RCC_LPTIM23CLKSOURCE_OFF (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0) 997 998 999 #define IS_RCC_LPTIM23CLKSOURCE(SOURCE) \ 1000 (((SOURCE) == RCC_LPTIM23CLKSOURCE_PCLK3) || \ 1001 ((SOURCE) == RCC_LPTIM23CLKSOURCE_PLL4) || \ 1002 ((SOURCE) == RCC_LPTIM23CLKSOURCE_PER) || \ 1003 ((SOURCE) == RCC_LPTIM23CLKSOURCE_LSE) || \ 1004 ((SOURCE) == RCC_LPTIM23CLKSOURCE_LSI) || \ 1005 ((SOURCE) == RCC_LPTIM23CLKSOURCE_OFF)) 1006 /** 1007 * @} 1008 */ 1009 1010 /** @defgroup RCCEx_LPTIM45_Clock_Source LPTIM45 Clock Source 1011 * @{ 1012 */ 1013 #define RCC_LPTIM45CLKSOURCE_PCLK3 0U 1014 #define RCC_LPTIM45CLKSOURCE_PLL4 RCC_LPTIM45CKSELR_LPTIM45SRC_0 1015 #define RCC_LPTIM45CLKSOURCE_PLL3 RCC_LPTIM45CKSELR_LPTIM45SRC_1 1016 #define RCC_LPTIM45CLKSOURCE_LSE (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0) 1017 #define RCC_LPTIM45CLKSOURCE_LSI RCC_LPTIM45CKSELR_LPTIM45SRC_2 1018 #define RCC_LPTIM45CLKSOURCE_PER (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0) 1019 #define RCC_LPTIM45CLKSOURCE_OFF (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1) 1020 1021 1022 1023 #define IS_RCC_LPTIM45CLKSOURCE(SOURCE) \ 1024 (((SOURCE) == RCC_LPTIM45CLKSOURCE_PCLK3) || \ 1025 ((SOURCE) == RCC_LPTIM45CLKSOURCE_PLL4) || \ 1026 ((SOURCE) == RCC_LPTIM45CLKSOURCE_PLL3) || \ 1027 ((SOURCE) == RCC_LPTIM45CLKSOURCE_LSE) || \ 1028 ((SOURCE) == RCC_LPTIM45CLKSOURCE_LSI) || \ 1029 ((SOURCE) == RCC_LPTIM45CLKSOURCE_PER) || \ 1030 ((SOURCE) == RCC_LPTIM45CLKSOURCE_OFF)) 1031 /** 1032 * @} 1033 */ 1034 1035 1036 /** @defgroup RCCEx_TIMG1_Prescaler_Selection TIMG1 Prescaler Selection 1037 * @{ 1038 */ 1039 #define RCC_TIMG1PRES_DEACTIVATED 0U 1040 #define RCC_TIMG1PRES_ACTIVATED RCC_TIMG1PRER_TIMG1PRE 1041 1042 #define IS_RCC_TIMG1PRES(PRES) (((PRES) == RCC_TIMG1PRES_DEACTIVATED) || \ 1043 ((PRES) == RCC_TIMG1PRES_ACTIVATED)) 1044 /** 1045 * @} 1046 */ 1047 1048 1049 /** @defgroup RCCEx_TIMG2_Prescaler_Selection TIMG2 Prescaler Selection 1050 * @{ 1051 */ 1052 #define RCC_TIMG2PRES_DEACTIVATED 0U 1053 #define RCC_TIMG2PRES_ACTIVATED RCC_TIMG2PRER_TIMG2PRE 1054 1055 #define IS_RCC_TIMG2PRES(PRES) (((PRES) == RCC_TIMG2PRES_DEACTIVATED) || \ 1056 ((PRES) == RCC_TIMG2PRES_ACTIVATED)) 1057 /** 1058 * @} 1059 */ 1060 1061 1062 /** @defgroup RCCEx_RCC_BootCx RCC BootCx 1063 * @{ 1064 */ 1065 #define RCC_BOOT_C1 RCC_MP_BOOTCR_MPU_BEN 1066 #define RCC_BOOT_C2 RCC_MP_BOOTCR_MCU_BEN 1067 1068 #define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ 1069 ((CORE) == RCC_BOOT_C2) || \ 1070 ((CORE) == (RCC_BOOT_C1 ||RCC_BOOT_C2) )) 1071 /** 1072 * @} 1073 */ 1074 /** 1075 * @} 1076 */ 1077 1078 /* Exported macros -----------------------------------------------------------*/ 1079 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1080 * @{ 1081 */ 1082 /** @brief macro to configure the I2C12 clock (I2C12CLK). 1083 * 1084 * @param __I2C12CLKSource__: specifies the I2C12 clock source. 1085 * This parameter can be one of the following values: 1086 * @arg RCC_I2C12CLKSOURCE_PCLK1: PCLK1 selected as I2C12 clock (default after reset) 1087 * @arg RCC_I2C12CLKSOURCE_PLL4: PLL4_R selected as I2C12 clock 1088 * @arg RCC_I2C12CLKSOURCE_HSI: HSI selected as I2C12 clock 1089 * @arg RCC_I2C12CLKSOURCE_CSI: CSI selected as I2C12 clock 1090 * @retval None 1091 */ 1092 #define __HAL_RCC_I2C12_CONFIG(__I2C12CLKSource__) \ 1093 MODIFY_REG(RCC->I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, (uint32_t)(__I2C12CLKSource__)) 1094 1095 /** @brief macro to get the I2C12 clock source. 1096 * @retval The clock source can be one of the following values: 1097 * @arg RCC_I2C12CLKSOURCE_PCLK1: PCLK1 selected as I2C12 clock 1098 * @arg RCC_I2C12CLKSOURCE_PLL4: PLL4_R selected as I2C12 clock 1099 * @arg RCC_I2C12CLKSOURCE_HSI: HSI selected as I2C12 clock 1100 * @arg RCC_I2C12CLKSOURCE_CSI: CSI selected as I2C12 clock 1101 */ 1102 #define __HAL_RCC_GET_I2C12_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC))) 1103 1104 /** @brief macro to configure the I2C35 clock (I2C35CLK). 1105 * 1106 * @param __I2C35CLKSource__: specifies the I2C35 clock source. 1107 * This parameter can be one of the following values: 1108 * @arg RCC_I2C35CLKSOURCE_PCLK1: PCLK1 selected as I2C35 clock (default after reset) 1109 * @arg RCC_I2C35CLKSOURCE_PLL4: PLL4_R selected as I2C35 clock 1110 * @arg RCC_I2C35CLKSOURCE_HSI: HSI selected as I2C35 clock 1111 * @arg RCC_I2C35CLKSOURCE_CSI: CSI selected as I2C35 clock 1112 * @retval None 1113 */ 1114 #define __HAL_RCC_I2C35_CONFIG(__I2C35CLKSource__) \ 1115 MODIFY_REG(RCC->I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, (uint32_t)(__I2C35CLKSource__)) 1116 1117 /** @brief macro to get the I2C35 clock source. 1118 * @retval The clock source can be one of the following values: 1119 * @arg RCC_I2C35CLKSOURCE_PCLK1: PCLK1 selected as I2C35 clock 1120 * @arg RCC_I2C35CLKSOURCE_PLL4: PLL4_R selected as I2C35 clock 1121 * @arg RCC_I2C35CLKSOURCE_HSI: HSI selected as I2C35 clock 1122 * @arg RCC_I2C35CLKSOURCE_CSI: CSI selected as I2C35 clock 1123 */ 1124 #define __HAL_RCC_GET_I2C35_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC))) 1125 1126 /** @brief macro to configure the I2C46 clock (I2C46CLK). 1127 * 1128 * @param __I2C46CLKSource__: specifies the I2C46 clock source. 1129 * This parameter can be one of the following values: 1130 * @arg RCC_I2C46CLKSOURCE_PCLK5: PCLK5 selected as I2C46 clock (default after reset) 1131 * @arg RCC_I2C46CLKSOURCE_PLL3: PLL3_Q selected as I2C46 clock 1132 * @arg RCC_I2C46CLKSOURCE_HSI: HSI selected as I2C46 clock 1133 * @arg RCC_I2C46CLKSOURCE_CSI: CSI selected as I2C46 clock 1134 * @retval None 1135 */ 1136 #define __HAL_RCC_I2C46_CONFIG(__I2C46CLKSource__) \ 1137 MODIFY_REG(RCC->I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, (uint32_t)(__I2C46CLKSource__)) 1138 1139 /** @brief macro to get the I2C46 clock source. 1140 * @retval The clock source can be one of the following values: 1141 * @arg RCC_I2C46CLKSOURCE_PCLK5: PCLK5 selected as I2C46 clock 1142 * @arg RCC_I2C46CLKSOURCE_PLL3: PLL3_Q selected as I2C46 clock 1143 * @arg RCC_I2C46CLKSOURCE_HSI: HSI selected as I2C46 clock 1144 * @arg RCC_I2C46CLKSOURCE_CSI: CSI selected as I2C46 clock 1145 */ 1146 #define __HAL_RCC_GET_I2C46_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC))) 1147 1148 /** 1149 * @brief Macro to Configure the SAI1 clock source. 1150 * @param __RCC_SAI1CLKSource__: defines the SAI1 clock source. 1151 * This parameter can be one of the following values: 1152 * @arg RCC_SAI1CLKSOURCE_PLL4: SAI1 clock = PLL4Q 1153 * @arg RCC_SAI1CLKSOURCE_PLL3_Q: SAI1 clock = PLL3Q 1154 * @arg RCC_SAI1CLKSOURCE_I2SCKIN: SAI1 clock = I2SCKIN 1155 * @arg RCC_SAI1CLKSOURCE_PER: SAI1 clock = PER 1156 * @arg RCC_SAI1CLKSOURCE_PLL3_R: SAI1 clock = PLL3R 1157 * @retval None 1158 */ 1159 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ ) \ 1160 MODIFY_REG(RCC->SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, (uint32_t)(__RCC_SAI1CLKSource__)) 1161 1162 /** @brief Macro to get the SAI1 clock source. 1163 * @retval The clock source can be one of the following values: 1164 * @arg RCC_SAI1CLKSOURCE_PLL4: SAI1 clock = PLL4Q 1165 * @arg RCC_SAI1CLKSOURCE_PLL3_Q: SAI1 clock = PLL3Q 1166 * @arg RCC_SAI1CLKSOURCE_I2SCKIN: SAI1 clock = I2SCKIN 1167 * @arg RCC_SAI1CLKSOURCE_PER: SAI1 clock = PER 1168 * @arg RCC_SAI1CLKSOURCE_PLL3_R: SAI1 clock = PLL3R 1169 */ 1170 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC))) 1171 1172 1173 /** 1174 * @brief Macro to Configure the SAI2 clock source. 1175 * @param __RCC_SAI2CLKSource__: defines the SAI2 clock source. 1176 * This parameter can be one of the following values: 1177 * @arg RCC_SAI2CLKSOURCE_PLL4: SAI2 clock = PLL4Q 1178 * @arg RCC_SAI2CLKSOURCE_PLL3_Q: SAI2 clock = PLL3Q 1179 * @arg RCC_SAI2CLKSOURCE_I2SCKIN: SAI2 clock = I2SCKIN 1180 * @arg RCC_SAI2CLKSOURCE_PER: SAI2 clock = PER 1181 * @arg RCC_SAI2CLKSOURCE_SPDIF: SAI2 clock = SPDIF_CK_SYMB 1182 * @arg RCC_SAI2CLKSOURCE_PLL3_R: SAI2 clock = PLL3R 1183 * @retval None 1184 */ 1185 #define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ ) \ 1186 MODIFY_REG(RCC->SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (uint32_t)(__RCC_SAI2CLKSource__)) 1187 1188 /** @brief Macro to get the SAI2 clock source. 1189 * @retval The clock source can be one of the following values: 1190 * @arg RCC_SAI2CLKSOURCE_PLL4: SAI2 clock = PLL4Q 1191 * @arg RCC_SAI2CLKSOURCE_PLL3_Q: SAI2 clock = PLL3Q 1192 * @arg RCC_SAI2CLKSOURCE_I2SCKIN: SAI2 clock = I2SCKIN 1193 * @arg RCC_SAI2CLKSOURCE_PER: SAI2 clock = PER 1194 * @arg RCC_SAI2CLKSOURCE_SPDIF: SAI2 clock = SPDIF_CK_SYMB 1195 * @arg RCC_SAI2CLKSOURCE_PLL3_R: SAI2 clock = PLL3R 1196 */ 1197 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC))) 1198 1199 1200 /** 1201 * @brief Macro to Configure the SAI3 clock source. 1202 * @param __RCC_SAI3CLKSource__: defines the SAI3 clock source. 1203 * This parameter can be one of the following values: 1204 * @arg RCC_SAI3CLKSOURCE_PLL4: SAI3 clock = PLL4Q 1205 * @arg RCC_SAI3CLKSOURCE_PLL3_Q: SAI3 clock = PLL3Q 1206 * @arg RCC_SAI3CLKSOURCE_I2SCKIN: SAI3 clock = I2SCKIN 1207 * @arg RCC_SAI3CLKSOURCE_PER: SAI3 clock = PER 1208 * @arg RCC_SAI3CLKSOURCE_PLL3_R: SAI3 clock = PLL3R 1209 * @retval None 1210 */ 1211 #define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ ) \ 1212 MODIFY_REG(RCC->SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, (uint32_t)(__RCC_SAI3CLKSource__)) 1213 1214 /** @brief Macro to get the SAI3 clock source. 1215 * @retval The clock source can be one of the following values: 1216 * @arg RCC_SAI3CLKSOURCE_PLL4: SAI3 clock = PLL4Q 1217 * @arg RCC_SAI3CLKSOURCE_PLL3_Q: SAI3 clock = PLL3Q 1218 * @arg RCC_SAI3CLKSOURCE_I2SCKIN: SAI3 clock = I2SCKIN 1219 * @arg RCC_SAI3CLKSOURCE_PER: SAI3 clock = PER 1220 * @arg RCC_SAI3CLKSOURCE_PLL3_R: SAI3 clock = PLL3R 1221 */ 1222 #define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC))) 1223 1224 1225 /** 1226 * @brief Macro to Configure the SAI4 clock source. 1227 * @param __RCC_SAI4CLKSource__: defines the SAI4 clock source. 1228 * This parameter can be one of the following values: 1229 * @arg RCC_SAI4CLKSOURCE_PLL4: SAI4 clock = PLL4Q 1230 * @arg RCC_SAI4CLKSOURCE_PLL3_Q: SAI4 clock = PLL3Q 1231 * @arg RCC_SAI4CLKSOURCE_I2SCKIN: SAI4 clock = I2SCKIN 1232 * @arg RCC_SAI4CLKSOURCE_PER: SAI4 clock = PER 1233 * @arg RCC_SAI4CLKSOURCE_PLL3_R: SAI4 clock = PLL3R 1234 * @retval None 1235 */ 1236 #define __HAL_RCC_SAI4_CONFIG(__RCC_SAI4CLKSource__ ) \ 1237 MODIFY_REG(RCC->SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, (uint32_t)(__RCC_SAI4CLKSource__)) 1238 1239 /** @brief Macro to get the SAI4 clock source. 1240 * @retval The clock source can be one of the following values: 1241 * @arg RCC_SAI4CLKSOURCE_PLL4: SAI4 clock = PLL4Q 1242 * @arg RCC_SAI4CLKSOURCE_PLL3_Q: SAI4 clock = PLL3Q 1243 * @arg RCC_SAI4CLKSOURCE_I2SCKIN: SAI4 clock = I2SCKIN 1244 * @arg RCC_SAI4CLKSOURCE_PER: SAI4 clock = PER 1245 * @arg RCC_SAI4CLKSOURCE_PLL3_R: SAI4 clock = PLL3R 1246 */ 1247 #define __HAL_RCC_GET_SAI4_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC))) 1248 1249 1250 /** 1251 * @brief Macro to Configure the SPI/I2S1 clock source. 1252 * @param __RCC_SPI1CLKSource__: defines the SPI/I2S1 clock source. 1253 * This parameter can be one of the following values: 1254 * @arg RCC_SPI1CLKSOURCE_PLL4: SPI1 clock = PLL4P 1255 * @arg RCC_SPI1CLKSOURCE_PLL3_Q: SPI1 clock = PLL3Q 1256 * @arg RCC_SPI1CLKSOURCE_I2SCKIN: SPI1 clock = I2SCKIN 1257 * @arg RCC_SPI1CLKSOURCE_PER: SPI1 clock = PER 1258 * @arg RCC_SPI1CLKSOURCE_PLL3_R: SPI1 clock = PLL3R 1259 * @retval None 1260 */ 1261 #define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__) \ 1262 MODIFY_REG(RCC->SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, (uint32_t)(__RCC_SPI1CLKSource__)) 1263 1264 /** @brief Macro to get the SPI/I2S1 clock source. 1265 * @retval The clock source can be one of the following values: 1266 * @arg RCC_SPI1CLKSOURCE_PLL4: SPI1 clock = PLL4P 1267 * @arg RCC_SPI1CLKSOURCE_PLL3_Q: SPI1 clock = PLL3Q 1268 * @arg RCC_SPI1CLKSOURCE_I2SCKIN: SPI1 clock = I2SCKIN 1269 * @arg RCC_SPI1CLKSOURCE_PER: SPI1 clock = PER 1270 * @arg RCC_SPI1CLKSOURCE_PLL3_R: SPI1 clock = PLL3R 1271 */ 1272 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC))) 1273 1274 1275 /** 1276 * @brief Macro to Configure the SPI/I2S2,3 clock source. 1277 * @param __RCC_SPI23CLKSource__: defines the SPI/I2S2,3 clock source. 1278 * This parameter can be one of the following values: 1279 * @arg RCC_SPI23CLKSOURCE_PLL4: SPI23 clock = PLL4P 1280 * @arg RCC_SPI23CLKSOURCE_PLL3_Q: SPI23 clock = PLL3Q 1281 * @arg RCC_SPI23CLKSOURCE_I2SCKIN: SPI23 clock = I2SCKIN 1282 * @arg RCC_SPI23CLKSOURCE_PER: SPI23 clock = PER 1283 * @arg RCC_SPI23CLKSOURCE_PLL3_R: SPI23 clock = PLL3R 1284 * @retval None 1285 */ 1286 #define __HAL_RCC_SPI23_CONFIG(__RCC_SPI23CLKSource__ ) \ 1287 MODIFY_REG(RCC->SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, (uint32_t)(__RCC_SPI23CLKSource__)) 1288 1289 /** @brief Macro to get the SPI/I2S2,3 clock source. 1290 * @retval The clock source can be one of the following values: 1291 * @arg RCC_SPI23CLKSOURCE_PLL4: SPI23 clock = PLL4P 1292 * @arg RCC_SPI23CLKSOURCE_PLL3_Q: SPI23 clock = PLL3Q 1293 * @arg RCC_SPI23CLKSOURCE_I2SCKIN: SPI23 clock = I2SCKIN 1294 * @arg RCC_SPI23CLKSOURCE_PER: SPI23 clock = PER 1295 * @arg RCC_SPI23CLKSOURCE_PLL3_R: SPI23 clock = PLL3R 1296 */ 1297 #define __HAL_RCC_GET_SPI23_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC))) 1298 1299 /** 1300 * @brief Macro to Configure the SPI45 clock source. 1301 * @param __RCC_SPI45CLKSource__: defines the SPI45 clock source. 1302 * This parameter can be one of the following values: 1303 * @arg RCC_SPI45CLKSOURCE_PCLK2: SPI45 clock = PCLK2 1304 * @arg RCC_SPI45CLKSOURCE_PLL4: SPI45 clock = PLL4Q 1305 * @arg RCC_SPI45CLKSOURCE_HSI: SPI45 clock = HSI 1306 * @arg RCC_SPI45CLKSOURCE_CSI: SPI45 clock = CSI 1307 * @arg RCC_SPI45CLKSOURCE_HSE: SPI45 clock = HSE 1308 * @retval None 1309 */ 1310 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ ) \ 1311 MODIFY_REG(RCC->SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, (uint32_t)(__RCC_SPI45CLKSource__)) 1312 1313 /** @brief Macro to get the SPI45 clock source. 1314 * @retval The clock source can be one of the following values: 1315 * @arg RCC_SPI45CLKSOURCE_PCLK2: SPI45 clock = PCLK2 1316 * @arg RCC_SPI45CLKSOURCE_PLL4: SPI45 clock = PLL4Q 1317 * @arg RCC_SPI45CLKSOURCE_HSI: SPI45 clock = HSI 1318 * @arg RCC_SPI45CLKSOURCE_CSI: SPI45 clock = CSI 1319 * @arg RCC_SPI45CLKSOURCE_HSE: SPI45 clock = HSE 1320 */ 1321 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC))) 1322 1323 /** 1324 * @brief Macro to Configure the SPI6 clock source. 1325 * @param __RCC_SPI6CLKSource__: defines the SPI6 clock source. 1326 * This parameter can be one of the following values: 1327 * @arg RCC_SPI6CLKSOURCE_PCLK5: SPI6 clock = PCLK5 1328 * @arg RCC_SPI6CLKSOURCE_PLL4: SPI6 clock = PLL4Q 1329 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 1330 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 1331 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 1332 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3Q 1333 * @retval None 1334 */ 1335 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ ) \ 1336 MODIFY_REG(RCC->SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (uint32_t)(__RCC_SPI6CLKSource__)) 1337 1338 /** @brief Macro to get the SPI6 clock source. 1339 * @retval The clock source can be one of the following values: 1340 * @arg RCC_SPI6CLKSOURCE_PCLK5: SPI6 clock = PCLK5 1341 * @arg RCC_SPI6CLKSOURCE_PLL4: SPI6 clock = PLL4Q 1342 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 1343 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 1344 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 1345 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3Q 1346 */ 1347 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC))) 1348 1349 1350 /** @brief macro to configure the USART1 clock (USART1CLK). 1351 * 1352 * @param __USART1CLKSource__: specifies the USART1 clock source. 1353 * This parameter can be one of the following values: 1354 * @arg RCC_USART1CLKSOURCE_PCLK5: PCLK5 Clock selected as USART1 clock (default after reset) 1355 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock USART1 1356 * @arg RCC_USART1CLKSOURCE_HSI: HSI Clock selected as USART1 clock USART1 1357 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock USART1 1358 * @arg RCC_USART1CLKSOURCE_PLL4: PLL4_Q Clock selected as USART1 clock USART1 1359 * @arg RCC_USART1CLKSOURCE_HSE: HSE Clock selected as USART1 clock USART1 1360 * @retval None 1361 */ 1362 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ 1363 MODIFY_REG(RCC->UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (uint32_t)(__USART1CLKSource__)) 1364 1365 /** @brief macro to get the USART1 clock source. 1366 * @retval The clock source can be one of the following values: 1367 * @arg RCC_USART1CLKSOURCE_PCLK5: PCLK5 Clock selected as USART1 clock (default after reset) 1368 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 1369 * @arg RCC_USART1CLKSOURCE_HSI: HSI Clock selected as USART1 clock 1370 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 1371 * @arg RCC_USART1CLKSOURCE_PLL4: PLL4_Q Clock selected as USART1 clock 1372 * @arg RCC_USART1CLKSOURCE_HSE: HSE Clock selected as USART1 clock 1373 */ 1374 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->UART1CKSELR, RCC_UART1CKSELR_UART1SRC))) 1375 1376 /** @brief macro to configure the UART24 clock (UART24CLK). 1377 * 1378 * @param __UART24CLKSource__: specifies the UART24 clock source. 1379 * This parameter can be one of the following values: 1380 * @arg RCC_UART24CLKSOURCE_PCLK1: PCLK1 Clock selected as UART24 1381 * clock (default after reset) 1382 * @arg RCC_UART24CLKSOURCE_PLL4: PLL4_Q Clock selected as UART24 clock 1383 * @arg RCC_UART24CLKSOURCE_HSI: HSI selected as UART24 clock 1384 * @arg RCC_UART24CLKSOURCE_CSI: CSI Clock selected as UART24 clock 1385 * @arg RCC_UART24CLKSOURCE_HSE: HSE selected as UART24 clock 1386 * @retval None 1387 */ 1388 #define __HAL_RCC_UART24_CONFIG(__UART24CLKSource__) \ 1389 MODIFY_REG(RCC->UART24CKSELR, RCC_UART24CKSELR_UART24SRC, (uint32_t)(__UART24CLKSource__)) 1390 1391 /** @brief macro to get the UART24 clock source. 1392 * @retval The clock source can be one of the following values: 1393 * @arg RCC_UART24CLKSOURCE_PCLK1: PCLK1 Clock selected as UART24 clock 1394 * @arg RCC_UART24CLKSOURCE_PLL4: PLL4_Q Clock selected as UART24 clock 1395 * @arg RCC_UART24CLKSOURCE_HSI: HSI selected as UART24 clock 1396 * @arg RCC_UART24CLKSOURCE_CSI: CSI Clock selected as UART24 clock 1397 * @arg RCC_UART24CLKSOURCE_HSE: HSE selected as UART24 clock 1398 */ 1399 #define __HAL_RCC_GET_UART24_SOURCE() ((uint32_t)(READ_BIT(RCC->UART24CKSELR, RCC_UART24CKSELR_UART24SRC))) 1400 1401 1402 /** @brief macro to configure the UART35 clock (UART35CLK). 1403 * 1404 * @param __UART35CLKSource__: specifies the UART35 clock source. 1405 * This parameter can be one of the following values: 1406 * @arg RCC_UART35CLKSOURCE_PCLK1: PCLK1 Clock selected as UART35 1407 * clock (default after reset) 1408 * @arg RCC_UART35CLKSOURCE_PLL4: PLL4_Q Clock selected as UART35 clock 1409 * @arg RCC_UART35CLKSOURCE_HSI: HSI selected as UART35 clock 1410 * @arg RCC_UART35CLKSOURCE_CSI: CSI Clock selected as UART35 clock 1411 * @arg RCC_UART35CLKSOURCE_HSE: HSE selected as UART35 clock 1412 * @retval None 1413 */ 1414 #define __HAL_RCC_UART35_CONFIG(__UART35CLKSource__) \ 1415 MODIFY_REG(RCC->UART35CKSELR, RCC_UART35CKSELR_UART35SRC, (uint32_t)(__UART35CLKSource__)) 1416 1417 /** @brief macro to get the UART35 clock source. 1418 * @retval The clock source can be one of the following values: 1419 * @arg RCC_UART35CLKSOURCE_PCLK1: PCLK1 Clock selected as UART35 clock 1420 * @arg RCC_UART35CLKSOURCE_PLL4: PLL4_Q Clock selected as UART35 clock 1421 * @arg RCC_UART35CLKSOURCE_HSI: HSI selected as UART35 clock 1422 * @arg RCC_UART35CLKSOURCE_CSI: CSI Clock selected as UART35 clock 1423 * @arg RCC_UART35CLKSOURCE_HSE: HSE selected as UART35 clock 1424 */ 1425 #define __HAL_RCC_GET_UART35_SOURCE() ((uint32_t)(READ_BIT(RCC->UART35CKSELR, RCC_UART35CKSELR_UART35SRC))) 1426 1427 1428 /** @brief macro to configure the USART6 clock (USART6CLK). 1429 * 1430 * @param __USART6CLKSource__: specifies the USART6 clock source. 1431 * This parameter can be one of the following values: 1432 * @arg RCC_USART6CLKSOURCE_PCLK2: PCLK2 Clock selected as USART6 clock (default after reset) 1433 * @arg RCC_USART6CLKSOURCE_PLL4: PLL4_Q Clock selected as USART6 clock 1434 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 1435 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 1436 * @arg RCC_USART6CLKSOURCE_HSE: HSE selected as USART6 clock 1437 * @retval None 1438 */ 1439 #define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \ 1440 MODIFY_REG(RCC->UART6CKSELR, RCC_UART6CKSELR_UART6SRC, (uint32_t)(__USART6CLKSource__)) 1441 1442 /** @brief macro to get the USART6 clock source. 1443 * @retval The clock source can be one of the following values: 1444 * @arg RCC_USART6CLKSOURCE_PCLK2: PCLK2 Clock selected as USART6 clock 1445 * @arg RCC_USART6CLKSOURCE_PLL4: PLL4_Q Clock selected as USART6 clock 1446 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 1447 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 1448 * @arg RCC_USART6CLKSOURCE_HSE: HSE selected as USART6 clock 1449 */ 1450 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->UART6CKSELR, RCC_UART6CKSELR_UART6SRC))) 1451 1452 /** @brief macro to configure the UART78clock (UART78CLK). 1453 * 1454 * @param __UART78CLKSource__: specifies the UART78 clock source. 1455 * This parameter can be one of the following values: 1456 * @arg RCC_UART78CLKSOURCE_PCLK1: PCLK1 Clock selected as UART78 clock (default after reset) 1457 * @arg RCC_UART78CLKSOURCE_PLL4: PLL4_Q Clock selected as UART78 clock 1458 * @arg RCC_UART78CLKSOURCE_HSI: HSI selected as UART78 clock 1459 * @arg RCC_UART78CLKSOURCE_CSI: CSI Clock selected as UART78 clock 1460 * @arg RCC_UART78CLKSOURCE_HSE: HSE selected as UART78 clock 1461 * @retval None 1462 */ 1463 #define __HAL_RCC_UART78_CONFIG(__UART78CLKSource__) \ 1464 MODIFY_REG(RCC->UART78CKSELR, RCC_UART78CKSELR_UART78SRC, (uint32_t)(__UART78CLKSource__)) 1465 1466 /** @brief macro to get the UART78 clock source. 1467 * @retval The clock source can be one of the following values: 1468 * @arg RCC_UART78CLKSOURCE_PCLK1: PCLK1 Clock selected as UART78 clock 1469 * @arg RCC_UART78CLKSOURCE_PLL4: PLL4_Q Clock selected as UART78 clock 1470 * @arg RCC_UART78CLKSOURCE_HSI: HSI selected as UART78 clock 1471 * @arg RCC_UART78CLKSOURCE_CSI: CSI Clock selected as UART78 clock 1472 * @arg RCC_UART78CLKSOURCE_HSE: HSE selected as UART78 clock 1473 */ 1474 #define __HAL_RCC_GET_UART78_SOURCE() ((uint32_t)(READ_BIT(RCC->UART78CKSELR, RCC_UART78CKSELR_UART78SRC))) 1475 1476 /** @brief macro to configure the SDMMC12 clock (SDMMC12CLK). 1477 * 1478 * @param __SDMMC12CLKSource__: specifies the SDMMC12 clock source. 1479 * This parameter can be one of the following values: 1480 * @arg RCC_SDMMC12CLKSOURCE_HCLK6: HCLK6 Clock selected as SDMMC12 clock (default after reset) 1481 * @arg RCC_SDMMC12CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC12 clock 1482 * @arg RCC_SDMMC12CLKSOURCE_PLL4: PLL4_P selected as SDMMC12 clock 1483 * @arg RCC_SDMMC12CLKSOURCE_HSI: HSI selected as SDMMC12 clock 1484 * @retval None 1485 */ 1486 #define __HAL_RCC_SDMMC12_CONFIG(__SDMMC12CLKSource__) \ 1487 MODIFY_REG(RCC->SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, (uint32_t)(__SDMMC12CLKSource__)) 1488 1489 /** @brief macro to get the SDMMC12 clock source. 1490 * @retval The clock source can be one of the following values: 1491 * @arg RCC_SDMMC12CLKSOURCE_HCLK6: HCLK6 Clock selected as SDMMC12 clock (default after reset) 1492 * @arg RCC_SDMMC12CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC12 clock 1493 * @arg RCC_SDMMC12CLKSOURCE_PLL4: PLL4_P selected as SDMMC12 clock 1494 * @arg RCC_SDMMC12CLKSOURCE_HSI: HSI selected as SDMMC12 clock 1495 */ 1496 #define __HAL_RCC_GET_SDMMC12_SOURCE() ((uint32_t)(READ_BIT(RCC->SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC))) 1497 1498 1499 /** @brief macro to configure the SDMMC3 clock (SDMMC3CLK). 1500 * 1501 * @param __SDMMC3CLKSource__: specifies the SDMMC3 clock source. 1502 * This parameter can be one of the following values: 1503 * @arg RCC_SDMMC3CLKSOURCE_HCLK2: HCLK2 Clock selected as SDMMC3 clock (default after reset) 1504 * @arg RCC_SDMMC3CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC3 clock 1505 * @arg RCC_SDMMC3CLKSOURCE_PLL4: PLL4_P selected as SDMMC3 clock 1506 * @arg RCC_SDMMC3CLKSOURCE_HSI: HSI selected as SDMMC3 clock 1507 * 1508 * @retval None 1509 */ 1510 #define __HAL_RCC_SDMMC3_CONFIG(__SDMMC3CLKSource__) \ 1511 MODIFY_REG(RCC->SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, (uint32_t)(__SDMMC3CLKSource__)) 1512 1513 /** @brief macro to get the SDMMC3 clock source. 1514 * @retval The clock source can be one of the following values: 1515 * @arg RCC_SDMMC3CLKSOURCE_HCLK2: HCLK2 Clock selected as SDMMC3 clock (default after reset) 1516 * @arg RCC_SDMMC3CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC3 clock 1517 * @arg RCC_SDMMC3CLKSOURCE_PLL4: PLL4_P selected as SDMMC3 clock 1518 * @arg RCC_SDMMC3CLKSOURCE_HSI: HSI selected as SDMMC3 clock 1519 */ 1520 #define __HAL_RCC_GET_SDMMC3_SOURCE() ((uint32_t)(READ_BIT(RCC->SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC))) 1521 1522 1523 /** @brief macro to configure the ETH clock (ETHCLK). 1524 * 1525 * @param __ETHCLKSource__: specifies the ETH clock source. 1526 * This parameter can be one of the following values: 1527 * @arg RCC_ETHCLKSOURCE_PLL4: PLL4_P selected as ETH clock (default after reset) 1528 * @arg RCC_ETHCLKSOURCE_PLL3: PLL3_Q Clock selected as ETH clock 1529 * @arg RCC_ETHCLKSOURCE_OFF: the kernel clock is disabled 1530 * @retval None 1531 */ 1532 #define __HAL_RCC_ETH_CONFIG(__ETHCLKSource__) \ 1533 MODIFY_REG(RCC->ETHCKSELR, RCC_ETHCKSELR_ETHSRC, (uint32_t)(__ETHCLKSource__)) 1534 1535 /** @brief macro to get the ETH clock source. 1536 * @retval The clock source can be one of the following values: 1537 * @arg RCC_ETHCLKSOURCE_PLL4: PLL4_P selected as ETH clock (default after reset) 1538 * @arg RCC_ETHCLKSOURCE_PLL3: PLL3_Q Clock selected as ETH clock 1539 * @arg RCC_ETHCLKSOURCE_OFF: the kernel clock is disabled 1540 */ 1541 #define __HAL_RCC_GET_ETH_SOURCE() ((uint32_t)(READ_BIT(RCC->ETHCKSELR, RCC_ETHCKSELR_ETHSRC))) 1542 1543 1544 /** @brief macro to configure the QSPI clock (QSPICLK). 1545 * 1546 * @param __QSPICLKSource__: specifies the QSPI clock source. 1547 * This parameter can be one of the following values: 1548 * @arg RCC_QSPICLKSOURCE_ACLK: ACLK Clock selected as QSPI clock (default after reset) 1549 * @arg RCC_QSPICLKSOURCE_PLL3: PLL3_R Clock selected as QSPI clock 1550 * @arg RCC_QSPICLKSOURCE_PLL4: PLL4_P selected as QSPI clock 1551 * @arg RCC_QSPICLKSOURCE_PER: PER selected as QSPI clock 1552 * @retval None 1553 */ 1554 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ 1555 MODIFY_REG(RCC->QSPICKSELR, RCC_QSPICKSELR_QSPISRC, (uint32_t)(__QSPICLKSource__)) 1556 1557 /** @brief macro to get the QSPI clock source. 1558 * @retval The clock source can be one of the following values: 1559 * @arg RCC_QSPICLKSOURCE_ACLK: ACLK Clock selected as QSPI clock (default after reset) 1560 * @arg RCC_QSPICLKSOURCE_PLL3: PLL3_R Clock selected as QSPI clock 1561 * @arg RCC_QSPICLKSOURCE_PLL4: PLL4_P selected as QSPI clock 1562 * @arg RCC_QSPICLKSOURCE_PER: PER selected as QSPI clock 1563 */ 1564 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->QSPICKSELR, RCC_QSPICKSELR_QSPISRC))) 1565 1566 1567 /** @brief macro to configure the FMC clock (FMCCLK). 1568 * 1569 * @param __FMCCLKSource__: specifies the FMC clock source. 1570 * This parameter can be one of the following values: 1571 * @arg RCC_FMCCLKSOURCE_ACLK: ACLK Clock selected as FMC clock (default after reset) 1572 * @arg RCC_FMCCLKSOURCE_PLL3: PLL3_R Clock selected as FMC clock 1573 * @arg RCC_FMCCLKSOURCE_PLL4: PLL4_P selected as FMC clock 1574 * @arg RCC_FMCCLKSOURCE_PER: PER selected as FMC clock 1575 * @retval None 1576 */ 1577 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 1578 MODIFY_REG(RCC->FMCCKSELR, RCC_FMCCKSELR_FMCSRC, (uint32_t)(__FMCCLKSource__)) 1579 1580 /** @brief macro to get the FMC clock source. 1581 * @retval The clock source can be one of the following values: 1582 * @arg RCC_FMCCLKSOURCE_ACLK: ACLK Clock selected as FMC clock (default after reset) 1583 * @arg RCC_FMCCLKSOURCE_PLL3: PLL3_R Clock selected as FMC clock 1584 * @arg RCC_FMCCLKSOURCE_PLL4: PLL4_P selected as FMC clock 1585 * @arg RCC_FMCCLKSOURCE_PER: PER selected as FMC clock 1586 */ 1587 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->FMCCKSELR, RCC_FMCCKSELR_FMCSRC))) 1588 1589 #if defined(FDCAN1) 1590 /** @brief macro to configure the FDCAN clock (FDCANCLK). 1591 * 1592 * @param __FDCANCLKSource__: specifies the FDCAN clock source. 1593 * This parameter can be one of the following values: 1594 * @arg RCC_FDCANCLKSOURCE_HSE: HSE Clock selected as FDCAN clock (default after reset) 1595 * @arg RCC_FDCANCLKSOURCE_PLL3: PLL3_Q Clock selected as FDCAN clock 1596 * @arg RCC_FDCANCLKSOURCE_PLL4_Q: PLL4_Q selected as FDCAN clock 1597 * @arg RCC_FDCANCLKSOURCE_PLL4_R: PLL4_R selected as FDCAN clock 1598 * @retval None 1599 */ 1600 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 1601 MODIFY_REG(RCC->FDCANCKSELR, RCC_FDCANCKSELR_FDCANSRC, (uint32_t)(__FDCANCLKSource__)) 1602 1603 /** @brief macro to get the FDCAN clock source. 1604 * @retval The clock source can be one of the following values: 1605 * @arg RCC_FDCANCLKSOURCE_HSE: HSE Clock selected as FDCAN clock (default after reset) 1606 * @arg RCC_FDCANCLKSOURCE_PLL3: PLL3_Q Clock selected as FDCAN clock 1607 * @arg RCC_FDCANCLKSOURCE_PLL4_Q: PLL4_Q selected as FDCAN clock 1608 * @arg RCC_FDCANCLKSOURCE_PLL4_R: PLL4_R selected as FDCAN clock 1609 */ 1610 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->FDCANCKSELR, RCC_FDCANCKSELR_FDCANSRC))) 1611 #endif /*FDCAN1*/ 1612 1613 /** @brief macro to configure the SPDIFRX clock (SPDIFCLK). 1614 * 1615 * @param __SPDIFCLKSource__: specifies the SPDIF clock source. 1616 * This parameter can be one of the following values: 1617 * @arg RCC_SPDIFRXCLKSOURCE_PLL4: PLL4_P Clock selected as SPDIF clock (default after reset) 1618 * @arg RCC_SPDIFRXCLKSOURCE_PLL3: PLL3_Q Clock selected as SPDIF clock 1619 * @arg RCC_SPDIFRXCLKSOURCE_HSI: HSI selected as SPDIF clock 1620 * @retval None 1621 */ 1622 #define __HAL_RCC_SPDIFRX_CONFIG(__SPDIFCLKSource__) \ 1623 MODIFY_REG(RCC->SPDIFCKSELR, RCC_SPDIFCKSELR_SPDIFSRC, (uint32_t)(__SPDIFCLKSource__)) 1624 1625 /** @brief macro to get the SPDIFRX clock source. 1626 * @retval The clock source can be one of the following values: 1627 * @arg RCC_SPDIFRXCLKSOURCE_PLL4: PLL4_P Clock selected as SPDIF clock (default after reset) 1628 * @arg RCC_SPDIFRXCLKSOURCE_PLL3: PLL3_Q Clock selected as SPDIF clock 1629 * @arg RCC_SPDIFRXCLKSOURCE_HSI: HSI selected as SPDIF clock 1630 */ 1631 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->SPDIFCKSELR, RCC_SPDIFCKSELR_SPDIFSRC))) 1632 1633 1634 /** @brief macro to configure the CEC clock (CECCLK). 1635 * 1636 * @param __CECCLKSource__: specifies the CEC clock source. 1637 * This parameter can be one of the following values: 1638 * @arg RCC_CECCLKSOURCE_LSE: LSE Clock selected as CEC clock (default after reset) 1639 * @arg RCC_CECCLKSOURCE_LSI: LSI Clock selected as CEC clock 1640 * @arg RCC_CECCLKSOURCE_CSI122: CSI/122 Clock selected as CEC clock 1641 * @retval None 1642 */ 1643 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 1644 MODIFY_REG(RCC->CECCKSELR, RCC_CECCKSELR_CECSRC, (uint32_t)(__CECCLKSource__)) 1645 1646 /** @brief macro to get the CEC clock source. 1647 * @retval The clock source can be one of the following values: 1648 * @arg RCC_CECCLKSOURCE_LSE: LSE Clock selected as CEC clock (default after reset) 1649 * @arg RCC_CECCLKSOURCE_LSI: LSI Clock selected as CEC clock 1650 * @arg RCC_CECCLKSOURCE_CSI122: CSI/122 Clock selected as CEC clock 1651 */ 1652 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CECCKSELR, RCC_CECCKSELR_CECSRC))) 1653 1654 1655 /** @brief macro to configure the USB PHY clock (USBPHYCLK). 1656 * 1657 * @param __USBPHYCLKSource__: specifies the USB PHY clock source. 1658 * This parameter can be one of the following values: 1659 * @arg RCC_USBPHYCLKSOURCE_HSE: HSE_KER Clock selected as USB PHY clock (default after reset) 1660 * @arg RCC_USBPHYCLKSOURCE_PLL4: PLL4_R Clock selected as USB PHY clock 1661 * @arg RCC_USBPHYCLKSOURCE_HSE2: HSE_KER/2 Clock selected as USB PHY clock 1662 * @retval None 1663 */ 1664 #define __HAL_RCC_USBPHY_CONFIG(__USBPHYCLKSource__) \ 1665 MODIFY_REG(RCC->USBCKSELR, RCC_USBCKSELR_USBPHYSRC, (uint32_t)(__USBPHYCLKSource__)) 1666 1667 /** @brief macro to get the USB PHY PLL clock source. 1668 * @retval The clock source can be one of the following values: 1669 * @arg RCC_USBPHYCLKSOURCE_HSE: HSE_KER Clock selected as USB PHY clock (default after reset) 1670 * @arg RCC_USBPHYCLKSOURCE_PLL4: PLL4_R Clock selected as USB PHY clock 1671 * @arg RCC_USBPHYCLKSOURCE_HSE2: HSE_KER/2 Clock selected as USB PHY clock 1672 */ 1673 #define __HAL_RCC_GET_USBPHY_SOURCE() ((uint32_t)(READ_BIT(RCC->USBCKSELR, RCC_USBCKSELR_USBPHYSRC))) 1674 1675 1676 /** @brief macro to configure the USB OTG clock (USBOCLK). 1677 * 1678 * @param __USBOCLKSource__: specifies the USB OTG clock source. 1679 * This parameter can be one of the following values: 1680 * @arg RCC_USBOCLKSOURCE_PLL4: PLL4_R Clock selected as USB OTG clock (default after reset) 1681 * @arg RCC_USBOCLKSOURCE_PHY: USB PHY Clock selected as USB OTG clock 1682 * @retval None 1683 */ 1684 #define __HAL_RCC_USBO_CONFIG(__USBOCLKSource__) \ 1685 MODIFY_REG(RCC->USBCKSELR, RCC_USBCKSELR_USBOSRC, (uint32_t)(__USBOCLKSource__)) 1686 1687 /** @brief macro to get the USB OTG PLL clock source. 1688 * @retval The clock source can be one of the following values: 1689 * @arg RCC_USBOCLKSOURCE_PLL4: PLL4_R Clock selected as USB OTG clock (default after reset) 1690 * @arg RCC_USBOCLKSOURCE_PHY: USB PHY Clock selected as USB OTG clock 1691 */ 1692 #define __HAL_RCC_GET_USBO_SOURCE() ((uint32_t)(READ_BIT(RCC->USBCKSELR, RCC_USBCKSELR_USBOSRC))) 1693 1694 1695 /** @brief macro to configure the RNG1 clock (RNG1CLK). 1696 * 1697 * @param __RNG1CLKSource__: specifies the RNG1 clock source. 1698 * This parameter can be one of the following values: 1699 * @arg RCC_RNG1CLKSOURCE_CSI: CSI Clock selected as RNG1 clock (default after reset) 1700 * @arg RCC_RNG1CLKSOURCE_PLL4: PLL4_R Clock selected as RNG1 clock 1701 * @arg RCC_RNG1CLKSOURCE_LSE: LSE Clock selected as RNG1 clock 1702 * @arg RCC_RNG1CLKSOURCE_LSI: LSI Clock selected as RNG1 clock 1703 * @retval None 1704 */ 1705 #define __HAL_RCC_RNG1_CONFIG(__RNG1CLKSource__) \ 1706 MODIFY_REG(RCC->RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, (uint32_t)(__RNG1CLKSource__)) 1707 1708 /** @brief macro to get the RNG1 clock source. 1709 * @retval The clock source can be one of the following values: 1710 * @arg RCC_RNG1CLKSOURCE_CSI: CSI Clock selected as RNG1 clock (default after reset) 1711 * @arg RCC_RNG1CLKSOURCE_PLL4: PLL4_R Clock selected as RNG1 clock 1712 * @arg RCC_RNG1CLKSOURCE_LSE: LSE Clock selected as RNG1 clock 1713 * @arg RCC_RNG1CLKSOURCE_LSI: LSI Clock selected as RNG1 clock 1714 */ 1715 #define __HAL_RCC_GET_RNG1_SOURCE() ((uint32_t)(READ_BIT(RCC->RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC))) 1716 1717 1718 /** @brief macro to configure the RNG2 clock (RNG2CLK). 1719 * 1720 * @param __RNG2CLKSource__: specifies the RNG2 clock source. 1721 * This parameter can be one of the following values: 1722 * @arg RCC_RNG2CLKSOURCE_CSI: CSI Clock selected as RNG2 clock (default after reset) 1723 * @arg RCC_RNG2CLKSOURCE_PLL4: PLL4_R Clock selected as RNG2 clock 1724 * @arg RCC_RNG2CLKSOURCE_LSE: LSE Clock selected as RNG2 clock 1725 * @arg RCC_RNG2CLKSOURCE_LSI: LSI Clock selected as RNG2 clock 1726 * @retval None 1727 */ 1728 #define __HAL_RCC_RNG2_CONFIG(__RNG2CLKSource__) \ 1729 MODIFY_REG(RCC->RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, (uint32_t)(__RNG2CLKSource__)) 1730 1731 /** @brief macro to get the RNG2 clock source. 1732 * @retval The clock source can be one of the following values: 1733 * @arg RCC_RNG2CLKSOURCE_CSI: CSI Clock selected as RNG2 clock (default after reset) 1734 * @arg RCC_RNG2CLKSOURCE_PLL4: PLL4_R Clock selected as RNG2 clock 1735 * @arg RCC_RNG2CLKSOURCE_LSE: LSE Clock selected as RNG2 clock 1736 * @arg RCC_RNG2CLKSOURCE_LSI: LSI Clock selected as RNG2 clock 1737 */ 1738 #define __HAL_RCC_GET_RNG2_SOURCE() ((uint32_t)(READ_BIT(RCC->RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC))) 1739 1740 1741 /** @brief macro to configure the CK_PER clock (CK_PERCLK). 1742 * 1743 * @param __CKPERCLKSource__: specifies the CPER clock source. 1744 * This parameter can be one of the following values: 1745 * @arg RCC_CKPERCLKSOURCE_HSI: HSI Clock selected as CK_PER clock (default after reset) 1746 * @arg RCC_CKPERCLKSOURCE_CSI: CSI Clock selected as CK_PER clock 1747 * @arg RCC_CKPERCLKSOURCE_HSE: HSE Clock selected as CK_PER clock 1748 * @arg RCC_CKPERCLKSOURCE_OFF: Clock disabled for CK_PER 1749 * @retval None 1750 */ 1751 #define __HAL_RCC_CKPER_CONFIG(__CKPERCLKSource__) \ 1752 MODIFY_REG(RCC->CPERCKSELR, RCC_CPERCKSELR_CKPERSRC, (uint32_t)(__CKPERCLKSource__)) 1753 1754 /** @brief macro to get the CPER clock source. 1755 * @retval The clock source can be one of the following values: 1756 * @arg RCC_CKPERCLKSOURCE_HSI: HSI Clock selected as CK_PER clock (default after reset) 1757 * @arg RCC_CKPERCLKSOURCE_CSI: CSI Clock selected as CK_PER clock 1758 * @arg RCC_CKPERCLKSOURCE_HSE: HSE Clock selected as CK_PER clock 1759 * @arg RCC_CKPERCLKSOURCE_OFF: Clock disabled for CK_PER 1760 */ 1761 #define __HAL_RCC_GET_CKPER_SOURCE() ((uint32_t)(READ_BIT(RCC->CPERCKSELR, RCC_CPERCKSELR_CKPERSRC))) 1762 1763 1764 /** @brief macro to configure the STGEN clock (STGENCLK). 1765 * 1766 * @param __STGENCLKSource__: specifies the STGEN clock source. 1767 * This parameter can be one of the following values: 1768 * @arg RCC_STGENCLKSOURCE_HSI: HSI Clock selected as STGEN clock (default after reset) 1769 * @arg RCC_STGENCLKSOURCE_HSE: HSE Clock selected as STGEN clock 1770 * @arg RCC_STGENCLKSOURCE_OFF: Clock disabled 1771 * 1772 * @retval None 1773 */ 1774 #define __HAL_RCC_STGEN_CONFIG(__STGENCLKSource__) \ 1775 MODIFY_REG(RCC->STGENCKSELR, RCC_STGENCKSELR_STGENSRC, (uint32_t)(__STGENCLKSource__)) 1776 1777 /** @brief macro to get the STGEN clock source. 1778 * @retval The clock source can be one of the following values: 1779 * @arg RCC_STGENCLKSOURCE_HSI: HSI Clock selected as STGEN clock (default after reset) 1780 * @arg RCC_STGENCLKSOURCE_HSE: HSE Clock selected as STGEN clock 1781 * @arg RCC_STGENCLKSOURCE_OFF: Clock disabled 1782 */ 1783 #define __HAL_RCC_GET_STGEN_SOURCE() ((uint32_t)(READ_BIT(RCC->STGENCKSELR, RCC_STGENCKSELR_STGENSRC))) 1784 1785 #if defined(DSI) 1786 /** @brief macro to configure the DSI clock (DSICLK). 1787 * 1788 * @param __DSICLKSource__: specifies the DSI clock source. 1789 * This parameter can be one of the following values: 1790 * @arg RCC_DSICLKSOURCE_PHY: DSIHOST clock from PHY is selected as DSI byte lane clock (default after reset) 1791 * @arg RCC_DSICLKSOURCE_PLL4: PLL4_P Clock selected as DSI byte lane clock 1792 * @retval None 1793 */ 1794 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ 1795 MODIFY_REG(RCC->DSICKSELR, RCC_DSICKSELR_DSISRC, (uint32_t)(__DSICLKSource__)) 1796 1797 /** @brief macro to get the DSI clock source. 1798 * @retval The clock source can be one of the following values: 1799 * @arg RCC_DSICLKSOURCE_PHY: DSIHOST clock from PHY is selected as DSI byte lane clock (default after reset) 1800 * @arg RCC_DSICLKSOURCE_PLL4: PLL4_P Clock selected as DSI byte lane clock 1801 */ 1802 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->DSICKSELR, RCC_DSICKSELR_DSISRC))) 1803 #endif /*DSI*/ 1804 1805 /** @brief macro to configure the ADC clock (ADCCLK). 1806 * 1807 * @param __ADCCLKSource__: specifies the ADC clock source. 1808 * This parameter can be one of the following values: 1809 * @arg RCC_ADCCLKSOURCE_PLL4: PLL4_R Clock selected as ADC clock (default after reset) 1810 * @arg RCC_ADCCLKSOURCE_PER: PER Clock selected as ADC clock 1811 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_Q Clock selected as ADC clock 1812 * @retval None 1813 */ 1814 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 1815 MODIFY_REG(RCC->ADCCKSELR, RCC_ADCCKSELR_ADCSRC, (uint32_t)(__ADCCLKSource__)) 1816 1817 /** @brief macro to get the ADC clock source. 1818 * @retval The clock source can be one of the following values: 1819 * @arg RCC_ADCCLKSOURCE_PLL4: PLL4_R Clock selected as ADC clock (default after reset) 1820 * @arg RCC_ADCCLKSOURCE_PER: PER Clock selected as ADC clock 1821 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_Q Clock selected as ADC clock 1822 */ 1823 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->ADCCKSELR, RCC_ADCCKSELR_ADCSRC))) 1824 1825 1826 /** @brief macro to configure the LPTIM1 clock (LPTIM1CLK). 1827 * 1828 * @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source. 1829 * This parameter can be one of the following values: 1830 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 Clock selected as LPTIM1 clock (default after reset) 1831 * @arg RCC_LPTIM1CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM1 clock 1832 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM1 clock 1833 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE Clock selected as LPTIM1 clock 1834 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 1835 * @arg RCC_LPTIM1CLKSOURCE_PER: PER Clock selected as LPTIM1 clock 1836 * @arg RCC_LPTIM1CLKSOURCE_OFF: The kernel clock is disabled 1837 * 1838 * @retval None 1839 */ 1840 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 1841 MODIFY_REG(RCC->LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (uint32_t)(__LPTIM1CLKSource__)) 1842 1843 /** @brief macro to get the LPTIM1 clock source. 1844 * @retval The clock source can be one of the following values: 1845 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 Clock selected as LPTIM1 clock (default after reset) 1846 * @arg RCC_LPTIM1CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM1 clock 1847 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM1 clock 1848 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE Clock selected as LPTIM1 clock 1849 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 1850 * @arg RCC_LPTIM1CLKSOURCE_PER: PER Clock selected as LPTIM1 clock 1851 * @arg RCC_LPTIM1CLKSOURCE_OFF: The kernel clock is disabled 1852 */ 1853 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC))) 1854 1855 /** @brief macro to configure the LPTIM23 clock (LPTIM23CLK). 1856 * 1857 * @param __LPTIM23CLKSource__: specifies the LPTIM23 clock source. 1858 * This parameter can be one of the following values: 1859 * @arg RCC_LPTIM23CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM23 clock (default after reset) 1860 * @arg RCC_LPTIM23CLKSOURCE_PLL4: PLL4_Q Clock selected as LPTIM23 clock 1861 * @arg RCC_LPTIM23CLKSOURCE_PER: PER Clock selected as LPTIM23 clock 1862 * @arg RCC_LPTIM23CLKSOURCE_LSE: LSE Clock selected as LPTIM23 clock 1863 * @arg RCC_LPTIM23CLKSOURCE_LSI: LSI Clock selected as LPTIM23 clock 1864 * @arg RCC_LPTIM23CLKSOURCE_OFF: The kernel clock is disabled 1865 * @retval None 1866 */ 1867 #define __HAL_RCC_LPTIM23_CONFIG(__LPTIM23CLKSource__) \ 1868 MODIFY_REG(RCC->LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (uint32_t)(__LPTIM23CLKSource__)) 1869 1870 /** @brief macro to get the LPTIM23 clock source. 1871 * @retval The clock source can be one of the following values: 1872 * @arg RCC_LPTIM23CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM23 clock (default after reset) 1873 * @arg RCC_LPTIM23CLKSOURCE_PLL4: PLL4_Q Clock selected as LPTIM23 clock 1874 * @arg RCC_LPTIM23CLKSOURCE_PER: PER Clock selected as LPTIM23 clock 1875 * @arg RCC_LPTIM23CLKSOURCE_LSE: LSE Clock selected as LPTIM23 clock 1876 * @arg RCC_LPTIM23CLKSOURCE_LSI: LSI Clock selected as LPTIM23 clock 1877 * @arg RCC_LPTIM23CLKSOURCE_OFF: The kernel clock is disabled 1878 */ 1879 #define __HAL_RCC_GET_LPTIM23_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC))) 1880 1881 /** @brief macro to configure the LPTIM45 clock (LPTIM45CLK). 1882 * 1883 * @param __LPTIM45CLKSource__: specifies the LPTIM45 clock source. 1884 * This parameter can be one of the following values: 1885 * @arg RCC_LPTIM45CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM45 clock (default after reset) 1886 * @arg RCC_LPTIM45CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM45 clock 1887 * @arg RCC_LPTIM45CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM45 clock 1888 * @arg RCC_LPTIM45CLKSOURCE_LSE: LSE Clock selected as LPTIM45 clock 1889 * @arg RCC_LPTIM45CLKSOURCE_LSI: LSI Clock selected as LPTIM45 clock 1890 * @arg RCC_LPTIM45CLKSOURCE_PER: PER Clock selected as LPTIM45 clock 1891 * @arg RCC_LPTIM45CLKSOURCE_OFF: The kernel clock is disabled 1892 * @retval None 1893 */ 1894 #define __HAL_RCC_LPTIM45_CONFIG(__LPTIM45CLKSource__) \ 1895 MODIFY_REG(RCC->LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (uint32_t)(__LPTIM45CLKSource__)) 1896 1897 /** @brief macro to get the LPTIM45 clock source. 1898 * @retval The clock source can be one of the following values: 1899 * @arg RCC_LPTIM45CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM45 clock (default after reset) 1900 * @arg RCC_LPTIM45CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM45 clock 1901 * @arg RCC_LPTIM45CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM45 clock 1902 * @arg RCC_LPTIM45CLKSOURCE_LSE: LSE Clock selected as LPTIM45 clock 1903 * @arg RCC_LPTIM45CLKSOURCE_LSI: LSI Clock selected as LPTIM45 clock 1904 * @arg RCC_LPTIM45CLKSOURCE_PER: PER Clock selected as LPTIM45 clock 1905 * @arg RCC_LPTIM45CLKSOURCE_OFF: The kernel clock is disabled 1906 */ 1907 #define __HAL_RCC_GET_LPTIM45_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC))) 1908 1909 1910 1911 /** 1912 * @brief Macro to set the APB1 timer clock prescaler 1913 * @note Set and reset by software to control the clock frequency of all the timers connected to APB1 domain. 1914 * It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. 1915 * @param __RCC_TIMG1PRES__: specifies the Timers clocks prescaler selection 1916 * This parameter can be one of the following values: 1917 * @arg RCC_TIMG1PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding 1918 * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset) 1919 * @arg RCC_TIMG1PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding 1920 * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 1921 */ 1922 #define __HAL_RCC_TIMG1PRES(__RCC_TIMG1PRES__) \ 1923 do{ MODIFY_REG( RCC->TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE , (__RCC_TIMG1PRES__));\ 1924 } while(0) 1925 1926 /** @brief Macro to get the APB1 timer clock prescaler. 1927 * @retval The APB1 timer clock prescaler. The returned value can be one 1928 * of the following: 1929 * - RCC_TIMG1PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding 1930 * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset) 1931 * - RCC_TIMG1PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding 1932 * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 1933 */ 1934 #define __HAL_RCC_GET_TIMG1PRES() ((uint32_t)(RCC->TIMG1PRER & RCC_TIMG1PRER_TIMG1PRE)) 1935 1936 /** 1937 * @brief Macro to set the APB2 timers clocks prescaler 1938 * @note Set and reset by software to control the clock frequency of all the timers connected to APB2 domain. 1939 * It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. 1940 * @param __RCC_TIMG2PRES__: specifies the timers clocks prescaler selection 1941 * This parameter can be one of the following values: 1942 * @arg RCC_TIMG2PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding 1943 * to a division by 1 or 2, else it is equal to 2 x Fck_pclk2 (default after reset) 1944 * @arg RCC_TIMG2PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding 1945 * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 1946 */ 1947 #define __HAL_RCC_TIMG2PRES(__RCC_TIMG2PRES__) \ 1948 do{ MODIFY_REG( RCC->TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE , (__RCC_TIMG2PRES__));\ 1949 } while(0) 1950 1951 /** @brief Macro to get the APB2 timer clock prescaler. 1952 * @retval The APB2 timer clock prescaler. The returned value can be one 1953 * of the following: 1954 * - RCC_TIMG2PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding 1955 * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset) 1956 * - RCC_TIMG2PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding 1957 * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 1958 */ 1959 #define __HAL_RCC_GET_TIMG2PRES() ((uint32_t)(RCC->TIMG2PRER & RCC_TIMG2PRER_TIMG2PRE)) 1960 1961 1962 1963 #define USB_PHY_VALUE ((uint32_t)48000000) /*!< Value of the USB_PHY_VALUE signal in Hz 1964 It is equal to rcc_hsphy_CLK_48M which is 1965 a constant value */ 1966 /** 1967 * @} 1968 */ 1969 1970 1971 /* Exported functions --------------------------------------------------------*/ 1972 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions 1973 * @{ 1974 */ 1975 1976 /** @addtogroup RCCEx_Exported_Functions_Group1 1977 * @{ 1978 */ 1979 1980 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); 1981 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1982 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1983 HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLLInitTypeDef *pll2); 1984 HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLLInitTypeDef *pll3); 1985 HAL_StatusTypeDef RCCEx_PLL4_Config(RCC_PLLInitTypeDef *pll4); 1986 1987 /** 1988 * @} 1989 */ 1990 1991 /** @addtogroup RCCEx_Exported_Functions_Group2 1992 * @{ 1993 */ 1994 1995 void HAL_RCCEx_EnableLSECSS(void); 1996 void HAL_RCCEx_DisableLSECSS(void); 1997 1998 #ifdef CORE_CA7 1999 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); 2000 void HAL_RCCEx_DisableBootCore(uint32_t RCC_BootCx); 2001 void HAL_RCCEx_HoldBootMCU(void); 2002 void HAL_RCCEx_BootMCU(void); 2003 #endif /* CORE_CA7 */ 2004 2005 /** 2006 * @} 2007 */ 2008 2009 /** 2010 * @} 2011 */ 2012 2013 /** 2014 * @} 2015 */ 2016 2017 /** 2018 * @} 2019 */ 2020 2021 #ifdef __cplusplus 2022 } 2023 #endif 2024 2025 #endif /* __STM32MP1xx_HAL_RCC_EX_H */ 2026
