1 /** 2 ****************************************************************************** 3 * @file stm32u0xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 #ifndef STM32U0xx_HAL_RCC_H 19 #define STM32U0xx_HAL_RCC_H 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /* Includes ------------------------------------------------------------------*/ 26 #include "stm32u0xx_hal_def.h" 27 28 /** @addtogroup STM32U0xx_HAL_Driver 29 * @{ 30 */ 31 32 /** @addtogroup RCC 33 * @{ 34 */ 35 36 /* Exported types ------------------------------------------------------------*/ 37 38 /** @defgroup RCC_Exported_Types RCC Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief RCC PLL configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t PLLState; /*!< The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 54 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 55 56 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 57 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 58 59 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 60 This parameter must be a number between Min_Data = 1 and Max_Data = 128 61 odd division factors are not allowed */ 62 63 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 65 66 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 67 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 68 69 uint32_t PLLClockOut; /*!< PLLClockOut: specifies PLL output clock to be enabled. 70 This parameter must be a value of @ref RCC_PLL_Clock_Output */ 71 72 } RCC_PLLInitTypeDef; 73 74 /** 75 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 76 */ 77 typedef struct 78 { 79 uint32_t OscillatorType; /*!< The oscillators to be configured. 80 This parameter can be a value of @ref RCC_Oscillator_Type */ 81 82 uint32_t HSEState; /*!< The new state of the HSE. 83 This parameter can be a value of @ref RCC_HSE_Config */ 84 85 uint32_t LSEState; /*!< The new state of the LSE. 86 This parameter can be a value of @ref RCC_LSE_Config */ 87 88 uint32_t HSIState; /*!< The new state of the HSI. 89 This parameter can be a value of @ref RCC_HSI_Config */ 90 91 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 92 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 93 on the other devices */ 94 95 uint32_t LSIState; /*!< The new state of the LSI. 96 This parameter can be a value of @ref RCC_LSI_Config */ 97 98 uint32_t LSIDiv; /*!< The division factor of the LSI. 99 This parameter can be a value of @ref RCC_LSI_Div */ 100 101 uint32_t MSIState; /*!< The new state of the MSI. 102 This parameter can be a value of @ref RCC_MSI_Config */ 103 104 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 105 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 106 107 uint32_t MSIClockRange; /*!< The MSI frequency range. 108 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 109 #if defined(RCC_CRRCR_HSI48ON) 110 uint32_t HSI48State; /*!< The new state of the HSI48. 111 This parameter can be a value of @ref RCC_HSI48_Config */ 112 #endif /* RCC_CRRCR_HSI48ON */ 113 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 114 115 } RCC_OscInitTypeDef; 116 117 /** 118 * @brief RCC System, AHB and APB busses clock configuration structure definition 119 */ 120 typedef struct 121 { 122 uint32_t ClockType; /*!< The clock to be configured. 123 This parameter can be a value of @ref RCC_System_Clock_Type */ 124 125 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 126 This parameter can be a value of @ref RCC_System_Clock_Source */ 127 128 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 129 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 130 131 uint32_t APB1CLKDivider; /*!< The APB clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 132 This parameter can be a value of @ref RCC_APB_Clock_Source */ 133 134 } RCC_ClkInitTypeDef; 135 136 /** 137 * @} 138 */ 139 /* Exported constants --------------------------------------------------------*/ 140 /** @defgroup RCC_Exported_Constants RCC Exported Constants 141 * @{ 142 */ 143 144 /** @defgroup RCC_Oscillator_Type Oscillator Type 145 * @{ 146 */ 147 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) /*!< Oscillator configuration unchanged */ 148 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) /*!< HSE to configure */ 149 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) /*!< HSI to configure */ 150 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) /*!< LSE to configure */ 151 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) /*!< LSI to configure */ 152 #define RCC_OSCILLATORTYPE_MSI (0x00000010U) /*!< MSI to configure */ 153 #if defined(RCC_CRRCR_HSI48ON) 154 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) /*!< HSI48 to configure */ 155 #endif /* RCC_CRRCR_HSI48ON */ 156 /** 157 * @} 158 */ 159 160 /** @defgroup RCC_HSE_Config HSE Config 161 * @{ 162 */ 163 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ 164 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 165 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 166 /** 167 * @} 168 */ 169 170 /** @defgroup RCC_LSE_Config LSE Config 171 * @{ 172 */ 173 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ 174 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ 175 #define RCC_LSE_ON (RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< LSE clock activation for RCC and peripherals */ 176 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 177 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 178 /** 179 * @} 180 */ 181 182 /** @defgroup RCC_HSI_Config HSI Config 183 * @{ 184 */ 185 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ 186 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 187 188 #define RCC_HSICALIBRATION_DEFAULT (0x40U) /*! Default HSI calibration trimming value */ 189 /** 190 * @} 191 */ 192 193 /** @defgroup RCC_LSI_Config LSI Config 194 * @{ 195 */ 196 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ 197 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 198 /** 199 * @} 200 */ 201 202 /** @defgroup RCC_LSI_Div LSI Div 203 * @{ 204 */ 205 #define RCC_LSI_DIV1 (0x00000000U) /*!< LSI clock is not divided */ 206 #define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock is divided by 128 */ 207 /** 208 * @} 209 */ 210 211 /** @defgroup RCC_MSI_Config MSI Config 212 * @{ 213 */ 214 #define RCC_MSI_OFF (0x00000000U) /*!< MSI clock deactivation */ 215 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 216 217 #define RCC_MSICALIBRATION_DEFAULT (0x0U) /*!< Default MSI calibration trimming value */ 218 /** 219 * @} 220 */ 221 222 /** @defgroup RCC_HSIK_Config HSIK Config 223 * @{ 224 */ 225 #define RCC_HSIK_OFF (0x00000000U) /*!< HSIK clock deactivation */ 226 #define RCC_HSIK_ON RCC_CR_HSIKERON /*!< HSIK clock activation */ 227 /** 228 * @} 229 */ 230 231 /** @defgroup RCC_HSIASFS_Config HSIASFS Config 232 * @{ 233 */ 234 #define RCC_HSIASFS_OFF (0x00000000U) /*!< HSIASFS clock deactivation */ 235 #define RCC_HSIASFS_ON RCC_CR_HSIASFSON /*!< HSIASFS clock activation */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup RCC_HSECSS_Config HSECSS Config 241 * @{ 242 */ 243 #define RCC_HSECSS_OFF (0x00000000U) /*!< HSECSS clock deactivation */ 244 #define RCC_HSECSS_ON RCC_CR_HSECSSON /*!< HSECSS clock activation */ 245 246 /** 247 * @} 248 */ 249 #if defined(RCC_CRRCR_HSI48ON) 250 /** @defgroup RCC_HSI48_Config HSI48 Config 251 * @{ 252 */ 253 #define RCC_HSI48_OFF (0x00000000U) /*!< HSI48 clock deactivation */ 254 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 255 #endif /* RCC_CRRCR_HSI48ON */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup RCC_PLL_Config RCC PLL Config 261 * @{ 262 */ 263 #define RCC_PLL_NONE (0x00000000U) 264 #define RCC_PLL_OFF (0x00000001U) 265 #define RCC_PLL_ON (0x00000002U) 266 267 /** 268 * @} 269 */ 270 271 /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output 272 * @{ 273 */ 274 #define RCC_PLL_DIVP RCC_PLLCFGR_PLLPEN 275 #define RCC_PLL_DIVQ RCC_PLLCFGR_PLLQEN 276 #define RCC_PLL_DIVR RCC_PLLCFGR_PLLREN 277 278 /** 279 * @} 280 */ 281 282 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 283 * @{ 284 */ 285 #define RCC_PLLM_DIV1 0x00000000U /*!< PLLM division factor = 8 */ 286 #define RCC_PLLM_DIV2 RCC_PLLCFGR_PLLM_0 /*!< PLLM division factor = 2 */ 287 #define RCC_PLLM_DIV3 RCC_PLLCFGR_PLLM_1 /*!< PLLM division factor = 3 */ 288 #define RCC_PLLM_DIV4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 4 */ 289 #define RCC_PLLM_DIV5 RCC_PLLCFGR_PLLM_2 /*!< PLLM division factor = 5 */ 290 #define RCC_PLLM_DIV6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 6 */ 291 #define RCC_PLLM_DIV7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLLM division factor = 7 */ 292 #define RCC_PLLM_DIV8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 8 */ 293 /** 294 * @} 295 */ 296 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 297 * @{ 298 */ 299 #define RCC_PLLP_DIV2 RCC_PLLCFGR_PLLP_0 /*!< PLLP division factor = 2 */ 300 #define RCC_PLLP_DIV3 RCC_PLLCFGR_PLLP_1 /*!< PLLP division factor = 3 */ 301 #define RCC_PLLP_DIV4 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 4 */ 302 #define RCC_PLLP_DIV5 RCC_PLLCFGR_PLLP_2 /*!< PLLP division factor = 5 */ 303 #define RCC_PLLP_DIV6 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 6 */ 304 #define RCC_PLLP_DIV7 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 7 */ 305 #define RCC_PLLP_DIV8 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 8 */ 306 #define RCC_PLLP_DIV9 RCC_PLLCFGR_PLLP_3 /*!< PLLP division factor = 9 */ 307 #define RCC_PLLP_DIV10 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 10 */ 308 #define RCC_PLLP_DIV11 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 11 */ 309 #define RCC_PLLP_DIV12 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 12 */ 310 #define RCC_PLLP_DIV13 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 13 */ 311 #define RCC_PLLP_DIV14 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 14 */ 312 #define RCC_PLLP_DIV15 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 15 */ 313 #define RCC_PLLP_DIV16 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 16 */ 314 #define RCC_PLLP_DIV17 RCC_PLLCFGR_PLLP_4 /*!< PLLP division factor = 17 */ 315 #define RCC_PLLP_DIV18 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 18 */ 316 #define RCC_PLLP_DIV19 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 19 */ 317 #define RCC_PLLP_DIV20 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 20 */ 318 #define RCC_PLLP_DIV21 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 21 */ 319 #define RCC_PLLP_DIV22 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 22 */ 320 #define RCC_PLLP_DIV23 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 23 */ 321 #define RCC_PLLP_DIV24 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 24 */ 322 #define RCC_PLLP_DIV25 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3) /*!< PLLP division factor = 25 */ 323 #define RCC_PLLP_DIV26 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 26 */ 324 #define RCC_PLLP_DIV27 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 27 */ 325 #define RCC_PLLP_DIV28 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 28 */ 326 #define RCC_PLLP_DIV29 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 29 */ 327 #define RCC_PLLP_DIV30 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 30 */ 328 #define RCC_PLLP_DIV31 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 31 */ 329 #define RCC_PLLP_DIV32 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | \ 330 RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 32 */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 336 * @{ 337 */ 338 #define RCC_PLLQ_DIV2 RCC_PLLCFGR_PLLQ_0 /*!< PLLQ division factor = 2 */ 339 #define RCC_PLLQ_DIV3 RCC_PLLCFGR_PLLQ_1 /*!< PLLQ division factor = 3 */ 340 #define RCC_PLLQ_DIV4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 4 */ 341 #define RCC_PLLQ_DIV5 RCC_PLLCFGR_PLLQ_2 /*!< PLLQ division factor = 5 */ 342 #define RCC_PLLQ_DIV6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 6 */ 343 #define RCC_PLLQ_DIV7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1) /*!< PLLQ division factor = 7 */ 344 #define RCC_PLLQ_DIV8 (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 8 */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 350 * @{ 351 */ 352 #define RCC_PLLR_DIV2 RCC_PLLCFGR_PLLR_0 /*!< PLLR division factor = 2 */ 353 #define RCC_PLLR_DIV3 RCC_PLLCFGR_PLLR_1 /*!< PLLR division factor = 3 */ 354 #define RCC_PLLR_DIV4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 4 */ 355 #define RCC_PLLR_DIV5 RCC_PLLCFGR_PLLR_2 /*!< PLLR division factor = 5 */ 356 #define RCC_PLLR_DIV6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 6 */ 357 #define RCC_PLLR_DIV7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1) /*!< PLLR division factor = 7 */ 358 #define RCC_PLLR_DIV8 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 8 */ 359 /** 360 * @} 361 */ 362 363 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source 364 * @{ 365 */ 366 #define RCC_PLLSOURCE_NONE (0x00000000U) 367 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 368 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 369 #define RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_0 | RCC_PLLCFGR_PLLSRC_1) 370 371 /** 372 * @} 373 */ 374 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 375 * @{ 376 */ 377 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 378 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 379 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 380 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 381 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 382 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 383 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 384 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 385 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 386 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 387 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 388 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 389 /** 390 * @} 391 */ 392 393 /** @defgroup RCC_System_Clock_Type System Clock Type 394 * @{ 395 */ 396 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ 397 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ 398 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ 399 /** 400 * @} 401 */ 402 403 /** @defgroup RCC_System_Clock_Source System Clock Source 404 * @{ 405 */ 406 #define RCC_SYSCLKSOURCE_MSI (0x00000000U) /*!< MSI selection as system clock */ 407 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */ 408 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */ 409 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */ 410 #define RCC_SYSCLKSOURCE_LSI RCC_CFGR_SW_2 /*!< LSI selection as system clock */ 411 #define RCC_SYSCLKSOURCE_LSE (RCC_CFGR_SW_2 |RCC_CFGR_SW_0) /*!< LSE selection as system clock */ 412 /** 413 * @} 414 */ 415 416 417 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 418 * @{ 419 */ 420 #define RCC_SYSCLKSOURCE_STATUS_MSI (0x00000000U) /*!< MSI used as system clock */ 421 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */ 422 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ 423 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */ 424 #define RCC_SYSCLKSOURCE_STATUS_LSI RCC_CFGR_SWS_2 /*!< LSI used as system clock */ 425 #define RCC_SYSCLKSOURCE_STATUS_LSE (RCC_CFGR_SWS_2 |RCC_CFGR_SWS_0) /*!< LSE used as system clock */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 431 * @{ 432 */ 433 #define RCC_SYSCLK_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 434 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ 435 #define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ 436 #define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ 437 #define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ 438 #define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ 439 #define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ 440 #define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ 441 #define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ 442 /** 443 * @} 444 */ 445 446 /** @defgroup RCC_APB_Clock_Source APB Clock Source 447 * @{ 448 */ 449 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 450 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ 451 #define RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ 452 #define RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ 453 #define RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ 454 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 460 * @{ 461 */ 462 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 463 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 464 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 465 #define RCC_RTCCLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 466 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_RTCCLKSOURCE_HSE 467 /** 468 * @} 469 */ 470 471 /** @defgroup RCC_MCO_Index MCO Index 472 * @{ 473 */ 474 /* 32 28 20 16 0 475 476 |-------|-------|-------|-------| 477 | MCO | GPIO | GPIO | GPIO | 478 | Index | AF | Port | Pin | 479 -------------------------------*/ 480 481 #define RCC_MCO_GPIOPORT_POS 16U 482 #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) 483 #define RCC_MCO_GPIOAF_POS 20U 484 #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) 485 #define RCC_MCO_INDEX_POS 28U 486 #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) 487 #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ 488 #define RCC_MCO1_PA8 (RCC_MCO1_INDEX |\ 489 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ 490 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 491 #define RCC_MCO1_PA9 (RCC_MCO1_INDEX |\ 492 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ 493 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) 494 #define RCC_MCO1_PF2 (RCC_MCO1_INDEX |\ 495 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ 496 (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) 497 #define RCC_MCO1 RCC_MCO1_PA8 498 499 #define RCC_MCO2_INDEX (0x1UL << RCC_MCO_INDEX_POS) /*!< MCO2 index */ 500 #define RCC_MCO2_PC2 (RCC_MCO2_INDEX |\ 501 (GPIO_AF0_MCO2 << RCC_MCO_GPIOAF_POS) | \ 502 (GPIO_GET_INDEX(GPIOC) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) 503 #define RCC_MCO2_PA10 (RCC_MCO2_INDEX |\ 504 (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ 505 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) 506 #define RCC_MCO2_PA8 (RCC_MCO2_INDEX |\ 507 (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ 508 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 509 #define RCC_MCO2 RCC_MCO2_PC2 510 511 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 512 /** 513 * @} 514 */ 515 516 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 517 * @{ 518 */ 519 #define RCC_MCO1SOURCE_NOCLOCK (0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */ 520 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO1SEL_0 /*!< SYSCLK selection as MCO1 source */ 521 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO1SEL_1 /*!< MSI selection as MCO1 source */ 522 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCO1SEL_0 | RCC_CFGR_MCO1SEL_1) /*!< HSI selection as MCO1 source */ 523 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1SEL_2 /*!< HSE selection as MCO1 source */ 524 #define RCC_MCO1SOURCE_PLLR (RCC_CFGR_MCO1SEL_0 | RCC_CFGR_MCO1SEL_2) /*!< PLLCLK selection as MCO1 source */ 525 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_2) /*!< LSI selection as MCO1 source */ 526 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCO1SEL_0 | RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_2) /*!< LSE selection as MCO1 source */ 527 #if defined(RCC_CRRCR_HSI48ON) 528 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1SEL_3 /*!< HSI48 selection as MCO1 source */ 529 #endif /* RCC_CRRCR_HSI48ON */ 530 #define RCC_MCO1SOURCE_RTC_ALT (RCC_CFGR_MCO1SEL_0 | RCC_CFGR_MCO1SEL_3) /*!< RTC alternative clock selection as MCO1 source */ 531 #define RCC_MCO1SOURCE_RTC_WAKEUP (RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_3) /*!< RTC wakeup interrupt signal selection as MCO1 source */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 537 * @{ 538 */ 539 #define RCC_MCO2SOURCE_NOCLOCK (0x00000000U) /*!< MCO2 output disabled, no clock on MCO2 */ 540 #define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ 541 #define RCC_MCO2SOURCE_MSI RCC_CFGR_MCO2SEL_1 /*!< MSI selection as MCO2 source */ 542 #define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_0 | RCC_CFGR_MCO2SEL_1) /*!< HSI selection as MCO2 source */ 543 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ 544 #define RCC_MCO2SOURCE_PLLR (RCC_CFGR_MCO2SEL_0 | RCC_CFGR_MCO2SEL_2) /*!< PLLCLK selection as MCO2 source */ 545 #define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_2) /*!< LSI selection as MCO2 source */ 546 #define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_0 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_2) /*!< LSE selection as MCO2 source */ 547 #if defined(RCC_CRRCR_HSI48ON) 548 #define RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_3 /*!< HSI48 selection as MCO2 source */ 549 #endif /* RCC_CRRCR_HSI48ON */ 550 #define RCC_MCO2SOURCE_RTC_ALT (RCC_CFGR_MCO2SEL_0 | RCC_CFGR_MCO2SEL_3) /*!< RTC alternative clock selection as MCO2 source */ 551 #define RCC_MCO2SOURCE_RTC_WAKEUP (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_3) /*!< RTC wakeup interrupt signal selection as MCO2 source */ 552 /** 553 * @} 554 */ 555 556 /** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler 557 * @{ 558 */ 559 #define RCC_MCO1DIV_1 (0x00000000U) /*!< MCO divided by 1 */ 560 #define RCC_MCO1DIV_2 RCC_CFGR_MCO1PRE_0 /*!< MCO divided by 2 */ 561 #define RCC_MCO1DIV_4 RCC_CFGR_MCO1PRE_1 /*!< MCO divided by 4 */ 562 #define RCC_MCO1DIV_8 (RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 8 */ 563 #define RCC_MCO1DIV_16 RCC_CFGR_MCO1PRE_2 /*!< MCO divided by 16 */ 564 #define RCC_MCO1DIV_32 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 32 */ 565 #define RCC_MCO1DIV_64 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 64 */ 566 #define RCC_MCO1DIV_128 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 128 */ 567 #define RCC_MCO1DIV_256 RCC_CFGR_MCO1PRE_3 /*!< MCO divided by 256 */ 568 #define RCC_MCO1DIV_512 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 512 */ 569 #define RCC_MCO1DIV_1024 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 1024 */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler 575 * @{ 576 */ 577 #define RCC_MCO2DIV_1 (0x00000000U) /*!< MCO divided by 1 */ 578 #define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO divided by 2 */ 579 #define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO divided by 4 */ 580 #define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 8 */ 581 #define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO divided by 16 */ 582 #define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 32 */ 583 #define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 64 */ 584 #define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 128 */ 585 #define RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO divided by 256 */ 586 #define RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 512 */ 587 #define RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 1024 */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup RCC_Interrupt Interrupts 593 * @{ 594 */ 595 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 596 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 597 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 598 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 599 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 600 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 601 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ 602 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 603 #if defined(RCC_CIFR_HSI48RDYF) 604 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 605 #endif /* RCC_CIFR_HSI48RDYF */ 606 607 /** 608 * @} 609 */ 610 611 /** @defgroup RCC_Flag Flags 612 * Elements values convention: XXXYYYYYb 613 * - YYYYY : Flag position in the register 614 * - XXX : Register index 615 * - 001: CR register 616 * - 010: BDCR register 617 * - 011: CSR register 618 * @{ 619 */ 620 /* Flags in the CR register */ 621 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */ 622 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ 623 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ 624 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */ 625 626 /* Flags in the BDCR register */ 627 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ 628 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ 629 #define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSE clock ready to be used by the system */ 630 631 /* Flags in the CSR register */ 632 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< LSI Ready flag */ 633 #define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ 634 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option byte loader reset flag */ 635 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< Pin reset flag */ 636 #define RCC_FLAG_PWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos)) /*!< PWR reset flag */ 637 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software reset flag */ 638 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent window Watchdog reset flag */ 639 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 640 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low Power reset flag */ 641 #if defined (RCC_CRRCR_HSI48ON) 642 #define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ 643 #endif /* RCC_CRRCR_HSI48ON */ 644 645 /** 646 * @} 647 */ 648 649 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 650 * @{ 651 */ 652 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */ 653 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 654 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 655 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup RCC_Reset_Flag Reset Flag 661 * @{ 662 */ 663 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 664 #define RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ 665 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 666 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 667 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 668 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 669 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 670 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | RCC_RESET_FLAG_SW | \ 671 RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | RCC_RESET_FLAG_LPWR | \ 672 RCC_RESET_FLAG_OBL) 673 /** 674 * @} 675 */ 676 677 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 678 * @{ 679 */ 680 #define RCC_STOP_WAKEUPCLOCK_MSI (0x00000000U) /*!< MSI selection after wake-up from STOP */ 681 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 682 /** 683 * @} 684 */ 685 686 /* Exported macros -----------------------------------------------------------*/ 687 688 /** @defgroup RCC_Exported_Macros RCC Exported Macros 689 * @{ 690 */ 691 692 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable 693 * @brief Enable or disable the AHB peripheral clock. 694 * @note After reset, the peripheral clock (used for registers read/write access) 695 * is disabled and the application software has to enable this clock before 696 * using it. 697 * @{ 698 */ 699 700 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 701 __IO uint32_t tmpreg; \ 702 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 703 /* Delay after an RCC peripheral clock enabling */ \ 704 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 705 UNUSED(tmpreg); \ 706 } while(0) 707 #if defined (DMA2) 708 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 709 __IO uint32_t tmpreg; \ 710 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 711 /* Delay after an RCC peripheral clock enabling */ \ 712 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 713 UNUSED(tmpreg); \ 714 } while(0) 715 #endif /* DMA2 */ 716 717 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 718 __IO uint32_t tmpreg; \ 719 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 720 /* Delay after an RCC peripheral clock enabling */ \ 721 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 722 UNUSED(tmpreg); \ 723 } while(0) 724 725 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 726 __IO uint32_t tmpreg; \ 727 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 728 /* Delay after an RCC peripheral clock enabling */ \ 729 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 730 UNUSED(tmpreg); \ 731 } while(0) 732 733 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 734 __IO uint32_t tmpreg; \ 735 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \ 736 /* Delay after an RCC peripheral clock enabling */ \ 737 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \ 738 UNUSED(tmpreg); \ 739 } while(0) 740 741 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 742 __IO uint32_t tmpreg; \ 743 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ 744 /* Delay after an RCC peripheral clock enabling */ \ 745 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ 746 UNUSED(tmpreg); \ 747 } while(0) 748 #if defined (AES) 749 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 750 __IO uint32_t tmpreg; \ 751 SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ 752 /* Delay after an RCC peripheral clock enabling */ \ 753 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ 754 UNUSED(tmpreg); \ 755 } while(0) 756 #endif /* AES */ 757 758 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) 759 #if defined (DMA2) 760 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) 761 #endif /* DMA2 */ 762 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) 763 764 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) 765 766 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) 767 768 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) 769 #if defined (AES) 770 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) 771 #endif /* AES */ 772 /** 773 * @} 774 */ 775 776 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable 777 * @brief Enable or disable the IO Ports clock. 778 * @note After reset, the IO ports clock (used for registers read/write access) 779 * is disabled and the application software has to enable this clock before 780 * using it. 781 * @{ 782 */ 783 784 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 785 __IO uint32_t tmpreg; \ 786 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 787 /* Delay after an RCC peripheral clock enabling */ \ 788 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 789 UNUSED(tmpreg); \ 790 } while(0U) 791 792 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 793 __IO uint32_t tmpreg; \ 794 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 795 /* Delay after an RCC peripheral clock enabling */ \ 796 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 797 UNUSED(tmpreg); \ 798 } while(0U) 799 800 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 801 __IO uint32_t tmpreg; \ 802 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 803 /* Delay after an RCC peripheral clock enabling */ \ 804 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 805 UNUSED(tmpreg); \ 806 } while(0U) 807 808 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 809 __IO uint32_t tmpreg; \ 810 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 811 /* Delay after an RCC peripheral clock enabling */ \ 812 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 813 UNUSED(tmpreg); \ 814 } while(0U) 815 816 #if defined (GPIOE) 817 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 818 __IO uint32_t tmpreg; \ 819 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ 820 /* Delay after an RCC peripheral clock enabling */ \ 821 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ 822 UNUSED(tmpreg); \ 823 } while(0U) 824 #endif /* GPIOE */ 825 826 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 827 __IO uint32_t tmpreg; \ 828 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 829 /* Delay after an RCC peripheral clock enabling */ \ 830 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 831 UNUSED(tmpreg); \ 832 } while(0U) 833 834 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) 835 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) 836 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) 837 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) 838 #if defined (GPIOE) 839 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) 840 #endif /* GPIOE */ 841 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) 842 843 /** 844 * @} 845 */ 846 847 /** @defgroup RCC_APB1_GRP1_Peripheral_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 848 * @brief Enable or disable the APB peripheral clock. 849 * @note After reset, the peripheral clock (used for registers read/write access) 850 * is disabled and the application software has to enable this clock before 851 * using it. 852 * @{ 853 */ 854 855 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 856 __IO uint32_t tmpreg; \ 857 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ 858 /* Delay after an RCC peripheral clock enabling */ \ 859 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ 860 UNUSED(tmpreg); \ 861 } while(0) 862 863 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 864 __IO uint32_t tmpreg; \ 865 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ 866 /* Delay after an RCC peripheral clock enabling */ \ 867 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ 868 UNUSED(tmpreg); \ 869 } while(0) 870 871 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 872 __IO uint32_t tmpreg; \ 873 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ 874 /* Delay after an RCC peripheral clock enabling */ \ 875 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ 876 UNUSED(tmpreg); \ 877 } while(0) 878 879 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 880 __IO uint32_t tmpreg; \ 881 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ 882 /* Delay after an RCC peripheral clock enabling */ \ 883 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ 884 UNUSED(tmpreg); \ 885 } while(0) 886 887 #define __HAL_RCC_LPUART2_CLK_ENABLE() do { \ 888 __IO uint32_t tmpreg; \ 889 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ 890 /* Delay after an RCC peripheral clock enabling */ \ 891 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ 892 UNUSED(tmpreg); \ 893 } while(0U) 894 #if defined (LCD) 895 #define __HAL_RCC_LCD_CLK_ENABLE() do { \ 896 __IO uint32_t tmpreg; \ 897 SET_BIT(RCC->APBENR1, RCC_APBENR1_LCDEN); \ 898 /* Delay after an RCC peripheral clock enabling */ \ 899 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LCDEN); \ 900 UNUSED(tmpreg); \ 901 } while(0) 902 #endif /* LCD */ 903 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 904 __IO uint32_t tmpreg; \ 905 SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ 906 /* Delay after an RCC peripheral clock enabling */ \ 907 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ 908 UNUSED(tmpreg); \ 909 } while(0U) 910 911 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 912 __IO uint32_t tmpreg; \ 913 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ 914 /* Delay after an RCC peripheral clock enabling */ \ 915 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ 916 UNUSED(tmpreg); \ 917 } while(0) 918 #if defined (LPUART3) 919 #define __HAL_RCC_LPUART3_CLK_ENABLE() do { \ 920 __IO uint32_t tmpreg; \ 921 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART3EN); \ 922 /* Delay after an RCC peripheral clock enabling */ \ 923 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART3EN); \ 924 UNUSED(tmpreg); \ 925 } while(0U) 926 #endif /* LPUART3 */ 927 #if defined (USB_DRD_FS) 928 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 929 __IO uint32_t tmpreg; \ 930 SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ 931 /* Delay after an RCC peripheral clock enabling */ \ 932 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ 933 UNUSED(tmpreg); \ 934 } while(0U) 935 #endif /* USB_DRD_FS */ 936 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 937 __IO uint32_t tmpreg; \ 938 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ 939 /* Delay after an RCC peripheral clock enabling */ \ 940 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ 941 UNUSED(tmpreg); \ 942 } while(0) 943 944 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 945 __IO uint32_t tmpreg; \ 946 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ 947 /* Delay after an RCC peripheral clock enabling */ \ 948 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ 949 UNUSED(tmpreg); \ 950 } while(0) 951 #if defined(CRS) 952 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 953 __IO uint32_t tmpreg; \ 954 SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ 955 /* Delay after an RCC peripheral clock enabling */ \ 956 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ 957 UNUSED(tmpreg); \ 958 } while(0) 959 #endif /* CRS */ 960 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 961 __IO uint32_t tmpreg; \ 962 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ 963 /* Delay after an RCC peripheral clock enabling */ \ 964 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ 965 UNUSED(tmpreg); \ 966 } while(0) 967 968 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 969 __IO uint32_t tmpreg; \ 970 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ 971 /* Delay after an RCC peripheral clock enabling */ \ 972 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ 973 UNUSED(tmpreg); \ 974 } while(0) 975 976 #define __HAL_RCC_USART4_CLK_ENABLE() do { \ 977 __IO uint32_t tmpreg; \ 978 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ 979 /* Delay after an RCC peripheral clock enabling */ \ 980 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ 981 UNUSED(tmpreg); \ 982 } while(0) 983 984 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 985 __IO uint32_t tmpreg; \ 986 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ 987 /* Delay after an RCC peripheral clock enabling */ \ 988 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ 989 UNUSED(tmpreg); \ 990 } while(0) 991 992 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 993 __IO uint32_t tmpreg; \ 994 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ 995 /* Delay after an RCC peripheral clock enabling */ \ 996 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ 997 UNUSED(tmpreg); \ 998 } while(0) 999 1000 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1001 __IO uint32_t tmpreg; \ 1002 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ 1003 /* Delay after an RCC peripheral clock enabling */ \ 1004 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ 1005 UNUSED(tmpreg); \ 1006 } while(0) 1007 1008 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1009 __IO uint32_t tmpreg; \ 1010 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ 1011 /* Delay after an RCC peripheral clock enabling */ \ 1012 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ 1013 UNUSED(tmpreg); \ 1014 } while(0) 1015 1016 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1017 __IO uint32_t tmpreg; \ 1018 SET_BIT(RCC->APBENR1, RCC_APBENR1_OPAMPEN); \ 1019 /* Delay after an RCC peripheral clock enabling */ \ 1020 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_OPAMPEN); \ 1021 UNUSED(tmpreg); \ 1022 } while(0) 1023 #if defined(I2C4) 1024 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1025 __IO uint32_t tmpreg; \ 1026 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C4EN); \ 1027 /* Delay after an RCC peripheral clock enabling */ \ 1028 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C4EN); \ 1029 UNUSED(tmpreg); \ 1030 } while(0) 1031 #endif /* I2C4 */ 1032 #if defined (LPTIM3) 1033 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1034 __IO uint32_t tmpreg; \ 1035 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM3EN); \ 1036 /* Delay after an RCC peripheral clock enabling */ \ 1037 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM3EN); \ 1038 UNUSED(tmpreg); \ 1039 } while(0) 1040 #endif /* LPTIM3 */ 1041 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1042 __IO uint32_t tmpreg; \ 1043 SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ 1044 /* Delay after an RCC peripheral clock enabling */ \ 1045 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ 1046 UNUSED(tmpreg); \ 1047 } while(0U) 1048 1049 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1050 __IO uint32_t tmpreg; \ 1051 SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ 1052 /* Delay after an RCC peripheral clock enabling */ \ 1053 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ 1054 UNUSED(tmpreg); \ 1055 } while(0U) 1056 1057 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1058 __IO uint32_t tmpreg; \ 1059 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ 1060 /* Delay after an RCC peripheral clock enabling */ \ 1061 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ 1062 UNUSED(tmpreg); \ 1063 } while(0) 1064 1065 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1066 __IO uint32_t tmpreg; \ 1067 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ 1068 /* Delay after an RCC peripheral clock enabling */ \ 1069 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ 1070 UNUSED(tmpreg); \ 1071 } while(0) 1072 1073 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) 1074 1075 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) 1076 1077 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) 1078 1079 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) 1080 1081 #define __HAL_RCC_LPUART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN) 1082 1083 #if defined (LCD) 1084 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LCDEN) 1085 #endif /* LCD */ 1086 1087 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) 1088 1089 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) 1090 1091 #if defined (LPUART3) 1092 #define __HAL_RCC_LPUART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART3EN) 1093 #endif /* LPUART3 */ 1094 #if defined (USB_DRD_FS) 1095 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) 1096 #endif /* USB_DRD_FS */ 1097 1098 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) 1099 1100 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) 1101 #if defined(CRS) 1102 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) 1103 #endif /* CRS */ 1104 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) 1105 1106 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) 1107 1108 #define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) 1109 1110 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN) 1111 1112 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) 1113 1114 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) 1115 1116 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) 1117 1118 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_OPAMPEN) 1119 #if defined(I2C4) 1120 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C4EN) 1121 #endif /* I2C4 */ 1122 #if defined (LPTIM3) 1123 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM3EN) 1124 #endif /* LPTIM3 */ 1125 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) 1126 1127 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) 1128 1129 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) 1130 1131 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) 1132 1133 /** 1134 * @} 1135 */ 1136 1137 /** @defgroup RCC_APB_Peripheral_Clock_Enable_Disable APB Peripheral Clock Enable Disable 1138 * @brief Enable or disable the APB peripheral clock. 1139 * @note After reset, the peripheral clock (used for registers read/write access) 1140 * is disabled and the application software has to enable this clock before 1141 * using it. 1142 * @{ 1143 */ 1144 1145 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1146 __IO uint32_t tmpreg; \ 1147 SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ 1148 /* Delay after an RCC peripheral clock enabling */ \ 1149 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ 1150 UNUSED(tmpreg); \ 1151 } while(0U) 1152 1153 #define __HAL_RCC_COMP_CLK_ENABLE() __HAL_RCC_SYSCFG_CLK_ENABLE() 1154 1155 #define __HAL_RCC_VREFBUF_CLK_ENABLE() __HAL_RCC_SYSCFG_CLK_ENABLE() 1156 1157 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1158 __IO uint32_t tmpreg; \ 1159 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ 1160 /* Delay after an RCC peripheral clock enabling */ \ 1161 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ 1162 UNUSED(tmpreg); \ 1163 } while(0U) 1164 1165 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1166 __IO uint32_t tmpreg; \ 1167 SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ 1168 /* Delay after an RCC peripheral clock enabling */ \ 1169 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ 1170 UNUSED(tmpreg); \ 1171 } while(0U) 1172 1173 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1174 __IO uint32_t tmpreg; \ 1175 SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ 1176 /* Delay after an RCC peripheral clock enabling */ \ 1177 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ 1178 UNUSED(tmpreg); \ 1179 } while(0U) 1180 1181 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1182 __IO uint32_t tmpreg; \ 1183 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ 1184 /* Delay after an RCC peripheral clock enabling */ \ 1185 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ 1186 UNUSED(tmpreg); \ 1187 } while(0U) 1188 1189 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1190 __IO uint32_t tmpreg; \ 1191 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ 1192 /* Delay after an RCC peripheral clock enabling */ \ 1193 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ 1194 UNUSED(tmpreg); \ 1195 } while(0U) 1196 1197 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 1198 __IO uint32_t tmpreg; \ 1199 SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ 1200 /* Delay after an RCC peripheral clock enabling */ \ 1201 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ 1202 UNUSED(tmpreg); \ 1203 } while(0U) 1204 1205 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) 1206 1207 #define __HAL_RCC_COMP_CLK_DISABLE() __HAL_RCC_SYSCFG_CLK_DISABLE() 1208 1209 #define __HAL_RCC_VREFBUF_CLK_DISABLE() __HAL_RCC_SYSCFG_CLK_DISABLE() 1210 1211 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) 1212 1213 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) 1214 1215 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) 1216 1217 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) 1218 1219 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) 1220 1221 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) 1222 1223 /** 1224 * @} 1225 */ 1226 1227 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status 1228 * @brief Check whether the AHB peripheral clock is enabled or not. 1229 * @note After reset, the peripheral clock (used for registers read/write access) 1230 * is disabled and the application software has to enable this clock before 1231 * using it. 1232 * @{ 1233 */ 1234 1235 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U) 1236 1237 #if defined (DMA2) 1238 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != 0U) 1239 #endif /*DMA2 */ 1240 1241 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != 0U) 1242 1243 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U) 1244 1245 #if defined (AES) 1246 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) != 0U) 1247 #endif /* AES */ 1248 1249 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != 0U) 1250 1251 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U) 1252 1253 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U) 1254 1255 #if defined (DMA2) 1256 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == 0U) 1257 #endif /* DMA2 */ 1258 1259 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == 0U) 1260 1261 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U) 1262 1263 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U) 1264 1265 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == 0U) 1266 1267 #if defined (AES) 1268 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) == 0U) 1269 #endif /* AES */ 1270 1271 /** 1272 * @} 1273 */ 1274 1275 /** @defgroup RCC__Peripheral_Clock_Enable_Disable_Status APB Peripheral Clock Enabled or Disabled Status 1276 * @brief Check whether the APB peripheral clock is enabled or not. 1277 * @note After reset, the peripheral clock (used for registers read/write access) 1278 * is disabled and the application software has to enable this clock before 1279 * using it. 1280 * @{ 1281 */ 1282 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U) 1283 1284 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U) 1285 1286 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U) 1287 1288 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U) 1289 1290 #define __HAL_RCC_LPUART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN) != 0U) 1291 1292 #if defined (LCD) 1293 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LCDEN) != 0U) 1294 #endif /* LCD */ 1295 1296 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U) 1297 1298 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U) 1299 1300 #if defined (LPUART3) 1301 #define __HAL_RCC_LPUART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART3EN) != 0U) 1302 #endif /* LPUART3 */ 1303 1304 #if defined (USB_DRD_FS) 1305 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U) 1306 #endif /* USB_DRD_FS */ 1307 1308 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U) 1309 1310 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U) 1311 #if defined(CRS) 1312 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U) 1313 #endif /* CRS */ 1314 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U) 1315 1316 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U) 1317 1318 #define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U) 1319 1320 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN) != 0U) 1321 1322 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U) 1323 1324 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U) 1325 1326 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U) 1327 1328 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_OPAMPEN) != 0U) 1329 #if defined(I2C4) 1330 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C4EN) != 0U) 1331 #endif /* I2C4 */ 1332 #if defined (LPTIM3) 1333 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM3EN) != 0U) 1334 #endif /* LPTIM3 */ 1335 1336 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U) 1337 1338 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U) 1339 1340 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U) 1341 1342 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1y_LPTIM1EN) != 0U) 1343 1344 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U) 1345 1346 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U) 1347 1348 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U) 1349 1350 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U) 1351 1352 #define __HAL_RCC_LPUART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN) == 0U) 1353 1354 #if defined (LCD) 1355 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LCDEN) == 0U) 1356 #endif /* LCD */ 1357 1358 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U) 1359 1360 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U) 1361 1362 #if defined (LPUART3) 1363 #define __HAL_RCC_LPUART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART3EN) == 0U) 1364 #endif /* LPUART3 */ 1365 1366 #if defined (USB_DRD_FS) 1367 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U) 1368 #endif /* USB_DRD_FS */ 1369 1370 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U) 1371 1372 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U) 1373 1374 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U) 1375 1376 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U) 1377 1378 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U) 1379 1380 #define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U) 1381 1382 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN) == 0U) 1383 1384 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U) 1385 1386 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U) 1387 1388 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U) 1389 1390 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_OPAMPEN) == 0U) 1391 1392 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C4EN) == 0U) 1393 1394 #if defined (LPTIM3) 1395 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM3EN) == 0U) 1396 #endif /* LPTIM3 */ 1397 1398 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U) 1399 1400 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U) 1401 1402 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U) 1403 1404 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U) 1405 /** 1406 * @} 1407 */ 1408 1409 /** @defgroup RCC_APB_2_Peripheral_Clock_Enable_Disable_Status APB_2 Peripheral Clock Enabled or Disabled Status 1410 * @brief Check whether the APB_2 peripheral clock is enabled or not. 1411 * @note After reset, the peripheral clock (used for registers read/write access) 1412 * is disabled and the application software has to enable this clock before 1413 * using it. 1414 * @{ 1415 */ 1416 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U) 1417 1418 #define __HAL_RCC_COMP_IS_CLK_DISABLED() __HAL_RCC_SYSCFG_IS_CLK_DISABLED() 1419 1420 #define __HAL_RCC_VREFBUF_IS_CLK_DISABLED() __HAL_RCC_SYSCFG_IS_CLK_DISABLED() 1421 1422 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U) 1423 1424 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U) 1425 1426 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U) 1427 1428 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U) 1429 1430 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U) 1431 1432 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U) 1433 1434 #define __HAL_RCC_COMP_IS_CLK_ENABLED() __HAL_RCC_SYSCFG_IS_CLK_ENABLED() 1435 1436 #define __HAL_RCC_VREFBUF_IS_CLK_ENABLED() __HAL_RCC_SYSCFG_IS_CLK_ENABLED() 1437 1438 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U) 1439 1440 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U) 1441 1442 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U) 1443 1444 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U) 1445 1446 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U) 1447 1448 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U) 1449 1450 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U) 1451 1452 /** 1453 * @} 1454 */ 1455 1456 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset 1457 * @brief Force or release AHB peripheral reset. 1458 * @{ 1459 */ 1460 1461 #define __HAL_RCC_AHB_FORCE_RESET() do { \ 1462 WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU); \ 1463 } while(0) 1464 1465 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) 1466 1467 #if defined (DMA2) 1468 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST) 1469 #endif /* DMA2 */ 1470 1471 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) 1472 1473 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) 1474 1475 #if defined (AES) 1476 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST) 1477 #endif /* AES */ 1478 1479 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST) 1480 1481 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_TSCRST) 1482 1483 #define __HAL_RCC_AHB_RELEASE_RESET() do { \ 1484 WRITE_REG(RCC->AHBRSTR, 0x00000000U); \ 1485 } while(0) 1486 1487 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) 1488 1489 #if defined (DMA2) 1490 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST) 1491 #endif /* DMA2 */ 1492 1493 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) 1494 1495 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) 1496 1497 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_TSCRST) 1498 1499 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST) 1500 1501 #if defined (AES) 1502 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST) 1503 #endif /* AES */ 1504 1505 /** 1506 * @} 1507 */ 1508 1509 /** @defgroup RCC_IOPRSTR_Force_Release_Reset IO Peripheral Force Release Reset 1510 * @brief Force or release IO peripheral reset. 1511 * @{ 1512 */ 1513 1514 #define __HAL_RCC_IOP_FORCE_RESET() do { \ 1515 WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU); \ 1516 } while(0) 1517 1518 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) 1519 1520 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) 1521 1522 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) 1523 1524 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) 1525 1526 #if defined(GPIOE) 1527 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST) 1528 #endif /* GPIOE */ 1529 1530 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) 1531 1532 #define __HAL_RCC_IOP_RELEASE_RESET() do { \ 1533 WRITE_REG(RCC->IOPRSTR, 0x00000000U); \ 1534 } while(0) 1535 1536 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) 1537 1538 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) 1539 1540 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) 1541 1542 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) 1543 1544 #if defined(GPIOE) 1545 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST) 1546 #endif /* GPIOE */ 1547 1548 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) 1549 1550 /** 1551 * @} 1552 */ 1553 1554 /** @defgroup RCC_APB_GRP1_Force_Release_Reset APB1_GRP1 Peripheral Force Release Reset 1555 * @brief Force or release APB peripheral reset. 1556 * @{ 1557 */ 1558 1559 #define __HAL_RCC_APB1_GRP1_FORCE_RESET() do { \ 1560 WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU); \ 1561 } while(0) 1562 1563 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) 1564 1565 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) 1566 1567 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST) 1568 1569 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST) 1570 1571 #define __HAL_RCC_LPUART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST) 1572 1573 #if defined (LCD) 1574 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LCDRST) 1575 #endif /* LCD */ 1576 1577 #if defined (LPUART3) 1578 #define __HAL_RCC_LPUART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART3RST) 1579 #endif /* LPUART3 */ 1580 1581 #if defined (USB_DRD_FS) 1582 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) 1583 #endif /* USB_DRD_FS */ 1584 1585 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) 1586 1587 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST) 1588 #if defined(CRS) 1589 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) 1590 #endif /* CRS */ 1591 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) 1592 1593 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) 1594 1595 #define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) 1596 1597 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST) 1598 1599 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) 1600 1601 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) 1602 1603 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST) 1604 1605 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_OPAMPRST) 1606 #if defined(I2C4) 1607 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C4RST) 1608 #endif /* I2C4 */ 1609 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) 1610 1611 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST) 1612 1613 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST) 1614 1615 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST) 1616 #if defined (LPTIM3) 1617 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM3RST) 1618 #endif /* LPTIM3 */ 1619 #define __HAL_RCC_APB1_GRP1_RELEASE_RESET() do { \ 1620 WRITE_REG(RCC->APBRSTR1, 0x00000000U); \ 1621 } while(0) 1622 1623 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) 1624 1625 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) 1626 1627 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST) 1628 1629 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST) 1630 1631 #define __HAL_RCC_LPUART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST) 1632 1633 #if defined (LCD) 1634 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LCDRST) 1635 #endif /* LCD */ 1636 1637 #if defined (LPUART3) 1638 #define __HAL_RCC_LPUART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART3RST) 1639 #endif /* LPUART3 */ 1640 1641 #if defined (USB_DRD_FS) 1642 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) 1643 #endif /* USB_DRD_FS */ 1644 1645 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) 1646 1647 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST) 1648 1649 #if defined(CRS) 1650 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) 1651 #endif /* CRS */ 1652 1653 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) 1654 1655 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) 1656 1657 #define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) 1658 1659 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST) 1660 1661 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) 1662 1663 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) 1664 1665 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST) 1666 1667 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_OPAMPRST) 1668 1669 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C4RST) 1670 1671 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) 1672 1673 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST) 1674 1675 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST) 1676 1677 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST) 1678 1679 #if defined (LPTIM3) 1680 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM3RST) 1681 #endif /* LPTIM3 */ 1682 /** 1683 * @} 1684 */ 1685 1686 /** @defgroup RCC_APB_GRP2_Force_Release_Reset APB1_GRP2 Peripheral Force Release Reset 1687 * @brief Force or release APB_2 peripheral reset. 1688 * @{ 1689 */ 1690 1691 #define __HAL_RCC_APB1_GRP2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU) 1692 1693 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) 1694 1695 #define __HAL_RCC_COMP_FORCE_RESET() __HAL_RCC_SYSCFG_FORCE_RESET() 1696 1697 #define __HAL_RCC_VREFBUF_FORCE_RESET() __HAL_RCC_SYSCFG_FORCE_RESET() 1698 1699 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) 1700 1701 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) 1702 1703 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) 1704 1705 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) 1706 1707 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) 1708 1709 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) 1710 1711 #define __HAL_RCC_APB1_GRP2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00000000U) 1712 1713 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) 1714 1715 #define __HAL_RCC_COMP_RELEASE_RESET() __HAL_RCC_SYSCFG_RELEASE_RESET() 1716 1717 #define __HAL_RCC_VREFBUF_RELEASE_RESET() __HAL_RCC_SYSCFG_RELEASE_RESET() 1718 1719 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) 1720 1721 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) 1722 1723 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) 1724 1725 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) 1726 1727 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) 1728 1729 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) 1730 1731 /** 1732 * @} 1733 */ 1734 1735 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB1_GRP1 Peripheral Clock Sleep Enable Disable 1736 * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode. 1737 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1738 * power consumption. 1739 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1740 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1741 * @{ 1742 */ 1743 1744 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) 1745 1746 #if defined (DMA2) 1747 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) 1748 #endif /* DMA2 */ 1749 1750 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) 1751 1752 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAM1SMEN) 1753 1754 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) 1755 1756 #if defined (AES) 1757 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) 1758 #endif /* AES */ 1759 1760 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) 1761 1762 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) 1763 1764 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) 1765 1766 #if defined (DMA2) 1767 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) 1768 #endif /* DMA2 */ 1769 1770 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) 1771 1772 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAM1SMEN) 1773 1774 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) 1775 1776 #if defined (AES) 1777 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) 1778 #endif /* AES */ 1779 1780 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) 1781 1782 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) 1783 1784 /** 1785 * @} 1786 */ 1787 1788 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable 1789 * @brief Enable or disable the IOPORT clock during Low Power (Sleep) mode. 1790 * @note IOPORT clock gating in SLEEP mode can be used to further reduce 1791 * power consumption. 1792 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1793 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1794 * @{ 1795 */ 1796 1797 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) 1798 1799 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) 1800 1801 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) 1802 1803 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) 1804 1805 #if defined (GPIOE) 1806 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) 1807 #endif /* GPIOE */ 1808 1809 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) 1810 1811 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) 1812 1813 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) 1814 1815 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) 1816 1817 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) 1818 1819 #if defined (GPIOE) 1820 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) 1821 #endif /* GPIOE */ 1822 1823 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) 1824 1825 /** 1826 * @} 1827 */ 1828 1829 /** @defgroup RCC_APB_Clock_Sleep_Enable_Disable APB Peripheral Clock Sleep Enable Disable 1830 * @brief Enable or disable the APB peripheral clock during Low Power (Sleep) mode. 1831 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1832 * power consumption. 1833 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1834 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1835 * @{ 1836 */ 1837 1838 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) 1839 1840 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) 1841 1842 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) 1843 1844 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) 1845 1846 #define __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN) 1847 1848 #if defined (LCD) 1849 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LCDSMEN) 1850 #endif /* LCD */ 1851 1852 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) 1853 1854 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) 1855 1856 #if defined (LPUART3) 1857 #define __HAL_RCC_LPUART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART3SMEN) 1858 #endif /* LPUART3 */ 1859 1860 #if defined (USB_DRD_FS) 1861 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) 1862 #endif /* USB_DRD_FS */ 1863 1864 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) 1865 1866 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) 1867 #if defined(CRS) 1868 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) 1869 #endif /* CRS */ 1870 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) 1871 1872 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) 1873 1874 #define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) 1875 1876 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN) 1877 1878 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) 1879 1880 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) 1881 1882 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) 1883 1884 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_OPAMPSMEN) 1885 #if defined(I2C4) 1886 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C4SMEN) 1887 #endif /* I2C4 */ 1888 #if defined (LPTIM3) 1889 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM3SMEN) 1890 #endif /* LPTIM3 */ 1891 1892 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) 1893 1894 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) 1895 1896 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) 1897 1898 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) 1899 1900 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) 1901 1902 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) 1903 1904 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) 1905 1906 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) 1907 1908 #define __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN) 1909 1910 #if defined (LCD) 1911 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LCDSMEN) 1912 #endif /* LCD */ 1913 1914 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) 1915 1916 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) 1917 1918 #if defined (LPUART3) 1919 #define __HAL_RCC_LPUART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART3SMEN) 1920 #endif /* LPUART3 */ 1921 1922 #if defined (USB_DRD_FS) 1923 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) 1924 #endif /* USB_DRD_FS */ 1925 1926 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) 1927 1928 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) 1929 1930 #if defined(CRS) 1931 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) 1932 #endif /* CRS */ 1933 1934 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) 1935 1936 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) 1937 1938 #define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) 1939 1940 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN) 1941 1942 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) 1943 1944 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) 1945 1946 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) 1947 1948 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_OPAMPSMEN) 1949 1950 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C4SMEN) 1951 1952 #if defined (LPTIM3) 1953 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM3SMEN) 1954 #endif /* LPTIM3 */ 1955 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) 1956 1957 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) 1958 1959 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) 1960 1961 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) 1962 1963 /** 1964 * @} 1965 */ 1966 1967 /** @defgroup RCC_APB1_GRP2_Clock_Sleep_Enable_Disable APB1_GRP2 Peripheral Clock Sleep Enable Disable 1968 * @brief Enable or disable the APB peripheral clock during Low Power (Sleep) mode. 1969 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1970 * power consumption. 1971 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1972 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1973 * @{ 1974 */ 1975 1976 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) 1977 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() 1978 #define __HAL_RCC_VREFBUF_CLK_SLEEP_ENABLE() __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() 1979 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) 1980 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) 1981 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) 1982 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) 1983 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) 1984 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) 1985 1986 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) 1987 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() 1988 #define __HAL_RCC_VREFBUF_CLK_SLEEP_DISABLE() __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() 1989 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) 1990 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) 1991 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) 1992 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) 1993 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) 1994 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) 1995 1996 /** 1997 * @} 1998 */ 1999 2000 /** @defgroup RCC_DBGMCU Enable , Disable , Force_Reset and Release_Reset 2001 * @brief Enable or Disable, Force or Release DBGMCU. 2002 * @{ 2003 */ 2004 #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ 2005 __IO uint32_t tmpreg; \ 2006 SET_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN); \ 2007 /* Delay after an RCC peripheral clock enabling */ \ 2008 tmpreg = READ_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN); \ 2009 UNUSED(tmpreg); \ 2010 } while(0) 2011 2012 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN) != 0U) 2013 2014 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN) 2015 2016 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGEN) == 0U) 2017 2018 #define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGRST) 2019 2020 #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->DBGCFGR, RCC_DBGCFGR_DBGRST) 2021 2022 /** 2023 * @} 2024 */ 2025 2026 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2027 * @{ 2028 */ 2029 2030 /** @brief Macros to force or release the Vswitch Backup domain reset. 2031 * @note This function resets the RTC peripheral (including the backup registers) 2032 * and the RTC clock source selection in RCC_CSR register. 2033 * @note The BKPSRAM is not affected by this reset. 2034 * @retval None 2035 */ 2036 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2037 2038 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2039 2040 /** 2041 * @} 2042 */ 2043 2044 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2045 * @{ 2046 */ 2047 2048 /** @brief Macros to enable or disable the RTC clock. 2049 * @note As the RTC is in the Backup domain and write access is denied to 2050 * this domain after reset, you have to enable write access using 2051 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 2052 * (to be done once after reset). 2053 * @note These macros must be used after the RTC clock source was selected. 2054 * @retval None 2055 */ 2056 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2057 2058 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2059 2060 /** 2061 * @} 2062 */ 2063 2064 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 2065 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 2066 * It is used (enabled by hardware) as system clock source after startup 2067 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 2068 * of the HSE used directly or indirectly as system clock (if the Clock 2069 * Security System CSS is enabled). 2070 * @note HSI can not be stopped if it is used as system clock source. In this case, 2071 * you have to select another source of the system clock then stop the HSI. 2072 * @note After enabling the HSI, the application software should wait on HSIRDY 2073 * flag to be set indicating that HSI clock is stable and can be used as 2074 * system clock source. 2075 * This parameter can be: ENABLE or DISABLE. 2076 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2077 * clock cycles. 2078 * @retval None 2079 */ 2080 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 2081 2082 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 2083 2084 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 2085 * @note The calibration is used to compensate for the variations in voltage 2086 * and temperature that influence the frequency of the internal HSI RC. 2087 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 2088 * (default is RCC_HSICALIBRATION_DEFAULT). 2089 * This parameter must be a number between 0 and 127. 2090 * @retval None 2091 */ 2092 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 2093 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 2094 2095 /** 2096 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2097 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 2098 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2099 * speed because of the HSI startup time. 2100 * @note The enable of this function has not effect on the HSION bit. 2101 * This parameter can be: ENABLE or DISABLE. 2102 * @retval None 2103 */ 2104 #define __HAL_RCC_HSI_STOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 2105 2106 #define __HAL_RCC_HSI_STOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 2107 2108 /** 2109 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 2110 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 2111 * @note The enable of this function has not effect on the HSION bit. 2112 * This parameter can be: ENABLE or DISABLE. 2113 * @retval None 2114 */ 2115 #define __HAL_RCC_HSI_AUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 2116 2117 #define __HAL_RCC_HSI_AUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 2118 2119 /** 2120 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 2121 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 2122 * It is used (enabled by hardware) as system clock source after 2123 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 2124 * of failure of the HSE used directly or indirectly as system clock 2125 * (if the Clock Security System CSS is enabled). 2126 * @note MSI can not be stopped if it is used as system clock source. 2127 * In this case, you have to select another source of the system 2128 * clock then stop the MSI. 2129 * @note After enabling the MSI, the application software should wait on 2130 * MSIRDY flag to be set indicating that MSI clock is stable and can 2131 * be used as system clock source. 2132 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 2133 * clock cycles. 2134 * @retval None 2135 */ 2136 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 2137 2138 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 2139 2140 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 2141 * @note The calibration is used to compensate for the variations in voltage 2142 * and temperature that influence the frequency of the internal MSI RC. 2143 * Refer to the Application Note AN3300 for more details on how to 2144 * calibrate the MSI. 2145 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 2146 * (default is RCC_MSICALIBRATION_DEFAULT). 2147 * This parameter must be a number between 0 and 255. 2148 * @retval None 2149 */ 2150 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 2151 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) 2152 2153 /** 2154 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 2155 * @note After restart from Reset , the MSI clock is around 4 MHz. 2156 * After stop the startup clock can be MSI (at any of its possible 2157 * frequencies, the one that was used before entering stop mode) or HSI. 2158 * After Standby its frequency can be selected between 4 possible values 2159 * (1, 2, 4 or 8 MHz). 2160 * @note MSISRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 2161 * (MSIRDY=1). 2162 * @note The MSI clock range after reset can be modified on the fly. 2163 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 2164 * This parameter must be one of the following values: 2165 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 2166 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 MHz 2167 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 2168 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 2169 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 2170 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2171 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz 2172 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 2173 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 400 KHz 2174 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 200 KHz 2175 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 150 KHz 2176 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 100 KHz 2177 * @retval None 2178 */ 2179 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 2180 do { \ 2181 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 2182 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 2183 } while(0) 2184 2185 /** 2186 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 2187 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 2188 * @param __MSISRANGEVALUE__ specifies the MSI clock range. 2189 * This parameter must be one of the following values: 2190 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2191 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2192 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2193 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2194 * @retval None 2195 */ 2196 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSISRANGEVALUE__) \ 2197 MODIFY_REG(RCC->CSR, RCC_CSR_MSISTBYRG, (__MSISRANGEVALUE__) << 4U) 2198 2199 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 2200 * @retval MSI clock range. 2201 * This parameter must be one of the following values: 2202 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 2203 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 2204 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 2205 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 2206 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2207 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2208 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2209 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2210 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2211 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2212 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2213 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2214 */ 2215 #define __HAL_RCC_GET_MSI_RANGE() \ 2216 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ 2217 READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ 2218 (READ_BIT(RCC->CSR, RCC_CSR_MSISTBYRG) >> 4U)) 2219 2220 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 2221 * @note After enabling the LSI, the application software should wait on 2222 * LSIRDY flag to be set indicating that LSI clock is stable and can 2223 * be used to clock the IWDG and/or the RTC. 2224 * @note LSI can not be disabled if the IWDG is running. 2225 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 2226 * clock cycles. 2227 * @retval None 2228 */ 2229 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 2230 2231 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 2232 2233 /** 2234 * @brief Macro to configure the External High Speed oscillator (HSE). 2235 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 2236 * supported by this macro. User should request a transition to HSE Off 2237 * first and then HSE On or HSE Bypass. 2238 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 2239 * software should wait on HSERDY flag to be set indicating that HSE clock 2240 * is stable and can be used to clock the PLL and/or system clock. 2241 * @note HSE state can not be changed if it is used directly or through the 2242 * PLL as system clock. In this case, you have to select another source 2243 * of the system clock then change the HSE state (ex. disable it). 2244 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 2245 * @note This function reset the CSSON bit, so if the clock security system(CSS) 2246 * was previously enabled you have to enable it again after calling this 2247 * function. 2248 * @param __STATE__: specifies the new state of the HSE. 2249 * This parameter can be one of the following values: 2250 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 2251 * 6 HSE oscillator clock cycles. 2252 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 2253 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 2254 * @retval None 2255 */ 2256 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 2257 do { \ 2258 if((__STATE__) == RCC_HSE_ON) \ 2259 { \ 2260 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2261 } \ 2262 else if((__STATE__) == RCC_HSE_BYPASS) \ 2263 { \ 2264 SET_BIT(RCC->CR, (RCC_CR_HSEBYP | RCC_CR_HSEON)); \ 2265 } \ 2266 else \ 2267 { \ 2268 CLEAR_BIT(RCC->CR, (RCC_CR_HSEON | RCC_CR_HSEBYP)); \ 2269 } \ 2270 } while(0) 2271 2272 /** 2273 * @brief Macro to configure the External Low Speed oscillator (LSE). 2274 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 2275 * supported by this macro. User should request a transition to LSE Off 2276 * first and then LSE On or LSE Bypass. 2277 * @note As the LSE is in the Backup domain and write access is denied to 2278 * this domain after reset, you have to enable write access using 2279 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2280 * (to be done once after reset). 2281 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2282 * software should wait on LSERDY flag to be set indicating that LSE clock 2283 * is stable and can be used to clock the RTC. 2284 * @param __STATE__ specifies the new state of the LSE. 2285 * This parameter can be one of the following values: 2286 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2287 * 6 LSE oscillator clock cycles. 2288 * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. 2289 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. 2290 * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. 2291 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock 2292 to be used by any peripheral. 2293 * @retval None 2294 */ 2295 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 2296 do { \ 2297 if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ 2298 { \ 2299 SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ 2300 } \ 2301 else if((__STATE__) == RCC_LSE_ON) \ 2302 { \ 2303 SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 2304 } \ 2305 else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ 2306 { \ 2307 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2308 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2309 } \ 2310 else if((__STATE__) == RCC_LSE_BYPASS) \ 2311 { \ 2312 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2313 SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 2314 } \ 2315 else \ 2316 { \ 2317 CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 2318 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2319 } \ 2320 } while(0) 2321 2322 /** @brief Macro to set Low-speed clock (LSI) divider. 2323 * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). 2324 * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. 2325 * 2326 * @param __DIVIDER__ : specifies the divider value 2327 * This parameter can be one of the following values 2328 * @arg @ref RCC_LSI_DIV1 2329 * @arg @ref RCC_LSI_DIV128 2330 * @retval None 2331 */ 2332 #define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) \ 2333 do { \ 2334 if((__DIVIDER__) == RCC_LSI_DIV128) \ 2335 { \ 2336 SET_BIT(RCC->CSR, RCC_CSR_LSIPREDIV); \ 2337 } \ 2338 else \ 2339 { \ 2340 CLEAR_BIT(RCC->CSR, RCC_CSR_LSIPREDIV);\ 2341 } \ 2342 } while(0) 2343 #if defined(RCC_CRRCR_HSI48ON) 2344 /** @brief Macros to enable or disable the RC 48MHz oscillator (RC48). 2345 * @note The RC48 is stopped by hardware when entering STOP and STANDBY modes. 2346 * @note After enabling the RC48, the application software should wait on HSI48RDY 2347 * flag to be set indicating that RC48 clock is stable. 2348 * This parameter can be: ENABLE or DISABLE. 2349 * @retval None 2350 */ 2351 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 2352 2353 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 2354 #endif /* RCC_CRRCR_HSI48ON */ 2355 /** @brief Macros to configure the RTC clock (RTCCLK). 2356 * @note As the RTC clock configuration bits are in the Backup domain and write 2357 * access is denied to this domain after reset, you have to enable write 2358 * access using the Power Backup Access macro before to configure 2359 * the RTC clock source (to be done once after reset). 2360 * @note Once the RTC clock is configured it cannot be changed unless the 2361 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 2362 * a Power On Reset (POR). 2363 * 2364 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 2365 * This parameter can be one of the following values: 2366 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 2367 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2368 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2369 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2370 * 2371 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 2372 * work in STOP and STANDBY modes, and can be used as wakeup source. 2373 * However, when the HSE clock is used as RTC clock source, the RTC 2374 * cannot be used in STOP and STANDBY modes. 2375 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 2376 * RTC clock source). 2377 * @retval None 2378 */ 2379 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 2380 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 2381 2382 /** @brief Macro to get the RTC clock source. 2383 * @retval The returned value can be one of the following: 2384 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 2385 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2386 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2387 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2388 */ 2389 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 2390 2391 /** @brief Macros to enable or disable the main PLL. 2392 * @note After enabling the main PLL, the application software should wait on 2393 * PLLRDY flag to be set indicating that PLL clock is stable and can 2394 * be used as system clock source. 2395 * @note The main PLL can not be disabled if it is used as system clock source 2396 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 2397 * @retval None 2398 */ 2399 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 2400 2401 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 2402 2403 /** @brief Macro to configure the PLL clock source. 2404 * @note This function must be used only when the main PLL is disabled. 2405 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2406 * This parameter can be one of the following values: 2407 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2408 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 2409 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2410 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2411 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 2412 * @retval None 2413 * 2414 */ 2415 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 2416 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 2417 2418 /** @brief Macro to configure the PLL source division factor M. 2419 * @note This function must be used only when the main PLL is disabled. 2420 * @param __PLLM__ specifies the division factor for PLL VCO input clock 2421 * This parameter must be a number between Min_Data = 1 and Max_Data = 8. 2422 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2423 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 2424 * of 16 MHz to limit PLL jitter. 2425 * @retval None 2426 * 2427 */ 2428 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 2429 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 2430 2431 /** 2432 * @brief Macro to configures the main PLL clock source, multiplication and division factors. 2433 * @note This function must be used only when the main PLL is disabled. 2434 * 2435 * @param __PLLSOURCE__: specifies the PLL entry clock source. 2436 * This parameter can be one of the following values: 2437 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 2438 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 2439 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 2440 * 2441 * @param __PLLM__: specifies the division factor for PLL VCO input clock 2442 * This parameter must be a number between 1 and 63. 2443 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2444 * frequency ranges from 1 to 16 MHz. 2445 * 2446 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock 2447 * This parameter must be a number between 4 and 127. 2448 * @note You have to set the PLLN parameter correctly to ensure that the VCO 2449 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 2450 * between 192 and 836 MHZ (when in wide VCO range) 2451 * 2452 * @param __PLLP__: specifies the division factor for system clock. 2453 * This parameter must be a number between 2 and 32 2454 * 2455 * @param __PLLQ__: specifies the division factor for peripheral kernel clocks 2456 * This parameter must be a number between 2 and 8 2457 * 2458 * @param __PLLR__: specifies the division factor for peripheral kernel clocks 2459 * This parameter must be a number between 2 and 8 2460 * 2461 * @retval None 2462 */ 2463 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 2464 MODIFY_REG(RCC->PLLCFGR, \ 2465 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 2466 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \ 2467 ((__PLLSOURCE__) | \ 2468 (__PLLM__) | \ 2469 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 2470 (__PLLQ__) | \ 2471 (__PLLR__) | \ 2472 (__PLLP__))) 2473 2474 /** @brief Macro to configure the PLL input clock division factor M. 2475 * 2476 * @note This function must be used only when the PLL is disabled. 2477 * @note PLL clock source is common with the main PLL (configured through 2478 * __HAL_RCC_PLL_CONFIG() macro) 2479 * 2480 * @param __PLLM__ specifies the division factor for PLL clock. 2481 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 2482 * 2483 * @retval None 2484 */ 2485 #define __HAL_RCC_PLL_DIVM_CONFIG(__PLLM__) \ 2486 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) 2487 2488 /** @brief Macro to get the oscillator used as PLL clock source. 2489 * @retval The oscillator used as PLL clock source. The returned value can be one 2490 * of the following: 2491 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 2492 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 2493 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 2494 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 2495 */ 2496 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 2497 2498 /** 2499 * @brief Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK, RCC_PLLPCLK) 2500 * @note Enabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK can be done at anytime 2501 * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot 2502 * be stopped if used as System Clock. 2503 * @note (*) RCC_PLLQCLK availability depends on devices 2504 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 2505 * This parameter can be one or a combination of the following values: 2506 * @arg @ref RCC_PLL_DIVP This clock is used to generate the clock for the ADC. 2507 * @arg @ref RCC_PLL_DIVQ This Clock is used to generate the clock for the High Speed Timers, 2508 * and the random analog generator (<=48 MHz). 2509 * @arg @ref RCC_PLL_DIVR This Clock is used to generate the high speed system clock (up to 48MHz) 2510 * @retval None 2511 */ 2512 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2513 2514 /** 2515 * @brief Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK, RCC_PLLPCLK) 2516 * @note Disabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK can be done at anytime 2517 * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot 2518 * be stopped if used as System Clock. 2519 * @note (*) RCC_PLLQCLK availability depends on devices 2520 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 2521 * This parameter can be one or a combination of the following values: 2522 * @arg @ref RCC_PLL_DIVP This clock may be used to generate the clock for the ADC, I2S1. 2523 * @arg @ref RCC_PLL_DIVQ This Clock may be used to generate the clock for the High Speed Timers, 2524 * and RNG (<=48 MHz). 2525 * @arg @ref RCC_PLL_DIVR This Clock is used to generate the high speed system clock (up to 48MHz) 2526 * @retval None 2527 */ 2528 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2529 2530 /** 2531 * @brief Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK, RCC_PLLPCLK) 2532 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 2533 * This parameter can be one of the following values: 2534 * @arg @ref RCC_PLL_DIVP This clock may be used to generate the clock for the ADC, I2S1. 2535 * @arg @ref RCC_PLL_DIVQ This Clock may be used to generate the clock for the High Speed Timers, 2536 * and RNG (<=48 MHz). 2537 * @arg @ref RCC_PLL_DIVR This Clock is used to generate the high speed system clock (up to 48MHz) 2538 * @retval SET / RESET 2539 * @note (*) RCC_PLLQCLK availability depends on devices 2540 * @retval SET / RESET 2541 */ 2542 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2543 2544 /** 2545 * @brief Macro to configure the system clock source. 2546 * @param __SYSCLKSOURCE__: specifies the system clock source. 2547 * This parameter can be one of the following values: 2548 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 2549 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 2550 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 2551 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 2552 * - RCC_SYSCLKSOURCE_LSI: LSI oscillator is used as system clock source. 2553 * - RCC_SYSCLKSOURCE_LSE: LSE oscillator is used as system clock source. 2554 * @retval None 2555 */ 2556 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 2557 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 2558 2559 /** @brief Macro to get the clock source used as system clock. 2560 * @retval The clock source used as system clock. The returned value can be one 2561 * of the following: 2562 * - RCC_SYSCLKSOURCE_MSI: MSI used as system clock. 2563 * - RCC_SYSCLKSOURCE_HSI: HSI used as system clock. 2564 * - RCC_SYSCLKSOURCE_HSE: HSE used as system clock. 2565 * - RCC_SYSCLKSOURCE_PLLCLK: PLL used as system clock. 2566 * - RCC_SYSCLKSOURCE_LSI: LSI used as system clock. 2567 * - RCC_SYSCLKSOURCE_LSE: LSE used as system clock. 2568 */ 2569 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) 2570 2571 /** 2572 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 2573 * @note As the LSE is in the Backup domain and write access is denied to 2574 * this domain after reset, you have to enable write access using 2575 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2576 * (to be done once after reset). 2577 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 2578 * This parameter can be one of the following values: 2579 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 2580 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 2581 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 2582 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 2583 * @retval None 2584 */ 2585 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 2586 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 2587 2588 /** 2589 * @brief Macro to configure the wake up from stop clock. 2590 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 2591 * This parameter can be one of the following values: 2592 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 2593 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 2594 * @retval None 2595 */ 2596 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 2597 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 2598 2599 /** @brief Macro to configure the MCO clock. 2600 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 2601 * This parameter can be one of the following values: 2602 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 2603 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 2604 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 2605 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 2606 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source 2607 * @arg @ref RCC_MCO1SOURCE_PLLR Main PLL clock selected as MCO source 2608 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 2609 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 2610 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 (*) 2611 * @param __MCODIV__ specifies the MCO clock prescaler. 2612 * This parameter can be one of the following values: 2613 * @arg @ref RCC_MCO1DIV_1 MCO clock source is divided by 1 2614 * @arg @ref RCC_MCO1DIV_2 MCO clock source is divided by 2 2615 * @arg @ref RCC_MCO1DIV_4 MCO clock source is divided by 4 2616 * @arg @ref RCC_MCO1DIV_8 MCO clock source is divided by 8 2617 * @arg @ref RCC_MCO1DIV_16 MCO clock source is divided by 16 2618 * @arg @ref RCC_MCO1DIV_32 MCO clock source is divided by 32 2619 * @arg @ref RCC_MCO1DIV_64 MCO clock source is divided by 64 2620 * @arg @ref RCC_MCO1DIV_128 MCO clock source is divided by 128 2621 * @arg @ref RCC_MCO1DIV_256 MCO clock source is divided by 256 2622 * @arg @ref RCC_MCO1DIV_512 MCO clock source is divided by 512 2623 * @arg @ref RCC_MCO1DIV_1024 MCO clock source is divided by 1024 2624 */ 2625 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 2626 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1SEL | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 2627 2628 /** @brief Macro to configure the MCO clock. 2629 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 2630 * This parameter can be one of the following values: 2631 * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO output disabled 2632 * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source 2633 * @arg @ref RCC_MCO2SOURCE_MSI MSI clock selected as MCO source 2634 * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO source 2635 * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO source 2636 * @arg @ref RCC_MCO2SOURCE_PLLR Main PLL clock selected as MCO source 2637 * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO source 2638 * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO source 2639 * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 (*) 2640 * @param __MCODIV__ specifies the MCO clock prescaler. 2641 * This parameter can be one of the following values: 2642 * @arg @ref RCC_MCO2DIV_1 MCO clock source is divided by 1 2643 * @arg @ref RCC_MCO2DIV_2 MCO clock source is divided by 2 2644 * @arg @ref RCC_MCO2DIV_4 MCO clock source is divided by 4 2645 * @arg @ref RCC_MCO2DIV_8 MCO clock source is divided by 8 2646 * @arg @ref RCC_MCO2DIV_16 MCO clock source is divided by 16 2647 * @arg @ref RCC_MCO2DIV_32 MCO clock source is divided by 32 2648 * @arg @ref RCC_MCO2DIV_64 MCO clock source is divided by 64 2649 * @arg @ref RCC_MCO2DIV_128 MCO clock source is divided by 128 2650 * @arg @ref RCC_MCO2DIV_256 MCO clock source is divided by 256 2651 * @arg @ref RCC_MCO2DIV_512 MCO clock source is divided by 512 2652 * @arg @ref RCC_MCO2DIV_1024 MCO clock source is divided by 1024 2653 */ 2654 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 2655 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 2656 2657 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 2658 * @brief macros to manage the specified RCC Flags and interrupts. 2659 * @{ 2660 */ 2661 2662 /** @brief Enable RCC interrupt (Perform access to RCC_CIER bits to enable 2663 * the selected interrupts). 2664 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 2665 * This parameter can be any combination of the following values: 2666 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 2667 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2668 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 2669 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2670 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2671 * @arg @ref RCC_IT_PLLRDY PLL ready interrupt 2672 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 2673 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (*) 2674 * @retval None 2675 */ 2676 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 2677 2678 /** @brief Disable RCC interrupt (Perform access to RCC_CIER bits to disable 2679 * the selected interrupts). 2680 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 2681 * This parameter can be any combination of the following values: 2682 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 2683 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2684 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 2685 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2686 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2687 * @arg @ref RCC_IT_PLLRDY PLL ready interrupt 2688 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 2689 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (*) 2690 * @retval None 2691 */ 2692 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 2693 2694 /** @brief Clear the RCC's interrupt pending bits (Perform access to RCC_CICR 2695 * bits to clear the selected interrupt pending bits. 2696 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 2697 * This parameter can be any combination of the following values: 2698 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 2699 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2700 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 2701 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2702 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2703 * @arg @ref RCC_IT_PLLRDY PLL ready interrupt 2704 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 2705 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (*) 2706 * @retval None 2707 */ 2708 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 2709 2710 /** @brief Check whether the RCC interrupt has occurred or not. 2711 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 2712 * This parameter can be one of the following values: 2713 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 2714 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2715 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 2716 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2717 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2718 * @arg @ref RCC_IT_PLLRDY PLL ready interrupt 2719 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 2720 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (*) 2721 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2722 */ 2723 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 2724 2725 /** @brief Set RMVF bit to clear the reset flags. 2726 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PADRST, RCC_FLAG_BORRST, 2727 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 2728 * @retval None 2729 */ 2730 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 2731 2732 /** @brief Check whether the selected RCC flag is set or not. 2733 * @param __FLAG__: specifies the flag to check. 2734 * This parameter can be one of the following values: 2735 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 2736 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 2737 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 2738 * @arg @ref RCC_FLAG_PLLRDY PLL clock ready 2739 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready (*) 2740 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 2741 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 2742 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 2743 * @arg @ref RCC_FLAG_PWRRST BOR reset 2744 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 2745 * @arg @ref RCC_FLAG_PINRST Pin reset 2746 * @arg @ref RCC_FLAG_RMV Remove reset Flag 2747 * @arg @ref RCC_FLAG_SFTRST Software reset 2748 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 2749 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 2750 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 2751 * @retval The new state of __FLAG__ (TRUE or FALSE). 2752 */ 2753 #if defined(RCC_CRRCR_HSI48ON) 2754 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 2755 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ 2756 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 2757 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 2758 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 2759 #else 2760 #define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 2761 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 2762 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 2763 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 2764 #endif /* HSI48 */ 2765 /** 2766 * @} 2767 */ 2768 2769 /** 2770 * @} 2771 */ 2772 2773 /* Private constants ---------------------------------------------------------*/ 2774 /** @defgroup RCC_Private_Constants RCC Private Constants 2775 * @{ 2776 */ 2777 #define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 2778 #define RCC_HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 2779 #define RCC_MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 2780 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 2781 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 2782 /* Defines used for Flags */ 2783 #define CR_REG_INDEX (1U) 2784 #define BDCR_REG_INDEX (2U) 2785 #define CSR_REG_INDEX (3U) 2786 #if defined(RCC_CRRCR_HSI48ON) 2787 #define CRRCR_REG_INDEX (4U) 2788 #endif /* RCC_CRRCR_HSI48ON */ 2789 #define CIFR_REG_INDEX (5U) 2790 #define RCC_FLAG_MASK (0x1FU) 2791 2792 /** 2793 * @} 2794 */ 2795 2796 /* Private macros ------------------------------------------------------------*/ 2797 /** @addtogroup RCC_Private_Macros 2798 * @{ 2799 */ 2800 #if defined(RCC_CRRCR_HSI48ON) 2801 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ 2802 (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 2803 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 2804 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 2805 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 2806 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 2807 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 2808 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 2809 #else 2810 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ 2811 (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 2812 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 2813 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 2814 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 2815 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 2816 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 2817 #endif /* RCC_CRRCR_HSI48ON */ 2818 2819 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 2820 ((__HSE__) == RCC_HSE_BYPASS)) 2821 2822 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 2823 ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ 2824 ((__LSE__) == RCC_LSE_BYPASS)) 2825 2826 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 2827 2828 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 2829 2830 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 2831 2832 #define IS_RCC_LSIDIV(__DIV__) (((__DIV__) == RCC_LSI_DIV1) || ((__DIV__) == RCC_LSI_DIV128)) 2833 2834 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 2835 2836 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) 2837 2838 #if defined(RCC_CRRCR_HSI48ON) 2839 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 2840 #endif /* RCC_CRRCR_HSI48ON */ 2841 2842 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ 2843 ((PLL) == RCC_PLL_ON)) 2844 2845 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ 2846 ((SOURCE) == RCC_PLLSOURCE_HSI) || \ 2847 ((SOURCE) == RCC_PLLSOURCE_NONE) || \ 2848 ((SOURCE) == RCC_PLLSOURCE_HSE)) 2849 2850 #define IS_RCC_PLL_DIVM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || ((__VALUE__) == RCC_PLLM_DIV2) || \ 2851 ((__VALUE__) == RCC_PLLM_DIV3) || ((__VALUE__) == RCC_PLLM_DIV4) || \ 2852 ((__VALUE__) == RCC_PLLM_DIV5) || ((__VALUE__) == RCC_PLLM_DIV6) || \ 2853 ((__VALUE__) == RCC_PLLM_DIV7) || ((__VALUE__) == RCC_PLLM_DIV8)) 2854 #define IS_RCC_PLL_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 127U)) 2855 #define IS_RCC_PLL_DIVP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) 2856 #define IS_RCC_PLL_DIVQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) 2857 #define IS_RCC_PLL_DIVR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) 2858 2859 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) ((((VALUE) & RCC_PLL_DIVP) == RCC_PLL_DIVP) || \ 2860 (((VALUE) & RCC_PLL_DIVQ) == RCC_PLL_DIVQ) || \ 2861 (((VALUE) & RCC_PLL_DIVR) == RCC_PLL_DIVR)) 2862 2863 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 2864 ((__RANGE__) == RCC_MSIRANGE_1) || \ 2865 ((__RANGE__) == RCC_MSIRANGE_2) || \ 2866 ((__RANGE__) == RCC_MSIRANGE_3) || \ 2867 ((__RANGE__) == RCC_MSIRANGE_4) || \ 2868 ((__RANGE__) == RCC_MSIRANGE_5) || \ 2869 ((__RANGE__) == RCC_MSIRANGE_6) || \ 2870 ((__RANGE__) == RCC_MSIRANGE_7) || \ 2871 ((__RANGE__) == RCC_MSIRANGE_8) || \ 2872 ((__RANGE__) == RCC_MSIRANGE_9) || \ 2873 ((__RANGE__) == RCC_MSIRANGE_10) || \ 2874 ((__RANGE__) == RCC_MSIRANGE_11)) 2875 2876 2877 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 2878 ((__RANGE__) == RCC_MSIRANGE_5) || \ 2879 ((__RANGE__) == RCC_MSIRANGE_6) || \ 2880 ((__RANGE__) == RCC_MSIRANGE_7)) 2881 2882 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) 2883 2884 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 2885 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 2886 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 2887 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)|| \ 2888 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \ 2889 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE)) 2890 2891 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 2892 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 2893 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 2894 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 2895 ((__HCLK__) == RCC_SYSCLK_DIV512)) 2896 2897 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 2898 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 2899 ((__PCLK__) == RCC_HCLK_DIV16)) 2900 2901 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 2902 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 2903 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 2904 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE)) 2905 2906 #define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1_PA8) || \ 2907 ((__MCOX__) == RCC_MCO1_PA9) || \ 2908 ((__MCOX__) == RCC_MCO1_PF2) || \ 2909 ((__MCOX__) == RCC_MCO2_PA10) || \ 2910 ((__MCOX__) == RCC_MCO2_PC2) || \ 2911 ((__MCOX__) == RCC_MCO2_PA8)) 2912 #if defined(RCC_MCO1SOURCE_HSI48) 2913 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 2914 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 2915 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 2916 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 2917 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 2918 ((__SOURCE__) == RCC_MCO1SOURCE_PLLR) || \ 2919 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 2920 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 2921 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \ 2922 ((__SOURCE__) == RCC_MCO1SOURCE_RTC_ALT) || \ 2923 ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WAKEUP)) 2924 #else 2925 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 2926 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 2927 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 2928 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 2929 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 2930 ((__SOURCE__) == RCC_MCO1SOURCE_PLLR) || \ 2931 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 2932 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 2933 ((__SOURCE__) == RCC_MCO1SOURCE_RTC_ALT) || \ 2934 ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WAKEUP)) 2935 #endif /* RCC_MCO1SOURCE_HSI48 */ 2936 #if defined(RCC_MCO2SOURCE_HSI48) 2937 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ 2938 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ 2939 ((__SOURCE__) == RCC_MCO2SOURCE_MSI) || \ 2940 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ 2941 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ 2942 ((__SOURCE__) == RCC_MCO2SOURCE_PLLR) || \ 2943 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ 2944 ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ 2945 ((__SOURCE__) == RCC_MCO2SOURCE_HSI48) || \ 2946 ((__SOURCE__) == RCC_MCO2SOURCE_RTC_ALT) || \ 2947 ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WAKEUP)) 2948 #else 2949 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ 2950 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ 2951 ((__SOURCE__) == RCC_MCO2SOURCE_MSI) || \ 2952 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ 2953 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ 2954 ((__SOURCE__) == RCC_MCO2SOURCE_PLLR) || \ 2955 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ 2956 ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ 2957 ((__SOURCE__) == RCC_MCO2SOURCE_RTC_ALT) || \ 2958 ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WAKEUP)) 2959 #endif /* RCC_MCO2SOURCE_HSI48 */ 2960 #define IS_RCC_MCO1DIV(__DIV__) (((__DIV__) == RCC_MCO1DIV_1) || ((__DIV__) == RCC_MCO1DIV_2) || \ 2961 ((__DIV__) == RCC_MCO1DIV_4) || ((__DIV__) == RCC_MCO1DIV_8) || \ 2962 ((__DIV__) == RCC_MCO1DIV_16)|| ((__DIV__) == RCC_MCO1DIV_32) || \ 2963 ((__DIV__) == RCC_MCO1DIV_64)|| ((__DIV__) == RCC_MCO1DIV_128)|| \ 2964 ((__DIV__) == RCC_MCO1DIV_256)|| ((__DIV__) == RCC_MCO1DIV_512)|| \ 2965 ((__DIV__) == RCC_MCO1DIV_1024)) 2966 2967 #define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ 2968 ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ 2969 ((__DIV__) == RCC_MCO2DIV_16)|| ((__DIV__) == RCC_MCO2DIV_32) || \ 2970 ((__DIV__) == RCC_MCO2DIV_64)|| ((__DIV__) == RCC_MCO2DIV_128)|| \ 2971 ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512)|| \ 2972 ((__DIV__) == RCC_MCO2DIV_1024)) 2973 2974 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 2975 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 2976 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 2977 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 2978 2979 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 2980 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 2981 2982 /** 2983 * @} 2984 */ 2985 2986 /* Include RCC HAL Extended module */ 2987 #include "stm32u0xx_hal_rcc_ex.h" 2988 2989 /* Exported functions --------------------------------------------------------*/ 2990 /** @addtogroup RCC_Exported_Functions 2991 * @{ 2992 */ 2993 2994 /** @addtogroup RCC_Exported_Functions_Group1 2995 * @{ 2996 */ 2997 2998 /* Initialization and de-initialization functions ******************************/ 2999 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3000 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3001 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const RCC_ClkInitStruct, uint32_t FLatency); 3002 3003 /** 3004 * @} 3005 */ 3006 3007 /** @addtogroup RCC_Exported_Functions_Group2 3008 * @{ 3009 */ 3010 3011 /* Peripheral Control functions ************************************************/ 3012 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3013 void HAL_RCC_EnableCSS(void); 3014 uint32_t HAL_RCC_GetSysClockFreq(void); 3015 uint32_t HAL_RCC_GetHCLKFreq(void); 3016 uint32_t HAL_RCC_GetPCLK1Freq(void); 3017 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3018 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 3019 uint32_t HAL_RCC_GetResetSource(void); 3020 /* CSS NMI IRQ handler */ 3021 void HAL_RCC_NMI_IRQHandler(void); 3022 /* User Callbacks in non blocking mode (IT mode) */ 3023 void HAL_RCC_CSSCallback(void); 3024 3025 /** 3026 * @} 3027 */ 3028 3029 /** 3030 * @} 3031 */ 3032 3033 /** 3034 * @} 3035 */ 3036 3037 /** 3038 * @} 3039 */ 3040 3041 /** 3042 * @} 3043 */ 3044 3045 #ifdef __cplusplus 3046 } 3047 #endif 3048 3049 #endif /* __STM32U0xx_HAL_RCC_H */ 3050
