1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32WBAxx_HAL_RCC_H 21 #define __STM32WBAxx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 #include "stm32wbaxx_ll_rcc.h" 30 31 /** @addtogroup STM32WBAxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCC_Exported_Types RCC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC PLL1 configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLLState; /*!< The new state of the PLL1. 50 This parameter can be a value of @ref RCC_PLL_Config */ 51 52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL1 entry clock source. 53 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 54 55 uint32_t PLLM; /*!< PLLM: Division factor for PLL1 VCO input clock. 56 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 57 58 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL1 VCO output clock. 59 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 60 61 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 62 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 63 64 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 65 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 66 67 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 68 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 69 70 uint32_t PLLFractional; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 71 PLL1 VCO It should be a value between 0 and 0x1FFF */ 72 73 } RCC_PLLInitTypeDef; 74 75 /** 76 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI1) configuration structure definition 77 */ 78 typedef struct 79 { 80 uint32_t OscillatorType; /*!< The oscillators to be configured. 81 This parameter can be a value of @ref RCC_Oscillator_Type */ 82 83 uint32_t HSEState; /*!< The new state of the HSE. 84 This parameter can be a value of @ref RCC_HSE_Config */ 85 86 uint32_t HSEDiv; /*!< The division factor of the HSE. Applicable only to SYSCLK when HSE is source. 87 This parameter can be a value of @ref RCC_HSE_Div */ 88 89 uint32_t LSEState; /*!< The new state of the LSE. 90 This parameter can be a value of @ref RCC_LSE_Config */ 91 92 uint32_t HSIState; /*!< The new state of the HSI. 93 This parameter can be a value of @ref RCC_HSI_Config */ 94 95 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 96 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 97 on the other devices */ 98 99 uint32_t LSIState; /*!< The new state of the LSI (LSI1 or LSI2 when applicable). 100 This parameter can be a value of @ref RCC_LSI_Config */ 101 102 uint32_t LSIDiv; /*!< The division factor of the LSI. Applicable only to LSI1. 103 This parameter can be a value of @ref RCC_LSI_Div */ 104 105 RCC_PLLInitTypeDef PLL1; /*!< Main PLL1 structure parameters */ 106 107 } RCC_OscInitTypeDef; 108 109 /** 110 * @brief RCC System, AHB and APB busses clock configuration structure definition 111 */ 112 typedef struct 113 { 114 uint32_t ClockType; /*!< The clock to be configured. 115 This parameter can be a value of @ref RCC_System_Clock_Type */ 116 117 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 118 This parameter can be a value of @ref RCC_System_Clock_Source */ 119 120 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 121 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 122 123 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 124 This parameter can be a value of @ref RCC_APB1_APB2_APB7_Clock_Source */ 125 126 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 127 This parameter can be a value of @ref RCC_APB1_APB2_APB7_Clock_Source */ 128 129 uint32_t APB7CLKDivider; /*!< The APB7 clock (PCLK7) divider. This clock is derived from the AHB clock (HCLK). 130 This parameter can be a value of @ref RCC_APB1_APB2_APB7_Clock_Source */ 131 132 uint32_t AHB5_PLL1_CLKDivider; /*!< The AHB5 clock (HCLK5) divider when PLL1 is source of SYSCLK. This clock is derived from the system clock (SYSCLK). 133 This parameter can be a value of @ref RCC_AHB5_PLL1_Clock_Source */ 134 135 uint32_t AHB5_HSEHSI_CLKDivider; /*!< The AHB5 clock (HCLK5) divider when HSI or HSE are sources of SYSCLK. This clock is derived from the system clock (SYSCLK). 136 This parameter can be a value of @ref RCC_AHB5_HSEHSI_Clock_Source */ 137 138 } RCC_ClkInitTypeDef; 139 140 /** 141 * @} 142 */ 143 144 /* Exported constants --------------------------------------------------------*/ 145 /** @defgroup RCC_Exported_Constants RCC Exported Constants 146 * @{ 147 */ 148 149 /** @defgroup RCC_Peripheral_Memory_Mapping Peripheral Memory Mapping 150 * @{ 151 */ 152 153 /** 154 * @} 155 */ 156 157 /** @defgroup RCC_Timeout_Value Timeout Values 158 * @{ 159 */ 160 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 161 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 162 /** 163 * @} 164 */ 165 166 /** @defgroup RCC_Oscillator_Type Oscillator Type 167 * @{ 168 */ 169 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 170 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE32 to configure */ 171 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI16 to configure */ 172 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 173 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 174 /** 175 * @} 176 */ 177 178 /** @defgroup RCC_HSE_Config HSE Config 179 * @{ 180 */ 181 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 182 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 183 /** 184 * @} 185 */ 186 187 /** @defgroup RCC_HSE_Div HSE Div 188 * @{ 189 */ 190 #define RCC_HSE_DIV1 0x00000000U /*!< HSE clock divided by 1 for SYSCLK */ 191 #define RCC_HSE_DIV2 RCC_CR_HSEPRE /*!< HSE clock divided by 2 for SYSCLK */ 192 /** 193 * @} 194 */ 195 196 /** @defgroup RCC_LSE_Config LSE Config 197 * @{ 198 */ 199 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 200 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR1_LSEON /*!< LSE clock activation for RTC only */ 201 #define RCC_LSE_ON (RCC_BDCR1_LSESYSEN | RCC_BDCR1_LSEON) /*!< LSE clock activation for RCC and peripherals */ 202 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR1_LSEBYP | RCC_BDCR1_LSEON) /*!< External clock source for LSE clock */ 203 #define RCC_LSE_BYPASS (RCC_BDCR1_LSEBYP | RCC_BDCR1_LSESYSEN | RCC_BDCR1_LSEON) /*!< External clock source for LSE clock */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup RCC_HSI_Config HSI Config 209 * @{ 210 */ 211 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 212 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 213 214 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup RCC_LSI_Config LSI Config 220 * @{ 221 */ 222 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 223 #define RCC_LSI1_ON RCC_BDCR1_LSI1ON /*!< LSI1 clock activation */ 224 #if defined(RCC_LSI2_SUPPORT) 225 #define RCC_LSI2_ON RCC_BDCR1_LSI2ON /*!< LSI2 clock activation */ 226 #endif 227 /** 228 * @} 229 */ 230 231 /** @defgroup RCC_LSI_Div LSI Div 232 * @{ 233 */ 234 #define RCC_LSI_DIV1 0U /*!< LSI1 clock is not divided */ 235 #define RCC_LSI_DIV128 RCC_BDCR1_LSI1PREDIV /*!< LSI1 clock is divided by 128 */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup RCC_PLL_Config RCC PLL1 Config 241 * @{ 242 */ 243 #define RCC_PLL_NONE 0x00000000U 244 #define RCC_PLL_OFF 0x00000001U 245 #define RCC_PLL_ON 0x00000002U 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_PLL_Clock_Source RCC PLL1 Clock Source 251 * @{ 252 */ 253 #define RCC_PLLSOURCE_NONE 0x00000000U 254 #define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 255 #define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_1 | RCC_PLL1CFGR_PLL1SRC_0) 256 /** 257 * @} 258 */ 259 260 /** @defgroup RCC_PLL_Clock_Output RCC PLL1 Clock Output 261 * @{ 262 */ 263 #define RCC_PLL1_PCLK RCC_PLL1CFGR_PLL1PEN 264 #define RCC_PLL1_QCLK RCC_PLL1CFGR_PLL1QEN 265 #define RCC_PLL1_RCLK RCC_PLL1CFGR_PLL1REN 266 /** 267 * @} 268 */ 269 270 /** @defgroup RCC_PLL_VCO_Input_Range RCC PLL1 VCO Input Range 271 * @{ 272 */ 273 #define RCC_PLL_VCOINPUT_RANGE0 0x00000000U 274 #define RCC_PLL_VCOINPUT_RANGE1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0) 275 /** 276 * @} 277 */ 278 279 /** @defgroup RCC_System_Clock_Type System Clock Type 280 * @{ 281 */ 282 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 283 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 284 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 285 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 286 #define RCC_CLOCKTYPE_PCLK7 0x00000010U /*!< PCLK7 to configure */ 287 #define RCC_CLOCKTYPE_HCLK5 0x00000020U /*!< HCLK5 to configure */ 288 /** 289 * @} 290 */ 291 292 /** @defgroup RCC_System_Clock_Source System Clock Source 293 * @{ 294 */ 295 #define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI16 selection as system clock */ 296 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE32 or HSE32/32 (depending on HSEPRE) selection as system clock */ 297 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1R selection as system clock */ 298 /** 299 * @} 300 */ 301 302 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 303 * @{ 304 */ 305 #define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI16 used as system clock */ 306 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE32 or HSE32/32 (depending on HSEPRE) used as system clock */ 307 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1R used as system clock */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 313 * @{ 314 */ 315 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 316 #define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_2 /*!< SYSCLK divided by 2 */ 317 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */ 318 #define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */ 319 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */ 320 /** 321 * @} 322 */ 323 324 /** @defgroup RCC_APB1_APB2_APB7_Clock_Source APB1 APB2 APB7 Clock Source 325 * @{ 326 */ 327 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 328 #define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 329 #define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */ 330 #define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */ 331 #define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */ 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCC_AHB5_PLL1_Clock_Source AHB5 PLL1 Clock Source 337 * @{ 338 */ 339 #define RCC_SYSCLK_PLL1_DIV1 0x00000000U /*!< SYSCLK when PLL1 is source not divided */ 340 #define RCC_SYSCLK_PLL1_DIV2 RCC_CFGR4_HPRE5_2 /*!< SYSCLK when PLL1 is source divided by 2 */ 341 #define RCC_SYSCLK_PLL1_DIV3 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK when PLL1 is source divided by 3 */ 342 #define RCC_SYSCLK_PLL1_DIV4 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1) /*!< SYSCLK when PLL1 is source divided by 4 */ 343 #define RCC_SYSCLK_PLL1_DIV6 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK when PLL1 is source divided by 6 */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup RCC_AHB5_HSEHSI_Clock_Source AHB5 HSEHSI Clock Source 349 * @{ 350 */ 351 #define RCC_SYSCLK_HSEHSI_DIV1 0x00000000U /*!< SYSCLK when HSE or HSI is source not divided */ 352 #define RCC_SYSCLK_HSEHSI_DIV2 RCC_CFGR4_HDIV5 /*!< SYSCLK when HSE or HSI is source divided by 2 */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 358 * @{ 359 */ 360 #define RCC_RTCCLKSOURCE_DISABLE 0x00000000U /*!< RTC clock is disabled */ 361 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 362 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR1_RTCSEL_1 /*!< LSI1 or LIS2 oscillator clock used as RTC clock */ 363 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR1_RTCSEL /*!< HSE32 oscillator clock divided by 32 used as RTC clock */ 364 /** 365 * @} 366 */ 367 368 /** @defgroup RCC_MCO_Index MCO Index 369 * @{ 370 */ 371 #define RCC_MCO1 0x00000000U 372 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 373 /** 374 * @} 375 */ 376 377 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 378 * @{ 379 */ 380 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 381 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 382 #define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_0) /*!< HSI16 selection as MCO1 source */ 383 #define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE32 selection as MCO1 source */ 384 #define RCC_MCO1SOURCE_PLL1RCLK (RCC_CFGR1_MCOSEL_2 | RCC_CFGR1_MCOSEL_0) /*!< PLL1RCLK selection as MCO1 source */ 385 #define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_2 | RCC_CFGR1_MCOSEL_1) /*!< LSI selection as MCO1 source */ 386 #define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_2 | RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_0) /*!< LSE selection as MCO1 source */ 387 #define RCC_MCO1SOURCE_PLL1PCLK RCC_CFGR1_MCOSEL_3 /*!< PLL1PCLK selection as MCO1 source */ 388 #define RCC_MCO1SOURCE_PLL1QCLK (RCC_CFGR1_MCOSEL_3 | RCC_CFGR1_MCOSEL_0) /*!< PLL1QCLK selection as MCO1 source */ 389 #define RCC_MCO1SOURCE_HCLK5 (RCC_CFGR1_MCOSEL_3 | RCC_CFGR1_MCOSEL_1) /*!< HCLK5 selection as MCO1 source */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 395 * @{ 396 */ 397 #define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */ 398 #define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */ 399 #define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */ 400 #define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO is divided by 8 */ 401 #define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */ 402 /** 403 * @} 404 */ 405 406 #if defined(RCC_CCIPR2_ASSEL) 407 /** @defgroup RCC_Interrupt Interrupts 408 * Elements values convention: XXXYYYYYb 409 * - YYYYY : Flag position in the register 410 * - XXX : Register index 411 * - 000: CIFR register 412 * - 001: ASSR register 413 * @{ 414 */ 415 /* Flags in the CIFR register */ 416 #define RCC_IT_LSI1RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSI1RDYF_Pos) /*!< LSI1 Ready Interrupt flag */ 417 #define RCC_IT_LSERDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSERDYF_Pos) /*!< LSE Ready Interrupt flag */ 418 #define RCC_IT_HSIRDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSIRDYF_Pos) /*!< HSI16 Ready Interrupt flag */ 419 #define RCC_IT_HSERDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSERDYF_Pos) /*!< HSE Ready Interrupt flag */ 420 #define RCC_IT_PLL1RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_PLL1RDYF_Pos) /*!< PLL1 Ready Interrupt flag */ 421 #define RCC_IT_CSS ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSECSSF_Pos) /*!< HSE32 Clock Security System Interrupt flag */ 422 #if defined(RCC_LSI2_SUPPORT) 423 #define RCC_IT_LSI2RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSI2RDYF_Pos) /*!< LSI2 Ready Interrupt flag */ 424 #endif /* RCC_BDCR1_LSI2ON */ 425 426 /* Flags in the ASSR register */ 427 #define RCC_IT_CAPTURE_ERROR ((ASSR_REG_INDEX << 5U) | RCC_ASSR_CAEF_Pos) /*!< Capture Error Interrupt flag */ 428 #define RCC_IT_COMPARER ((ASSR_REG_INDEX << 5U) | RCC_ASSR_COF_Pos) /*!< Comparer Interrupt flag */ 429 #define RCC_IT_CAPTURE_TRIGGER ((ASSR_REG_INDEX << 5U) | RCC_ASSR_CAF_Pos) /*!< Capture Trigger Interrupt flag */ 430 /** 431 * @} 432 */ 433 #else 434 /** @defgroup RCC_Interrupt Interrupts 435 * @{ 436 */ 437 #define RCC_IT_LSI1RDY RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */ 438 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 439 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 440 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 441 #define RCC_IT_PLL1RDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ 442 #define RCC_IT_CSS RCC_CIFR_HSECSSF /*!< HSE32 Clock Security System Interrupt flag */ 443 #if defined(RCC_LSI2_SUPPORT) 444 #define RCC_IT_LSI2RDY RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */ 445 #endif /* RCC_BDCR1_LSI2ON */ 446 /** 447 * @} 448 */ 449 #endif /* RCC_CCIPR2_ASSEL */ 450 451 /** @defgroup RCC_Flag Flags 452 * Elements values convention: XXXYYYYYb 453 * - YYYYY : Flag position in the register 454 * - XXX : Register index 455 * - 001: CR register 456 * - 010: BDCR1 register 457 * - 011: CSR register 458 * @{ 459 */ 460 /* Flags in the CR register */ 461 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 462 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 463 #define RCC_FLAG_PLL1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos) /*!< PLL1 Ready flag */ 464 465 /* Flags in the BDCR1 register */ 466 #define RCC_FLAG_LSERDY ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSERDY_Pos) /*!< LSE Ready flag */ 467 #define RCC_FLAG_LSESYSRDY ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSESYSRDY_Pos) /*!< LSESYS Ready flag */ 468 #define RCC_FLAG_LSECSSD ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 469 #define RCC_FLAG_LSI1RDY ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSI1RDY_Pos) /*!< LSI1 Ready flag */ 470 #if defined(RCC_LSI2_SUPPORT) 471 #define RCC_FLAG_LSI2RDY ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSI2RDY_Pos) /*!< LSI2 Ready flag */ 472 #endif /* RCC_BDCR1_LSI2ON */ 473 474 /* Flags in the CSR register */ 475 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 476 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 477 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 478 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 479 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 480 #if defined(WWDG) 481 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 482 #endif /* WWDG */ 483 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 489 * @{ 490 */ 491 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR1_LSEDRV_0 /*!< LSE medium low drive capability */ 492 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR1_LSEDRV_1 /*!< LSE medium high drive capability */ 493 #define RCC_LSEDRIVE_HIGH RCC_BDCR1_LSEDRV /*!< LSE high drive capability */ 494 /** 495 * @} 496 */ 497 498 /** @defgroup RCC_Reset_Flag Reset Flag 499 * @{ 500 */ 501 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 502 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 503 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 504 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 505 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 506 #if defined(WWDG) 507 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 508 #endif /* WWDG */ 509 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 510 #if defined(WWDG) 511 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 512 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 513 RCC_RESET_FLAG_LPWR) 514 #else 515 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 516 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_LPWR) 517 #endif /* WWDG */ 518 /** 519 * @} 520 */ 521 522 /** @defgroup RCC_items RCC items 523 * @brief RCC items to configure attributes on 524 * @{ 525 */ 526 #define RCC_HSI RCC_SECCFGR_HSISEC 527 #define RCC_HSE RCC_SECCFGR_HSESEC 528 #define RCC_LSI RCC_SECCFGR_LSISEC 529 #define RCC_LSE RCC_SECCFGR_LSESEC 530 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 531 #define RCC_PRESC RCC_SECCFGR_PRESCSEC 532 #define RCC_PLL1 RCC_SECCFGR_PLL1SEC 533 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 534 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_LSI|RCC_LSE|RCC_SYSCLK| \ 535 RCC_PRESC|RCC_PLL1|RCC_RMVF) 536 /** 537 * @} 538 */ 539 540 /** @defgroup RCC_attributes RCC attributes 541 * @brief RCC privilege/non-privilege and secure/non-secure attributes 542 * @{ 543 */ 544 #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ 545 #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ 546 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 547 #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ 548 #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ 549 #endif 550 /** 551 * @} 552 */ 553 554 /* Exported macros -----------------------------------------------------------*/ 555 556 /** @defgroup RCC_Exported_Macros RCC Exported Macros 557 * @{ 558 */ 559 560 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 561 * @brief Enable or disable the AHB1 peripheral clock. 562 * @note After reset, the peripheral clock (used for registers read/write access) 563 * is disabled and the application software has to enable this clock before 564 * using it. 565 * @{ 566 */ 567 568 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 569 __IO uint32_t tmpreg; \ 570 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 571 /* Delay after an RCC peripheral clock enabling */ \ 572 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 573 UNUSED(tmpreg); \ 574 } while(0) 575 576 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 577 __IO uint32_t tmpreg; \ 578 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 579 /* Delay after an RCC peripheral clock enabling */ \ 580 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 581 UNUSED(tmpreg); \ 582 } while(0) 583 584 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 585 __IO uint32_t tmpreg; \ 586 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 587 /* Delay after an RCC peripheral clock enabling */ \ 588 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 589 UNUSED(tmpreg); \ 590 } while(0) 591 592 #if defined(TSC) 593 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 594 __IO uint32_t tmpreg; \ 595 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 596 /* Delay after an RCC peripheral clock enabling */ \ 597 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 598 UNUSED(tmpreg); \ 599 } while(0) 600 #endif /* TSC */ 601 602 #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ 603 __IO uint32_t tmpreg; \ 604 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 605 /* Delay after an RCC peripheral clock enabling */ \ 606 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 607 UNUSED(tmpreg); \ 608 } while(0) 609 610 #if defined(GTZC_TZSC) 611 #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ 612 __IO uint32_t tmpreg; \ 613 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 614 /* Delay after an RCC peripheral clock enabling */ \ 615 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 616 UNUSED(tmpreg); \ 617 } while(0) 618 #endif /* GTZC_TZSC */ 619 620 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 621 __IO uint32_t tmpreg; \ 622 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 623 /* Delay after an RCC peripheral clock enabling */ \ 624 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 625 UNUSED(tmpreg); \ 626 } while(0) 627 628 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 629 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 630 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 631 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 632 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) 633 #if defined(GTZC_TZSC) 634 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) 635 #endif /* GTZC_TZSC */ 636 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) 637 638 /** 639 * @} 640 */ 641 642 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 643 * @brief Enable or disable the AHB2 peripheral clock. 644 * @note After reset, the peripheral clock (used for registers read/write access) 645 * is disabled and the application software has to enable this clock before 646 * using it. 647 * @{ 648 */ 649 650 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 651 __IO uint32_t tmpreg; \ 652 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 653 /* Delay after an RCC peripheral clock enabling */ \ 654 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 655 UNUSED(tmpreg); \ 656 } while(0) 657 658 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 659 __IO uint32_t tmpreg; \ 660 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 661 /* Delay after an RCC peripheral clock enabling */ \ 662 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 663 UNUSED(tmpreg); \ 664 } while(0) 665 666 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 667 __IO uint32_t tmpreg; \ 668 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 669 /* Delay after an RCC peripheral clock enabling */ \ 670 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 671 UNUSED(tmpreg); \ 672 } while(0) 673 674 675 676 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 677 __IO uint32_t tmpreg; \ 678 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 679 /* Delay after an RCC peripheral clock enabling */ \ 680 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 681 UNUSED(tmpreg); \ 682 } while(0) 683 684 685 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 686 __IO uint32_t tmpreg; \ 687 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 688 /* Delay after an RCC peripheral clock enabling */ \ 689 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 690 UNUSED(tmpreg); \ 691 } while(0) 692 693 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 694 __IO uint32_t tmpreg; \ 695 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 696 /* Delay after an RCC peripheral clock enabling */ \ 697 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 698 UNUSED(tmpreg); \ 699 } while(0) 700 701 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 702 __IO uint32_t tmpreg; \ 703 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 704 /* Delay after an RCC peripheral clock enabling */ \ 705 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 706 UNUSED(tmpreg); \ 707 } while(0) 708 709 #if defined(SAES) 710 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 711 __IO uint32_t tmpreg; \ 712 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ 713 /* Delay after an RCC peripheral clock enabling */ \ 714 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ 715 UNUSED(tmpreg); \ 716 } while(0) 717 #endif /* SAES */ 718 719 #if defined(HSEM) 720 #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ 721 __IO uint32_t tmpreg; \ 722 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN); \ 723 /* Delay after an RCC peripheral clock enabling */ \ 724 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN); \ 725 UNUSED(tmpreg); \ 726 } while(0) 727 #endif /* HSEM */ 728 729 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 730 __IO uint32_t tmpreg; \ 731 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 732 /* Delay after an RCC peripheral clock enabling */ \ 733 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 734 UNUSED(tmpreg); \ 735 } while(0) 736 737 738 739 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 740 __IO uint32_t tmpreg; \ 741 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ 742 /* Delay after an RCC peripheral clock enabling */ \ 743 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ 744 UNUSED(tmpreg); \ 745 } while(0) 746 747 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 748 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 749 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 750 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 751 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) 752 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 753 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 754 #if defined(SAES) 755 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) 756 #endif /* SAES */ 757 #if defined(HSEM) 758 #define __HAL_RCC_HSEM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) 759 #endif /* HSEM */ 760 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 761 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) 762 /** 763 * @} 764 */ 765 766 /** @defgroup RCC_AHB4_Clock_Enable_Disable AHB4ENR Peripheral Clock Enable Disable 767 * @brief Enable or disable the AHB4ENR peripheral clock. 768 * @note After reset, the peripheral clock (used for registers read/write access) 769 * is disabled and the application software has to enable this clock before 770 * using it. 771 * @{ 772 */ 773 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 774 __IO uint32_t tmpreg; \ 775 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_PWREN); \ 776 /* Delay after an RCC peripheral clock enabling */ \ 777 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_PWREN); \ 778 UNUSED(tmpreg); \ 779 } while(0) 780 781 #define __HAL_RCC_ADC4_CLK_ENABLE() do { \ 782 __IO uint32_t tmpreg; \ 783 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); \ 784 /* Delay after an RCC peripheral clock enabling */ \ 785 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); \ 786 UNUSED(tmpreg); \ 787 } while(0) 788 789 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_PWREN) 790 #define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN) 791 /** 792 * @} 793 */ 794 795 /** @defgroup RCC_AHB5_Clock_Enable_Disable AHB5ENR Peripheral Clock Enable Disable 796 * @brief Enable or disable the AHB5ENR peripheral clock. 797 * @note After reset, the peripheral clock (used for registers read/write access) 798 * is disabled and the application software has to enable this clock before 799 * using it. 800 * @{ 801 */ 802 #define __HAL_RCC_RADIO_CLK_ENABLE() do { \ 803 __IO uint32_t tmpreg; \ 804 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN); \ 805 /* Delay after an RCC peripheral clock enabling */ \ 806 tmpreg = READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN); \ 807 UNUSED(tmpreg); \ 808 } while(0) 809 810 #if defined(PTACONV) 811 #define __HAL_RCC_PTACONV_CLK_ENABLE() do { \ 812 __IO uint32_t tmpreg; \ 813 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN); \ 814 /* Delay after an RCC peripheral clock enabling */ \ 815 tmpreg = READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN); \ 816 UNUSED(tmpreg); \ 817 } while(0) 818 #endif /* PTACONV */ 819 820 #define __HAL_RCC_RADIO_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN) 821 822 #if defined(PTACONV) 823 #define __HAL_RCC_PTACONV_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN) 824 #endif /* PTACONV */ 825 /** 826 * @} 827 */ 828 829 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 830 * @brief Enable or disable the APB1 peripheral clock. 831 * @note After reset, the peripheral clock (used for registers read/write access) 832 * is disabled and the application software has to enable this clock before 833 * using it. 834 * @{ 835 */ 836 837 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 838 __IO uint32_t tmpreg; \ 839 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 840 /* Delay after an RCC peripheral clock enabling */ \ 841 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 842 UNUSED(tmpreg); \ 843 } while(0) 844 845 #if defined(TIM3) 846 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 847 __IO uint32_t tmpreg; \ 848 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 849 /* Delay after an RCC peripheral clock enabling */ \ 850 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 851 UNUSED(tmpreg); \ 852 } while(0) 853 #endif /* TIM3 */ 854 855 856 #if defined(WWDG) 857 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 858 __IO uint32_t tmpreg; \ 859 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 860 /* Delay after an RCC peripheral clock enabling */ \ 861 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 862 UNUSED(tmpreg); \ 863 } while(0) 864 #endif /* WWDG */ 865 866 867 #if defined(USART2) 868 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 869 __IO uint32_t tmpreg; \ 870 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 871 /* Delay after an RCC peripheral clock enabling */ \ 872 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 873 UNUSED(tmpreg); \ 874 } while(0) 875 #endif /* USART2 */ 876 877 878 #if defined(I2C1) 879 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 880 __IO uint32_t tmpreg; \ 881 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 882 /* Delay after an RCC peripheral clock enabling */ \ 883 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 884 UNUSED(tmpreg); \ 885 } while(0) 886 #endif /* I2C1 */ 887 888 889 890 #if defined(LPTIM2) 891 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 892 __IO uint32_t tmpreg; \ 893 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 894 /* Delay after an RCC peripheral clock enabling */ \ 895 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 896 UNUSED(tmpreg); \ 897 } while(0) 898 #endif /* LPTIM2 */ 899 900 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 901 #if defined(TIM3) 902 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 903 #endif /* TIM3 */ 904 #if defined(USART2) 905 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 906 #endif /* USART2 */ 907 #if defined(I2C1) 908 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 909 #endif /* I2C1 */ 910 #if defined(LPTIM2) 911 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 912 #endif /* LPTIM2 */ 913 /** 914 * @} 915 */ 916 917 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 918 * @brief Enable or disable the APB2 peripheral clock. 919 * @note After reset, the peripheral clock (used for registers read/write access) 920 * is disabled and the application software has to enable this clock before 921 * using it. 922 * @{ 923 */ 924 #if defined(TIM1) 925 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 926 __IO uint32_t tmpreg; \ 927 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 928 /* Delay after an RCC peripheral clock enabling */ \ 929 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 930 UNUSED(tmpreg); \ 931 } while(0) 932 #endif /* TIM1 */ 933 934 #if defined(SPI1) 935 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 936 __IO uint32_t tmpreg; \ 937 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 938 /* Delay after an RCC peripheral clock enabling */ \ 939 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 940 UNUSED(tmpreg); \ 941 } while(0) 942 #endif /* SPI1 */ 943 944 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 945 __IO uint32_t tmpreg; \ 946 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 947 /* Delay after an RCC peripheral clock enabling */ \ 948 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 949 UNUSED(tmpreg); \ 950 } while(0) 951 952 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 953 __IO uint32_t tmpreg; \ 954 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 955 /* Delay after an RCC peripheral clock enabling */ \ 956 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 957 UNUSED(tmpreg); \ 958 } while(0) 959 960 #if defined(TIM17) 961 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 962 __IO uint32_t tmpreg; \ 963 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 964 /* Delay after an RCC peripheral clock enabling */ \ 965 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 966 UNUSED(tmpreg); \ 967 } while(0) 968 #endif /* TIM17 */ 969 970 #if defined(SAI1) 971 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 972 __IO uint32_t tmpreg; \ 973 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 974 /* Delay after an RCC peripheral clock enabling */ \ 975 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 976 UNUSED(tmpreg); \ 977 } while(0) 978 #endif /* SAI1 */ 979 980 981 #if defined(TIM1) 982 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 983 #endif /* TIM1 */ 984 #if defined(SPI1) 985 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 986 #endif /* SPI1 */ 987 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 988 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 989 #if defined(TIM17) 990 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 991 #endif /* TIM17 */ 992 #if defined(SAI1) 993 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 994 #endif /* SAI1 */ 995 /** 996 * @} 997 */ 998 999 /** @defgroup RCC_APB7_Clock_Enable_Disable APB7 Peripheral Clock Enable Disable 1000 * @brief Enable or disable the APB7 peripheral clock. 1001 * @note After reset, the peripheral clock (used for registers read/write access) 1002 * is disabled and the application software has to enable this clock before 1003 * using it. 1004 * @{ 1005 */ 1006 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1007 __IO uint32_t tmpreg; \ 1008 SET_BIT(RCC->APB7ENR, RCC_APB7ENR_SYSCFGEN); \ 1009 /* Delay after an RCC peripheral clock enabling */ \ 1010 tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_SYSCFGEN); \ 1011 UNUSED(tmpreg); \ 1012 } while(0) 1013 1014 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1015 __IO uint32_t tmpreg; \ 1016 SET_BIT(RCC->APB7ENR, RCC_APB7ENR_SPI3EN); \ 1017 /* Delay after an RCC peripheral clock enabling */ \ 1018 tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_SPI3EN); \ 1019 UNUSED(tmpreg); \ 1020 } while(0) 1021 1022 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1023 __IO uint32_t tmpreg; \ 1024 SET_BIT(RCC->APB7ENR, RCC_APB7ENR_LPUART1EN); \ 1025 /* Delay after an RCC peripheral clock enabling */ \ 1026 tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPUART1EN); \ 1027 UNUSED(tmpreg); \ 1028 } while(0) 1029 1030 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1031 __IO uint32_t tmpreg; \ 1032 SET_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN); \ 1033 /* Delay after an RCC peripheral clock enabling */ \ 1034 tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN); \ 1035 UNUSED(tmpreg); \ 1036 } while(0) 1037 1038 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 1039 __IO uint32_t tmpreg; \ 1040 SET_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN); \ 1041 /* Delay after an RCC peripheral clock enabling */ \ 1042 tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN); \ 1043 UNUSED(tmpreg); \ 1044 } while(0) 1045 1046 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1047 __IO uint32_t tmpreg; \ 1048 SET_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN); \ 1049 /* Delay after an RCC peripheral clock enabling */ \ 1050 tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN); \ 1051 UNUSED(tmpreg); \ 1052 } while(0) 1053 1054 1055 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1056 __IO uint32_t tmpreg; \ 1057 SET_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN); \ 1058 /* Delay after an RCC peripheral clock enabling */ \ 1059 tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN); \ 1060 UNUSED(tmpreg); \ 1061 } while(0) 1062 1063 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_SYSCFGEN) 1064 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_SPI3EN) 1065 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_LPUART1EN) 1066 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN) 1067 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN) 1068 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN) 1069 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN) 1070 /** 1071 * @} 1072 */ 1073 1074 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1075 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1076 * @{ 1077 */ 1078 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 1079 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1080 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1081 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 1082 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) 1083 #if defined(GTZC_TZSC) 1084 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) 1085 #endif /* GTZC_TZSC */ 1086 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) 1087 /** 1088 * @} 1089 */ 1090 1091 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1092 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1093 * @{ 1094 */ 1095 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 1096 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 1097 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1098 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 1099 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 1100 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 1101 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 1102 #if defined(SAES) 1103 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U) 1104 #endif /* SAES */ 1105 #if defined(HSEM) 1106 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) != 0U) 1107 #endif /* HSEM */ 1108 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 1109 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) 1110 /** 1111 * @} 1112 */ 1113 1114 /** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable_Status AHB4 Peripheral Clock Enabled or Disabled Status 1115 * @brief Check whether the AHB4 peripheral clock is enabled or not. 1116 * @{ 1117 */ 1118 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_PWREN) != 0U) 1119 #define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN) != 0U) 1120 /** 1121 * @} 1122 */ 1123 1124 /** @defgroup RCC_AHB5_Peripheral_Clock_Enable_Disable_Status AHB5 Peripheral Clock Enabled or Disabled Status 1125 * @brief Check whether the AHB5 peripheral clock is enabled or not. 1126 * @{ 1127 */ 1128 #define __HAL_RCC_RADIO_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN) != 0U) 1129 #if defined(PTACONV) 1130 #define __HAL_RCC_PTACONV_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN) != 0U) 1131 #endif 1132 /** 1133 * @} 1134 */ 1135 1136 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1137 * @brief Check whether the APB1 peripheral clock is enabled or not. 1138 * @{ 1139 */ 1140 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1141 #if defined(TIM3) 1142 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1143 #endif /* TIM3 */ 1144 #if defined(WWDG) 1145 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1146 #endif /* WWDG */ 1147 #if defined(USART2) 1148 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1149 #endif /* USART2 */ 1150 #if defined(I2C1) 1151 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1152 #endif /* I2C1 */ 1153 #if defined(LPTIM2) 1154 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 1155 #endif /* LPTIM2 */ 1156 /** 1157 * @} 1158 */ 1159 1160 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1161 * @brief Check whether the APB2 peripheral clock is enabled or not. 1162 * @{ 1163 */ 1164 #if defined(TIM1) 1165 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 1166 #endif /* TIM1 */ 1167 #if defined(SPI1) 1168 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 1169 #endif /* SPI1 */ 1170 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 1171 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 1172 #if defined(TIM17) 1173 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 1174 #endif /* TIM17 */ 1175 #if defined(SAI1) 1176 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 1177 #endif /* SAI1 */ 1178 /** 1179 * @} 1180 */ 1181 1182 /** @defgroup RCC_APB7_Peripheral_Clock_Enable_Disable_Status APB7 Peripheral Clock Enabled or Disabled Status 1183 * @brief Check whether the APB7 peripheral clock is enabled or not. 1184 * @{ 1185 */ 1186 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_SYSCFGEN) != 0U) 1187 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_SPI3EN) != 0U) 1188 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPUART1EN) != 0U) 1189 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN) != 0U) 1190 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN) != 0U) 1191 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN) != 0U) 1192 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN) != 0U) 1193 /** 1194 * @} 1195 */ 1196 1197 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1198 * @brief Force or release AHB1 peripheral reset. 1199 * @{ 1200 */ 1201 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) 1202 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 1203 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 1204 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 1205 1206 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 1207 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 1208 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 1209 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 1210 /** 1211 * @} 1212 */ 1213 1214 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1215 * @brief Force or release AHB2 peripheral reset. 1216 * @{ 1217 */ 1218 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) 1219 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 1220 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 1221 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 1222 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 1223 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 1224 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 1225 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 1226 #if defined(SAES) 1227 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) 1228 #endif /* SAES */ 1229 #if defined(HSEM) 1230 #define __HAL_RCC_HSEM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) 1231 #endif /* HSEM */ 1232 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 1233 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 1234 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 1235 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 1236 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 1237 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 1238 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 1239 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 1240 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 1241 #if defined(SAES) 1242 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) 1243 #endif /* SAES */ 1244 #if defined(HSEM) 1245 #define __HAL_RCC_HSEM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) 1246 #endif /* HSEM */ 1247 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 1248 /** 1249 * @} 1250 */ 1251 1252 /** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset 1253 * @brief Force or release AHB4 peripheral reset. 1254 * @{ 1255 */ 1256 #define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0xFFFFFFFFU) 1257 #define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_ADC4RST) 1258 1259 #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) 1260 #define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_ADC4RST) 1261 /** 1262 * @} 1263 */ 1264 1265 /** @defgroup RCC_AHB5_Force_Release_Reset AHB5 Peripheral Force Release Reset 1266 * @brief Force or release AHB5 peripheral reset. 1267 * @{ 1268 */ 1269 #define __HAL_RCC_AHB5_FORCE_RESET() WRITE_REG(RCC->AHB5RSTR, 0xFFFFFFFFU) 1270 #define __HAL_RCC_RADIO_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_RADIORST) 1271 #if defined(PTACONV) 1272 #define __HAL_RCC_PTACONV_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_PTACONVRST) 1273 #endif /* PTACONV */ 1274 1275 #define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTR, 0x00000000U) 1276 #define __HAL_RCC_RADIO_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_RADIORST) 1277 #if defined(PTACONV) 1278 #define __HAL_RCC_PTACONV_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_PTACONVRST) 1279 #endif /* PTACONV */ 1280 /** 1281 * @} 1282 */ 1283 1284 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1285 * @brief Force or release APB1 peripheral reset. 1286 * @{ 1287 */ 1288 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 1289 WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU); \ 1290 WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFU); \ 1291 } while(0) 1292 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 1293 #if defined(TIM3) 1294 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 1295 #endif /* TIM3 */ 1296 #if defined(USART2) 1297 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 1298 #endif /* USART2 */ 1299 #if defined(I2C1) 1300 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 1301 #endif /* I2C1 */ 1302 #if defined(LPTIM2) 1303 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 1304 #endif /* LPTIM2 */ 1305 1306 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 1307 WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ 1308 WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \ 1309 } while(0) 1310 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 1311 #if defined(TIM3) 1312 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 1313 #endif /* TIM3 */ 1314 #if defined(USART2) 1315 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 1316 #endif /* USART2 */ 1317 #if defined(I2C1) 1318 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 1319 #endif /* I2C1 */ 1320 #if defined(LPTIM2) 1321 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 1322 #endif /* LPTIM2 */ 1323 /** 1324 * @} 1325 */ 1326 1327 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1328 * @brief Force or release APB2 peripheral reset. 1329 * @{ 1330 */ 1331 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) 1332 #if defined(TIM1) 1333 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 1334 #endif /* TIM1 */ 1335 #if defined(SPI1) 1336 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 1337 #endif /* SPI1 */ 1338 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 1339 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 1340 #if defined(TIM17) 1341 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 1342 #endif /* TIM17 */ 1343 #if defined(SAI1) 1344 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 1345 #endif /* SAI1 */ 1346 1347 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 1348 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 1349 #if defined(SPI1) 1350 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 1351 #endif /* SPI1 */ 1352 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 1353 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 1354 #if defined(TIM17) 1355 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 1356 #endif /* TIM17 */ 1357 #if defined(SAI1) 1358 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 1359 #endif /* SAI1 */ 1360 /** 1361 * @} 1362 */ 1363 1364 /** @defgroup RCC_APB7_Force_Release_Reset APB7 Peripheral Force Release Reset 1365 * @brief Force or release APB7 peripheral reset. 1366 * @{ 1367 */ 1368 #define __HAL_RCC_APB7_FORCE_RESET() WRITE_REG(RCC->APB7RSTR, 0xFFFFFFFFU) 1369 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SYSCFGRST) 1370 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SPI3RST) 1371 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPUART1RST) 1372 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_I2C3RST) 1373 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPTIM1RST) 1374 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_COMPRST) 1375 1376 #define __HAL_RCC_APB7_RELEASE_RESET() WRITE_REG(RCC->APB7RSTR, 0x00000000U) 1377 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SYSCFGRST) 1378 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SPI3RST) 1379 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPUART1RST) 1380 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_I2C3RST) 1381 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPTIM1RST) 1382 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_COMPRST) 1383 /** 1384 * @} 1385 */ 1386 1387 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 1388 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode. 1389 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 1390 * power consumption. 1391 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 1392 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 1393 * is enabled only when a peripheral requests AHB clock. 1394 * @{ 1395 */ 1396 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 1397 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 1398 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 1399 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 1400 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 1401 #if defined(GTZC_TZSC) 1402 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 1403 #endif /* GTZC_TZSC */ 1404 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 1405 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 1406 1407 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 1408 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 1409 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 1410 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 1411 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 1412 #if defined(GTZC_TZSC) 1413 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 1414 #endif /* GTZC_TZSC */ 1415 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 1416 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 1417 /** 1418 * @} 1419 */ 1420 1421 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 1422 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode. 1423 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 1424 * power consumption. 1425 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 1426 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 1427 * is enabled only when a peripheral requests AHB clock. 1428 * @{ 1429 */ 1430 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 1431 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 1432 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 1433 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 1434 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 1435 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 1436 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 1437 #if defined(SAES) 1438 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) 1439 #endif /* SAES */ 1440 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 1441 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 1442 1443 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 1444 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 1445 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 1446 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 1447 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 1448 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 1449 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 1450 #if defined(SAES) 1451 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) 1452 #endif /* SAES */ 1453 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 1454 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 1455 /** 1456 * @} 1457 */ 1458 1459 /** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4SMENR Peripheral Clock Sleep Enable Disable 1460 * @brief Enable or disable the AHB4SMENR peripheral clock during Low Power (Sleep and STOP ) mode. 1461 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 1462 * power consumption. 1463 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 1464 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 1465 * is enabled only when a peripheral requests AHB clock. 1466 * @{ 1467 */ 1468 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_PWRSMEN) 1469 #define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_ADC4SMEN) 1470 1471 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_PWRSMEN) 1472 #define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_ADC4SMEN) 1473 /** 1474 * @} 1475 */ 1476 1477 /** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable AHB5SMENR Peripheral Clock Sleep Enable Disable 1478 * @brief Enable or disable the AHB5SMENR peripheral clock during Low Power (Sleep and STOP ) mode. 1479 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 1480 * power consumption. 1481 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 1482 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 1483 * is enabled only when a peripheral requests AHB clock. 1484 * @{ 1485 */ 1486 #define __HAL_RCC_RADIO_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_RADIOSMEN) 1487 #define __HAL_RCC_RADIO_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_RADIOSMEN) 1488 1489 #if defined(PTACONV) 1490 #define __HAL_RCC_PTACONV_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) 1491 #define __HAL_RCC_PTACONV_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) 1492 #endif /* PTACONV */ 1493 /** 1494 * @} 1495 */ 1496 1497 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 1498 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode. 1499 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 1500 * power consumption. 1501 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 1502 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 1503 * is enabled only when a peripheral requests APB clock. 1504 * @{ 1505 */ 1506 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 1507 #if defined(TIM3) 1508 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 1509 #endif /* TIM3 */ 1510 #if defined(WWDG) 1511 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 1512 #endif /* WWDG */ 1513 #if defined(USART2) 1514 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 1515 #endif /* USART2 */ 1516 #if defined(I2C1) 1517 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 1518 #endif /* I2C1 */ 1519 #if defined(LPTIM2) 1520 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 1521 #endif /* LPTIM2 */ 1522 1523 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 1524 #if defined(TIM3) 1525 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 1526 #endif /* TIM3 */ 1527 #if defined(WWDG) 1528 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 1529 #endif /* WWDG */ 1530 #if defined(USART2) 1531 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 1532 #endif /* USART2 */ 1533 #if defined(I2C1) 1534 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 1535 #endif /* I2C1 */ 1536 #if defined(LPTIM2) 1537 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 1538 #endif /* LPTIM2 */ 1539 /** 1540 * @} 1541 */ 1542 1543 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 1544 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode. 1545 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 1546 * power consumption. 1547 * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again. 1548 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 1549 * is enabled only when a peripheral requests APB clock. 1550 * @{ 1551 */ 1552 #if defined(TIM1) 1553 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 1554 #endif /* TIM1 */ 1555 #if defined(SPI1) 1556 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 1557 #endif /* SPI1 */ 1558 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 1559 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 1560 #if defined(TIM17) 1561 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 1562 #endif /* TIM17 */ 1563 #if defined(SAI1) 1564 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 1565 #endif /* SAI1 */ 1566 1567 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 1568 #if defined(SPI1) 1569 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 1570 #endif /* SPI1 */ 1571 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 1572 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 1573 #if defined(TIM17) 1574 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 1575 #endif /* TIM17 */ 1576 #if defined(SAI1) 1577 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 1578 #endif /* SAI1 */ 1579 /** 1580 * @} 1581 */ 1582 1583 /** @defgroup RCC_APB7_Clock_Sleep_Enable_Disable APB7 Peripheral Clock Sleep Enable Disable 1584 * @brief Enable or disable the APB7 peripheral clock during Low Power (Sleep and Stop) mode. 1585 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 1586 * power consumption. 1587 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 1588 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 1589 * is enabled only when a peripheral requests APB clock. 1590 * @{ 1591 */ 1592 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SYSCFGSMEN) 1593 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SPI3SMEN) 1594 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPUART1SMEN) 1595 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_I2C3SMEN) 1596 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) 1597 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) 1598 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) 1599 1600 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SYSCFGSMEN) 1601 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SPI3SMEN) 1602 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPUART1SMEN) 1603 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_I2C3SMEN) 1604 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) 1605 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) 1606 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) 1607 /** 1608 * @} 1609 */ 1610 1611 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enabled_Status AHB1 Peripheral Clock Sleep Enabled Status 1612 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) is enabled or not. 1613 * @{ 1614 */ 1615 #define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) != 0U) 1616 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) 1617 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) 1618 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) 1619 #define __HAL_RCC_RAMCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) != 0U) 1620 #if defined(GTZC_TZSC) 1621 #define __HAL_RCC_GTZC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) != 0U) 1622 #endif /* GTZC_TZSC */ 1623 #define __HAL_RCC_ICACHE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) != 0U) 1624 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) 1625 /** 1626 * @} 1627 */ 1628 1629 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enabled_Status AHB2 Peripheral Clock Sleep Enabled Status 1630 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) is enabled or not. 1631 * @{ 1632 */ 1633 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) 1634 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) 1635 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) 1636 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) 1637 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) 1638 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) 1639 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) 1640 #if defined(SAES) 1641 #define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) != 0U) 1642 #endif /* SAES */ 1643 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U) 1644 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) 1645 /** 1646 * @} 1647 */ 1648 1649 /** @defgroup RCC_AHB4_Peripheral_Clock_Sleep_Enabled_Status AHB4 Peripheral Clock Sleep Enabled Status 1650 * @brief Check whether the AHB4 peripheral clock during Low Power (Sleep) is enabled or not. 1651 * @{ 1652 */ 1653 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_PWRSMEN) != 0U) 1654 #define __HAL_RCC_ADC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_ADC4SMEN) != 0U) 1655 /** 1656 * @} 1657 */ 1658 1659 /** @defgroup RCC_AHB5_Peripheral_Clock_Sleep_Enabled_Status AHB5 Peripheral Clock Sleep Enabled Status 1660 * @brief Check whether the AHB5 peripheral clock during Low Power (Sleep) is enabled or not. 1661 * @{ 1662 */ 1663 #define __HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_RADIOSMEN) != 0U) 1664 #if defined(PTACONV) 1665 #define __HAL_RCC_PTACONV_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) != 0U) 1666 #endif /* PTACONV */ 1667 /** 1668 * @} 1669 */ 1670 1671 /** @defgroup RCC_APB1_Peripheral_Clock_Sleep_Enabled_Status APB1 Peripheral Clock Sleep Enabled Status 1672 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) is enabled or not. 1673 * @{ 1674 */ 1675 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) 1676 #if defined(TIM3) 1677 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) 1678 #endif /* TIM3 */ 1679 #if defined(WWDG) 1680 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) 1681 #endif /* WWDG */ 1682 #if defined(USART2) 1683 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) 1684 #endif /* USART2 */ 1685 #if defined(I2C1) 1686 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) 1687 #endif /* I2C1 */ 1688 #if defined(LPTIM2) 1689 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) 1690 #endif /* LPTIM2 */ 1691 /** 1692 * @} 1693 */ 1694 1695 /** @defgroup RCC_APB2_Peripheral_Clock_Sleep_Enabled_Status APB2 Peripheral Clock Sleep Enabled Status 1696 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 1697 * @{ 1698 */ 1699 #if defined(TIM1) 1700 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) 1701 #endif /* TIM1 */ 1702 #if defined(SPI1) 1703 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 1704 #endif /* SPI1 */ 1705 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 1706 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) 1707 #if defined(TIM17) 1708 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) 1709 #endif /* TIM17 */ 1710 #if defined(SAI1) 1711 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) 1712 #endif /* SAI1 */ 1713 /** 1714 * @} 1715 */ 1716 1717 /** @defgroup RCC_APB7_Peripheral_Clock_Sleep_Enabled_Status APB7 Peripheral Clock Sleep Enabled Status 1718 * @brief Check whether the APB7 peripheral clock during Low Power (Sleep) mode is enabled or not. 1719 * @{ 1720 */ 1721 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SYSCFGSMEN) != 0U) 1722 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SPI3SMEN) != 0U) 1723 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPUART1SMEN) != 0U) 1724 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_I2C3SMEN) != 0U) 1725 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) != 0U) 1726 #define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) != 0U) 1727 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) != 0U) 1728 /** 1729 * @} 1730 */ 1731 1732 1733 1734 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 1735 * @{ 1736 */ 1737 1738 /** @brief Macros to force or release the Backup domain reset. 1739 * @note This function resets the RTC peripheral (including the backup registers) 1740 * and the RTC clock source selection in RCC_CSR register. 1741 * @retval None 1742 */ 1743 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR1, RCC_BDCR1_BDRST) 1744 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_BDRST) 1745 /** 1746 * @} 1747 */ 1748 1749 1750 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 1751 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1752 * It is used (enabled by hardware) as system clock source after startup 1753 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1754 * of the HSE used directly or indirectly as system clock (if the Clock 1755 * Security System CSS is enabled). 1756 * @note HSI can not be stopped if it is used as system clock source. In this case, 1757 * you have to select another source of the system clock then stop the HSI. 1758 * @note After enabling the HSI, the application software should wait on HSIRDY 1759 * flag to be set indicating that HSI clock is stable and can be used as 1760 * system clock source. 1761 * This parameter can be: ENABLE or DISABLE. 1762 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1763 * clock cycles. 1764 * @retval None 1765 */ 1766 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 1767 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 1768 1769 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 1770 * @note The calibration is used to compensate for the variations in voltage 1771 * and temperature that influence the frequency of the internal HSI RC. 1772 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 1773 * (default is RCC_HSICALIBRATION_DEFAULT). 1774 * This parameter must be a number between 0 and 0x1F. 1775 * @retval None 1776 */ 1777 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 1778 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) 1779 1780 /** 1781 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 1782 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 1783 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 1784 * speed because of the HSI startup time. 1785 * @note The enable of this function has not effect on the HSION bit. 1786 * This parameter can be: ENABLE or DISABLE. 1787 * @retval None 1788 */ 1789 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 1790 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 1791 1792 1793 1794 /** @brief Macros to enable or disable the Internal Low Speed oscillator LSI1. 1795 * @note After enabling the LSI1, the application software should wait on 1796 * LSI1RDY flag to be set indicating that LSI1 clock is stable and can 1797 * be used to clock the IWDG and/or the RTC. 1798 * @note When the IWDG is started the LSI clock is forced on and cannot be disabled. 1799 * When both LSI1 and LSI2 are disabled LSI1 will be forced on. When LSI selects 1800 * LSI2 RC source, the LSI1 RC source can be disabled. 1801 * @note When the LSI1 is stopped, LSI1RDY flag goes low after 3 LSI1 oscillator 1802 * clock cycles. 1803 * @retval None 1804 */ 1805 #define __HAL_RCC_LSI1_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON) 1806 #define __HAL_RCC_LSI1_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON) 1807 1808 /** @brief Macro to set Low-speed clock LSI1 divider. 1809 * @note Only LSI1 clock can be divided 1810 * @note This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). 1811 * The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC. 1812 * @param __DIVIDER__ : specifies the divider value 1813 * This parameter can be one of the following values 1814 * @arg @ref RCC_LSI_DIV1 1815 * @arg @ref RCC_LSI_DIV128 1816 * @retval None 1817 */ 1818 #define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV, __DIVIDER__) 1819 1820 #if defined(RCC_LSI2_SUPPORT) 1821 /** @brief Macros to enable or disable the Internal Low Speed oscillator LSI2. 1822 * @note After enabling the LSI2, the application software should wait on 1823 * LSI2RDY flag to be set indicating that LSI2 clock is stable and can 1824 * be used to clock the IWDG and/or the RTC. 1825 * @note When the IWDG is started the LSI clock is forced on and cannot be disabled. 1826 * When both LSI1 and LSI2 are disabled LSI1 will be forced on. When LSI selects 1827 * LSI2 RC source, the LSI1 RC source can be disabled. 1828 * @note When the LSI2 is stopped, LSI2RDY flag goes low after 3 LSI1 oscillator 1829 * clock cycles. 1830 * @retval None 1831 */ 1832 #define __HAL_RCC_LSI2_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON) 1833 #define __HAL_RCC_LSI2_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON) 1834 #endif /* RCC_BDCR1_LSI2ON */ 1835 1836 /** 1837 * @brief Macro to configure the External High Speed oscillator (HSE). 1838 * @note After enabling the HSE (RCC_HSE_ON), the application 1839 * software should wait on HSERDY flag to be set indicating that HSE clock 1840 * is stable and can be used to clock the PLL1 and/or system clock. 1841 * @note HSE state can not be changed if it is used directly or through the 1842 * PLL1 as system clock. In this case, you have to select another source 1843 * of the system clock then change the HSE state (ex. disable it). 1844 * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes. 1845 * @note HSERDY flag may remain high when HSEON bit is cleared. This is when the 2.4 GHz 1846 * RADIO uses the HSE32 as its kernel clock. 1847 * @param __STATE__: specifies the new state of the HSE. 1848 * This parameter can be a combination of the following values: 1849 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 1850 * 6 HSE oscillator clock cycles. 1851 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 1852 * @arg @ref RCC_HSE_DIV1 Divide HSE by 1 for SYSCLK 1853 * @arg @ref RCC_HSE_DIV2 Divide HSE by 2 for SYSCLK 1854 * @retval None 1855 */ 1856 #define __HAL_RCC_HSE_CONFIG(__STATE__) MODIFY_REG(RCC->CR, (RCC_CR_HSEON | RCC_CR_HSEPRE), __STATE__) 1857 1858 1859 /** @brief Macro to enable or disable the LSE system clock. 1860 * @note This clock can be used by any peripheral when its source clock is the LSE or at system 1861 * in case of one of the LSCOSEL, MCO or CSS on LSE is needed. 1862 * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by 1863 * the CSS on LSE, by a peripheral or any other source clock using LSE. 1864 * @retval None 1865 */ 1866 #define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR1,RCC_BDCR1_LSESYSEN) 1867 #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR1,RCC_BDCR1_LSESYSEN) 1868 1869 1870 /** @brief Macros to enable or disable LSE clock glitch filter . 1871 * @note The glitches on LSE can be filtred by setting the LSEGFON. 1872 * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). 1873 * @retval None 1874 */ 1875 #define __HAL_RCC_LSE_GlitchFilter_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON ) 1876 #define __HAL_RCC_LSE_GlitchFilter_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON ) 1877 1878 /** 1879 * @brief Macro to configure the External Low Speed oscillator (LSE). 1880 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 1881 * supported by this macro. User should request a transition to LSE Off 1882 * first and then LSE On or LSE Bypass. 1883 * @note As the LSE is in the Backup domain and write access is denied to 1884 * this domain after reset, you have to enable write access using 1885 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 1886 * (to be done once after reset). 1887 * @note After enabling the LSE, the application 1888 * software should wait on LSERDY flag to be set indicating that LSE clock 1889 * is stable and can be used to clock the RTC. 1890 * @param __STATE__: specifies the new state of the LSE. 1891 * This parameter can be one of the following values: 1892 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 1893 * 6 LSE oscillator clock cycles. 1894 * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. 1895 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. 1896 * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. 1897 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral. 1898 * @retval None 1899 */ 1900 #define __HAL_RCC_LSE_CONFIG(__STATE__) do { \ 1901 if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ 1902 { \ 1903 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); \ 1904 } \ 1905 else if((__STATE__) == RCC_LSE_ON) \ 1906 { \ 1907 SET_BIT(RCC->BDCR1, (RCC_BDCR1_LSEON | RCC_BDCR1_LSESYSEN)); \ 1908 } \ 1909 else if((__STATE__) == RCC_LSE_BYPASS) \ 1910 { \ 1911 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); \ 1912 SET_BIT(RCC->BDCR1, (RCC_BDCR1_LSEON | RCC_BDCR1_LSESYSEN)); \ 1913 } \ 1914 else if((__STATE__) == RCC_LSE_BYPASS) \ 1915 { \ 1916 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); \ 1917 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); \ 1918 } \ 1919 else \ 1920 { \ 1921 CLEAR_BIT(RCC->BDCR1, (RCC_BDCR1_LSEON | RCC_BDCR1_LSESYSEN)); \ 1922 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); \ 1923 } \ 1924 } while(0) 1925 1926 1927 /** @brief Macros to configure the RTC clock (RTCCLK). 1928 * @note As the RTC clock configuration bits are in the Backup domain and write 1929 * access is denied to this domain after reset, you have to enable write 1930 * access using the Power Backup Access macro before to configure 1931 * the RTC clock source (to be done once after reset). 1932 * @note Once the RTC clock is configured it cannot be changed unless the 1933 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 1934 * a Power On Reset (POR). 1935 * 1936 * @param __RTC_CLKSOURCE__: specifies the RTC clock source. 1937 * This parameter can be one of the following values: 1938 * @arg @ref RCC_RTCCLKSOURCE_DISABLE RTC clock is disabled. 1939 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 1940 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 1941 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 1942 * 1943 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1944 * work in STOP and STANDBY modes, and can be used as wakeup source. 1945 * However, when the HSE clock is used as RTC clock source, the RTC 1946 * cannot be used in STOP and STANDBY modes. 1947 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 1948 * RTC clock source). 1949 * @retval None 1950 */ 1951 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 1952 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RTCSEL, (__RTC_CLKSOURCE__)) 1953 1954 1955 /** @brief Macro to get the RTC clock source. 1956 * @retval The returned value can be one of the following: 1957 * @arg @ref RCC_RTCCLKSOURCE_DISABLE RTC clock is disabled. 1958 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 1959 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 1960 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 1961 */ 1962 #define __HAL_RCC_GET_RTC_SOURCE() READ_BIT(RCC->BDCR1, RCC_BDCR1_RTCSEL) 1963 1964 /** @brief Macros to enable or disable the main PLL1. 1965 * @note After enabling the main PLL1, the application software should wait on 1966 * PLLRDY flag to be set indicating that PLL1 clock is stable and can 1967 * be used as system clock source. 1968 * @note The main PLL1 can not be disabled if it is used as system clock source 1969 * @note The main PLL1 is disabled by hardware when entering STOP and STANDBY modes. 1970 */ 1971 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 1972 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 1973 1974 /** 1975 * @brief Enables or disables each clock output (PLL_PCLK, PLL_QCLK, PLL_RCLK) 1976 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL1, 1977 * This is mainly used to save Power. 1978 * @param __PLL1_CLOCKOUT__: specifies the PLL1 clock to be output 1979 * This parameter can be a combination of the following values: 1980 * @arg RCC_PLL1_PCLK: This clock can be used to generate an accurate clock for SAI1 1981 * interface and/or ADC4 1982 * @arg RCC_PLL1_QCLK: This Clock is used to generate an accurate clock for RNG (<= 48 MHz). 1983 * @arg RCC_PLL1_RCLK: This Clock is used to generate and high speed system clock (up to 100MHz) 1984 * @retval None 1985 * 1986 */ 1987 #define __HAL_RCC_PLL1CLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 1988 #define __HAL_RCC_PLL1CLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 1989 1990 /** 1991 * @brief Macro to get the PLL1 clock output enable status. 1992 * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. 1993 * This parameter can be one of the following values: 1994 * @arg RCC_PLL1_PCLK 1995 * @arg RCC_PLL1_QCLK 1996 * @arg RCC_PLL1_RCLK 1997 * @retval SET / RESET 1998 */ 1999 #define __HAL_RCC_GET_PLL1CLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 2000 2001 /** 2002 * @brief Macro to configures the main PLL1 clock source, multiplication and division factors. 2003 * @note This function must be used only when the main PLL1 is disabled. 2004 * @param __PLL1SOURCE__: specifies the PLL1 entry clock source. 2005 * This parameter can be one of the following values: 2006 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry 2007 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry 2008 * @param __PLL1M__: specifies the division factor for PLL1 VCO input clock 2009 * This parameter must be a number between 1 and 8. 2010 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2011 * frequency ranges from 4 to 16 MHz. 2012 * @param __PLL1N__: specifies the multiplication factor for PLL1 VCO output clock 2013 * This parameter must be a number between 4 and 512. 2014 * @note You have to set the PLLN parameter correctly to ensure that the VCO output 2015 * frequency is between 128 and 544 MHz. 2016 * @param __PLL1P__: specifies the division factor for system clock. 2017 * This parameter must be an even number between 2 and 128. 2018 * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks 2019 * This parameter must be a number between 1 and 128 2020 * @param __PLL1R__: specifies the division factor for peripheral kernel clocks 2021 * This parameter must be a number between 1 and 128 2022 * @retval None 2023 */ 2024 #define __HAL_RCC_PLL1_CONFIG(__PLL1SOURCE__, __PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ 2025 do{ \ 2026 MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), ((__PLL1SOURCE__) | (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos))); \ 2027 WRITE_REG(RCC->PLL1DIVR, (((__PLL1N__) - 1U) | (((__PLL1P__) - 1U) << RCC_PLL1DIVR_PLL1P_Pos) | (((__PLL1Q__) - 1U) << RCC_PLL1DIVR_PLL1Q_Pos) | \ 2028 (((__PLL1R__) - 1U) << RCC_PLL1DIVR_PLL1R_Pos))); \ 2029 } while(0) 2030 2031 /** 2032 * @brief Macro to configure the PLL1 clock source. 2033 * @note This function must be used only when PLL1 is disabled. 2034 * @param __PLL1SOURCE__: specifies the PLLs entry clock source. 2035 * This parameter can be one of the following values: 2036 * @arg RCC_PLLSOURCE_NONE: No clock selected as PLL1 clock entry (used to save Power) 2037 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry 2038 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry 2039 * 2040 */ 2041 #define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLL1SOURCE__) \ 2042 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) 2043 2044 /** 2045 *@brief Macro to select the PLL1 VCO input frequency range. 2046 * @param __VCOINPUTRANGE__: specifies VCO input frequency range 2047 * This parameter can be one of the following values: 2048 * @arg RCC_PLL_VCOINPUT_RANGE0: Range frequency is between 4 and 8 MHz 2049 * @arg RCC_PLL_VCOINPUT_RANGE1: Range frequency is between 8 and 16 MHz 2050 * @retval None 2051 */ 2052 #define __HAL_RCC_PLL1_VCOINPUTRANGE_CONFIG(__VCOINPUTRANGE__) \ 2053 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__VCOINPUTRANGE__)) 2054 2055 /** 2056 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 2057 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 2058 * @retval None 2059 */ 2060 #define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 2061 #define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 2062 2063 /** 2064 * @brief Macro to configures the main PLL1 clock fractional part of The multiplication factor 2065 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 2066 * @param __PLL1FRACN__: specifies Fractional part of the multiplication factor for PLL1 VCO 2067 * It should be a value between 0 and 8191 2068 * @retval None 2069 */ 2070 #define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, (__PLL1FRACN__) << RCC_PLL1FRACR_PLL1FRACN_Pos) 2071 2072 2073 /** 2074 * @brief Macro to get the oscillator used as PLL1 clock source. 2075 * @retval The oscillator used as PLL1 clock source. The returned value can be one 2076 * of the following: 2077 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL1 clock source. 2078 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL1 clock source. 2079 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL1 clock source. 2080 */ 2081 #define __HAL_RCC_GET_PLL1_OSCSOURCE() (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC) 2082 2083 /** 2084 * @brief Macro to configure the system clock source. 2085 * @param __SYSCLKSOURCE__: specifies the system clock source. 2086 * This parameter can be one of the following values: 2087 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 2088 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 2089 * - RCC_SYSCLKSOURCE_PLLCLK: PLL1 output is used as system clock source. 2090 * @retval None 2091 */ 2092 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) 2093 2094 /** 2095 * @brief Macro to get the clock source used as system clock. 2096 * @retval The clock source used as system clock. The returned value can be one 2097 * of the following: 2098 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 2099 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 2100 * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock. 2101 */ 2102 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR1 & RCC_CFGR1_SWS) 2103 2104 /** 2105 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 2106 * @note As the LSE is in the Backup domain and write access is denied to 2107 * this domain after reset, you have to enable write access using 2108 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2109 * (to be done once after reset). 2110 * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0) 2111 * when the LSE is ON. However, once LSEDRV is selected, the drive 2112 * capability can not be increased if LSEON = 1. 2113 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 2114 * This parameter can be one of the following values: 2115 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 2116 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 2117 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 2118 * @retval None 2119 */ 2120 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSEDRV, (__LSEDRIVE__)) 2121 2122 /** 2123 * @brief Macro to configure the MCO clock. 2124 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 2125 * This parameter can be one of the following values: 2126 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 2127 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 2128 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 2129 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source 2130 * @arg @ref RCC_MCO1SOURCE_PLL1RCLK Main PLL1 clock selected as MCO source 2131 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 2132 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 2133 * @arg @ref RCC_MCO1SOURCE_PLL1PCLK pll1pclk selected as MCO source 2134 * @arg @ref RCC_MCO1SOURCE_PLL1QCLK pll1qclk selected as MCO source 2135 * @arg @ref RCC_MCO1SOURCE_HCLK5 phclk5 selected as MCO source 2136 * @param __MCODIV__ specifies the MCO clock prescaler. 2137 * This parameter can be one of the following values: 2138 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 2139 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 2140 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 2141 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 2142 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 2143 */ 2144 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 2145 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 2146 2147 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 2148 * @brief macros to manage the specified RCC Flags and interrupts. 2149 * @{ 2150 */ 2151 2152 /** 2153 * @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 2154 * the selected interrupts). 2155 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 2156 * This parameter can be any combination of the following values: 2157 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt 2158 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2159 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2160 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2161 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 2162 * @arg @ref RCC_IT_CSS HSE32 Clock Security System Interrupt 2163 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) 2164 #if defined(RCC_CCIPR2_ASSEL) 2165 * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) 2166 * @arg @ref RCC_IT_COMPARER Comparer Interrupt flag(*) 2167 * @arg @ref RCC_IT_CAPTURE_TRIGGER Capture Trigger Interrupt flag(*) 2168 #endif 2169 * (*) Feature not available on all devices of the family 2170 * @retval None 2171 */ 2172 #if defined(RCC_CCIPR2_ASSEL) 2173 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ 2174 SET_BIT(RCC->CIER,1U << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ 2175 SET_BIT(RCC->ASIER,1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) 2176 #else 2177 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 2178 #endif /* RCC_CCIPR2_ASSEL */ 2179 2180 /** 2181 * @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 2182 * the selected interrupts). 2183 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 2184 * This parameter can be any combination of the following values: 2185 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt 2186 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2187 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2188 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2189 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 2190 * @arg @ref RCC_IT_CSS HSE32 Clock Security System Interrupt 2191 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) 2192 #if defined(RCC_CCIPR2_ASSEL) 2193 * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) 2194 * @arg @ref RCC_IT_COMPARER Comparer Interrupt flag(*) 2195 * @arg @ref RCC_IT_CAPTURE_TRIGGER Capture Trigger Interrupt flag(*) 2196 #endif 2197 * (*) Feature not available on all devices of the family 2198 * @retval None 2199 */ 2200 #if defined(RCC_CCIPR2_ASSEL) 2201 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ 2202 CLEAR_BIT(RCC->CIER,1U << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ 2203 CLEAR_BIT(RCC->ASIER,1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) 2204 #else 2205 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 2206 #endif /* RCC_CCIPR2_ASSEL */ 2207 2208 /** 2209 * @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 2210 * bits to clear the selected interrupt pending bits. 2211 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 2212 * This parameter can be any combination of the following values: 2213 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt 2214 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2215 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2216 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2217 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 2218 * @arg @ref RCC_IT_CSS HSE32 Clock Security System Interrupt 2219 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) 2220 #if defined(RCC_CCIPR2_ASSEL) 2221 * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) 2222 * @arg @ref RCC_IT_COMPARER Comparer Interrupt flag(*) 2223 * @arg @ref RCC_IT_CAPTURE_TRIGGER Capture Trigger Interrupt flag(*) 2224 #endif 2225 * (*) Feature not available on all devices of the family 2226 * @retval None 2227 */ 2228 #if defined(RCC_CCIPR2_ASSEL) 2229 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ 2230 WRITE_REG(RCC->CICR,1U << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ 2231 CLEAR_BIT(RCC->ASSR,1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) 2232 #else 2233 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 2234 #endif /* RCC_CCIPR2_ASSEL */ 2235 2236 /** @brief Check whether the RCC interrupt has occurred or not. 2237 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 2238 * This parameter can be one of the following values: 2239 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt 2240 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2241 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2242 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2243 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 2244 * @arg @ref RCC_IT_CSS HSE32 Clock Security System Interrupt 2245 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) 2246 #if defined(RCC_CCIPR2_ASSEL) 2247 * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) 2248 * @arg @ref RCC_IT_COMPARER Comparer Interrupt flag(*) 2249 * @arg @ref RCC_IT_CAPTURE_TRIGGER Capture Trigger Interrupt flag(*) 2250 #endif 2251 * (*) Feature not available on all devices of the family 2252 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2253 */ 2254 #if defined(RCC_CCIPR2_ASSEL) 2255 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ 2256 ((RCC->CIFR & (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) : \ 2257 ((RCC->ASSR & (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1U << ((__INTERRUPT__) & RCC_FLAG_MASK)))) 2258 #else 2259 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 2260 #endif /* RCC_CCIPR2_ASSEL */ 2261 2262 /** @brief Set RMVF bit to clear the reset flags. 2263 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 2264 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 2265 * @retval None 2266 */ 2267 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 2268 2269 /** 2270 * @brief Check whether the selected RCC flag is set or not. 2271 * @param __FLAG__: specifies the flag to check. 2272 * This parameter can be one of the following values: 2273 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 2274 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 2275 * @arg @ref RCC_FLAG_PLL1RDY PLL1 clock ready 2276 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 2277 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 2278 * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready 2279 * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready(*) 2280 * @arg @ref RCC_FLAG_BORRST BOR reset 2281 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 2282 * @arg @ref RCC_FLAG_PINRST Pin reset 2283 * @arg @ref RCC_FLAG_SFTRST Software reset 2284 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 2285 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset(*) 2286 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 2287 * (*) Feature not available on all devices of the family 2288 * @retval The new state of __FLAG__ (TRUE or FALSE). 2289 */ 2290 #define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 2291 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR1 : \ 2292 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 2293 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 2294 /** 2295 * @} 2296 */ 2297 2298 /** 2299 * @} 2300 */ 2301 2302 /* Private constants ---------------------------------------------------------*/ 2303 /** @defgroup RCC_Private_Constants RCC Private Constants 2304 * @{ 2305 */ 2306 #define PLL_VCOINPUTFREQ_MAX 16000000U /* Maximum VCO input frequency is 16 MHz */ 2307 #define PLL_VCOINPUTFREQ_MIN 4000000U /* Minimum VCO input frequency is 4 MHz */ 2308 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 2309 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 2310 2311 2312 /* Defines used for Flags */ 2313 #define CR_REG_INDEX (1U) 2314 #define BDCR1_REG_INDEX (2U) 2315 #define CSR_REG_INDEX (3U) 2316 #if defined(RCC_CCIPR2_ASSEL) 2317 /* Defines used for Interrupt Flags */ 2318 #define CIFR_REG_INDEX (0U) 2319 #define ASSR_REG_INDEX (1U) 2320 #endif /* RCC_CCIPR2_ASSEL */ 2321 2322 #define RCC_FLAG_MASK (0x1FU) 2323 2324 /* Define used for IS_RCC_* below */ 2325 #define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_HCLK5 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK7) /*!< All clocktype to configure */ 2326 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI) /*!< All Oscillator to configure */ 2327 2328 /** 2329 * @} 2330 */ 2331 2332 /* Private macros ------------------------------------------------------------*/ 2333 /** @addtogroup RCC_Private_Macros 2334 * @{ 2335 */ 2336 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 2337 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 2338 2339 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON)) 2340 2341 #define IS_RCC_HSEDIV(__HSEDIV__) (((__HSEDIV__) == RCC_HSE_DIV1) || ((__HSEDIV__) == RCC_HSE_DIV2)) 2342 2343 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || \ 2344 ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ 2345 ((__LSE__) == RCC_LSE_BYPASS)) 2346 2347 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 2348 2349 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR3_HSITRIM >> RCC_ICSCR3_HSITRIM_Pos)) 2350 2351 #if defined(RCC_LSI2_SUPPORT) 2352 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI1_ON) || \ 2353 ((__LSI__) == RCC_LSI2_ON)) 2354 #else 2355 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI1_ON)) 2356 #endif /* RCC_BDCR1_LSI2ON */ 2357 2358 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) 2359 2360 #define IS_RCC_PLL(PLL1) (((PLL1) == RCC_PLL_NONE) ||((PLL1) == RCC_PLL_OFF) || \ 2361 ((PLL1) == RCC_PLL_ON)) 2362 2363 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ 2364 ((SOURCE) == RCC_PLLSOURCE_HSE)) 2365 2366 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 8U)) 2367 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 2368 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 2369 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 2370 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 2371 2372 #define IS_RCC_PLL_VCOINPUTFREQ(VALUE) ((PLL_VCOINPUTFREQ_MIN <= (VALUE)) && ((VALUE) <= PLL_VCOINPUTFREQ_MAX)) 2373 2374 #define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= (RCC_PLL1FRACR_PLL1FRACN >> RCC_PLL1FRACR_PLL1FRACN_Pos)) 2375 2376 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) 2377 2378 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 2379 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 2380 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 2381 2382 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 2383 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 2384 ((__HCLK__) == RCC_SYSCLK_DIV16)) 2385 2386 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 2387 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 2388 ((__PCLK__) == RCC_HCLK_DIV16)) 2389 2390 #define IS_RCC_HCLK5_PLL1(__HCLK5__) (((__HCLK5__) == RCC_SYSCLK_PLL1_DIV1) || ((__HCLK5__) == RCC_SYSCLK_PLL1_DIV2) || \ 2391 ((__HCLK5__) == RCC_SYSCLK_PLL1_DIV3) || ((__HCLK5__) == RCC_SYSCLK_PLL1_DIV4) || \ 2392 ((__HCLK5__) == RCC_SYSCLK_PLL1_DIV6)) 2393 2394 #define IS_RCC_HCLK5_HSEHSI(__HCLK5__) (((__HCLK5__) == RCC_SYSCLK_HSEHSI_DIV1) || ((__HCLK5__) == RCC_SYSCLK_HSEHSI_DIV2)) 2395 2396 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_DISABLE) || \ 2397 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 2398 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 2399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 2400 2401 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 2402 2403 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 2404 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 2405 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 2406 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 2407 ((__SOURCE__) == RCC_MCO1SOURCE_PLL1RCLK) || \ 2408 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 2409 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 2410 ((__SOURCE__) == RCC_MCO1SOURCE_PLL1PCLK) || \ 2411 ((__SOURCE__) == RCC_MCO1SOURCE_PLL1QCLK) || \ 2412 ((__SOURCE__) == RCC_MCO1SOURCE_HCLK5)) 2413 2414 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 2415 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 2416 ((__DIV__) == RCC_MCODIV_16)) 2417 2418 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 2419 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 2420 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 2421 2422 #define IS_RCC_ITEM_ATTRIBUTES(__ITEM__) (((__ITEM__) != 0x00U) && (((__ITEM__) & ~RCC_ALL) == 0x00U)) 2423 2424 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2425 #define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == RCC_SEC_PRIV) || \ 2426 ((__ATTRIBUTES__) == RCC_SEC_NPRIV) || \ 2427 ((__ATTRIBUTES__) == RCC_NSEC_PRIV) || \ 2428 ((__ATTRIBUTES__) == RCC_NSEC_NPRIV)) 2429 #else 2430 #define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == RCC_NSEC_NPRIV) || ((__ATTRIBUTES__) == RCC_NSEC_PRIV)) 2431 #endif /* __ARM_FEATURE_CMSE */ 2432 /** 2433 * @} 2434 */ 2435 2436 /** 2437 * @} 2438 */ 2439 /* Include RCC HAL Extended module */ 2440 #include "stm32wbaxx_hal_rcc_ex.h" 2441 2442 /* Exported functions ----------------------------------------------------------*/ 2443 /** @addtogroup RCC_Exported_Functions 2444 * @{ 2445 */ 2446 2447 /** @addtogroup RCC_Exported_Functions_Group1 2448 * @{ 2449 */ 2450 2451 /* Initialization and de-initialization functions ******************************/ 2452 HAL_StatusTypeDef HAL_RCC_DeInit(void); 2453 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); 2454 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 2455 2456 /** 2457 * @} 2458 */ 2459 2460 /** @addtogroup RCC_Exported_Functions_Group2 2461 * @{ 2462 */ 2463 /* Peripheral Control functions **********************************************/ 2464 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 2465 void HAL_RCC_EnableCSS(void); 2466 uint32_t HAL_RCC_GetSysClockFreq(void); 2467 uint32_t HAL_RCC_GetHCLKFreq(void); 2468 uint32_t HAL_RCC_GetPCLK1Freq(void); 2469 uint32_t HAL_RCC_GetPCLK2Freq(void); 2470 uint32_t HAL_RCC_GetPCLK7Freq(void); 2471 uint32_t HAL_RCC_GetHCLK5Freq(void); 2472 uint32_t HAL_RCC_GetPLL1PFreq(void); 2473 uint32_t HAL_RCC_GetPLL1QFreq(void); 2474 uint32_t HAL_RCC_GetPLL1RFreq(void); 2475 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 2476 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 2477 /* CSS NMI IRQ handler */ 2478 void HAL_RCC_NMI_IRQHandler(void); 2479 /* User Callbacks in non blocking mode (IT mode) */ 2480 void HAL_RCC_CSSCallback(void); 2481 uint32_t HAL_RCC_GetResetSource(void); 2482 /** 2483 * @} 2484 */ 2485 2486 /** @addtogroup RCC_Exported_Functions_Group3 2487 * @{ 2488 */ 2489 /* Attributes management functions ********************************************/ 2490 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 2491 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 2492 /** 2493 * @} 2494 */ 2495 2496 /** 2497 * @} 2498 */ 2499 2500 /** 2501 * @} 2502 */ 2503 2504 /** 2505 * @} 2506 */ 2507 2508 #ifdef __cplusplus 2509 } 2510 #endif 2511 2512 #endif /* __STM32WBAxx_HAL_RCC_H */ 2513 2514
