1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L5xx_HAL_RCC_EX_H 22 #define STM32L5xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_hal_def.h" 30 31 /** @addtogroup STM32L5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief PLLSAI1 Clock structure definition 47 */ 48 typedef struct 49 { 50 51 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. 52 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Source */ 53 54 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 55 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 56 57 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. 58 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 59 60 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. 61 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 62 63 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. 64 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 65 66 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. 67 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 68 69 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. 70 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ 71 } RCC_PLLSAI1InitTypeDef; 72 73 /** 74 * @brief PLLSAI2 Clock structure definition 75 */ 76 typedef struct 77 { 78 79 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. 80 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Source */ 81 82 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 83 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 84 85 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. 86 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 87 88 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. 89 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 90 91 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. 92 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ 93 } RCC_PLLSAI2InitTypeDef; 94 95 /** 96 * @brief RCC extended clocks structure definition 97 */ 98 typedef struct 99 { 100 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 101 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 102 103 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. 104 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ 105 106 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. 107 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ 108 109 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 110 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 111 112 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 113 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 114 115 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 116 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 117 118 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 119 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 120 121 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 122 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 123 124 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 125 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 126 127 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 128 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 129 130 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 131 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 132 133 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 134 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 135 136 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 137 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 138 139 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 140 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 141 142 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 143 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 144 145 uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. 146 This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ 147 148 uint32_t FdcanClockSelection; /*!< Specifies FDCAN kernel clock source. 149 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 150 151 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 152 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 153 154 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 155 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 156 157 #if defined(USB) 158 159 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). 160 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 161 162 #endif /* USB */ 163 164 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). 165 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 166 167 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). 168 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 169 170 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 171 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 172 173 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. 174 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 175 176 uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. 177 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 178 179 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 180 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 181 182 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 183 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 184 } RCC_PeriphCLKInitTypeDef; 185 186 187 #if defined(CRS) 188 189 /** 190 * @brief RCC_CRS Init structure definition 191 */ 192 typedef struct 193 { 194 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 195 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 196 197 uint32_t Source; /*!< Specifies the SYNC signal source. 198 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 199 200 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 201 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 202 203 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 204 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 205 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 206 207 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 208 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 209 210 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 211 This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 212 213 } RCC_CRSInitTypeDef; 214 215 /** 216 * @brief RCC_CRS Synchronization structure definition 217 */ 218 typedef struct 219 { 220 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 221 This parameter must be a number between 0 and 0xFFFF */ 222 223 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 224 This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 225 226 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 227 value latched in the time of the last SYNC event. 228 This parameter must be a number between 0 and 0xFFFF */ 229 230 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 231 frequency error counter latched in the time of the last SYNC event. 232 It shows whether the actual frequency is below or above the target. 233 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 234 235 } RCC_CRSSynchroInfoTypeDef; 236 237 #endif /* CRS */ 238 /** 239 * @} 240 */ 241 242 /* Exported constants --------------------------------------------------------*/ 243 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 244 * @{ 245 */ 246 247 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 248 * @{ 249 */ 250 #define RCC_LSCOSOURCE_LSI 0U /*!< LSI selection for low speed clock output */ 251 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 252 /** 253 * @} 254 */ 255 256 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 257 * @{ 258 */ 259 #define RCC_PERIPHCLK_USART1 0x00000001U 260 #define RCC_PERIPHCLK_USART2 0x00000002U 261 #define RCC_PERIPHCLK_USART3 0x00000004U 262 #define RCC_PERIPHCLK_UART4 0x00000008U 263 #define RCC_PERIPHCLK_UART5 0x00000010U 264 #define RCC_PERIPHCLK_LPUART1 0x00000020U 265 #define RCC_PERIPHCLK_I2C1 0x00000040U 266 #define RCC_PERIPHCLK_I2C2 0x00000080U 267 #define RCC_PERIPHCLK_I2C3 0x00000100U 268 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 269 #define RCC_PERIPHCLK_LPTIM2 0x00000400U 270 #define RCC_PERIPHCLK_SAI1 0x00000800U 271 #define RCC_PERIPHCLK_SAI2 0x00001000U 272 #if defined(USB) 273 #define RCC_PERIPHCLK_USB 0x00002000U 274 #endif /* USB */ 275 #define RCC_PERIPHCLK_ADC 0x00004000U 276 #define RCC_PERIPHCLK_DFSDM1 0x00010000U 277 #define RCC_PERIPHCLK_RTC 0x00020000U 278 #define RCC_PERIPHCLK_RNG 0x00040000U 279 #define RCC_PERIPHCLK_SDMMC1 0x00080000U 280 #define RCC_PERIPHCLK_I2C4 0x00100000U 281 #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U 282 #define RCC_PERIPHCLK_LPTIM3 0x00400000U 283 #define RCC_PERIPHCLK_OSPI 0x01000000U 284 #define RCC_PERIPHCLK_FDCAN 0x02000000U 285 /** 286 * @} 287 */ 288 289 290 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 291 * @{ 292 */ 293 #define RCC_USART1CLKSOURCE_PCLK2 0U /*!< PCLK2 */ 294 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR1_USART1SEL_0 /*!< System clock */ 295 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR1_USART1SEL_1 /*!< HSI */ 296 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) /*!< LSE */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 302 * @{ 303 */ 304 #define RCC_USART2CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 305 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR1_USART2SEL_0 /*!< System clock */ 306 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR1_USART2SEL_1 /*!< HSI */ 307 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) /*!< LSE */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 313 * @{ 314 */ 315 #define RCC_USART3CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 316 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR1_USART3SEL_0 /*!< System clock */ 317 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR1_USART3SEL_1 /*!< HSI */ 318 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) /*!< LSE */ 319 /** 320 * @} 321 */ 322 323 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 324 * @{ 325 */ 326 #define RCC_UART4CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 327 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR1_UART4SEL_0 /*!< System clock */ 328 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR1_UART4SEL_1 /*!< HSI */ 329 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) /*!< LSE */ 330 /** 331 * @} 332 */ 333 334 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 335 * @{ 336 */ 337 #define RCC_UART5CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 338 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR1_UART5SEL_0 /*!< System clock */ 339 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR1_UART5SEL_1 /*!< HSI */ 340 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) /*!< LSE */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 346 * @{ 347 */ 348 #define RCC_LPUART1CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 349 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR1_LPUART1SEL_0 /*!< System clock */ 350 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR1_LPUART1SEL_1 /*!< HSI */ 351 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR1_LPUART1SEL_0 | RCC_CCIPR1_LPUART1SEL_1) /*!< LSE */ 352 /** 353 * @} 354 */ 355 356 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 357 * @{ 358 */ 359 #define RCC_I2C1CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 360 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 /*!< System clock */ 361 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR1_I2C1SEL_1 /*!< HSI */ 362 /** 363 * @} 364 */ 365 366 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 367 * @{ 368 */ 369 #define RCC_I2C2CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 370 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR1_I2C2SEL_0 /*!< System clock */ 371 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR1_I2C2SEL_1 /*!< HSI */ 372 /** 373 * @} 374 */ 375 376 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 377 * @{ 378 */ 379 #define RCC_I2C3CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 380 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR1_I2C3SEL_0 /*!< System clock */ 381 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR1_I2C3SEL_1 /*!< HSI */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 387 * @{ 388 */ 389 #define RCC_I2C4CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 390 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 /*!< System clock */ 391 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 /*!< HSI */ 392 /** 393 * @} 394 */ 395 396 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 397 * @{ 398 */ 399 #define RCC_SAI1CLKSOURCE_PLLSAI1 0U /*!< PLLSAI1 "P" clock (PLLSAI1CLK) */ 400 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 /*!< PLLSAI2 "P" clock (PLLSAI2CLK) */ 401 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 /*!< PLL "P" clock (PLLSAI3CLK) */ 402 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) /*!< External clock SAI1_EXTCLK */ 403 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 /*!< HSI */ 404 /** 405 * @} 406 */ 407 408 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 409 * @{ 410 */ 411 #define RCC_SAI2CLKSOURCE_PLLSAI1 0U /*!< PLLSAI1 "P" clock (PLLSAI1CLK) */ 412 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 /*!< PLLSAI2 "P" clock (PLLSAI2CLK) */ 413 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 /*!< PLL "P" clock (PLLSAI3CLK) */ 414 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) /*!< External clock SAI1_EXTCLK */ 415 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 /*!< HSI */ 416 /** 417 * @} 418 */ 419 420 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 421 * @{ 422 */ 423 #define RCC_LPTIM1CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 424 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR1_LPTIM1SEL_0 /*!< LSI */ 425 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR1_LPTIM1SEL_1 /*!< HSI */ 426 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR1_LPTIM1SEL /*!< LSE */ 427 /** 428 * @} 429 */ 430 431 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 432 * @{ 433 */ 434 #define RCC_LPTIM2CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 435 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR1_LPTIM2SEL_0 /*!< LSI */ 436 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR1_LPTIM2SEL_1 /*!< HSI */ 437 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR1_LPTIM2SEL /*!< LSE */ 438 /** 439 * @} 440 */ 441 442 /** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source 443 * @{ 444 */ 445 #define RCC_LPTIM3CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 446 #define RCC_LPTIM3CLKSOURCE_LSI RCC_CCIPR1_LPTIM3SEL_0 /*!< LSI */ 447 #define RCC_LPTIM3CLKSOURCE_HSI RCC_CCIPR1_LPTIM3SEL_1 /*!< HSI */ 448 #define RCC_LPTIM3CLKSOURCE_LSE RCC_CCIPR1_LPTIM3SEL /*!< LSE */ 449 /** 450 * @} 451 */ 452 453 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Kernel Clock Source 454 * @{ 455 */ 456 #define RCC_FDCANCLKSOURCE_HSE 0U /*!< LSE */ 457 #define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR1_FDCANSEL_0 /*!< PLL "Q" clock (PLL48M1CLK) */ 458 #define RCC_FDCANCLKSOURCE_PLLSAI1 RCC_CCIPR1_FDCANSEL_1 /*!< PLLSAI1 "P" clock (PLLSAI1CLK) */ 459 /** 460 * @} 461 */ 462 463 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source 464 * @{ 465 */ 466 #define RCC_SDMMC1CLKSOURCE_HSI48 0U /*!< HSI48 via internal multiplexer */ 467 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 "Q" clock (PLL48M2CLK) via internal multiplexer */ 468 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL "Q" clock (PLL48M1CLK) via internal multiplexer */ 469 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI via internal multiplexer */ 470 #define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "Q" clock (PLLSAI3CLK) */ 471 /** 472 * @} 473 */ 474 475 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 476 * @{ 477 */ 478 #define RCC_RNGCLKSOURCE_HSI48 0U /*!< HSI48 */ 479 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 "Q" clock (PLL48M2CLK) */ 480 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL "Q" clock (PLL48M1CLK) */ 481 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI */ 482 /** 483 * @} 484 */ 485 486 #if defined(USB) 487 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 488 * @{ 489 */ 490 #define RCC_USBCLKSOURCE_HSI48 0U /*!< HSI48 */ 491 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 "Q" clock (PLL48M2CLK) */ 492 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL "Q" clock (PLL48M1CLK) */ 493 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI */ 494 /** 495 * @} 496 */ 497 #endif /* USB */ 498 499 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 500 * @{ 501 */ 502 #define RCC_ADCCLKSOURCE_NONE 0U /*!< No clock */ 503 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR1_ADCSEL_0 /*!< PLLSAI "R" clock (PLLADC1CLK) */ 504 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR1_ADCSEL /*!< System clock */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source 510 * @{ 511 */ 512 #define RCC_DFSDM1CLKSOURCE_PCLK2 0U /*!< PCLK2 */ 513 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDMSEL /*!< System clock */ 514 /** 515 * @} 516 */ 517 518 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source 519 * @{ 520 */ 521 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0U /*!< SAI1 clock */ 522 #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDMSEL_0 /*!< HSI */ 523 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDMSEL_1 /*!< MSI */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 529 * @{ 530 */ 531 #define RCC_OSPICLKSOURCE_SYSCLK 0U /*!< System clock */ 532 #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI */ 533 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL "Q" clock (PLL48M1CLK) */ 534 /** 535 * @} 536 */ 537 538 539 /** @defgroup RCCEx_SecureMode RCCEx Secure Mode 540 * @note Only available when system implements security (TZEN=1) 541 * @{ 542 */ 543 #define RCC_SECURE_NONE 0U /*!< No security on RCC resources (default) */ 544 #define RCC_SECURE_ALL 0x1FFFU /*!< Security on all RCC resources */ 545 546 #define RCC_SECURE_HSI RCC_SECCFGR_HSISEC /*!< HSI clock configuration security */ 547 #define RCC_SECURE_HSE RCC_SECCFGR_HSESEC /*!< HSE clock configuration security */ 548 #define RCC_SECURE_MSI RCC_SECCFGR_MSISEC /*!< MSI clock configuration security */ 549 #define RCC_SECURE_LSI RCC_SECCFGR_LSISEC /*!< LSI clock configuration security */ 550 #define RCC_SECURE_SYSCLK RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration security */ 551 #define RCC_SECURE_PRESCALERS RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration security */ 552 #define RCC_SECURE_PLL RCC_SECCFGR_PLLSEC /*!< main PLL clock configuration security */ 553 #define RCC_SECURE_PLLSAI1 RCC_SECCFGR_PLLSAI1SEC /*!< PLLSAI1 clock configuration security */ 554 #define RCC_SECURE_PLLSAI2 RCC_SECCFGR_PLLSAI2SEC /*!< PLLSAI2 clock configuration security */ 555 #define RCC_SECURE_CLK48M RCC_SECCFGR_CLK48MSEC /*!< 48MHz clock source selection security */ 556 #define RCC_SECURE_HSI48 RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration security */ 557 #define RCC_SECURE_RESET_FLAGS RCC_SECCFGR_RMVFSEC /*!< Remove reset flag security */ 558 /** 559 * @} 560 */ 561 562 #if defined(CRS) 563 564 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 565 * @{ 566 */ 567 #define RCC_CRS_NONE 0x00000000U 568 #define RCC_CRS_TIMEOUT 0x00000001U 569 #define RCC_CRS_SYNCOK 0x00000002U 570 #define RCC_CRS_SYNCWARN 0x00000004U 571 #define RCC_CRS_SYNCERR 0x00000008U 572 #define RCC_CRS_SYNCMISS 0x00000010U 573 #define RCC_CRS_TRIMOVF 0x00000020U 574 /** 575 * @} 576 */ 577 578 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 579 * @{ 580 */ 581 #define RCC_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchro Signal source GPIO */ 582 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 583 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 584 /** 585 * @} 586 */ 587 588 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 589 * @{ 590 */ 591 #define RCC_CRS_SYNC_DIV1 0U /*!< Synchro Signal not divided (default) */ 592 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 593 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 594 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 595 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 596 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 597 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 598 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 604 * @{ 605 */ 606 #define RCC_CRS_SYNC_POLARITY_RISING 0U /*!< Synchro Active on rising edge (default) */ 607 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 608 /** 609 * @} 610 */ 611 612 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 613 * @{ 614 */ 615 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 616 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 617 /** 618 * @} 619 */ 620 621 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 622 * @{ 623 */ 624 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 625 /** 626 * @} 627 */ 628 629 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 630 * @{ 631 */ 632 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. 633 The trimming step is specified in the product datasheet. A higher TRIM value corresponds 634 to a higher output frequency */ 635 /** 636 * @} 637 */ 638 639 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 640 * @{ 641 */ 642 #define RCC_CRS_FREQERRORDIR_UP 0U /*!< Upcounting direction, the actual frequency is above the target */ 643 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 644 /** 645 * @} 646 */ 647 648 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 649 * @{ 650 */ 651 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 652 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 653 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 654 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 655 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 656 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 657 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 658 659 /** 660 * @} 661 */ 662 663 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 664 * @{ 665 */ 666 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 667 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 668 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 669 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 670 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 671 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 672 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 673 674 /** 675 * @} 676 */ 677 678 #endif /* CRS */ 679 680 /** 681 * @} 682 */ 683 684 /* Exported macros -----------------------------------------------------------*/ 685 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 686 * @{ 687 */ 688 689 690 /** 691 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. 692 * 693 * @note This macro must be used only when the PLLSAI1 is disabled. 694 * @note This macro preserves the PLLSAI1's output clocks enable state. 695 * 696 * @param __PLLSAI1SOURCE__ specifies the PLLSAI1 entry clock source. 697 * This parameter can be one of the following values: 698 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLLSAI1 clock entry 699 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLLSAI1 clock entry 700 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLLSAI1 clock entry 701 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLLSAI1 clock entry 702 * 703 * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. 704 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 705 * 706 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 707 * This parameter must be a number between Min_Data = 8 and Max_Data = 86. 708 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 709 * output frequency is between 64 and 344 MHz. 710 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 711 * 712 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 713 * This parameter must be a number between Min_Data = 2 to Max_Data = 31. 714 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 715 * 716 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 717 * This parameter must be in the range (2, 4, 6 or 8). 718 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 719 * 720 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. 721 * This parameter must be in the range (2, 4, 6 or 8). 722 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R 723 * 724 * @retval None 725 */ 726 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1SOURCE__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 727 MODIFY_REG(RCC->PLLSAI1CFGR, \ 728 (RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | \ 729 RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | \ 730 RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ 731 ((__PLLSAI1SOURCE__) | \ 732 (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ 733 ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 734 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 735 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 736 ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) 737 738 /** 739 * @brief Macro to configure the PLLSAI1 clock multiplication factor N. 740 * 741 * @note This function must be used only when the PLLSAI1 is disabled. 742 * @note PLLSAI1 clock source is common with the main PLL (configured through 743 * __HAL_RCC_PLL_CONFIG() macro) 744 * 745 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 746 * This parameter must be a number between 8 and 86. 747 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 748 * output frequency is between 64 and 344 MHz. 749 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 750 * 751 * @retval None 752 */ 753 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ 754 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) 755 756 /** @brief Macro to configure the PLLSAI1 input clock division factor M. 757 * 758 * @note This function must be used only when the PLLSAI1 is disabled. 759 * @note PLLSAI1 clock source is common with the main PLL (configured through 760 * __HAL_RCC_PLL_CONFIG() macro) 761 * 762 * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. 763 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 764 * 765 * @retval None 766 */ 767 #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ 768 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) 769 770 /** @brief Macro to configure the PLLSAI1 clock division factor P. 771 * 772 * @note This function must be used only when the PLLSAI1 is disabled. 773 * @note PLLSAI1 clock source is common with the main PLL (configured through 774 * __HAL_RCC_PLL_CONFIG() macro) 775 * 776 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 777 * This parameter must be a number in the range (2 to 31). 778 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 779 * 780 * @retval None 781 */ 782 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 783 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) 784 785 /** @brief Macro to configure the PLLSAI1 clock division factor Q. 786 * 787 * @note This function must be used only when the PLLSAI1 is disabled. 788 * @note PLLSAI1 clock source is common with the main PLL (configured through 789 * __HAL_RCC_PLL_CONFIG() macro) 790 * 791 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 792 * This parameter must be in the range (2, 4, 6 or 8). 793 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 794 * 795 * @retval None 796 */ 797 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ 798 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) 799 800 /** @brief Macro to configure the PLLSAI1 clock division factor R. 801 * 802 * @note This function must be used only when the PLLSAI1 is disabled. 803 * @note PLLSAI1 clock source is common with the main PLL (configured through 804 * __HAL_RCC_PLL_CONFIG() macro) 805 * 806 * @param __PLLSAI1R__ specifies the division factor for ADC clock. 807 * This parameter must be in the range (2, 4, 6 or 8) 808 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R 809 * 810 * @retval None 811 */ 812 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ 813 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) 814 815 /** 816 * @brief Macros to enable or disable the PLLSAI1. 817 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 818 * @retval None 819 */ 820 821 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 822 823 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 824 825 /** 826 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 827 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 828 * This is mainly used to save Power. 829 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 830 * This parameter can be one or a combination of the following values: 831 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 832 * high-quality audio performance on SAI interface in case. 833 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB FS (48 MHz), 834 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 835 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 836 * @retval None 837 */ 838 839 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 840 841 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 842 843 /** 844 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 845 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 846 * This parameter can be one of the following values: 847 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 848 * high-quality audio performance on SAI interface in case. 849 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB FS (48 MHz), 850 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 851 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 852 * @retval SET / RESET 853 */ 854 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 855 856 /** 857 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. 858 * 859 * @note This macro must be used only when the PLLSAIS is disabled. 860 * @note This macro preserves the PLLSAI2's output clocks enable state. 861 * 862 * @param __PLLSAI2SOURCE__ specifies the PLLSAI1 entry clock source. 863 * This parameter can be one of the following values: 864 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLLSAI2 clock entry 865 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLLSAI2 clock entry 866 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLLSAI2 clock entry 867 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLLSAI2 clock entry 868 * 869 * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. 870 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 871 * 872 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 873 * This parameter must be a number between Min_Data = 8 and Max_Data = 86. 874 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 875 * output frequency is between 64 and 344 MHz. 876 * 877 * @param __PLLSAI2P__ specifies the division factor for SAI clock. 878 * This parameter must be a number between Min_Data = 2 and Max_Data = 31. 879 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P 880 * 881 * @retval None 882 */ 883 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2SOURCE__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ 884 MODIFY_REG(RCC->PLLSAI2CFGR, \ 885 (RCC_PLLSAI2CFGR_PLLSAI2SRC | RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | \ 886 RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 887 ((__PLLSAI2SOURCE__) | \ 888 (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ 889 ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 890 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 891 892 /** 893 * @brief Macro to configure the PLLSAI2 clock multiplication factor N. 894 * 895 * @note This function must be used only when the PLLSAI2 is disabled. 896 * @note PLLSAI2 clock source is common with the main PLL (configured through 897 * __HAL_RCC_PLL_CONFIG() macro) 898 * 899 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 900 * This parameter must be a number between 8 and 86. 901 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 902 * output frequency is between 64 and 344 MHz. 903 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N 904 * 905 * @retval None 906 */ 907 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ 908 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) 909 910 /** @brief Macro to configure the PLLSAI2 input clock division factor M. 911 * 912 * @note This function must be used only when the PLLSAI2 is disabled. 913 * @note PLLSAI2 clock source is common with the main PLL (configured through 914 * __HAL_RCC_PLL_CONFIG() macro) 915 * 916 * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. 917 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 918 * 919 * @retval None 920 */ 921 922 #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ 923 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) 924 925 /** @brief Macro to configure the PLLSAI2 clock division factor P. 926 * 927 * @note This function must be used only when the PLLSAI2 is disabled. 928 * @note PLLSAI2 clock source is common with the main PLL (configured through 929 * __HAL_RCC_PLL_CONFIG() macro) 930 * 931 * @param __PLLSAI2P__ specifies the division factor. 932 * This parameter must be a number in the range (7 or 17). 933 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ 934 * 935 * @retval None 936 */ 937 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ 938 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) 939 940 /** 941 * @brief Macros to enable or disable the PLLSAI2. 942 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. 943 * @retval None 944 */ 945 946 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 947 948 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 949 950 /** 951 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2). 952 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 953 * This is mainly used to save Power. 954 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 955 * This parameter can be one or a combination of the following values: 956 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 957 * high-quality audio performance on SAI interface in case. 958 * @retval None 959 */ 960 961 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 962 963 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 964 965 /** 966 * @brief Macro to get clock output enable status (PLLSAI2_SAI2). 967 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 968 * This parameter can be one of the following values: 969 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 970 * high-quality audio performance on SAI interface in case. 971 * @retval SET / RESET 972 */ 973 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 974 975 /** 976 * @brief Macro to configure the SAI1 clock source. 977 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 978 * from the PLLSAI1, system PLL or external clock (through a dedicated pin). 979 * This parameter can be one of the following values: 980 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 981 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 982 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 983 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 984 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 985 * 986 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. 987 * 988 * @retval None 989 */ 990 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 991 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) 992 993 /** @brief Macro to get the SAI1 clock source. 994 * @retval The clock source can be one of the following values: 995 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 996 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 997 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 998 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 999 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 1000 * 1001 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 1002 * clock source when PLLs are disabled for devices without PLLSAI2. 1003 * 1004 */ 1005 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) 1006 1007 /** 1008 * @brief Macro to configure the SAI2 clock source. 1009 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived 1010 * from the PLLSAI2, system PLL or external clock (through a dedicated pin). 1011 * This parameter can be one of the following values: 1012 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1013 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 1014 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 1015 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1016 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 1017 * 1018 * @retval None 1019 */ 1020 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 1021 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) 1022 1023 /** @brief Macro to get the SAI2 clock source. 1024 * @retval The clock source can be one of the following values: 1025 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1026 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 1027 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 1028 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1029 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 1030 */ 1031 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) 1032 1033 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1034 * 1035 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1036 * This parameter can be one of the following values: 1037 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1038 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1039 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1040 * @retval None 1041 */ 1042 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1043 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 1044 1045 /** @brief Macro to get the I2C1 clock source. 1046 * @retval The clock source can be one of the following values: 1047 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1048 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1049 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1050 */ 1051 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL))) 1052 1053 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 1054 * 1055 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 1056 * This parameter can be one of the following values: 1057 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1058 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1059 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1060 * @retval None 1061 */ 1062 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 1063 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 1064 1065 /** @brief Macro to get the I2C2 clock source. 1066 * @retval The clock source can be one of the following values: 1067 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1068 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1069 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1070 */ 1071 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL))) 1072 1073 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 1074 * 1075 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1076 * This parameter can be one of the following values: 1077 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1078 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1079 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1080 * @retval None 1081 */ 1082 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1083 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 1084 1085 /** @brief Macro to get the I2C3 clock source. 1086 * @retval The clock source can be one of the following values: 1087 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1088 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1089 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1090 */ 1091 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C3SEL))) 1092 1093 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 1094 * 1095 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 1096 * This parameter can be one of the following values: 1097 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1098 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1099 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1100 * @retval None 1101 */ 1102 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 1103 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 1104 1105 /** @brief Macro to get the I2C4 clock source. 1106 * @retval The clock source can be one of the following values: 1107 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1108 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1109 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1110 */ 1111 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))) 1112 1113 1114 /** @brief Macro to configure the USART1 clock (USART1CLK). 1115 * 1116 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1117 * This parameter can be one of the following values: 1118 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1119 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1120 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1121 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 1122 * @retval None 1123 */ 1124 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1125 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 1126 1127 /** @brief Macro to get the USART1 clock source. 1128 * @retval The clock source can be one of the following values: 1129 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1130 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1131 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1132 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1133 */ 1134 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) 1135 1136 /** @brief Macro to configure the USART2 clock (USART2CLK). 1137 * 1138 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 1139 * This parameter can be one of the following values: 1140 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1141 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1142 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1143 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1144 * @retval None 1145 */ 1146 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 1147 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 1148 1149 /** @brief Macro to get the USART2 clock source. 1150 * @retval The clock source can be one of the following values: 1151 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1152 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1153 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1154 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1155 */ 1156 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) 1157 1158 /** @brief Macro to configure the USART3 clock (USART3CLK). 1159 * 1160 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 1161 * This parameter can be one of the following values: 1162 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1163 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1164 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1165 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1166 * @retval None 1167 */ 1168 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 1169 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 1170 1171 /** @brief Macro to get the USART3 clock source. 1172 * @retval The clock source can be one of the following values: 1173 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1174 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1175 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1176 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1177 */ 1178 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) 1179 1180 /** @brief Macro to configure the UART4 clock (UART4CLK). 1181 * 1182 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 1183 * This parameter can be one of the following values: 1184 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1185 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1186 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1187 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1188 * @retval None 1189 */ 1190 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 1191 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 1192 1193 /** @brief Macro to get the UART4 clock source. 1194 * @retval The clock source can be one of the following values: 1195 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1196 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1197 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1198 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1199 */ 1200 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) 1201 1202 /** @brief Macro to configure the UART5 clock (UART5CLK). 1203 * 1204 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 1205 * This parameter can be one of the following values: 1206 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1207 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1208 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1209 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1210 * @retval None 1211 */ 1212 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 1213 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 1214 1215 /** @brief Macro to get the UART5 clock source. 1216 * @retval The clock source can be one of the following values: 1217 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1218 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1219 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1220 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1221 */ 1222 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) 1223 1224 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1225 * 1226 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1227 * This parameter can be one of the following values: 1228 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1229 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1230 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1231 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1232 * @retval None 1233 */ 1234 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1235 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 1236 1237 /** @brief Macro to get the LPUART1 clock source. 1238 * @retval The clock source can be one of the following values: 1239 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1240 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1241 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1242 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1243 */ 1244 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL))) 1245 1246 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1247 * 1248 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1249 * This parameter can be one of the following values: 1250 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 1251 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1252 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 1253 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1254 * @retval None 1255 */ 1256 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1257 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1258 1259 /** @brief Macro to get the LPTIM1 clock source. 1260 * @retval The clock source can be one of the following values: 1261 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 1262 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1263 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 1264 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1265 */ 1266 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM1SEL))) 1267 1268 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1269 * 1270 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1271 * This parameter can be one of the following values: 1272 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1273 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1274 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 1275 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1276 * @retval None 1277 */ 1278 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1279 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 1280 1281 /** @brief Macro to get the LPTIM2 clock source. 1282 * @retval The clock source can be one of the following values: 1283 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1284 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1285 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 1286 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1287 */ 1288 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL))) 1289 1290 /** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK). 1291 * 1292 * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. 1293 * This parameter can be one of the following values: 1294 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK1 selected as LPTIM3 clock 1295 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 1296 * @arg @ref RCC_LPTIM3CLKSOURCE_HSI HSI selected as LPTIM3 clock 1297 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 1298 * @retval None 1299 */ 1300 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ 1301 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) 1302 1303 /** @brief Macro to get the LPTIM3 clock source. 1304 * @retval The clock source can be one of the following values: 1305 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK1 selected as LPTIM3 clock 1306 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 1307 * @arg @ref RCC_LPTIM3CLKSOURCE_HSI HSI selected as LPTIM3 clock 1308 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 1309 */ 1310 #define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM3SEL))) 1311 1312 /** @brief Macro to configure the FDCAN kernel clock (FDCANCLK). 1313 * 1314 * @param __FDCAN_CLKSOURCE__ specifies the FDCAN kernel clock source. 1315 * This parameter can be one of the following values: 1316 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock 1317 * @arg @ref RCC_FDCANCLKSOURCE_PLL PLL Clock selected as FDCAN kernel clock 1318 * @arg @ref RCC_FDCANCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as FDCAN kernel clock 1319 * @retval None 1320 */ 1321 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ 1322 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 1323 1324 /** @brief Macro to get the FDCAN clock source. 1325 * @retval The clock source can be one of the following values: 1326 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock 1327 * @arg @ref RCC_FDCANCLKSOURCE_PLL PLL Clock selected as FDCAN kernel clock 1328 * @arg @ref RCC_FDCANCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as FDCAN kernel clock 1329 */ 1330 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL))) 1331 1332 /** @brief Macro to configure the SDMMC1 clock. 1333 * 1334 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. 1335 * This parameter can be one of the following values: 1336 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock via internal multiplexer 1337 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock via internal multiplexer 1338 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock via internal multiplexer 1339 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock via internal multiplexer 1340 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock 1341 * @retval None 1342 */ 1343 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 1344 do \ 1345 { \ 1346 if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ 1347 { \ 1348 SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 1349 } \ 1350 else \ 1351 { \ 1352 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \ 1353 CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 1354 } \ 1355 } while(0) 1356 1357 /** @brief Macro to get the SDMMC1 clock. 1358 * @retval The clock source can be one of the following values: 1359 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock via internal multiplexer 1360 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock via internal multiplexer 1361 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock via internal multiplexer 1362 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock via internal multiplexer 1363 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 clock 1364 */ 1365 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 1366 ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL)))) 1367 1368 /** @brief Macro to configure the RNG clock. 1369 * 1370 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1371 * 1372 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 1373 * This parameter can be one of the following values: 1374 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock 1375 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 1376 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock 1377 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 1378 * @retval None 1379 */ 1380 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 1381 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__RNG_CLKSOURCE__)) 1382 1383 /** @brief Macro to get the RNG clock. 1384 * @retval The clock source can be one of the following values: 1385 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock 1386 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 1387 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock 1388 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock 1389 */ 1390 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))) 1391 1392 #if defined(USB) 1393 1394 /** @brief Macro to configure the USB clock (USBCLK). 1395 * 1396 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1397 * 1398 * @param __USB_CLKSOURCE__ specifies the USB clock source. 1399 * This parameter can be one of the following values: 1400 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock 1401 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1402 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1403 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1404 * @retval None 1405 */ 1406 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 1407 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__USB_CLKSOURCE__)) 1408 1409 /** @brief Macro to get the USB clock source. 1410 * @retval The clock source can be one of the following values: 1411 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock 1412 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1413 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1414 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1415 */ 1416 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))) 1417 1418 #endif /* USB */ 1419 1420 /** @brief Macro to configure the ADC interface clock. 1421 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 1422 * This parameter can be one of the following values: 1423 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1424 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1425 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1426 * @retval None 1427 */ 1428 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 1429 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) 1430 1431 /** @brief Macro to get the ADC clock source. 1432 * @retval The clock source can be one of the following values: 1433 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1434 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1435 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1436 */ 1437 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCSEL))) 1438 1439 /** @brief Macro to configure the DFSDM1 clock. 1440 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 1441 * This parameter can be one of the following values: 1442 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 1443 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 1444 * @retval None 1445 */ 1446 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 1447 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) 1448 1449 /** @brief Macro to get the DFSDM1 clock source. 1450 * @retval The clock source can be one of the following values: 1451 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 1452 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 1453 */ 1454 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL))) 1455 1456 /** @brief Macro to configure the DFSDM1 audio clock. 1457 * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. 1458 * This parameter can be one of the following values: 1459 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 1460 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 1461 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 1462 * @retval None 1463 */ 1464 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ 1465 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) 1466 1467 /** @brief Macro to get the DFSDM1 audio clock source. 1468 * @retval The clock source can be one of the following values: 1469 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 1470 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 1471 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 1472 */ 1473 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL))) 1474 1475 /** @brief Macro to configure the OctoSPI clock. 1476 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 1477 * This parameter can be one of the following values: 1478 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 1479 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 1480 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 1481 * @retval None 1482 */ 1483 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 1484 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) 1485 1486 /** @brief Macro to get the OctoSPI clock source. 1487 * @retval The clock source can be one of the following values: 1488 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 1489 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 1490 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 1491 */ 1492 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))) 1493 1494 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 1495 * @brief macros to manage the specified RCC Flags and interrupts. 1496 * @{ 1497 */ 1498 1499 /** @brief Enable PLLSAI1RDY interrupt. 1500 * @retval None 1501 */ 1502 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 1503 1504 /** @brief Disable PLLSAI1RDY interrupt. 1505 * @retval None 1506 */ 1507 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 1508 1509 /** @brief Clear the PLLSAI1RDY interrupt pending bit. 1510 * @retval None 1511 */ 1512 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) 1513 1514 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. 1515 * @retval TRUE or FALSE. 1516 */ 1517 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) 1518 1519 /** @brief Check whether the PLLSAI1RDY flag is set or not. 1520 * @retval TRUE or FALSE. 1521 */ 1522 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) 1523 1524 /** @brief Enable PLLSAI2RDY interrupt. 1525 * @retval None 1526 */ 1527 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 1528 1529 /** @brief Disable PLLSAI2RDY interrupt. 1530 * @retval None 1531 */ 1532 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 1533 1534 /** @brief Clear the PLLSAI2RDY interrupt pending bit. 1535 * @retval None 1536 */ 1537 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) 1538 1539 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. 1540 * @retval TRUE or FALSE. 1541 */ 1542 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) 1543 1544 /** @brief Check whether the PLLSAI2RDY flag is set or not. 1545 * @retval TRUE or FALSE. 1546 */ 1547 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) 1548 1549 1550 /** @defgroup RCCEx_Security_Extensions RCCEx Security Extensions 1551 * @{ 1552 */ 1553 /* Clock/System Security status */ 1554 #define __HAL_RCC_HSI_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_HSISECF) != 0U) 1555 1556 #define __HAL_RCC_HSE_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_HSESECF) != 0U) 1557 1558 #define __HAL_RCC_MSI_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_MSISECF) != 0U) 1559 1560 #define __HAL_RCC_LSI_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_LSISECF) != 0U) 1561 1562 #define __HAL_RCC_LSE_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_LSESECF) != 0U) 1563 1564 #define __HAL_RCC_HSI48_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_HSI48SECF) != 0U) 1565 1566 #define __HAL_RCC_SYSCLK_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_CKSYSSECF) != 0U) 1567 1568 #define __HAL_RCC_PRESCALER_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_PRESCSECF) != 0U) 1569 1570 #define __HAL_RCC_PLL_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_PLLSECF) != 0U) 1571 1572 #define __HAL_RCC_PLLSAI1_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_PLLSAI1SECF) != 0U) 1573 1574 #define __HAL_RCC_PLLSAI2_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_PLLSAI2SECF) != 0U) 1575 1576 #define __HAL_RCC_CLK48_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_SEL48SECF) != 0U) 1577 1578 #define __HAL_RCC_RMVF_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_RMVFSECF) != 0U) 1579 1580 /* Peripheral Security status */ 1581 #define __HAL_RCC_DMA1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_DMA1SECF) != 0U) 1582 1583 #define __HAL_RCC_DMA2_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_DMA2SECF) != 0U) 1584 1585 #define __HAL_RCC_DMAMUX1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_DMAMUX1SECF) != 0U) 1586 1587 #define __HAL_RCC_FLASH_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_FLASHSECF) != 0U) 1588 1589 #define __HAL_RCC_SRAM1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_SRAM1SECF) != 0U) 1590 1591 #define __HAL_RCC_CRC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_CRCSECF) != 0U) 1592 1593 #define __HAL_RCC_TSC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_TSCSECF) != 0U) 1594 1595 #define __HAL_RCC_GTZC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_GTZCSECF) != 0U) 1596 1597 #define __HAL_RCC_ICACHE_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_ICACHESECF) != 0U) 1598 1599 #define __HAL_RCC_GPIOA_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOASECF) != 0U) 1600 1601 #define __HAL_RCC_GPIOB_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOBSECF) != 0U) 1602 1603 #define __HAL_RCC_GPIOC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOCSECF) != 0U) 1604 1605 #define __HAL_RCC_GPIOD_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIODSECF) != 0U) 1606 1607 #define __HAL_RCC_GPIOE_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOESECF) != 0U) 1608 1609 #define __HAL_RCC_GPIOF_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOFSECF) != 0U) 1610 1611 #define __HAL_RCC_GPIOG_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOGSECF) != 0U) 1612 1613 #define __HAL_RCC_GPIOH_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOHSECF) != 0U) 1614 1615 #define __HAL_RCC_SRAM2_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_SRAM2SECF) != 0U) 1616 1617 #define __HAL_RCC_ADC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_ADCSECF) != 0U) 1618 1619 #define __HAL_RCC_AES_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_AESSECF) != 0U) 1620 1621 #define __HAL_RCC_HASH_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_HASHSECF) != 0U) 1622 1623 #define __HAL_RCC_RNG_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_RNGSECF) != 0U) 1624 1625 #define __HAL_RCC_PKA_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_PKASECF) != 0U) 1626 1627 #define __HAL_RCC_OTFDEC1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_OTFDEC1SECF) != 0U) 1628 1629 #define __HAL_RCC_SDMMC1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_SDMMC1SECF) != 0U) 1630 1631 #define __HAL_RCC_FMC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB3SECSR, RCC_AHB3SECSR_FMCSECF) != 0U) 1632 1633 #define __HAL_RCC_OSPI1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB3SECSR, RCC_AHB3SECSR_OSPI1SECF) != 0U) 1634 1635 #define __HAL_RCC_TIM2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM2SECF) != 0U) 1636 1637 #define __HAL_RCC_TIM3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM3SECF) != 0U) 1638 1639 #define __HAL_RCC_TIM4_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM4SECF) != 0U) 1640 1641 #define __HAL_RCC_TIM5_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM5SECF) != 0U) 1642 1643 #define __HAL_RCC_TIM6_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM6SECF) != 0U) 1644 1645 #define __HAL_RCC_TIM7_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM7SECF) != 0U) 1646 1647 #define __HAL_RCC_RTCAPB_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_RTCAPBSECF) != 0U) 1648 1649 #define __HAL_RCC_WWDG_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_WWDGSECF) != 0U) 1650 1651 #define __HAL_RCC_SPI2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_SPI2SECF) != 0U) 1652 1653 #define __HAL_RCC_SPI3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_SPI3SECF) != 0U) 1654 1655 #define __HAL_RCC_USART2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_USART2SECF) != 0U) 1656 1657 #define __HAL_RCC_USART3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_USART3SECF) != 0U) 1658 1659 #define __HAL_RCC_UART4_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_UART4SECF) != 0U) 1660 1661 #define __HAL_RCC_UART5_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_UART5SECF) != 0U) 1662 1663 #define __HAL_RCC_I2C1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_I2C1SECF) != 0U) 1664 1665 #define __HAL_RCC_I2C2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_I2C2SECF) != 0U) 1666 1667 #define __HAL_RCC_I2C3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_I2C3SECF) != 0U) 1668 1669 #define __HAL_RCC_CRS_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_CRSSECF) != 0U) 1670 1671 #define __HAL_RCC_PWR_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_PWRSECF) != 0U) 1672 1673 #define __HAL_RCC_DAC1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_DAC1SECF) != 0U) 1674 1675 #define __HAL_RCC_OPAMP_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_OPAMPSECF) != 0U) 1676 1677 #define __HAL_RCC_LPTIM1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_LPTIM1SECF) != 0U) 1678 1679 #define __HAL_RCC_LPUART1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_LPUART1SECF) != 0U) 1680 1681 #define __HAL_RCC_I2C4_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_I2C4SECF) != 0U) 1682 1683 #define __HAL_RCC_LPTIM2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_LPTIM2SECF) != 0U) 1684 1685 #define __HAL_RCC_LPTIM3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_LPTIM3SECF) != 0U) 1686 1687 #define __HAL_RCC_FDCAN1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_FDCAN1SECF) != 0U) 1688 1689 #if defined(USB) 1690 #define __HAL_RCC_USB_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_USBFSSECF) != 0U) 1691 #endif /* USB */ 1692 1693 #define __HAL_RCC_UCPD1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_UCPD1SECF) != 0U) 1694 1695 #define __HAL_RCC_SYSCFG_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_SYSCFGSECF) != 0U) 1696 1697 #define __HAL_RCC_TIM1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM1SECF) != 0U) 1698 1699 #define __HAL_RCC_SPI1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_SPI1SECF) != 0U) 1700 1701 #define __HAL_RCC_TIM8_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM8SECF) != 0U) 1702 1703 #define __HAL_RCC_USART1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_USART1SECF) != 0U) 1704 1705 #define __HAL_RCC_TIM15_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM15SECF) != 0U) 1706 1707 #define __HAL_RCC_TIM16_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM16SECF) != 0U) 1708 1709 #define __HAL_RCC_TIM17_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM17SECF) != 0U) 1710 1711 #define __HAL_RCC_SAI1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_SAI1SECF) != 0U) 1712 1713 #define __HAL_RCC_SAI2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_SAI2SECF) != 0U) 1714 1715 #define __HAL_RCC_DFSDM1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_DFSDM1SECF) != 0U) 1716 /** 1717 * @} 1718 */ 1719 1720 1721 #if defined(CRS) 1722 1723 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1724 * @{ 1725 */ 1726 1727 /** 1728 * @brief Enable the specified CRS interrupts. 1729 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1730 * This parameter can be any combination of the following values: 1731 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1732 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1733 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1734 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1735 * @retval None 1736 */ 1737 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1738 1739 /** 1740 * @brief Disable the specified CRS interrupts. 1741 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1742 * This parameter can be any combination of the following values: 1743 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1744 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1745 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1746 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1747 * @retval None 1748 */ 1749 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1750 1751 /** @brief Check whether the CRS interrupt has occurred or not. 1752 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1753 * This parameter can be one of the following values: 1754 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1755 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1756 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1757 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1758 * @retval The new state of __INTERRUPT__ (0 or 1). 1759 */ 1760 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? 1U : 0U) 1761 1762 /** @brief Clear the CRS interrupt pending bits 1763 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1764 * This parameter can be any combination of the following values: 1765 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1766 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1767 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1768 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1769 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1770 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1771 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1772 */ 1773 /* CRS IT Error Mask */ 1774 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF\ 1775 | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 1776 1777 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1778 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1779 { \ 1780 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1781 } \ 1782 else \ 1783 { \ 1784 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1785 } \ 1786 } while(0) 1787 1788 /** 1789 * @brief Check whether the specified CRS flag is set or not. 1790 * @param __FLAG__ specifies the flag to check. 1791 * This parameter can be one of the following values: 1792 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1793 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1794 * @arg @ref RCC_CRS_FLAG_ERR Error 1795 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1796 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1797 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1798 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1799 * @retval The new state of _FLAG_ (TRUE or FALSE). 1800 */ 1801 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1802 1803 /** 1804 * @brief Clear the CRS specified FLAG. 1805 * @param __FLAG__ specifies the flag to clear. 1806 * This parameter can be one of the following values: 1807 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1808 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1809 * @arg @ref RCC_CRS_FLAG_ERR Error 1810 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1811 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1812 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1813 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1814 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1815 * @retval None 1816 */ 1817 1818 /* CRS Flag Error Mask */ 1819 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF\ 1820 | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 1821 1822 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1823 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1824 { \ 1825 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1826 } \ 1827 else \ 1828 { \ 1829 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1830 } \ 1831 } while(0) 1832 1833 /** 1834 * @brief Enable the oscillator clock for frequency error counter. 1835 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1836 * @retval None 1837 */ 1838 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1839 1840 /** 1841 * @brief Disable the oscillator clock for frequency error counter. 1842 * @retval None 1843 */ 1844 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1845 1846 /** 1847 * @brief Enable the automatic hardware adjustment of TRIM bits. 1848 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1849 * @retval None 1850 */ 1851 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1852 1853 /** 1854 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1855 * @retval None 1856 */ 1857 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1858 1859 /** 1860 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1861 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1862 * of the synchronization source after prescaling. It is then decreased by one in order to 1863 * reach the expected synchronization on the zero value. The formula is the following: 1864 * RELOAD = (fTARGET / fSYNC) -1 1865 * @param __FTARGET__ Target frequency (value in Hz). 1866 * @param __FSYNC__ Synchronization signal frequency (value in Hz). 1867 * @retval None 1868 */ 1869 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1870 1871 /** 1872 * @} 1873 */ 1874 1875 #endif /* CRS */ 1876 1877 /** 1878 * @} 1879 */ 1880 1881 /* Exported functions --------------------------------------------------------*/ 1882 /** @addtogroup RCCEx_Exported_Functions 1883 * @{ 1884 */ 1885 1886 /** @addtogroup RCCEx_Exported_Functions_Group1 1887 * @{ 1888 */ 1889 1890 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1891 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1892 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1893 1894 /** 1895 * @} 1896 */ 1897 1898 /** @addtogroup RCCEx_Exported_Functions_Group2 1899 * @{ 1900 */ 1901 1902 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); 1903 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); 1904 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); 1905 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); 1906 1907 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 1908 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 1909 void HAL_RCCEx_EnableLSECSS(void); 1910 void HAL_RCCEx_DisableLSECSS(void); 1911 void HAL_RCCEx_LSECSS_IRQHandler(void); 1912 void HAL_RCCEx_LSECSS_Callback(void); 1913 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1914 void HAL_RCCEx_DisableLSCO(void); 1915 void HAL_RCCEx_EnableMSIPLLMode(void); 1916 void HAL_RCCEx_DisableMSIPLLMode(void); 1917 1918 /** 1919 * @} 1920 */ 1921 1922 #if defined(CRS) 1923 1924 /** @addtogroup RCCEx_Exported_Functions_Group3 1925 * @{ 1926 */ 1927 1928 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1929 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1930 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1931 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1932 void HAL_RCCEx_CRS_IRQHandler(void); 1933 void HAL_RCCEx_CRS_SyncOkCallback(void); 1934 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1935 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1936 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1937 1938 /** 1939 * @} 1940 */ 1941 1942 #endif /* CRS */ 1943 1944 /** 1945 * @} 1946 */ 1947 1948 /* Private macros ------------------------------------------------------------*/ 1949 /** @addtogroup RCCEx_Private_Macros 1950 * @{ 1951 */ 1952 1953 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 1954 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 1955 1956 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1957 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1958 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1959 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1960 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1961 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1962 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1963 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1964 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1965 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1966 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1967 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1968 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 1969 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) || \ 1970 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1971 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 1972 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1973 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 1974 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 1975 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ 1976 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 1977 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1978 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 1979 (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ 1980 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)) 1981 1982 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 1983 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 1984 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 1985 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 1986 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 1987 1988 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 1989 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 1990 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 1991 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 1992 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 1993 1994 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 1995 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 1996 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 1997 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 1998 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 1999 2000 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 2001 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 2002 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 2003 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 2004 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 2005 2006 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 2007 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 2008 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 2009 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 2010 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 2011 2012 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 2013 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 2014 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 2015 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 2016 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 2017 2018 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 2019 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 2020 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 2021 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 2022 2023 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 2024 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 2025 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 2026 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 2027 2028 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 2029 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 2030 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 2031 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 2032 2033 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 2034 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 2035 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 2036 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 2037 2038 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2039 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 2040 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 2041 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2042 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 2043 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 2044 2045 #define IS_RCC_SAI2CLK(__SOURCE__) \ 2046 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 2047 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 2048 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 2049 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 2050 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) 2051 2052 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 2053 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 2054 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 2055 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 2056 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 2057 2058 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 2059 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 2060 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 2061 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 2062 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 2063 2064 #define IS_RCC_LPTIM3CLK(__SOURCE__) \ 2065 (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \ 2066 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ 2067 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \ 2068 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE)) 2069 2070 #define IS_RCC_FDCANCLK(__SOURCE__) \ 2071 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 2072 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 2073 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLLSAI1)) 2074 2075 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2076 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 2077 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 2078 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 2079 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI) || \ 2080 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP)) 2081 2082 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 2083 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 2084 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 2085 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 2086 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 2087 2088 #if defined(USB) 2089 2090 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 2091 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 2092 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 2093 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 2094 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 2095 2096 #endif /* USB */ 2097 2098 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2099 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 2100 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 2101 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 2102 2103 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ 2104 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 2105 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 2106 2107 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ 2108 (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ 2109 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ 2110 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) 2111 2112 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 2113 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ 2114 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ 2115 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) 2116 2117 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 2118 2119 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 2120 2121 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 2122 2123 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 2124 2125 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 2126 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 2127 2128 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 2129 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 2130 2131 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 2132 2133 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 2134 2135 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 2136 2137 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 2138 2139 #if defined(CRS) 2140 2141 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 2142 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 2143 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 2144 2145 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 2146 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 2147 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 2148 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 2149 2150 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 2151 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 2152 2153 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 2154 2155 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 2156 2157 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 2158 2159 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 2160 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 2161 2162 #endif /* CRS */ 2163 2164 /** 2165 * @} 2166 */ 2167 2168 /** 2169 * @} 2170 */ 2171 2172 /** 2173 * @} 2174 */ 2175 2176 /** 2177 * @} 2178 */ 2179 2180 #ifdef __cplusplus 2181 } 2182 #endif 2183 2184 #endif /* STM32L5xx_HAL_RCC_EX_H */ 2185 2186 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2187
