1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBAxx_HAL_PWR_EX_H 21 #define STM32WBAxx_HAL_PWR_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbaxx_hal_def.h" 29 30 /** @addtogroup STM32WBAxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWREx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 41 * @{ 42 */ 43 44 45 /* Exported constants --------------------------------------------------------*/ 46 47 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 48 * @{ 49 */ 50 51 /** @defgroup PWREx_RAM_Contents_Stop_Retention PWR Extended SRAM Contents Stop Retention 52 * @{ 53 */ 54 /* SRAM1 pages retention defines */ 55 #define PWR_SRAM1_FULL_STOP_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 full retention in Stop modes (Stop 0, 1) */ 56 /* SRAM2 pages retention defines */ 57 #define PWR_SRAM2_FULL_STOP_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 full retention in Stop modes (Stop 0, 1) */ 58 /* Cache RAMs retention defines */ 59 #define PWR_ICACHE_FULL_STOP_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop modes (Stop 0, 1) */ 60 /** 61 * @} 62 */ 63 64 65 /** @defgroup PWREx_RAM_Contents_Standby_Retention PWR Extended SRAM Contents Standby Retention 66 * @{ 67 */ 68 #if defined(PWR_CR1_R1RSB1) 69 #define PWR_SRAM1_FULL_STANDBY_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 full retention in Standby mode */ 70 #endif /* defined(PWR_CR1_R1RSB1) */ 71 #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 full retention in Standby mode */ 72 #define PWR_RADIOSRAM_FULL_STANDBY_RETENTION PWR_CR1_RADIORSB /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) 73 and Sleep clock retention in Standby mode */ 74 /** 75 * @} 76 */ 77 78 #if defined(PWR_CR3_REGSEL) 79 /** @defgroup PWREx_Supply_Configuration PWR Extended Supply Configuration 80 * @{ 81 */ 82 #define PWR_LDO_SUPPLY (0U) /* LDO supply */ 83 #define PWR_SMPS_SUPPLY PWR_CR3_REGSEL /* SMPS supply */ 84 /** 85 * @} 86 */ 87 #endif /* defined(PWR_CR3_REGSEL) */ 88 89 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale 90 * @{ 91 */ 92 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */ 93 #define PWR_REGULATOR_VOLTAGE_SCALE2 (0U) /*!< Voltage scaling range 2 */ 94 /** 95 * @} 96 */ 97 98 /** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port 99 * @{ 100 */ 101 #define PWR_GPIO_A (0x00U) /*!< GPIO port A */ 102 #define PWR_GPIO_B (0x01U) /*!< GPIO port B */ 103 #define PWR_GPIO_C (0x02U) /*!< GPIO port C */ 104 #define PWR_GPIO_H (0x07U) /*!< GPIO port H */ 105 /** 106 * @} 107 */ 108 109 /** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask 110 * @{ 111 */ 112 #define PWR_GPIO_BIT_0 (0x00001U) /*!< GPIO port I/O pin 0 */ 113 #define PWR_GPIO_BIT_1 (0x00002U) /*!< GPIO port I/O pin 1 */ 114 #define PWR_GPIO_BIT_2 (0x00004U) /*!< GPIO port I/O pin 2 */ 115 #define PWR_GPIO_BIT_3 (0x00008U) /*!< GPIO port I/O pin 3 */ 116 #define PWR_GPIO_BIT_4 (0x00010U) /*!< GPIO port I/O pin 4 */ 117 #define PWR_GPIO_BIT_5 (0x00020U) /*!< GPIO port I/O pin 5 */ 118 #define PWR_GPIO_BIT_6 (0x00040U) /*!< GPIO port I/O pin 6 */ 119 #define PWR_GPIO_BIT_7 (0x00080U) /*!< GPIO port I/O pin 7 */ 120 #define PWR_GPIO_BIT_8 (0x00100U) /*!< GPIO port I/O pin 8 */ 121 #define PWR_GPIO_BIT_9 (0x00200U) /*!< GPIO port I/O pin 9 */ 122 #define PWR_GPIO_BIT_10 (0x00400U) /*!< GPIO port I/O pin 10 */ 123 #define PWR_GPIO_BIT_11 (0x00800U) /*!< GPIO port I/O pin 11 */ 124 #define PWR_GPIO_BIT_12 (0x01000U) /*!< GPIO port I/O pin 12 */ 125 #define PWR_GPIO_BIT_13 (0x02000U) /*!< GPIO port I/O pin 13 */ 126 #define PWR_GPIO_BIT_14 (0x04000U) /*!< GPIO port I/O pin 14 */ 127 #define PWR_GPIO_BIT_15 (0x08000U) /*!< GPIO port I/O pin 15 */ 128 #define PWR_GPIO_PIN_MASK (0x0FFFFU) 129 /** 130 * @} 131 */ 132 133 /** @defgroup PWREx_RADIO_Mode PWR Extended 2.4 GHz RADIO operating mode 134 * @{ 135 */ 136 #define PWR_RADIO_DEEPSLEEP_MODE (0x0U) /*!< 2.4 GHz RADIO deep sleep mode */ 137 #define PWR_RADIO_SLEEP_MODE PWR_RADIOSCR_MODE_0 /*!< 2.4 GHz RADIO sleep mode */ 138 #define PWR_RADIO_ACTIVE_MODE PWR_RADIOSCR_MODE_1 /*!< 2.4 GHz RADIO active mode */ 139 /** 140 * @} 141 */ 142 143 /** @defgroup PWREx_RADIO_PHY_Mode PWR Extended 2.4 GHz RADIO PHY operating mode 144 * @{ 145 */ 146 #define PWR_RADIO_PHY_SLEEP_MODE (0x0U) /*!< 2.4 GHz RADIO PHY sleep mode */ 147 #define PWR_RADIO_PHY_STANDBY_MODE PWR_RADIOSCR_PHYMODE /*!< 2.4 GHz RADIO PHY standby mode */ 148 /** 149 * @} 150 */ 151 152 /** @defgroup PWREx_RADIO_ENCODE_Mode PWR Extended 2.4 GHz RADIO encryption operating mode 153 * @{ 154 */ 155 #define PWR_RADIO_ENCMODE_DISABLED (0x0U) /*!< 2.4 GHz RADIO encryption function disabled */ 156 #define PWR_RADIO_ENCMODE_ENABLED PWR_RADIOSCR_ENCMODE /*!< 2.4 GHz RADIO encryption function enabled */ 157 /** 158 * @} 159 */ 160 161 #if defined(PWR_RADIOSCR_REGPASEL) 162 /** @defgroup PWREx_Regulator_Input_Supply_Selection PWR Extended RADIO regulator input supply selection 163 * @{ 164 */ 165 #define PWR_RADIO_REG_VDDRFPA (0x0U) /*!< VDDRFPA pin selected as regulator REG_VDDHPA input supply */ 166 #define PWR_RADIO_REG_VDDHPA_VD11 PWR_RADIOSCR_REGPASEL 167 /*!< Regulator REG_VDDHPA input supply selection between VDDRFPA 168 and VDD11 dependent on requested regulated output voltage */ 169 /** 170 * @} 171 */ 172 #endif /* defined(PWR_RADIOSCR_REGPASEL) */ 173 174 175 /** 176 * @} 177 */ 178 179 /* Exported macros -----------------------------------------------------------*/ 180 181 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 182 * @{ 183 */ 184 185 /** 186 * @brief Configure the main internal regulator output voltage. 187 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but 188 * doesn't check whether or not VOSRDY flag is set. User may resort 189 * to __HAL_PWR_GET_FLAG() macro to check VOSRDY bit state. 190 * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a 191 * tradeoff between performance and power consumption. 192 * This parameter can be one of the following values : 193 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. 194 * Provides a typical output voltage at 1.2 V. 195 * It allows a system clock frequency up to 100 MHz, 196 * and is required for any 2.4 GHz RADIO transmit and 197 * receive operation. 198 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. 199 * The system clock frequency can be up to 16 MHz. 200 * The 2.4 GHz RADIO shall not transmit nor receive. 201 * @retval None. 202 */ 203 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 204 do \ 205 { \ 206 __IO uint32_t tmpreg; \ 207 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, (__REGULATOR__)); \ 208 /* Delay after an RCC peripheral clock enabling */ \ 209 tmpreg = READ_BIT(PWR->VOSR, PWR_VOSR_VOS); \ 210 UNUSED(tmpreg); \ 211 } while(0) 212 /** 213 * @} 214 */ 215 216 /* Private constants ---------------------------------------------------------*/ 217 218 /** @addtogroup PWREx_Private_Constants PWR Extended Private Constants 219 * @{ 220 */ 221 222 223 /* All available RAM retention in Stop mode define */ 224 #define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ 225 PWR_ICACHE_FULL_STOP_RETENTION ) 226 /* All available RAM retention in Standby mode define */ 227 #if defined(PWR_CR1_R1RSB1) 228 #define PWR_ALL_RAM_STANDBY_RETENTION_MASK (PWR_SRAM1_FULL_STANDBY_RETENTION | PWR_SRAM2_FULL_STANDBY_RETENTION) 229 #else 230 #define PWR_ALL_RAM_STANDBY_RETENTION_MASK PWR_SRAM2_FULL_STANDBY_RETENTION 231 #endif /* defined(PWR_CR1_R1RSB1) */ 232 /** 233 * @} 234 */ 235 236 /* Private macros --------------------------------------------------------*/ 237 238 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 239 * @{ 240 */ 241 242 #if defined(PWR_CR3_REGSEL) 243 /* Supply selection check macro */ 244 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 245 ((PWR_SOURCE) == PWR_SMPS_SUPPLY)) 246 #endif /* defined(PWR_CR3_REGSEL) */ 247 248 /* Voltage scaling range check macro */ 249 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ 250 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 251 /* GPIO port check macro */ 252 #define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ 253 ((GPIO_PORT) == PWR_GPIO_B) ||\ 254 ((GPIO_PORT) == PWR_GPIO_C) ||\ 255 ((GPIO_PORT) == PWR_GPIO_H)) 256 257 /* GPIO pin mask check macro */ 258 #define IS_PWR_GPIO_PIN_MASK(BIT_MASK) ((((BIT_MASK) & PWR_GPIO_PIN_MASK) != 0U) &&\ 259 ((BIT_MASK) <= PWR_GPIO_PIN_MASK)) 260 261 #if defined(PWR_CR1_R1RSB1) 262 /* SRAM1 retention in Standby mode check macro */ 263 #define IS_PWR_SRAM1_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_SRAM1_FULL_STANDBY_RETENTION) 264 #endif /* defined(PWR_CR1_R1RSB1) */ 265 266 /* SRAM2 retention in Standby mode check macro */ 267 #define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION) 268 269 /* RADIO SRAM retention in Standby mode check macro */ 270 #define IS_PWR_RADIOSRAM_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_RADIOSRAM_FULL_STANDBY_RETENTION) 271 272 /* RAMs retention in Stop mode check macro */ 273 #define IS_PWR_RAM_STOP_RETENTION(RAMCONTENT) (((RAMCONTENT) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ 274 ((RAMCONTENT) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ 275 ((RAMCONTENT) == PWR_ICACHE_FULL_STOP_RETENTION)) 276 /** 277 * @} 278 */ 279 280 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 281 * @{ 282 */ 283 284 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions 285 * @{ 286 */ 287 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 288 uint32_t HAL_PWREx_GetVoltageRange(void); 289 290 #if defined(PWR_CR3_REGSEL) 291 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); 292 uint32_t HAL_PWREx_GetSupplyConfig(void); 293 #endif /* defined(PWR_CR3_REGSEL) */ 294 #if defined(PWR_CR2_FPWM) 295 void HAL_PWREx_EnableSMPSPWM(void); 296 void HAL_PWREx_DisableSMPSPWM(void); 297 #endif /* defined(PWR_CR2_FPWM) */ 298 void HAL_PWREx_EnableFastSoftStart(void); 299 void HAL_PWREx_DisableFastSoftStart(void); 300 /** 301 * @} 302 */ 303 304 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions 305 * @{ 306 */ 307 void HAL_PWREx_EnableUltraLowPowerMode(void); 308 void HAL_PWREx_DisableUltraLowPowerMode(void); 309 /** 310 * @} 311 */ 312 313 /** @addtogroup PWREx_Exported_Functions_Group4 Memories Retention Functions 314 * @{ 315 */ 316 void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); 317 void HAL_PWREx_DisableSRAM2ContentStandbyRetention(void); 318 void HAL_PWREx_EnableRadioSRAMClockStandbyRetention(uint32_t RadioSRAM); 319 void HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void); 320 #if defined(PWR_CR1_R1RSB1) 321 void HAL_PWREx_EnableSRAM1ContentStandbyRetention(uint32_t SRAM1Pages); 322 void HAL_PWREx_DisableSRAM1ContentStandbyRetention(void); 323 #endif /* defined(PWR_CR1_R1RSB1) */ 324 void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection); 325 void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection); 326 void HAL_PWREx_EnableFlashFastWakeUp(void); 327 void HAL_PWREx_DisableFlashFastWakeUp(void); 328 /** 329 * @} 330 */ 331 332 /** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions 333 * @{ 334 */ 335 HAL_StatusTypeDef HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin); 336 HAL_StatusTypeDef HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin); 337 uint32_t HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port); 338 HAL_StatusTypeDef HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port, uint32_t GPIO_Pin); 339 /** 340 * @} 341 */ 342 343 /** @addtogroup PWREx_Exported_Functions_Group6 I/O RADIO Configuration and Status Reading Functions 344 * @{ 345 */ 346 uint32_t HAL_PWREx_GetRADIOOperatingMode(void); 347 uint32_t HAL_PWREx_GetRADIOPHYOperatingMode(void); 348 uint32_t HAL_PWREx_GetRADIOEncryptionOperatingMode(void); 349 uint32_t HAL_PWREx_GetRFVDDHPA(void); 350 351 #if defined(PWR_RADIOSCR_REGPASEL) 352 HAL_StatusTypeDef HAL_PWREx_SetREGVDDHPAInputSupply(uint32_t SupplySelection); 353 uint32_t HAL_PWREx_GetREGVDDHPAInputSupply(void); 354 #endif /* defined(PWR_RADIOSCR_REGPASEL) */ 355 #if defined(PWR_RADIOSCR_REGPABYPEN) 356 void HAL_PWREx_EnableREGVDDHPABypass(void); 357 void HAL_PWREx_DisableREGVDDHPABypass(void); 358 #endif /* defined(PWR_RADIOSCR_REGPABYPEN) */ 359 /** 360 * @} 361 */ 362 363 /** 364 * @} 365 */ 366 367 /** 368 * @} 369 */ 370 371 /** 372 * @} 373 */ 374 375 /** 376 * @} 377 */ 378 379 #ifdef __cplusplus 380 } 381 #endif /* __cplusplus */ 382 383 384 #endif /* STM32WBAxx_HAL_PWR_EX_H */ 385 386
