1 /**
2   ******************************************************************************
3   * @file    stm32l4xx_hal_ospi.h
4   * @author  MCD Application Team
5   * @brief   Header file of OSPI HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
10   *
11   * Redistribution and use in source and binary forms, with or without modification,
12   * are permitted provided that the following conditions are met:
13   *   1. Redistributions of source code must retain the above copyright notice,
14   *      this list of conditions and the following disclaimer.
15   *   2. Redistributions in binary form must reproduce the above copyright notice,
16   *      this list of conditions and the following disclaimer in the documentation
17   *      and/or other materials provided with the distribution.
18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
19   *      may be used to endorse or promote products derived from this software
20   *      without specific prior written permission.
21   *
22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32   *
33   ******************************************************************************
34   */
35 
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32L4xx_HAL_OSPI_H
38 #define STM32L4xx_HAL_OSPI_H
39 
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32l4xx_hal_def.h"
46 
47 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
48 
49 /** @addtogroup STM32L4xx_HAL_Driver
50   * @{
51   */
52 
53 /** @addtogroup OSPI
54   * @{
55   */
56 
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup OSPI_Exported_Types OSPI Exported Types
59   * @{
60   */
61 
62 /**
63   * @brief OSPI Init structure definition
64   */
65 typedef struct
66 {
67   uint32_t FifoThreshold;             /* This is the threshold used byt the IP to generate the interrupt
68                                          indicating that data are available in reception or free place
69                                          is available in transmission.
70                                          This parameter can be a value between 1 and 32 */
71   uint32_t DualQuad;                  /* It enables or not the dual-quad mode which allow to access up to
72                                          quad mode on two different devices to increase the throughput.
73                                          This parameter can be a value of @ref OSPI_DualQuad */
74   uint32_t MemoryType;                /* It indicates the external device type connected to the OSPI.
75                                          This parameter can be a value of @ref OSPI_MemoryType */
76   uint32_t DeviceSize;                /* It defines the size of the external device connected to the OSPI,
77                                          it corresponds to the number of address bits required to access
78                                          the external device.
79                                          This parameter can be a value between 1 and 32 */
80   uint32_t ChipSelectHighTime;        /* It defines the minimun number of clocks which the chip select
81                                          must remain high between commands.
82                                          This parameter can be a value between 1 and 8 */
83   uint32_t FreeRunningClock;          /* It enables or not the free running clock.
84                                          This parameter can be a value of @ref OSPI_FreeRunningClock */
85   uint32_t ClockMode;                 /* It indicates the level of clock when the chip select is released.
86                                          This parameter can be a value of @ref OSPI_ClockMode */
87   uint32_t WrapSize;                  /* It indicates the wrap-size corresponding the external device configuration.
88                                          This parameter can be a value of @ref OSPI_WrapSize */
89   uint32_t ClockPrescaler;            /* It specifies the prescaler factor used for generating
90                                          the external clock based on the AHB clock.
91                                          This parameter can be a value between 1 and 256 */
92   uint32_t SampleShifting;            /* It allows to delay to 1/2 cycle the data sampling in order
93                                          to take in account external signal delays.
94                                          This parameter can be a value of @ref OSPI_SampleShifting */
95   uint32_t DelayHoldQuarterCycle;     /* It allows to hold to 1/4 cycle the data.
96                                          This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
97   uint32_t ChipSelectBoundary;        /* It enables the transaction boundary feature and
98                                          defines the boundary of bytes to release the chip select.
99                                          This parameter can be a value between 0 and 31 */
100 }OSPI_InitTypeDef;
101 
102 /**
103   * @brief  HAL OSPI Handle Structure definition
104   */
105 typedef struct __OSPI_HandleTypeDef
106 {
107   OCTOSPI_TypeDef            *Instance;     /* OSPI registers base address                      */
108   OSPI_InitTypeDef           Init;          /* OSPI initialization parameters                   */
109   uint8_t                    *pBuffPtr;     /* Address of the OSPI buffer for transfer          */
110   __IO uint32_t              XferSize;      /* Number of data to transfer                       */
111   __IO uint32_t              XferCount;     /* Counter of data transferred                      */
112   DMA_HandleTypeDef          *hdma;         /* Handle of the DMA channel used for the transfer  */
113   __IO uint32_t              State;         /* Internal state of the OSPI HAL driver            */
114   __IO uint32_t              ErrorCode;     /* Error code in case of HAL driver internal error  */
115   uint32_t                   Timeout;       /* Timeout used for the OSPI external device access */
116 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
117   void (* ErrorCallback)        (struct __OSPI_HandleTypeDef *hospi);
118   void (* AbortCpltCallback)    (struct __OSPI_HandleTypeDef *hospi);
119   void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
120   void (* CmdCpltCallback)      (struct __OSPI_HandleTypeDef *hospi);
121   void (* RxCpltCallback)       (struct __OSPI_HandleTypeDef *hospi);
122   void (* TxCpltCallback)       (struct __OSPI_HandleTypeDef *hospi);
123   void (* RxHalfCpltCallback)   (struct __OSPI_HandleTypeDef *hospi);
124   void (* TxHalfCpltCallback)   (struct __OSPI_HandleTypeDef *hospi);
125   void (* StatusMatchCallback)  (struct __OSPI_HandleTypeDef *hospi);
126   void (* TimeOutCallback)      (struct __OSPI_HandleTypeDef *hospi);
127 
128   void (* MspInitCallback)      (struct __OSPI_HandleTypeDef *hospi);
129   void (* MspDeInitCallback)    (struct __OSPI_HandleTypeDef *hospi);
130 #endif
131 }OSPI_HandleTypeDef;
132 
133 /**
134   * @brief  HAL OSPI Regular Command Structure definition
135   */
136 typedef struct
137 {
138   uint32_t OperationType;             /* It indicates if the configuration applies to the common regsiters or
139                                          to the registers for the write operation (these registers are only
140                                          used for memory-mapped mode).
141                                          This parameter can be a value of @ref OSPI_OperationType */
142   uint32_t FlashId;                   /* It indicates which external device is selected for this command (it
143                                          applies only if Dualquad is disabled in the initialization structure).
144                                          This parameter can be a value of @ref OSPI_FlashId */
145   uint32_t Instruction;               /* It contains the instruction to be sent to the device.
146                                          This parameter can be a value between 0 and 0xFFFFFFFF */
147   uint32_t InstructionMode;           /* It indicates the mode of the instruction.
148                                          This parameter can be a value of @ref OSPI_InstructionMode */
149   uint32_t InstructionSize;           /* It indicates the size of the instruction.
150                                          This parameter can be a value of @ref OSPI_InstructionSize */
151   uint32_t InstructionDtrMode;        /* It enables or not the DTR mode for the instruction phase.
152                                          This parameter can be a value of @ref OSPI_InstructionDtrMode */
153   uint32_t Address;                   /* It contains the address to be sent to the device.
154                                          This parameter can be a value between 0 and 0xFFFFFFFF */
155   uint32_t AddressMode;               /* It indicates the mode of the address.
156                                          This parameter can be a value of @ref OSPI_AddressMode */
157   uint32_t AddressSize;               /* It indicates the size of the address.
158                                          This parameter can be a value of @ref OSPI_AddressSize */
159   uint32_t AddressDtrMode;            /* It enables or not the DTR mode for the address phase.
160                                          This parameter can be a value of @ref OSPI_AddressDtrMode */
161   uint32_t AlternateBytes;            /* It contains the alternate bytes to be sent to the device.
162                                          This parameter can be a value between 0 and 0xFFFFFFFF */
163   uint32_t AlternateBytesMode;        /* It indicates the mode of the alternate bytes.
164                                          This parameter can be a value of @ref OSPI_AlternateBytesMode */
165   uint32_t AlternateBytesSize;        /* It indicates the size of the alternate bytes.
166                                          This parameter can be a value of @ref OSPI_AlternateBytesSize */
167   uint32_t AlternateBytesDtrMode;     /* It enables or not the DTR mode for the alternate bytes phase.
168                                          This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
169   uint32_t DataMode;                  /* It indicates the mode of the data.
170                                          This parameter can be a value of @ref OSPI_DataMode */
171   uint32_t NbData;                    /* It indicates the number of data transferred with this command.
172                                          This field is only used for indirect mode.
173                                          This parameter can be a value between 1 and 0xFFFFFFFF */
174   uint32_t DataDtrMode;               /* It enables or not the DTR mode for the data phase.
175                                          This parameter can be a value of @ref OSPI_DataDtrMode */
176   uint32_t DummyCycles;               /* It indicates the number of dummy cycles inserted before data phase.
177                                          This parameter can be a value between 0 and 31 */
178   uint32_t DQSMode;                   /* It enables or not the data strobe management.
179                                          This parameter can be a value of @ref OSPI_DQSMode */
180   uint32_t SIOOMode;                  /* It enables or not the SIOO mode.
181                                          This parameter can be a value of @ref OSPI_SIOOMode */
182 }OSPI_RegularCmdTypeDef;
183 
184 /**
185   * @brief  HAL OSPI Hyperbus Configuration Structure definition
186   */
187 typedef struct
188 {
189   uint32_t RWRecoveryTime;       /* It indicates the number of cycles for the device read write recovery time.
190                                     This parameter can be a value between 0 and 255 */
191   uint32_t AccessTime;           /* It indicates the number of cycles for the device acces time.
192                                     This parameter can be a value between 0 and 255 */
193   uint32_t WriteZeroLatency;     /* It enables or not the latency for the write access.
194                                     This parameter can be a value of @ref OSPI_WriteZeroLatency */
195   uint32_t LatencyMode;          /* It configures the latency mode.
196                                     This parameter can be a value of @ref OSPI_LatencyMode */
197 }OSPI_HyperbusCfgTypeDef;
198 
199 /**
200   * @brief  HAL OSPI Hyperbus Command Structure definition
201   */
202 typedef struct
203 {
204   uint32_t AddressSpace;     /* It indicates the address space accessed by the command.
205                                 This parameter can be a value of @ref OSPI_AddressSpace */
206   uint32_t Address;          /* It contains the address to be sent tot he device.
207                                 This parameter can be a value between 0 and 0xFFFFFFFF */
208   uint32_t AddressSize;      /* It indicates the size of the address.
209                                 This parameter can be a value of @ref OSPI_AddressSize */
210   uint32_t NbData;           /* It indicates the number of data transferred with this command.
211                                 This field is only used for indirect mode.
212                                 This parameter can be a value between 1 and 0xFFFFFFFF
213                                 In case of autopolling mode, this parameter can be any value between 1 and 4 */
214   uint32_t DQSMode;          /* It enables or not the data strobe management.
215                                 This parameter can be a value of @ref OSPI_DQSMode */
216 }OSPI_HyperbusCmdTypeDef;
217 
218 /**
219   * @brief  HAL OSPI Auto Polling mode configuration structure definition
220   */
221 typedef struct
222 {
223   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
224                                   This parameter can be any value between 0 and 0xFFFFFFFF */
225   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
226                                   This parameter can be any value between 0 and 0xFFFFFFFF */
227   uint32_t MatchMode;          /* Specifies the method used for determining a match.
228                                   This parameter can be a value of @ref OSPI_MatchMode */
229   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
230                                   This parameter can be a value of @ref OSPI_AutomaticStop */
231   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
232                                   This parameter can be any value between 0 and 0xFFFF */
233 }OSPI_AutoPollingTypeDef;
234 
235 /**
236   * @brief  HAL OSPI Memory Mapped mode configuration structure definition
237   */
238 typedef struct
239 {
240   uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
241                                   This parameter can be a value of @ref OSPI_TimeOutActivation */
242   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
243                                   This parameter can be any value between 0 and 0xFFFF */
244 }OSPI_MemoryMappedTypeDef;
245 
246 /**
247   * @brief HAL OSPI IO Manager Configuration structure definition
248   */
249 typedef struct
250 {
251   uint32_t ClkPort;                /* It indicates which port of the OSPI IO Manager is used for the CLK pins.
252                                       This parameter can be a value between 1 and 8 */
253   uint32_t DQSPort;                /* It indicates which port of the OSPI IO Manager is used for the DQS pin.
254                                       This parameter can be a value between 1 and 8 */
255   uint32_t NCSPort;                /* It indicates which port of the OSPI IO Manager is used for the NCS pin.
256                                       This parameter can be a value between 1 and 8 */
257   uint32_t IOLowPort;              /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins.
258                                       This parameter can be a value of @ref OSPIM_IOPort */
259   uint32_t IOHighPort;             /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
260                                       This parameter can be a value of @ref OSPIM_IOPort */
261 }OSPIM_CfgTypeDef;
262 
263 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
264 /**
265   * @brief  HAL OSPI Callback ID enumeration definition
266   */
267 typedef enum
268 {
269   HAL_OSPI_ERROR_CB_ID          = 0x00U,  /*!< OSPI Error Callback ID            */
270   HAL_OSPI_ABORT_CB_ID          = 0x01U,  /*!< OSPI Abort Callback ID            */
271   HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< OSPI FIFO Threshold Callback ID   */
272   HAL_OSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< OSPI Command Complete Callback ID */
273   HAL_OSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< OSPI Rx Complete Callback ID      */
274   HAL_OSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< OSPI Tx Complete Callback ID      */
275   HAL_OSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< OSPI Rx Half Complete Callback ID */
276   HAL_OSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< OSPI Tx Half Complete Callback ID */
277   HAL_OSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< OSPI Status Match Callback ID     */
278   HAL_OSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< OSPI Timeout Callback ID          */
279 
280   HAL_OSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< OSPI MspInit Callback ID          */
281   HAL_OSPI_MSP_DEINIT_CB_ID     = 0x0BU   /*!< OSPI MspDeInit Callback ID        */
282 }HAL_OSPI_CallbackIDTypeDef;
283 
284 /**
285   * @brief  HAL OSPI Callback pointer definition
286   */
287 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
288 #endif
289 /**
290   * @}
291   */
292 
293 /* Exported constants --------------------------------------------------------*/
294 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants
295   * @{
296   */
297 
298 /** @defgroup OSPI_State OSPI State
299   * @{
300   */
301 #define HAL_OSPI_STATE_RESET                 ((uint32_t)0x00000000U)      /*!< Initial state                                                          */
302 #define HAL_OSPI_STATE_HYPERBUS_INIT         ((uint32_t)0x00000001U)      /*!< Initialization done in hyperbus mode but timing configuration not done */
303 #define HAL_OSPI_STATE_READY                 ((uint32_t)0x00000002U)      /*!< Driver ready to be used                                                */
304 #define HAL_OSPI_STATE_CMD_CFG               ((uint32_t)0x00000004U)      /*!< Command (regular or hyperbus) configured, ready for an action          */
305 #define HAL_OSPI_STATE_READ_CMD_CFG          ((uint32_t)0x00000014U)      /*!< Read command configuration done, not the write command configuration   */
306 #define HAL_OSPI_STATE_WRITE_CMD_CFG         ((uint32_t)0x00000024U)      /*!< Write command configuration done, not the read command configuration   */
307 #define HAL_OSPI_STATE_BUSY_CMD              ((uint32_t)0x00000008U)      /*!< Command without data on-going                                          */
308 #define HAL_OSPI_STATE_BUSY_TX               ((uint32_t)0x00000018U)      /*!< Indirect Tx on-going                                                   */
309 #define HAL_OSPI_STATE_BUSY_RX               ((uint32_t)0x00000028U)      /*!< Indirect Rx on-going                                                   */
310 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING     ((uint32_t)0x00000048U)      /*!< Auto-polling on-going                                                  */
311 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED       ((uint32_t)0x00000088U)      /*!< Memory-mapped on-going                                                 */
312 #define HAL_OSPI_STATE_ABORT                 ((uint32_t)0x00000100U)      /*!< Abort on-going                                                         */
313 #define HAL_OSPI_STATE_ERROR                 ((uint32_t)0x00000200U)      /*!< Blocking error, driver should be re-initialized                        */
314 /**
315   * @}
316   */
317 
318 /** @defgroup OSPI_ErrorCode OSPI Error Code
319   * @{
320   */
321 #define HAL_OSPI_ERROR_NONE                  ((uint32_t)0x00000000U)                                         /*!< No error                                   */
322 #define HAL_OSPI_ERROR_TIMEOUT               ((uint32_t)0x00000001U)                                         /*!< Timeout error                              */
323 #define HAL_OSPI_ERROR_TRANSFER              ((uint32_t)0x00000002U)                                         /*!< Transfer error                             */
324 #define HAL_OSPI_ERROR_DMA                   ((uint32_t)0x00000004U)                                         /*!< DMA transfer error                         */
325 #define HAL_OSPI_ERROR_INVALID_PARAM         ((uint32_t)0x00000008U)                                         /*!< Invalid parameters error                   */
326 #define HAL_OSPI_ERROR_INVALID_SEQUENCE      ((uint32_t)0x00000010U)                                         /*!< Sequence of the state machine is incorrect */
327 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
328 #define HAL_OSPI_ERROR_INVALID_CALLBACK      ((uint32_t)0x00000020U)                                         /*!< Invalid callback error                     */
329 #endif
330 /**
331   * @}
332   */
333 
334 /** @defgroup OSPI_DualQuad OSPI Dual-Quad
335   * @{
336   */
337 #define HAL_OSPI_DUALQUAD_DISABLE            ((uint32_t)0x00000000U)                                         /*!< Dual-Quad mode disabled */
338 #define HAL_OSPI_DUALQUAD_ENABLE             ((uint32_t)OCTOSPI_CR_DQM)                                      /*!< Dual-Quad mode enabled  */
339 /**
340   * @}
341   */
342 
343 /** @defgroup OSPI_MemoryType OSPI Memory Type
344   * @{
345   */
346 #define HAL_OSPI_MEMTYPE_MICRON              ((uint32_t)0x00000000U)                                         /*!< Micron mode       */
347 #define HAL_OSPI_MEMTYPE_MACRONIX            ((uint32_t)OCTOSPI_DCR1_MTYP_0)                                 /*!< Macronix mode     */
348 #if !defined(STM32L4R5xx)&&!defined(STM32L4R7xx)&&!defined(STM32L4R9xx)&&!defined(STM32L4S5xx)&&!defined(STM32L4S7xx)&&!defined(STM32L4S9xx)
349 #define HAL_OSPI_MEMTYPE_APMEMORY            ((uint32_t)OCTOSPI_DCR1_MTYP_1)                                 /*!< AP Memory mode    */
350 #endif
351 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM        ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0))         /*!< Macronix RAM mode */
352 #define HAL_OSPI_MEMTYPE_HYPERBUS            ((uint32_t)OCTOSPI_DCR1_MTYP_2)                                 /*!< Hyperbus mode     */
353 /**
354   * @}
355   */
356 
357 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock
358   * @{
359   */
360 #define HAL_OSPI_FREERUNCLK_DISABLE          ((uint32_t)0x00000000U)                                         /*!< CLK is not free running               */
361 #define HAL_OSPI_FREERUNCLK_ENABLE           ((uint32_t)OCTOSPI_DCR1_FRCK)                                   /*!< CLK is free running (always provided) */
362 /**
363   * @}
364   */
365 
366 /** @defgroup OSPI_ClockMode OSPI Clock Mode
367   * @{
368   */
369 #define HAL_OSPI_CLOCK_MODE_0                ((uint32_t)0x00000000U)                                         /*!< CLK must stay low while nCS is high  */
370 #define HAL_OSPI_CLOCK_MODE_3                ((uint32_t)OCTOSPI_DCR1_CKMODE)                                 /*!< CLK must stay high while nCS is high */
371 /**
372   * @}
373   */
374 
375 /** @defgroup OSPI_WrapSize OSPI Wrap-Size
376   * @{
377   */
378 #define HAL_OSPI_WRAP_NOT_SUPPORTED          ((uint32_t)0x00000000U)                                         /*!< wrapped reads are not supported by the memory   */
379 #define HAL_OSPI_WRAP_16_BYTES               ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1)                             /*!< external memory supports wrap size of 16 bytes  */
380 #define HAL_OSPI_WRAP_32_BYTES               ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes  */
381 #define HAL_OSPI_WRAP_64_BYTES               ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2)                             /*!< external memory supports wrap size of 64 bytes  */
382 #define HAL_OSPI_WRAP_128_BYTES              ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */
383 /**
384   * @}
385   */
386 
387 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting
388   * @{
389   */
390 #define HAL_OSPI_SAMPLE_SHIFTING_NONE        ((uint32_t)0x00000000U)                                         /*!< No shift        */
391 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE   ((uint32_t)OCTOSPI_TCR_SSHIFT)                                  /*!< 1/2 cycle shift */
392 /**
393   * @}
394   */
395 
396 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle
397   * @{
398   */
399 #define HAL_OSPI_DHQC_DISABLE                ((uint32_t)0x00000000U)                                         /*!< No Delay             */
400 #define HAL_OSPI_DHQC_ENABLE                 ((uint32_t)OCTOSPI_TCR_DHQC)                                    /*!< Delay Hold 1/4 cycle */
401 /**
402   * @}
403   */
404 
405 /** @defgroup OSPI_OperationType OSPI Operation Type
406   * @{
407   */
408 #define HAL_OSPI_OPTYPE_COMMON_CFG           ((uint32_t)0x00000000U)                                         /*!< Common configuration (indirect or auto-polling mode) */
409 #define HAL_OSPI_OPTYPE_READ_CFG             ((uint32_t)0x00000001U)                                         /*!< Read configuration (memory-mapped mode)              */
410 #define HAL_OSPI_OPTYPE_WRITE_CFG            ((uint32_t)0x00000002U)                                         /*!< Write configuration (memory-mapped mode)             */
411 /**
412   * @}
413   */
414 
415 /** @defgroup OSPI_FlashID OSPI Flash Id
416   * @{
417   */
418 #define HAL_OSPI_FLASH_ID_1                  ((uint32_t)0x00000000U)                                         /*!< FLASH 1 selected */
419 #define HAL_OSPI_FLASH_ID_2                  ((uint32_t)OCTOSPI_CR_FSEL)                                     /*!< FLASH 2 selected */
420 /**
421   * @}
422   */
423 
424 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode
425   * @{
426   */
427 #define HAL_OSPI_INSTRUCTION_NONE            ((uint32_t)0x00000000U)                                         /*!< No instruction               */
428 #define HAL_OSPI_INSTRUCTION_1_LINE          ((uint32_t)OCTOSPI_CCR_IMODE_0)                                 /*!< Instruction on a single line */
429 #define HAL_OSPI_INSTRUCTION_2_LINES         ((uint32_t)OCTOSPI_CCR_IMODE_1)                                 /*!< Instruction on two lines     */
430 #define HAL_OSPI_INSTRUCTION_4_LINES         ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))         /*!< Instruction on four lines    */
431 #define HAL_OSPI_INSTRUCTION_8_LINES         ((uint32_t)OCTOSPI_CCR_IMODE_2)                                 /*!< Instruction on eight lines   */
432 /**
433   * @}
434   */
435 
436 /** @defgroup OSPI_InstructionSize OSPI Instruction Size
437   * @{
438   */
439 #define HAL_OSPI_INSTRUCTION_8_BITS          ((uint32_t)0x00000000U)                                         /*!< 8-bit instruction  */
440 #define HAL_OSPI_INSTRUCTION_16_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE_0)                                 /*!< 16-bit instruction */
441 #define HAL_OSPI_INSTRUCTION_24_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE_1)                                 /*!< 24-bit instruction */
442 #define HAL_OSPI_INSTRUCTION_32_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE)                                   /*!< 32-bit instruction */
443 /**
444   * @}
445   */
446 
447 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
448   * @{
449   */
450 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE     ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for instruction phase */
451 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE      ((uint32_t)OCTOSPI_CCR_IDTR)                                    /*!< DTR mode enabled for instruction phase  */
452 /**
453   * @}
454   */
455 
456 /** @defgroup OSPI_AddressMode OSPI Address Mode
457   * @{
458   */
459 #define HAL_OSPI_ADDRESS_NONE                ((uint32_t)0x00000000U)                                         /*!< No address               */
460 #define HAL_OSPI_ADDRESS_1_LINE              ((uint32_t)OCTOSPI_CCR_ADMODE_0)                                /*!< Address on a single line */
461 #define HAL_OSPI_ADDRESS_2_LINES             ((uint32_t)OCTOSPI_CCR_ADMODE_1)                                /*!< Address on two lines     */
462 #define HAL_OSPI_ADDRESS_4_LINES             ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))       /*!< Address on four lines    */
463 #define HAL_OSPI_ADDRESS_8_LINES             ((uint32_t)OCTOSPI_CCR_ADMODE_2)                                /*!< Address on eight lines   */
464 /**
465   * @}
466   */
467 
468 /** @defgroup OSPI_AddressSize OSPI Address Size
469   * @{
470   */
471 #define HAL_OSPI_ADDRESS_8_BITS              ((uint32_t)0x00000000U)                                         /*!< 8-bit address  */
472 #define HAL_OSPI_ADDRESS_16_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE_0)                                /*!< 16-bit address */
473 #define HAL_OSPI_ADDRESS_24_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE_1)                                /*!< 24-bit address */
474 #define HAL_OSPI_ADDRESS_32_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE)                                  /*!< 32-bit address */
475 /**
476   * @}
477   */
478 
479 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
480   * @{
481   */
482 #define HAL_OSPI_ADDRESS_DTR_DISABLE         ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for address phase */
483 #define HAL_OSPI_ADDRESS_DTR_ENABLE          ((uint32_t)OCTOSPI_CCR_ADDTR)                                   /*!< DTR mode enabled for address phase  */
484 /**
485   * @}
486   */
487 
488 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
489   * @{
490   */
491 #define HAL_OSPI_ALTERNATE_BYTES_NONE        ((uint32_t)0x00000000U)                                         /*!< No alternate bytes               */
492 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE      ((uint32_t)OCTOSPI_CCR_ABMODE_0)                                /*!< Alternate bytes on a single line */
493 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES     ((uint32_t)OCTOSPI_CCR_ABMODE_1)                                /*!< Alternate bytes on two lines     */
494 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES     ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))       /*!< Alternate bytes on four lines    */
495 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES     ((uint32_t)OCTOSPI_CCR_ABMODE_2)                                /*!< Alternate bytes on eight lines   */
496 /**
497   * @}
498   */
499 
500 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size
501   * @{
502   */
503 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS      ((uint32_t)0x00000000U)                                         /*!< 8-bit alternate bytes  */
504 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE_0)                                /*!< 16-bit alternate bytes */
505 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE_1)                                /*!< 24-bit alternate bytes */
506 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE)                                  /*!< 32-bit alternate bytes */
507 /**
508   * @}
509   */
510 
511 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
512   * @{
513   */
514 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for alternate bytes phase */
515 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE  ((uint32_t)OCTOSPI_CCR_ABDTR)                                   /*!< DTR mode enabled for alternate bytes phase  */
516 /**
517   * @}
518   */
519 
520 /** @defgroup OSPI_DataMode OSPI Data Mode
521   * @{
522   */
523 #define HAL_OSPI_DATA_NONE                   ((uint32_t)0x00000000U)                                         /*!< No data               */
524 #define HAL_OSPI_DATA_1_LINE                 ((uint32_t)OCTOSPI_CCR_DMODE_0)                                 /*!< Data on a single line */
525 #define HAL_OSPI_DATA_2_LINES                ((uint32_t)OCTOSPI_CCR_DMODE_1)                                 /*!< Data on two lines     */
526 #define HAL_OSPI_DATA_4_LINES                ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))         /*!< Data on four lines    */
527 #define HAL_OSPI_DATA_8_LINES                ((uint32_t)OCTOSPI_CCR_DMODE_2)                                 /*!< Data on eight lines   */
528 /**
529   * @}
530   */
531 
532 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
533   * @{
534   */
535 #define HAL_OSPI_DATA_DTR_DISABLE            ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for data phase */
536 #define HAL_OSPI_DATA_DTR_ENABLE             ((uint32_t)OCTOSPI_CCR_DDTR)                                    /*!< DTR mode enabled for data phase  */
537 /**
538   * @}
539   */
540 
541 /** @defgroup OSPI_DQSMode OSPI DQS Mode
542   * @{
543   */
544 #define HAL_OSPI_DQS_DISABLE                 ((uint32_t)0x00000000U)                                         /*!< DQS disabled */
545 #define HAL_OSPI_DQS_ENABLE                  ((uint32_t)OCTOSPI_CCR_DQSE)                                    /*!< DQS enabled  */
546 /**
547   * @}
548   */
549 
550 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode
551   * @{
552   */
553 #define HAL_OSPI_SIOO_INST_EVERY_CMD         ((uint32_t)0x00000000U)                                         /*!< Send instruction on every transaction       */
554 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD    ((uint32_t)OCTOSPI_CCR_SIOO)                                    /*!< Send instruction only for the first command */
555 /**
556   * @}
557   */
558 
559 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation
560   * @{
561   */
562 #define HAL_OSPI_LATENCY_ON_WRITE            ((uint32_t)0x00000000U)                                         /*!< Latency on write accesses    */
563 #define HAL_OSPI_NO_LATENCY_ON_WRITE         ((uint32_t)OCTOSPI_HLCR_WZL)                                    /*!< No latency on write accesses */
564 /**
565   * @}
566   */
567 
568 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
569   * @{
570   */
571 #define HAL_OSPI_VARIABLE_LATENCY            ((uint32_t)0x00000000U)                                         /*!< Variable initial latency */
572 #define HAL_OSPI_FIXED_LATENCY               ((uint32_t)OCTOSPI_HLCR_LM)                                     /*!< Fixed latency            */
573 /**
574   * @}
575   */
576 
577 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space
578   * @{
579   */
580 #define HAL_OSPI_MEMORY_ADDRESS_SPACE        ((uint32_t)0x00000000U)                                         /*!< HyperBus memory mode   */
581 #define HAL_OSPI_REGISTER_ADDRESS_SPACE      ((uint32_t)OCTOSPI_DCR1_MTYP_0)                                 /*!< HyperBus register mode */
582 /**
583   * @}
584   */
585 
586 /** @defgroup OSPI_MatchMode OSPI Match Mode
587   * @{
588   */
589 #define HAL_OSPI_MATCH_MODE_AND              ((uint32_t)0x00000000U)                                         /*!< AND match mode between unmasked bits */
590 #define HAL_OSPI_MATCH_MODE_OR               ((uint32_t)OCTOSPI_CR_PMM)                                      /*!< OR match mode between unmasked bits  */
591 /**
592   * @}
593   */
594 
595 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop
596   * @{
597   */
598 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE      ((uint32_t)0x00000000U)                                         /*!< AutoPolling stops only with abort or OSPI disabling */
599 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE       ((uint32_t)OCTOSPI_CR_APMS)                                     /*!< AutoPolling stops as soon as there is a match       */
600 /**
601   * @}
602   */
603 
604 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation
605   * @{
606   */
607 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE     ((uint32_t)0x00000000U)                                         /*!< Timeout counter disabled, nCS remains active               */
608 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE      ((uint32_t)OCTOSPI_CR_TCEN)                                     /*!< Timeout counter enabled, nCS released when timeout expires */
609 /**
610   * @}
611   */
612 
613 /** @defgroup OSPI_Flags OSPI Flags
614   * @{
615   */
616 #define HAL_OSPI_FLAG_BUSY                   OCTOSPI_SR_BUSY                                                 /*!< Busy flag: operation is ongoing                                                                          */
617 #define HAL_OSPI_FLAG_TO                     OCTOSPI_SR_TOF                                                  /*!< Timeout flag: timeout occurs in memory-mapped mode                                                       */
618 #define HAL_OSPI_FLAG_SM                     OCTOSPI_SR_SMF                                                  /*!< Status match flag: received data matches in autopolling mode                                             */
619 #define HAL_OSPI_FLAG_FT                     OCTOSPI_SR_FTF                                                  /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete              */
620 #define HAL_OSPI_FLAG_TC                     OCTOSPI_SR_TCF                                                  /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */
621 #define HAL_OSPI_FLAG_TE                     OCTOSPI_SR_TEF                                                  /*!< Transfer error flag: invalid address is being accessed                                                   */
622 /**
623   * @}
624   */
625 
626 /** @defgroup OSPI_Interrupts OSPI Interrupts
627   * @{
628   */
629 #define HAL_OSPI_IT_TO                       OCTOSPI_CR_TOIE                                                 /*!< Interrupt on the timeout flag           */
630 #define HAL_OSPI_IT_SM                       OCTOSPI_CR_SMIE                                                 /*!< Interrupt on the status match flag      */
631 #define HAL_OSPI_IT_FT                       OCTOSPI_CR_FTIE                                                 /*!< Interrupt on the fifo threshold flag    */
632 #define HAL_OSPI_IT_TC                       OCTOSPI_CR_TCIE                                                 /*!< Interrupt on the transfer complete flag */
633 #define HAL_OSPI_IT_TE                       OCTOSPI_CR_TEIE                                                 /*!< Interrupt on the transfer error flag    */
634 /**
635   * @}
636   */
637 
638 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition
639   * @{
640   */
641 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE       ((uint32_t)5000U)                                               /* 5 s */
642 /**
643   * @}
644   */
645 
646 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port
647   * @{
648   */
649 #define HAL_OSPIM_IOPORT_1_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U))                          /*!< Port 1 - IO[3:0] */
650 #define HAL_OSPIM_IOPORT_1_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U))                          /*!< Port 1 - IO[7:4] */
651 #define HAL_OSPIM_IOPORT_2_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U))                          /*!< Port 2 - IO[3:0] */
652 #define HAL_OSPIM_IOPORT_2_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U))                          /*!< Port 2 - IO[7:4] */
653 /**
654   * @}
655   */
656 /**
657   * @}
658   */
659 
660 /* Exported macros -----------------------------------------------------------*/
661 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros
662   * @{
663   */
664 /** @brief Reset OSPI handle state.
665   * @param  __HANDLE__: OSPI handle.
666   * @retval None
667   */
668 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
669 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
670                                                                   (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \
671                                                                   (__HANDLE__)->MspInitCallback = NULL;       \
672                                                                   (__HANDLE__)->MspDeInitCallback = NULL;     \
673                                                                } while(0)
674 #else
675 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
676 #endif
677 
678 /** @brief  Enable the OSPI peripheral.
679   * @param  __HANDLE__: specifies the OSPI Handle.
680   * @retval None
681   */
682 #define __HAL_OSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
683 
684 /** @brief  Disable the OSPI peripheral.
685   * @param  __HANDLE__: specifies the OSPI Handle.
686   * @retval None
687   */
688 #define __HAL_OSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
689 
690 /** @brief  Enable the specified OSPI interrupt.
691   * @param  __HANDLE__: specifies the OSPI Handle.
692   * @param  __INTERRUPT__: specifies the OSPI interrupt source to enable.
693   *          This parameter can be one of the following values:
694   *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
695   *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
696   *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
697   *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
698   *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
699   * @retval None
700   */
701 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
702 
703 
704 /** @brief  Disable the specified OSPI interrupt.
705   * @param  __HANDLE__: specifies the OSPI Handle.
706   * @param  __INTERRUPT__: specifies the OSPI interrupt source to disable.
707   *          This parameter can be one of the following values:
708   *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
709   *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
710   *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
711   *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
712   *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
713   * @retval None
714   */
715 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
716 
717 /** @brief  Check whether the specified OSPI interrupt source is enabled or not.
718   * @param  __HANDLE__: specifies the OSPI Handle.
719   * @param  __INTERRUPT__: specifies the OSPI interrupt source to check.
720   *          This parameter can be one of the following values:
721   *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
722   *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
723   *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
724   *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
725   *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
726   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
727   */
728 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
729 
730 /**
731   * @brief  Check whether the selected OSPI flag is set or not.
732   * @param  __HANDLE__: specifies the OSPI Handle.
733   * @param  __FLAG__: specifies the OSPI flag to check.
734   *          This parameter can be one of the following values:
735   *            @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag
736   *            @arg HAL_OSPI_FLAG_TO:   OSPI Timeout flag
737   *            @arg HAL_OSPI_FLAG_SM:   OSPI Status match flag
738   *            @arg HAL_OSPI_FLAG_FT:   OSPI FIFO threshold flag
739   *            @arg HAL_OSPI_FLAG_TC:   OSPI Transfer complete flag
740   *            @arg HAL_OSPI_FLAG_TE:   OSPI Transfer error flag
741   * @retval None
742   */
743 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
744 
745 /** @brief  Clears the specified OSPI's flag status.
746   * @param  __HANDLE__: specifies the OSPI Handle.
747   * @param  __FLAG__: specifies the OSPI clear register flag that needs to be set
748   *          This parameter can be one of the following values:
749   *            @arg HAL_OSPI_FLAG_TO:   OSPI Timeout flag
750   *            @arg HAL_OSPI_FLAG_SM:   OSPI Status match flag
751   *            @arg HAL_OSPI_FLAG_TC:   OSPI Transfer complete flag
752   *            @arg HAL_OSPI_FLAG_TE:   OSPI Transfer error flag
753   * @retval None
754   */
755 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
756 
757 /**
758   * @}
759   */
760 
761 /* Exported functions --------------------------------------------------------*/
762 /** @addtogroup OSPI_Exported_Functions
763   * @{
764   */
765 
766 /* Initialization/de-initialization functions  ********************************/
767 /** @addtogroup OSPI_Exported_Functions_Group1
768   * @{
769   */
770 HAL_StatusTypeDef     HAL_OSPI_Init                 (OSPI_HandleTypeDef *hospi);
771 void                  HAL_OSPI_MspInit              (OSPI_HandleTypeDef *hospi);
772 HAL_StatusTypeDef     HAL_OSPI_DeInit               (OSPI_HandleTypeDef *hospi);
773 void                  HAL_OSPI_MspDeInit            (OSPI_HandleTypeDef *hospi);
774 
775 /**
776   * @}
777   */
778 
779 /* IO operation functions *****************************************************/
780 /** @addtogroup OSPI_Exported_Functions_Group2
781   * @{
782   */
783 /* OSPI IRQ handler function */
784 void                  HAL_OSPI_IRQHandler           (OSPI_HandleTypeDef *hospi);
785 
786 /* OSPI command configuration functions */
787 HAL_StatusTypeDef     HAL_OSPI_Command              (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
788 HAL_StatusTypeDef     HAL_OSPI_Command_IT           (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
789 HAL_StatusTypeDef     HAL_OSPI_HyperbusCfg          (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
790 HAL_StatusTypeDef     HAL_OSPI_HyperbusCmd          (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
791 
792 /* OSPI indirect mode functions */
793 HAL_StatusTypeDef     HAL_OSPI_Transmit             (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
794 HAL_StatusTypeDef     HAL_OSPI_Receive              (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
795 HAL_StatusTypeDef     HAL_OSPI_Transmit_IT          (OSPI_HandleTypeDef *hospi, uint8_t *pData);
796 HAL_StatusTypeDef     HAL_OSPI_Receive_IT           (OSPI_HandleTypeDef *hospi, uint8_t *pData);
797 HAL_StatusTypeDef     HAL_OSPI_Transmit_DMA         (OSPI_HandleTypeDef *hospi, uint8_t *pData);
798 HAL_StatusTypeDef     HAL_OSPI_Receive_DMA          (OSPI_HandleTypeDef *hospi, uint8_t *pData);
799 
800 /* OSPI status flag polling mode functions */
801 HAL_StatusTypeDef     HAL_OSPI_AutoPolling          (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
802 HAL_StatusTypeDef     HAL_OSPI_AutoPolling_IT       (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
803 
804 /* OSPI memory-mapped mode functions */
805 HAL_StatusTypeDef     HAL_OSPI_MemoryMapped         (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
806 
807 /* Callback functions in non-blocking modes ***********************************/
808 void                  HAL_OSPI_ErrorCallback        (OSPI_HandleTypeDef *hospi);
809 void                  HAL_OSPI_AbortCpltCallback    (OSPI_HandleTypeDef *hospi);
810 void                  HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
811 
812 /* OSPI indirect mode functions */
813 void                  HAL_OSPI_CmdCpltCallback      (OSPI_HandleTypeDef *hospi);
814 void                  HAL_OSPI_RxCpltCallback       (OSPI_HandleTypeDef *hospi);
815 void                  HAL_OSPI_TxCpltCallback       (OSPI_HandleTypeDef *hospi);
816 void                  HAL_OSPI_RxHalfCpltCallback   (OSPI_HandleTypeDef *hospi);
817 void                  HAL_OSPI_TxHalfCpltCallback   (OSPI_HandleTypeDef *hospi);
818 
819 /* OSPI status flag polling mode functions */
820 void                  HAL_OSPI_StatusMatchCallback  (OSPI_HandleTypeDef *hospi);
821 
822 /* OSPI memory-mapped mode functions */
823 void                  HAL_OSPI_TimeOutCallback      (OSPI_HandleTypeDef *hospi);
824 
825 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
826 /* OSPI callback registering/unregistering */
827 HAL_StatusTypeDef     HAL_OSPI_RegisterCallback     (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback);
828 HAL_StatusTypeDef     HAL_OSPI_UnRegisterCallback   (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
829 #endif
830 /**
831   * @}
832   */
833 
834 /* Peripheral Control and State functions  ************************************/
835 /** @addtogroup OSPI_Exported_Functions_Group3
836   * @{
837   */
838 HAL_StatusTypeDef     HAL_OSPI_Abort                (OSPI_HandleTypeDef *hospi);
839 HAL_StatusTypeDef     HAL_OSPI_Abort_IT             (OSPI_HandleTypeDef *hospi);
840 HAL_StatusTypeDef     HAL_OSPI_SetFifoThreshold     (OSPI_HandleTypeDef *hospi, uint32_t Threshold);
841 uint32_t              HAL_OSPI_GetFifoThreshold     (OSPI_HandleTypeDef *hospi);
842 HAL_StatusTypeDef     HAL_OSPI_SetTimeout           (OSPI_HandleTypeDef *hospi, uint32_t Timeout);
843 uint32_t              HAL_OSPI_GetError             (OSPI_HandleTypeDef *hospi);
844 uint32_t              HAL_OSPI_GetState             (OSPI_HandleTypeDef *hospi);
845 
846 /**
847   * @}
848   */
849 
850 /* OSPI IO Manager configuration function  ************************************/
851 /** @addtogroup OSPI_Exported_Functions_Group4
852   * @{
853   */
854 HAL_StatusTypeDef     HAL_OSPIM_Config              (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
855 
856 /**
857   * @}
858   */
859 
860 /**
861   * @}
862   */
863 /* End of exported functions -------------------------------------------------*/
864 
865 /* Private macros ------------------------------------------------------------*/
866 /**
867   @cond 0
868   */
869 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD)  (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U))
870 
871 #define IS_OSPI_DUALQUAD_MODE(MODE)        (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \
872                                             ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
873 
874 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
875 #define IS_OSPI_MEMORY_TYPE(TYPE)          (((TYPE) == HAL_OSPI_MEMTYPE_MICRON)       || \
876                                             ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX)     || \
877                                             ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
878                                             ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
879 #else
880 #define IS_OSPI_MEMORY_TYPE(TYPE)          (((TYPE) == HAL_OSPI_MEMTYPE_MICRON)       || \
881                                             ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX)     || \
882                                             ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY)     || \
883                                             ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
884                                             ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
885 #endif
886 
887 #define IS_OSPI_DEVICE_SIZE(SIZE)          (((SIZE) >= 1U) && ((SIZE) <= 32U))
888 
889 #define IS_OSPI_CS_HIGH_TIME(TIME)         (((TIME) >= 1U) && ((TIME) <= 8U))
890 
891 #define IS_OSPI_FREE_RUN_CLK(CLK)          (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \
892                                             ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))
893 
894 #define IS_OSPI_CLOCK_MODE(MODE)           (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \
895                                             ((MODE) == HAL_OSPI_CLOCK_MODE_3))
896 
897 #define IS_OSPI_WRAP_SIZE(SIZE)            (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \
898                                             ((SIZE) == HAL_OSPI_WRAP_16_BYTES)      || \
899                                             ((SIZE) == HAL_OSPI_WRAP_32_BYTES)      || \
900                                             ((SIZE) == HAL_OSPI_WRAP_64_BYTES)      || \
901                                             ((SIZE) == HAL_OSPI_WRAP_128_BYTES))
902 
903 #define IS_OSPI_CLK_PRESCALER(PRESCALER)   (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U))
904 
905 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE)     (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE)      || \
906                                             ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))
907 
908 #define IS_OSPI_DHQC(CYCLE)                (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \
909                                             ((CYCLE) == HAL_OSPI_DHQC_ENABLE))
910 
911 #define IS_OSPI_OPERATION_TYPE(TYPE)       (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \
912                                             ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG)   || \
913                                             ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG))
914 
915 #define IS_OSPI_FLASH_ID(FLASH)            (((FLASH) == HAL_OSPI_FLASH_ID_1) || \
916                                             ((FLASH) == HAL_OSPI_FLASH_ID_2))
917 
918 #define IS_OSPI_INSTRUCTION_MODE(MODE)     (((MODE) == HAL_OSPI_INSTRUCTION_NONE)    || \
919                                             ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE)  || \
920                                             ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
921                                             ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
922                                             ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
923 
924 #define IS_OSPI_INSTRUCTION_SIZE(SIZE)     (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS)  || \
925                                             ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \
926                                             ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \
927                                             ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS))
928 
929 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \
930                                             ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
931 
932 #define IS_OSPI_ADDRESS_MODE(MODE)         (((MODE) == HAL_OSPI_ADDRESS_NONE)    || \
933                                             ((MODE) == HAL_OSPI_ADDRESS_1_LINE)  || \
934                                             ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
935                                             ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
936                                             ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
937 
938 #define IS_OSPI_ADDRESS_SIZE(SIZE)         (((SIZE) == HAL_OSPI_ADDRESS_8_BITS)  || \
939                                             ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \
940                                             ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \
941                                             ((SIZE) == HAL_OSPI_ADDRESS_32_BITS))
942 
943 #define IS_OSPI_ADDRESS_DTR_MODE(MODE)     (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \
944                                             ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
945 
946 #define IS_OSPI_ALT_BYTES_MODE(MODE)       (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE)    || \
947                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE)  || \
948                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
949                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
950                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
951 
952 #define IS_OSPI_ALT_BYTES_SIZE(SIZE)       (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS)  || \
953                                             ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \
954                                             ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \
955                                             ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS))
956 
957 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE)   (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \
958                                             ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
959 
960 #define IS_OSPI_DATA_MODE(MODE)            (((MODE) == HAL_OSPI_DATA_NONE)    || \
961                                             ((MODE) == HAL_OSPI_DATA_1_LINE)  || \
962                                             ((MODE) == HAL_OSPI_DATA_2_LINES) || \
963                                             ((MODE) == HAL_OSPI_DATA_4_LINES) || \
964                                             ((MODE) == HAL_OSPI_DATA_8_LINES))
965 
966 #define IS_OSPI_NUMBER_DATA(NUMBER)        ((NUMBER) >= 1U)
967 
968 #define IS_OSPI_DATA_DTR_MODE(MODE)        (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \
969                                             ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
970 
971 #define IS_OSPI_DUMMY_CYCLES(NUMBER)       ((NUMBER) <= 31U)
972 
973 #define IS_OSPI_DQS_MODE(MODE)             (((MODE) == HAL_OSPI_DQS_DISABLE) || \
974                                             ((MODE) == HAL_OSPI_DQS_ENABLE))
975 
976 #define IS_OSPI_SIOO_MODE(MODE)            (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \
977                                             ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
978 
979 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER)   ((NUMBER) <= 255U)
980 
981 #define IS_OSPI_ACCESS_TIME(NUMBER)        ((NUMBER) <= 255U)
982 
983 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE)   (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \
984                                             ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
985 
986 #define IS_OSPI_LATENCY_MODE(MODE)         (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \
987                                             ((MODE) == HAL_OSPI_FIXED_LATENCY))
988 
989 #define IS_OSPI_ADDRESS_SPACE(SPACE)       (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \
990                                             ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE))
991 
992 #define IS_OSPI_MATCH_MODE(MODE)           (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \
993                                             ((MODE) == HAL_OSPI_MATCH_MODE_OR))
994 
995 #define IS_OSPI_AUTOMATIC_STOP(MODE)       (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \
996                                             ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
997 
998 #define IS_OSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= 0xFFFFU)
999 
1000 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))
1001 
1002 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE)   (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \
1003                                             ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
1004 
1005 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
1006 
1007 #define IS_OSPI_CS_BOUNDARY(BOUNDARY)      ((BOUNDARY) <= 31U)
1008 
1009 #define IS_OSPIM_PORT(NUMBER)              (((NUMBER) >= 1U) && ((NUMBER) <= 2U))
1010 
1011 #define IS_OSPIM_IO_PORT(PORT)             (((PORT) == HAL_OSPIM_IOPORT_1_LOW)  || \
1012                                             ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
1013                                             ((PORT) == HAL_OSPIM_IOPORT_2_LOW)  || \
1014                                             ((PORT) == HAL_OSPIM_IOPORT_2_HIGH))
1015 /**
1016   @endcond
1017   */
1018 
1019 /* End of private macros -----------------------------------------------------*/
1020 
1021 /**
1022   * @}
1023   */
1024 
1025 /**
1026   * @}
1027   */
1028 
1029 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
1030 
1031 #ifdef __cplusplus
1032 }
1033 #endif
1034 
1035 #endif /* STM32L4xx_HAL_OSPI_H */
1036 
1037 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1038