1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32H5xx_HAL_CORTEX_H 21 #define __STM32H5xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 40 * @{ 41 */ 42 43 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 44 * @{ 45 */ 46 typedef struct 47 { 48 uint8_t Enable; /*!< Specifies the status of the region. 49 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 50 uint8_t Number; /*!< Specifies the index of the region to protect. 51 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 52 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 53 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 54 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 55 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 56 uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter 57 can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 58 uint8_t DisableExec; /*!< Specifies the instruction access status. 59 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 60 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 61 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 62 } MPU_Region_InitTypeDef; 63 /** 64 * @} 65 */ 66 67 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes 68 * Initialization Structure Definition 69 * @{ 70 */ 71 typedef struct 72 { 73 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 74 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 75 76 uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter 77 can be a combination of @ref CORTEX_MPU_Attributes */ 78 79 } MPU_Attributes_InitTypeDef; 80 /** 81 * @} 82 */ 83 84 85 /** 86 * @} 87 */ 88 89 /* Exported constants --------------------------------------------------------*/ 90 91 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 92 * @{ 93 */ 94 95 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 96 * @{ 97 */ 98 #define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority, 99 4 bits for subpriority */ 100 #define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority, 101 3 bits for subpriority */ 102 #define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority, 103 2 bits for subpriority */ 104 #define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority, 105 1 bit for subpriority */ 106 #define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority, 107 0 bit for subpriority */ 108 /** 109 * @} 110 */ 111 112 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 113 * @{ 114 */ 115 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */ 116 #define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */ 117 #define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */ 118 #define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */ 119 /** 120 * @} 121 */ 122 123 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 124 * @{ 125 */ 126 #define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ 127 #define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ 128 #define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ 129 #define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ 130 /** 131 * @} 132 */ 133 134 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 135 * @{ 136 */ 137 #define MPU_REGION_ENABLE 1U /*!< Enable region */ 138 #define MPU_REGION_DISABLE 0U /*!< Disable region */ 139 /** 140 * @} 141 */ 142 143 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 144 * @{ 145 */ 146 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ 147 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ 148 /** 149 * @} 150 */ 151 152 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 153 * @{ 154 */ 155 #define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ 156 #define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ 157 #define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ 158 /** 159 * @} 160 */ 161 162 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 163 * @{ 164 */ 165 #define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ 166 #define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ 167 #define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ 168 #define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ 169 /** 170 * @} 171 */ 172 173 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 174 * @{ 175 */ 176 #define MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */ 177 #define MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */ 178 #define MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */ 179 #define MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */ 180 #define MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */ 181 #define MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */ 182 #define MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */ 183 #define MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */ 184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 185 #define MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */ 186 #define MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */ 187 #define MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */ 188 #define MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */ 189 #endif /* __ARM_FEATURE_CMSE */ 190 /** 191 * @} 192 */ 193 194 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 195 * @{ 196 */ 197 #define MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */ 198 #define MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */ 199 #define MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */ 200 #define MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */ 201 #define MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */ 202 #define MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */ 203 #define MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */ 204 #define MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */ 205 /** 206 * @} 207 */ 208 209 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 210 * @{ 211 */ 212 /* Device memory attributes */ 213 #define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ 214 #define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ 215 #define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ 216 #define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ 217 218 /* Normal memory attributes */ 219 /* To set with INNER_OUTER() macro for both inner/outer cache attributes */ 220 221 /* Non-cacheable memory attribute */ 222 #define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ 223 224 /* Cacheable memory attributes: combination of cache write policy, transient and allocation */ 225 /* - cache write policy */ 226 #define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ 227 #define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ 228 /* - transient mode attribute */ 229 #define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ 230 #define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ 231 /* - allocation attribute */ 232 #define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ 233 #define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ 234 #define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ 235 #define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */ 236 237 /** 238 * @} 239 */ 240 241 /** 242 * @} 243 */ 244 245 /* Exported macros -----------------------------------------------------------*/ 246 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 247 * @{ 248 */ 249 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 250 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 251 252 /** 253 * @} 254 */ 255 256 /* Exported functions --------------------------------------------------------*/ 257 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 258 * @{ 259 */ 260 261 /** @defgroup CORTEX_Exported_Functions_Group1 NVIC functions 262 * @brief NVIC functions 263 * @{ 264 */ 265 /* NVIC functions *****************************/ 266 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 267 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 268 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 269 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 270 void HAL_NVIC_SystemReset(void); 271 uint32_t HAL_NVIC_GetPriorityGrouping(void); 272 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 273 uint32_t *const pSubPriority); 274 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 275 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 276 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 277 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 278 /** 279 * @} 280 */ 281 282 /** @defgroup CORTEX_Exported_Functions_Group2 SYSTICK functions 283 * @brief SYSTICK functions 284 * @{ 285 */ 286 /* SYSTICK functions ***********************************************/ 287 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 288 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 289 uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); 290 void HAL_SYSTICK_IRQHandler(void); 291 void HAL_SYSTICK_Callback(void); 292 /** 293 * @} 294 */ 295 296 /** @defgroup CORTEX_Exported_Functions_Group3 MPU functions 297 * @brief MPU functions 298 * @{ 299 */ 300 /* MPU functions ***********************************************/ 301 void HAL_MPU_Enable(uint32_t MPU_Control); 302 void HAL_MPU_Disable(void); 303 void HAL_MPU_EnableRegion(uint32_t RegionNumber); 304 void HAL_MPU_DisableRegion(uint32_t RegionNumber); 305 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 306 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 307 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 308 /* MPU_NS Control functions ***********************************************/ 309 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 310 void HAL_MPU_Disable_NS(void); 311 void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); 312 void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); 313 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 314 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 315 #endif /* __ARM_FEATURE_CMSE */ 316 /** 317 * @} 318 */ 319 320 /** 321 * @} 322 */ 323 324 /* Private types -------------------------------------------------------------*/ 325 /* Private variables ---------------------------------------------------------*/ 326 /* Private constants ---------------------------------------------------------*/ 327 /* Private macros ------------------------------------------------------------*/ 328 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 329 * @{ 330 */ 331 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 332 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 333 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 334 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 335 ((GROUP) == NVIC_PRIORITYGROUP_4)) 336 337 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 338 339 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 340 341 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 342 343 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ 344 ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ 345 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ 346 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 347 348 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 349 #define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS)) 350 #endif /* __ARM_FEATURE_CMSE */ 351 352 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 353 ((STATE) == MPU_REGION_DISABLE)) 354 355 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 356 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 357 358 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ 359 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ 360 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 361 362 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ 363 ((TYPE) == MPU_REGION_ALL_RW) || \ 364 ((TYPE) == MPU_REGION_PRIV_RO) || \ 365 ((TYPE) == MPU_REGION_ALL_RO)) 366 367 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 368 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 369 ((NUMBER) == MPU_REGION_NUMBER1) || \ 370 ((NUMBER) == MPU_REGION_NUMBER2) || \ 371 ((NUMBER) == MPU_REGION_NUMBER3) || \ 372 ((NUMBER) == MPU_REGION_NUMBER4) || \ 373 ((NUMBER) == MPU_REGION_NUMBER5) || \ 374 ((NUMBER) == MPU_REGION_NUMBER6) || \ 375 ((NUMBER) == MPU_REGION_NUMBER7) || \ 376 ((NUMBER) == MPU_REGION_NUMBER8) || \ 377 ((NUMBER) == MPU_REGION_NUMBER9) || \ 378 ((NUMBER) == MPU_REGION_NUMBER10)|| \ 379 ((NUMBER) == MPU_REGION_NUMBER11)) 380 381 #define IS_MPU_REGION_NUMBER_NS(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 382 ((NUMBER) == MPU_REGION_NUMBER1) || \ 383 ((NUMBER) == MPU_REGION_NUMBER2) || \ 384 ((NUMBER) == MPU_REGION_NUMBER3) || \ 385 ((NUMBER) == MPU_REGION_NUMBER4) || \ 386 ((NUMBER) == MPU_REGION_NUMBER5) || \ 387 ((NUMBER) == MPU_REGION_NUMBER6) || \ 388 ((NUMBER) == MPU_REGION_NUMBER7)) 389 #else 390 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 391 ((NUMBER) == MPU_REGION_NUMBER1) || \ 392 ((NUMBER) == MPU_REGION_NUMBER2) || \ 393 ((NUMBER) == MPU_REGION_NUMBER3) || \ 394 ((NUMBER) == MPU_REGION_NUMBER4) || \ 395 ((NUMBER) == MPU_REGION_NUMBER5) || \ 396 ((NUMBER) == MPU_REGION_NUMBER6) || \ 397 ((NUMBER) == MPU_REGION_NUMBER7)) 398 #endif /* __ARM_FEATURE_CMSE */ 399 400 #define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ 401 ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ 402 ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ 403 ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ 404 ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ 405 ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ 406 ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ 407 ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) 408 409 /** 410 * @} 411 */ 412 413 /* Private functions ---------------------------------------------------------*/ 414 415 /** 416 * @} 417 */ 418 419 /** 420 * @} 421 */ 422 423 #ifdef __cplusplus 424 } 425 #endif 426 427 #endif /* __STM32H5xx_HAL_CORTEX_H */ 428
