1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_LL_FMC_H 38 #define __STM32L4xx_LL_FMC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup FMC_LL 52 * @{ 53 */ 54 55 /** @addtogroup FMC_LL_Private_Macros 56 * @{ 57 */ 58 #if defined(FMC_BANK1) 59 60 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 61 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 62 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 63 ((__BANK__) == FMC_NORSRAM_BANK4)) 64 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 65 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 66 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 67 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM) || \ 68 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 69 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 70 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 71 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 72 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 73 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 74 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 75 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 76 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 77 #if defined(FMC_BCR1_WFDIS) 78 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 79 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 80 #endif /* FMC_BCR1_WFDIS */ 81 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 82 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 83 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 84 ((__MODE__) == FMC_ACCESS_MODE_D)) 85 #if defined(FMC_BCRx_NBLSET) 86 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 87 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 88 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 89 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 90 #endif /* FMC_BCRx_NBLSET */ 91 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 92 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 93 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 94 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 95 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 96 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 97 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 98 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 99 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 100 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 101 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 102 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 103 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 104 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 105 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) 106 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 107 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 108 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 109 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 110 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) 111 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) 112 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) 113 #if defined(FMC_BTRx_DATAHLD) 114 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3) 115 #endif /* FMC_BTRx_DATAHLD */ 116 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) 117 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) 118 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 119 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 120 121 #endif /* FMC_BANK1 */ 122 #if defined(FMC_BANK3) 123 124 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 125 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 126 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 127 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 128 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 129 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 130 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 131 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 132 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 133 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 134 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 135 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 136 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 137 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) 138 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) 139 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254) 140 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254) 141 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254) 142 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254) 143 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 144 145 #endif /* FMC_BANK3 */ 146 147 /** 148 * @} 149 */ 150 151 /* Exported typedef ----------------------------------------------------------*/ 152 153 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 154 * @{ 155 */ 156 157 #if defined(FMC_BANK1) 158 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 159 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 160 #endif /* FMC_BANK1 */ 161 #if defined(FMC_BANK3) 162 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 163 #endif /* FMC_BANK3 */ 164 165 #if defined(FMC_BANK1) 166 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 167 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 168 #endif /* FMC_BANK1 */ 169 #if defined(FMC_BANK3) 170 #define FMC_NAND_DEVICE FMC_Bank3_R 171 #endif /* FMC_BANK3 */ 172 173 #if defined(FMC_BANK1) 174 /** 175 * @brief FMC NORSRAM Configuration Structure definition 176 */ 177 typedef struct 178 { 179 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 180 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 181 182 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 183 multiplexed on the data bus or not. 184 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 185 186 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 187 the corresponding memory device. 188 This parameter can be a value of @ref FMC_Memory_Type */ 189 190 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 191 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 192 193 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 194 valid only with synchronous burst Flash memories. 195 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 196 197 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 198 the Flash memory in burst mode. 199 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 200 201 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 202 clock cycle before the wait state or during the wait state, 203 valid only when accessing memories in burst mode. 204 This parameter can be a value of @ref FMC_Wait_Timing */ 205 206 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 207 This parameter can be a value of @ref FMC_Write_Operation */ 208 209 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 210 signal, valid for Flash memory access in burst mode. 211 This parameter can be a value of @ref FMC_Wait_Signal */ 212 213 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 214 This parameter can be a value of @ref FMC_Extended_Mode */ 215 216 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 217 valid only with asynchronous Flash memories. 218 This parameter can be a value of @ref FMC_AsynchronousWait */ 219 220 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 221 This parameter can be a value of @ref FMC_Write_Burst */ 222 223 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 224 This parameter is only enabled through the FMC_BCR1 register, and don't care 225 through FMC_BCR2..4 registers. 226 This parameter can be a value of @ref FMC_Continous_Clock */ 227 228 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 229 This parameter is only enabled through the FMC_BCR1 register, and don't care 230 through FMC_BCR2..4 registers. 231 This parameter can be a value of @ref FMC_Write_FIFO. 232 @note This Parameter is not available for STM32L47x/L48x devices. */ 233 234 uint32_t PageSize; /*!< Specifies the memory page size. 235 This parameter can be a value of @ref FMC_Page_Size */ 236 237 #if defined(FMC_BCRx_NBLSET) 238 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 239 This parameter can be a value of @ref FMC_Byte_Lane */ 240 #endif /* FMC_BCRx_NBLSET */ 241 242 }FMC_NORSRAM_InitTypeDef; 243 244 /** 245 * @brief FMC NORSRAM Timing parameters structure definition 246 */ 247 typedef struct 248 { 249 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 250 the duration of the address setup time. 251 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 252 @note This parameter is not used with synchronous NOR Flash memories. */ 253 254 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 255 the duration of the address hold time. 256 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 257 @note This parameter is not used with synchronous NOR Flash memories. */ 258 259 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 260 the duration of the data setup time. 261 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 262 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 263 NOR Flash memories. */ 264 265 #if defined(FMC_BTRx_DATAHLD) 266 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 267 the duration of the data hold time. 268 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 269 @note This parameter is used for used in asynchronous accesses. */ 270 #endif /* FMC_BTRx_DATAHLD */ 271 272 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 273 the duration of the bus turnaround. 274 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 275 @note This parameter is only used for multiplexed NOR Flash memories. */ 276 277 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 278 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. 279 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 280 accesses. */ 281 282 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 283 to the memory before getting the first data. 284 The parameter value depends on the memory type as shown below: 285 - It must be set to 0 in case of a CRAM 286 - It is don't care in asynchronous NOR, SRAM or ROM accesses 287 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories 288 with synchronous burst mode enable */ 289 290 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 291 This parameter can be a value of @ref FMC_Access_Mode */ 292 }FMC_NORSRAM_TimingTypeDef; 293 #endif /* FMC_BANK1 */ 294 295 #if defined(FMC_BANK3) 296 /** 297 * @brief FMC NAND Configuration Structure definition 298 */ 299 typedef struct 300 { 301 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 302 This parameter can be a value of @ref FMC_NAND_Bank */ 303 304 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 305 This parameter can be any value of @ref FMC_Wait_feature */ 306 307 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 308 This parameter can be any value of @ref FMC_NAND_Data_Width */ 309 310 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 311 This parameter can be any value of @ref FMC_ECC */ 312 313 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 314 This parameter can be any value of @ref FMC_ECC_Page_Size */ 315 316 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 317 delay between CLE low and RE low. 318 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 319 320 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 321 delay between ALE low and RE low. 322 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 323 }FMC_NAND_InitTypeDef; 324 325 /** 326 * @brief FMC NAND Timing parameters structure definition 327 */ 328 typedef struct 329 { 330 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 331 the command assertion for NAND-Flash read or write access 332 to common/Attribute or I/O memory space (depending on 333 the memory space timing to be configured). 334 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 335 336 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 337 command for NAND-Flash read or write access to 338 common/Attribute or I/O memory space (depending on the 339 memory space timing to be configured). 340 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 341 342 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 343 (and data for write access) after the command de-assertion 344 for NAND-Flash read or write access to common/Attribute 345 or I/O memory space (depending on the memory space timing 346 to be configured). 347 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 348 349 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 350 data bus is kept in HiZ after the start of a NAND-Flash 351 write access to common/Attribute or I/O memory space (depending 352 on the memory space timing to be configured). 353 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 354 }FMC_NAND_PCC_TimingTypeDef; 355 #endif /* FMC_BANK3 */ 356 357 /** 358 * @} 359 */ 360 361 /* Exported constants --------------------------------------------------------*/ 362 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 363 * @{ 364 */ 365 #if defined(FMC_BANK1) 366 367 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 368 * @{ 369 */ 370 371 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 372 * @{ 373 */ 374 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) 375 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) 376 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) 377 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) 378 /** 379 * @} 380 */ 381 382 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 383 * @{ 384 */ 385 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) 386 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) 387 /** 388 * @} 389 */ 390 391 /** @defgroup FMC_Memory_Type FMC Memory Type 392 * @{ 393 */ 394 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) 395 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) 396 #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) 397 /** 398 * @} 399 */ 400 401 /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width 402 * @{ 403 */ 404 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 405 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) 406 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) 407 /** 408 * @} 409 */ 410 411 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 412 * @{ 413 */ 414 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) 415 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) 416 /** 417 * @} 418 */ 419 420 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 421 * @{ 422 */ 423 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) 424 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) 425 /** 426 * @} 427 */ 428 429 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 430 * @{ 431 */ 432 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) 433 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) 434 /** 435 * @} 436 */ 437 438 /** @defgroup FMC_Wait_Timing FMC Wait Timing 439 * @{ 440 */ 441 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) 442 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) 443 /** 444 * @} 445 */ 446 447 /** @defgroup FMC_Write_Operation FMC Write Operation 448 * @{ 449 */ 450 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) 451 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) 452 /** 453 * @} 454 */ 455 456 /** @defgroup FMC_Wait_Signal FMC Wait Signal 457 * @{ 458 */ 459 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) 460 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) 461 /** 462 * @} 463 */ 464 465 /** @defgroup FMC_Extended_Mode FMC Extended Mode 466 * @{ 467 */ 468 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) 469 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) 470 /** 471 * @} 472 */ 473 474 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 475 * @{ 476 */ 477 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) 478 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) 479 /** 480 * @} 481 */ 482 483 /** @defgroup FMC_Page_Size FMC Page Size 484 * @{ 485 */ 486 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) 487 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) 488 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) 489 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) 490 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) 491 /** 492 * @} 493 */ 494 495 /** @defgroup FMC_Write_Burst FMC Write Burst 496 * @{ 497 */ 498 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) 499 #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) 500 /** 501 * @} 502 */ 503 504 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 505 * @{ 506 */ 507 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) 508 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) 509 /** 510 * @} 511 */ 512 513 #if defined(FMC_BCR1_WFDIS) 514 /** @defgroup FMC_Write_FIFO FMC Write FIFO 515 * @{ 516 */ 517 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) 518 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) 519 /** 520 * @} 521 */ 522 #endif /* FMC_BCR1_WFDIS */ 523 524 /** @defgroup FMC_Access_Mode FMC Access Mode 525 * @{ 526 */ 527 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) 528 #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) 529 #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) 530 #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1)) 531 532 /** 533 * @} 534 */ 535 #if defined(FMC_BCRx_NBLSET) 536 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 537 * @{ 538 */ 539 #define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U) 540 #define FMC_NBL_SETUPTIME_1 ((uint32_t)FMC_BCRx_NBLSET_0) 541 #define FMC_NBL_SETUPTIME_2 ((uint32_t)FMC_BCRx_NBLSET_1) 542 #define FMC_NBL_SETUPTIME_3 ((uint32_t)(FMC_BCRx_NBLSET_0 | FMC_BCRx_NBLSET_1)) 543 /** 544 * @} 545 */ 546 #endif /* FMC_BCRx_NBLSET */ 547 548 /** 549 * @} 550 */ 551 #endif /* FMC_BANK1 */ 552 553 #if defined(FMC_BANK3) 554 555 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 556 * @{ 557 */ 558 /** @defgroup FMC_NAND_Bank FMC NAND Bank 559 * @{ 560 */ 561 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U) 562 /** 563 * @} 564 */ 565 566 /** @defgroup FMC_Wait_feature FMC Wait feature 567 * @{ 568 */ 569 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) 570 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) 571 /** 572 * @} 573 */ 574 575 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 576 * @{ 577 */ 578 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) 579 /** 580 * @} 581 */ 582 583 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 584 * @{ 585 */ 586 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 587 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) 588 /** 589 * @} 590 */ 591 592 /** @defgroup FMC_ECC FMC ECC 593 * @{ 594 */ 595 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) 596 #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) 597 /** 598 * @} 599 */ 600 601 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 602 * @{ 603 */ 604 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) 605 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) 606 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) 607 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) 608 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) 609 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) 610 /** 611 * @} 612 */ 613 614 /** 615 * @} 616 */ 617 #endif /* FMC_BANK3 */ 618 619 620 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 621 * @{ 622 */ 623 #if defined(FMC_BANK3) 624 #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) 625 #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) 626 #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) 627 #endif /* FMC_BANK3 */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 633 * @{ 634 */ 635 #if defined(FMC_BANK3) 636 #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) 637 #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) 638 #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) 639 #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) 640 #endif /* FMC_BANK3 */ 641 /** 642 * @} 643 */ 644 /** 645 * @} 646 */ 647 648 /** 649 * @} 650 */ 651 652 /* Private macro -------------------------------------------------------------*/ 653 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 654 * @{ 655 */ 656 657 #if defined(FMC_BANK1) 658 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 659 * @brief macros to handle NOR device enable/disable and read/write operations 660 * @{ 661 */ 662 663 /** 664 * @brief Enable the NORSRAM device access. 665 * @param __INSTANCE__ FMC_NORSRAM Instance 666 * @param __BANK__ FMC_NORSRAM Bank 667 * @retval None 668 */ 669 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN) 670 671 /** 672 * @brief Disable the NORSRAM device access. 673 * @param __INSTANCE__ FMC_NORSRAM Instance 674 * @param __BANK__ FMC_NORSRAM Bank 675 * @retval None 676 */ 677 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN) 678 679 /** 680 * @} 681 */ 682 #endif /* FMC_BANK1 */ 683 684 #if defined(FMC_BANK3) 685 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 686 * @brief macros to handle NAND device enable/disable 687 * @{ 688 */ 689 690 /** 691 * @brief Enable the NAND device access. 692 * @param __INSTANCE__ FMC_NAND Instance 693 * @retval None 694 */ 695 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 696 697 /** 698 * @brief Disable the NAND device access. 699 * @param __INSTANCE__ FMC_NAND Instance 700 * @retval None 701 */ 702 #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) 703 704 /** 705 * @} 706 */ 707 708 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 709 * @brief macros to handle NAND interrupts 710 * @{ 711 */ 712 713 /** 714 * @brief Enable the NAND device interrupt. 715 * @param __INSTANCE__ FMC_NAND instance 716 * @param __INTERRUPT__ FMC_NAND interrupt 717 * This parameter can be any combination of the following values: 718 * @arg FMC_IT_RISING_EDGE Interrupt rising edge. 719 * @arg FMC_IT_LEVEL Interrupt level. 720 * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. 721 * @retval None 722 */ 723 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 724 725 /** 726 * @brief Disable the NAND device interrupt. 727 * @param __INSTANCE__ FMC_NAND Instance 728 * @param __INTERRUPT__ FMC_NAND interrupt 729 * This parameter can be any combination of the following values: 730 * @arg FMC_IT_RISING_EDGE Interrupt rising edge. 731 * @arg FMC_IT_LEVEL Interrupt level. 732 * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. 733 * @retval None 734 */ 735 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 736 737 /** 738 * @brief Get flag status of the NAND device. 739 * @param __INSTANCE__ FMC_NAND Instance 740 * @param __BANK__ FMC_NAND Bank 741 * @param __FLAG__ FMC_NAND flag 742 * This parameter can be any combination of the following values: 743 * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. 744 * @arg FMC_FLAG_LEVEL Interrupt level edge flag. 745 * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. 746 * @arg FMC_FLAG_FEMPT FIFO empty flag. 747 * @retval The state of FLAG (SET or RESET). 748 */ 749 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 750 751 /** 752 * @brief Clear flag status of the NAND device. 753 * @param __INSTANCE__ FMC_NAND Instance 754 * @param __FLAG__ FMC_NAND flag 755 * This parameter can be any combination of the following values: 756 * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. 757 * @arg FMC_FLAG_LEVEL Interrupt level edge flag. 758 * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. 759 * @arg FMC_FLAG_FEMPT FIFO empty flag. 760 * @retval None 761 */ 762 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 763 764 /** 765 * @} 766 */ 767 #endif /* FMC_BANK3 */ 768 769 /** 770 * @} 771 */ 772 773 /** 774 * @} 775 */ 776 777 /* Private functions ---------------------------------------------------------*/ 778 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 779 * @{ 780 */ 781 782 #if defined(FMC_BANK1) 783 /** @defgroup FMC_LL_NORSRAM NOR SRAM 784 * @{ 785 */ 786 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 787 * @{ 788 */ 789 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); 790 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 791 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); 792 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 793 /** 794 * @} 795 */ 796 797 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 798 * @{ 799 */ 800 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 801 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 802 /** 803 * @} 804 */ 805 /** 806 * @} 807 */ 808 #endif /* FMC_BANK1 */ 809 810 #if defined(FMC_BANK3) 811 /** @defgroup FMC_LL_NAND NAND 812 * @{ 813 */ 814 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 815 * @{ 816 */ 817 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 818 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 819 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 820 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 821 /** 822 * @} 823 */ 824 825 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 826 * @{ 827 */ 828 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 829 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 830 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); 831 /** 832 * @} 833 */ 834 /** 835 * @} 836 */ 837 #endif /* FMC_BANK3 */ 838 839 840 841 /** 842 * @} 843 */ 844 845 /** 846 * @} 847 */ 848 849 /** 850 * @} 851 */ 852 853 #ifdef __cplusplus 854 } 855 #endif 856 857 #endif /* __STM32L4xx_LL_FMC_H */ 858 859 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 860
