1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_dsi.h 4 * @author MCD Application Team 5 * @brief Header file of DSI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_DSI_H 21 #define STM32U5xx_HAL_DSI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 #if defined(DSI) 31 32 /** @addtogroup STM32U5xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @defgroup DSI DSI 37 * @brief DSI HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup DSI_Exported_Types DSI Exported Types 43 * @{ 44 */ 45 /** 46 * @brief DSI Init Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control 51 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ 52 53 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division 54 The values 0 and 1 stop the TX_ESC clock generation */ 55 56 uint32_t NumberOfLanes; /*!< Number of lanes 57 This parameter can be any value of @ref DSI_Number_Of_Lanes */ 58 uint32_t PHYFrequencyRange; /*!< PHY Frequency Range 59 This parameter can be any value of @arg DSI_PHYFrequencyRange */ 60 61 uint32_t PHYLowPowerOffset; /*!< PHY Low Power Offset 62 This parameter can be any value of @arg PHYLowPowerOffset */ 63 64 } DSI_InitTypeDef; 65 66 /** 67 * @brief DSI PLL Clock structure definition 68 */ 69 typedef struct 70 { 71 uint32_t PLLNDIV; /*!< PLL Loop Division Factor 72 This parameter must be a value between 10 and 125 */ 73 74 uint32_t PLLIDF; /*!< PLL Input Division Factor 75 This parameter can be any value of @ref DSI_PLL_IDF */ 76 77 uint32_t PLLODF; /*!< PLL Output Division Factor 78 This parameter can be any value of @ref DSI_PLL_ODF */ 79 80 uint32_t PLLVCORange; /*!< PLLVCORange 81 This parameter can be any value of @ref DSI_DPHY_VCO_Frequency_RANGE */ 82 83 uint32_t PLLChargePump; /*!< PLLChargePump 84 This parameter can be any value of @ref DSI_PLL_Charge_Pump */ 85 86 uint32_t PLLTuning; /*!< PLLTuning 87 This parameter can be any value of @ref DSI_PLL_Tuning */ 88 89 90 } DSI_PLLInitTypeDef; 91 92 /** 93 * @brief DSI Video mode configuration 94 */ 95 typedef struct 96 { 97 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 98 99 uint32_t ColorCoding; /*!< Color coding for LTDC interface 100 This parameter can be any value of @ref DSI_Color_Coding */ 101 102 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using 103 18-bit configuration). 104 This parameter can be any value of @ref DSI_LooselyPacked */ 105 106 uint32_t Mode; /*!< Video mode type 107 This parameter can be any value of @ref DSI_Video_Mode_Type */ 108 109 uint32_t PacketSize; /*!< Video packet size */ 110 111 uint32_t NumberOfChunks; /*!< Number of chunks */ 112 113 uint32_t NullPacketSize; /*!< Null packet size */ 114 115 uint32_t HSPolarity; /*!< HSYNC pin polarity 116 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 117 118 uint32_t VSPolarity; /*!< VSYNC pin polarity 119 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 120 121 uint32_t DEPolarity; /*!< Data Enable pin polarity 122 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 123 124 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ 125 126 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ 127 128 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ 129 130 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ 131 132 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ 133 134 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ 135 136 uint32_t VerticalActive; /*!< Vertical active duration */ 137 138 uint32_t LPCommandEnable; /*!< Low-power command enable 139 This parameter can be any value of @ref DSI_LP_Command */ 140 141 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 142 can fit in a line during VSA, VBP and VFP regions */ 143 144 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 145 can fit in a line during VACT region */ 146 147 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable 148 This parameter can be any value of @ref DSI_LP_HFP */ 149 150 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable 151 This parameter can be any value of @ref DSI_LP_HBP */ 152 153 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable 154 This parameter can be any value of @ref DSI_LP_VACT */ 155 156 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable 157 This parameter can be any value of @ref DSI_LP_VFP */ 158 159 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable 160 This parameter can be any value of @ref DSI_LP_VBP */ 161 162 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable 163 This parameter can be any value of @ref DSI_LP_VSYNC */ 164 165 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable 166 This parameter can be any value of @ref DSI_FBTA_acknowledge */ 167 168 } DSI_VidCfgTypeDef; 169 170 /** 171 * @brief DSI Adapted command mode configuration 172 */ 173 typedef struct 174 { 175 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 176 177 uint32_t ColorCoding; /*!< Color coding for LTDC interface 178 This parameter can be any value of @ref DSI_Color_Coding */ 179 180 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in 181 pixels. This parameter can be any value between 0x00 and 0xFFFFU */ 182 183 uint32_t TearingEffectSource; /*!< Tearing effect source 184 This parameter can be any value of @ref DSI_TearingEffectSource */ 185 186 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity 187 This parameter can be any value of @ref DSI_TearingEffectPolarity */ 188 189 uint32_t HSPolarity; /*!< HSYNC pin polarity 190 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 191 192 uint32_t VSPolarity; /*!< VSYNC pin polarity 193 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 194 195 uint32_t DEPolarity; /*!< Data Enable pin polarity 196 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 197 198 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted 199 This parameter can be any value of @ref DSI_Vsync_Polarity */ 200 201 uint32_t AutomaticRefresh; /*!< Automatic refresh mode 202 This parameter can be any value of @ref DSI_AutomaticRefresh */ 203 204 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable 205 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ 206 207 } DSI_CmdCfgTypeDef; 208 209 /** 210 * @brief DSI command transmission mode configuration 211 */ 212 typedef struct 213 { 214 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission 215 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ 216 217 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission 218 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ 219 220 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission 221 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ 222 223 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission 224 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ 225 226 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission 227 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ 228 229 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission 230 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ 231 232 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission 233 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ 234 235 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission 236 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ 237 238 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission 239 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ 240 241 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission 242 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ 243 244 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission 245 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ 246 247 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission 248 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ 249 250 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable 251 This parameter can be any value of @ref DSI_AcknowledgeRequest */ 252 253 } DSI_LPCmdTypeDef; 254 255 /** 256 * @brief DSI PHY Timings definition 257 */ 258 typedef struct 259 { 260 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed 261 to low-power transmission */ 262 263 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power 264 to high-speed transmission */ 265 266 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed 267 to low-power transmission */ 268 269 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power 270 to high-speed transmission */ 271 272 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ 273 274 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the 275 Stop state */ 276 277 } DSI_PHY_TimerTypeDef; 278 279 /** 280 * @brief DSI HOST Timeouts definition 281 */ 282 typedef struct 283 { 284 uint32_t TimeoutCkdiv; /*!< Time-out clock division */ 285 286 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ 287 288 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ 289 290 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ 291 292 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ 293 294 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ 295 296 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode 297 This parameter can be any value of @ref DSI_HS_PrespMode */ 298 299 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ 300 301 uint32_t BTATimeout; /*!< BTA time-out */ 302 303 } DSI_HOST_TimeoutTypeDef; 304 305 /** 306 * @brief DSI States Structure definition 307 */ 308 typedef enum 309 { 310 HAL_DSI_STATE_RESET = 0x00U, 311 HAL_DSI_STATE_READY = 0x01U, 312 HAL_DSI_STATE_ERROR = 0x02U, 313 HAL_DSI_STATE_BUSY = 0x03U, 314 HAL_DSI_STATE_TIMEOUT = 0x04U 315 } HAL_DSI_StateTypeDef; 316 317 /** 318 * @brief DSI Handle Structure definition 319 */ 320 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 321 typedef struct __DSI_HandleTypeDef 322 #else 323 typedef struct 324 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 325 { 326 DSI_TypeDef *Instance; /*!< Register base address */ 327 DSI_InitTypeDef Init; /*!< DSI required parameters */ 328 HAL_LockTypeDef Lock; /*!< DSI peripheral status */ 329 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ 330 __IO uint32_t ErrorCode; /*!< DSI Error code */ 331 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ 332 333 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 334 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ 335 void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ 336 void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ 337 338 void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ 339 void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ 340 341 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 342 343 } DSI_HandleTypeDef; 344 345 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 346 /** 347 * @brief HAL DSI Callback ID enumeration definition 348 */ 349 typedef enum 350 { 351 HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ 352 HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ 353 354 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ 355 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ 356 HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ 357 358 } HAL_DSI_CallbackIDTypeDef; 359 360 /** 361 * @brief HAL DSI Callback pointer definition 362 */ 363 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ 364 365 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 366 /** 367 * @} 368 */ 369 370 /* Exported constants --------------------------------------------------------*/ 371 /** @defgroup DSI_Exported_Constants DSI Exported Constants 372 * @{ 373 */ 374 /** @defgroup DSI_DCS_Command DSI DCS Command 375 * @{ 376 */ 377 #define DSI_ENTER_IDLE_MODE 0x39U 378 #define DSI_ENTER_INVERT_MODE 0x21U 379 #define DSI_ENTER_NORMAL_MODE 0x13U 380 #define DSI_ENTER_PARTIAL_MODE 0x12U 381 #define DSI_ENTER_SLEEP_MODE 0x10U 382 #define DSI_EXIT_IDLE_MODE 0x38U 383 #define DSI_EXIT_INVERT_MODE 0x20U 384 #define DSI_EXIT_SLEEP_MODE 0x11U 385 #define DSI_GET_3D_CONTROL 0x3FU 386 #define DSI_GET_ADDRESS_MODE 0x0BU 387 #define DSI_GET_BLUE_CHANNEL 0x08U 388 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU 389 #define DSI_GET_DISPLAY_MODE 0x0DU 390 #define DSI_GET_GREEN_CHANNEL 0x07U 391 #define DSI_GET_PIXEL_FORMAT 0x0CU 392 #define DSI_GET_POWER_MODE 0x0AU 393 #define DSI_GET_RED_CHANNEL 0x06U 394 #define DSI_GET_SCANLINE 0x45U 395 #define DSI_GET_SIGNAL_MODE 0x0EU 396 #define DSI_NOP 0x00U 397 #define DSI_READ_DDB_CONTINUE 0xA8U 398 #define DSI_READ_DDB_START 0xA1U 399 #define DSI_READ_MEMORY_CONTINUE 0x3EU 400 #define DSI_READ_MEMORY_START 0x2EU 401 #define DSI_SET_3D_CONTROL 0x3DU 402 #define DSI_SET_ADDRESS_MODE 0x36U 403 #define DSI_SET_COLUMN_ADDRESS 0x2AU 404 #define DSI_SET_DISPLAY_OFF 0x28U 405 #define DSI_SET_DISPLAY_ON 0x29U 406 #define DSI_SET_GAMMA_CURVE 0x26U 407 #define DSI_SET_PAGE_ADDRESS 0x2BU 408 #define DSI_SET_PARTIAL_COLUMNS 0x31U 409 #define DSI_SET_PARTIAL_ROWS 0x30U 410 #define DSI_SET_PIXEL_FORMAT 0x3AU 411 #define DSI_SET_SCROLL_AREA 0x33U 412 #define DSI_SET_SCROLL_START 0x37U 413 #define DSI_SET_TEAR_OFF 0x34U 414 #define DSI_SET_TEAR_ON 0x35U 415 #define DSI_SET_TEAR_SCANLINE 0x44U 416 #define DSI_SET_VSYNC_TIMING 0x40U 417 #define DSI_SOFT_RESET 0x01U 418 #define DSI_WRITE_LUT 0x2DU 419 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU 420 #define DSI_WRITE_MEMORY_START 0x2CU 421 /** 422 * @} 423 */ 424 425 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type 426 * @{ 427 */ 428 #define DSI_VID_MODE_NB_PULSES 0U 429 #define DSI_VID_MODE_NB_EVENTS 1U 430 #define DSI_VID_MODE_BURST 2U 431 /** 432 * @} 433 */ 434 435 /** @defgroup DSI_Color_Mode DSI Color Mode 436 * @{ 437 */ 438 #define DSI_COLOR_MODE_FULL 0x00000000U 439 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM 440 /** 441 * @} 442 */ 443 444 /** @defgroup DSI_ShutDown DSI ShutDown 445 * @{ 446 */ 447 #define DSI_DISPLAY_ON 0x00000000U 448 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN 449 /** 450 * @} 451 */ 452 453 /** @defgroup DSI_LP_Command DSI LP Command 454 * @{ 455 */ 456 #define DSI_LP_COMMAND_DISABLE 0x00000000U 457 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE 458 /** 459 * @} 460 */ 461 462 /** @defgroup DSI_LP_HFP DSI LP HFP 463 * @{ 464 */ 465 #define DSI_LP_HFP_DISABLE 0x00000000U 466 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE 467 /** 468 * @} 469 */ 470 471 /** @defgroup DSI_LP_HBP DSI LP HBP 472 * @{ 473 */ 474 #define DSI_LP_HBP_DISABLE 0x00000000U 475 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE 476 /** 477 * @} 478 */ 479 480 /** @defgroup DSI_LP_VACT DSI LP VACT 481 * @{ 482 */ 483 #define DSI_LP_VACT_DISABLE 0x00000000U 484 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE 485 /** 486 * @} 487 */ 488 489 /** @defgroup DSI_LP_VFP DSI LP VFP 490 * @{ 491 */ 492 #define DSI_LP_VFP_DISABLE 0x00000000U 493 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE 494 /** 495 * @} 496 */ 497 498 /** @defgroup DSI_LP_VBP DSI LP VBP 499 * @{ 500 */ 501 #define DSI_LP_VBP_DISABLE 0x00000000U 502 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE 503 /** 504 * @} 505 */ 506 507 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC 508 * @{ 509 */ 510 #define DSI_LP_VSYNC_DISABLE 0x00000000U 511 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE 512 /** 513 * @} 514 */ 515 516 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge 517 * @{ 518 */ 519 #define DSI_FBTAA_DISABLE 0x00000000U 520 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE 521 /** 522 * @} 523 */ 524 525 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source 526 * @{ 527 */ 528 #define DSI_TE_DSILINK 0x00000000U 529 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC 530 /** 531 * @} 532 */ 533 534 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity 535 * @{ 536 */ 537 #define DSI_TE_RISING_EDGE 0x00000000U 538 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL 539 /** 540 * @} 541 */ 542 543 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity 544 * @{ 545 */ 546 #define DSI_VSYNC_FALLING 0x00000000U 547 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL 548 /** 549 * @} 550 */ 551 552 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh 553 * @{ 554 */ 555 #define DSI_AR_DISABLE 0x00000000U 556 #define DSI_AR_ENABLE DSI_WCFGR_AR 557 /** 558 * @} 559 */ 560 561 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request 562 * @{ 563 */ 564 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U 565 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE 566 /** 567 * @} 568 */ 569 570 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request 571 * @{ 572 */ 573 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U 574 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE 575 /** 576 * @} 577 */ 578 579 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP 580 * @{ 581 */ 582 #define DSI_LP_GSW0P_DISABLE 0x00000000U 583 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX 584 /** 585 * @} 586 */ 587 588 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP 589 * @{ 590 */ 591 #define DSI_LP_GSW1P_DISABLE 0x00000000U 592 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX 593 /** 594 * @} 595 */ 596 597 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP 598 * @{ 599 */ 600 #define DSI_LP_GSW2P_DISABLE 0x00000000U 601 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX 602 /** 603 * @} 604 */ 605 606 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP 607 * @{ 608 */ 609 #define DSI_LP_GSR0P_DISABLE 0x00000000U 610 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX 611 /** 612 * @} 613 */ 614 615 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP 616 * @{ 617 */ 618 #define DSI_LP_GSR1P_DISABLE 0x00000000U 619 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX 620 /** 621 * @} 622 */ 623 624 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP 625 * @{ 626 */ 627 #define DSI_LP_GSR2P_DISABLE 0x00000000U 628 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX 629 /** 630 * @} 631 */ 632 633 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite 634 * @{ 635 */ 636 #define DSI_LP_GLW_DISABLE 0x00000000U 637 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX 638 /** 639 * @} 640 */ 641 642 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP 643 * @{ 644 */ 645 #define DSI_LP_DSW0P_DISABLE 0x00000000U 646 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX 647 /** 648 * @} 649 */ 650 651 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP 652 * @{ 653 */ 654 #define DSI_LP_DSW1P_DISABLE 0x00000000U 655 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX 656 /** 657 * @} 658 */ 659 660 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP 661 * @{ 662 */ 663 #define DSI_LP_DSR0P_DISABLE 0x00000000U 664 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX 665 /** 666 * @} 667 */ 668 669 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write 670 * @{ 671 */ 672 #define DSI_LP_DLW_DISABLE 0x00000000U 673 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX 674 /** 675 * @} 676 */ 677 678 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet 679 * @{ 680 */ 681 #define DSI_LP_MRDP_DISABLE 0x00000000U 682 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS 683 /** 684 * @} 685 */ 686 687 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode 688 * @{ 689 */ 690 #define DSI_HS_PM_DISABLE 0x00000000U 691 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM 692 /** 693 * @} 694 */ 695 696 697 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control 698 * @{ 699 */ 700 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U 701 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR 702 /** 703 * @} 704 */ 705 706 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes 707 * @{ 708 */ 709 #define DSI_ONE_DATA_LANE 0U 710 #define DSI_TWO_DATA_LANES 1U 711 /** 712 * @} 713 */ 714 715 /** @defgroup DSI_FlowControl DSI Flow Control 716 * @{ 717 */ 718 #define DSI_FLOW_CONTROL_EOTP_TX_LP DSI_PCR_ETTXLPE 719 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE 720 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE 721 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE 722 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE 723 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE 724 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ 725 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ 726 DSI_FLOW_CONTROL_EOTP_TX | DSI_FLOW_CONTROL_EOTP_TX_LP) 727 /** 728 * @} 729 */ 730 731 /** @defgroup DSI_Color_Coding DSI Color Coding 732 * @{ 733 */ 734 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ 735 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ 736 #define DSI_RGB888 0x00000005U 737 /** 738 * @} 739 */ 740 741 /** @defgroup DSI_LooselyPacked DSI Loosely Packed 742 * @{ 743 */ 744 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE 745 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U 746 /** 747 * @} 748 */ 749 750 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity 751 * @{ 752 */ 753 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U 754 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP 755 /** 756 * @} 757 */ 758 759 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity 760 * @{ 761 */ 762 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U 763 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP 764 /** 765 * @} 766 */ 767 768 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity 769 * @{ 770 */ 771 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U 772 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP 773 /** 774 * @} 775 */ 776 777 /** @defgroup DSI_PLL_IDF DSI PLL IDF 778 * @{ 779 */ 780 #define DSI_PLL_IN_DIV1 0x00000001U 781 #define DSI_PLL_IN_DIV2 0x00000002U 782 #define DSI_PLL_IN_DIV3 0x00000003U 783 #define DSI_PLL_IN_DIV4 0x00000004U 784 #define DSI_PLL_IN_DIV5 0x00000005U 785 #define DSI_PLL_IN_DIV6 0x00000006U 786 #define DSI_PLL_IN_DIV7 0x00000007U 787 /** 788 * @} 789 */ 790 791 /** @defgroup DSI_PLL_ODF DSI PLL ODF 792 * @{ 793 */ 794 #define DSI_PLL_OUT_DIV1 0x00000001U 795 #define DSI_PLL_OUT_DIV2 0x00000002U 796 #define DSI_PLL_OUT_DIV3 0x00000003U 797 #define DSI_PLL_OUT_DIV4 0x00000004U 798 #define DSI_PLL_OUT_DIV5 0x00000005U 799 #define DSI_PLL_OUT_DIV6 0x00000006U 800 #define DSI_PLL_OUT_DIV7 0x00000007U 801 #define DSI_PLL_OUT_DIV8 0x00000008U 802 #define DSI_PLL_OUT_DIV9 0x00000009U 803 /** 804 * @} 805 */ 806 807 /** @defgroup DSI_Flags DSI Flags 808 * @{ 809 */ 810 #define DSI_FLAG_TE DSI_WISR_TEIF 811 #define DSI_FLAG_ER DSI_WISR_ERIF 812 #define DSI_FLAG_BUSY DSI_WISR_BUSY 813 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS 814 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF 815 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF 816 /** 817 * @} 818 */ 819 820 /** @defgroup DSI_Interrupts DSI Interrupts 821 * @{ 822 */ 823 #define DSI_IT_TE DSI_WIER_TEIE 824 #define DSI_IT_ER DSI_WIER_ERIE 825 #define DSI_IT_PLLL DSI_WIER_PLLLIE 826 #define DSI_IT_PLLU DSI_WIER_PLLUIE 827 /** 828 * @} 829 */ 830 831 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type 832 * @{ 833 */ 834 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ 835 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ 836 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ 837 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ 838 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ 839 /** 840 * @} 841 */ 842 843 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type 844 * @{ 845 */ 846 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ 847 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ 848 /** 849 * @} 850 */ 851 852 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type 853 * @{ 854 */ 855 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ 856 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ 857 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ 858 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ 859 /** 860 * @} 861 */ 862 863 /** @defgroup DSI_Error_Data_Type DSI Error Data Type 864 * @{ 865 */ 866 #define HAL_DSI_ERROR_NONE 0U 867 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */ 868 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ 869 #define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */ 870 #define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */ 871 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ 872 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ 873 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ 874 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ 875 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ 876 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ 877 #define HAL_DSI_ERROR_PBU 0x00000400U /*!< Payload Buffer Underflow error */ 878 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 879 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000800U /*!< DSI Invalid Callback error */ 880 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 881 /** 882 * @} 883 */ 884 885 /** @defgroup DSI_Lane_Group DSI Lane Group 886 * @{ 887 */ 888 #define DSI_CLOCK_LANE 0x00000000U 889 #define DSI_DATA_LANES 0x00000001U 890 /** 891 * @} 892 */ 893 894 895 /** @defgroup DSI_CustomLane DSI CustomLane 896 * @{ 897 */ 898 #define DSI_SWAP_LANE_PINS 0x00000000U 899 /** 900 * @} 901 */ 902 903 /** @defgroup DSI_Lane_Select DSI Lane Select 904 * @{ 905 */ 906 #define DSI_CLK_LANE 0x00000000U 907 #define DSI_DATA_LANE0 0x00000001U 908 #define DSI_DATA_LANE1 0x00000002U 909 /** 910 * @} 911 */ 912 913 914 /** @defgroup DSI_DPHY_VCO_Frequency_RANGE DSI DPHY VCO Frequency Range 915 * @{ 916 */ 917 #define DSI_DPHY_VCO_FRANGE_500MHZ_800MHZ 0x00000000U /*!< 500-800 MHz */ 918 #define DSI_DPHY_VCO_FRANGE_800MHZ_1GHZ 0x00000001U /*!< 800-1000 MHz */ 919 /** 920 * @} 921 */ 922 923 924 /** @defgroup DSI_PHYFrequencyRange DSI DPHY Frequency Range 925 * @{ 926 */ 927 #define DSI_DPHY_FRANGE_80MHZ_100MHZ 0x00000000U /*!< 80-100 MHz */ 928 #define DSI_DPHY_FRANGE_100MHZ_120MHZ 0x00000001U /*!< 100-120 MHz */ 929 #define DSI_DPHY_FRANGE_120MHZ_160MHZ 0x00000002U /*!< 120-160 MHz */ 930 #define DSI_DPHY_FRANGE_160MHZ_200MHZ 0x00000003U /*!< 160-200 MHz */ 931 #define DSI_DPHY_FRANGE_200MHZ_240MHZ 0x00000004U /*!< 200-240 MHz */ 932 #define DSI_DPHY_FRANGE_240MHZ_320MHZ 0x00000005U /*!< 240-320 MHz */ 933 #define DSI_DPHY_FRANGE_320MHZ_390MHZ 0x00000006U /*!< 320-390 MHz */ 934 #define DSI_DPHY_FRANGE_390MHZ_450MHZ 0x00000007U /*!< 390-450 MHz */ 935 #define DSI_DPHY_FRANGE_450MHZ_510MHZ 0x00000008U /*!< 450-510 MHz */ 936 937 /** 938 * @} 939 */ 940 941 /** @defgroup DSI_DPHY_Slew_Rate DSI D-PHY Slew rate 942 * @{ 943 */ 944 #define DSI_DPHY_SLEW_HS_TX_SPEED 0x0000000EU /*!< 80-750Mbits/s */ 945 /** 946 * @} 947 */ 948 949 /** @defgroup DSI_HS_PREPARE_Offset DSI HS Prepare Offset 950 * @{ 951 */ 952 #define DSI_HS_PREPARE_OFFSET0 0x00000000U /*!< 100-120 & 120-160 & 240-320 MHz */ 953 #define DSI_HS_PREPARE_OFFSET1 0x00000001U /*!< 80-100 & 160-200 & 200-240 & 320-390 MHz */ 954 #define DSI_HS_PREPARE_OFFSET2 0x00000002U /*!< 390-450 & 450-510 MHz */ 955 /** 956 * @} 957 */ 958 959 /** @defgroup DSI_PHYLowPowerOffset DSI PHY Low Power Offset 960 * @{ 961 */ 962 #define PHY_LP_OFFSSET_0_CLKP 0x00000000U 963 #define PHY_LP_OFFSSET_1_CLKP 0x00000001U 964 #define PHY_LP_OFFSSET_2_CLKP 0x00000002U 965 #define PHY_LP_OFFSSET_3_CLKP 0x00000003U 966 #define PHY_LP_OFFSSET_4_CLKP 0x00000004U 967 #define PHY_LP_OFFSSET_5_CLKP 0x00000005U 968 #define PHY_LP_OFFSSET_6_CLKP 0x00000006U 969 #define PHY_LP_OFFSSET_7_CLKP 0x00000007U 970 #define PHY_LP_OFFSSET_MINUS_1_CLKP 0x00000008U 971 #define PHY_LP_OFFSSET_MINUS_2_CLKP 0x00000009U 972 #define PHY_LP_OFFSSET_MINUS_3_CLKP 0x0000000AU 973 #define PHY_LP_OFFSSET_MINUS_4_CLKP 0x0000000BU 974 #define PHY_LP_OFFSSET_MINUS_5_CLKP 0x0000000CU 975 #define PHY_LP_OFFSSET_MINUS_6_CLKP 0x0000000DU 976 #define PHY_LP_OFFSSET_MINUS_7_CLKP 0x0000000EU 977 #define PHY_LP_OFFSSET_MINUS_8_CLKP 0x0000000FU 978 /** 979 * @} 980 */ 981 982 983 /** @defgroup DSI_PLL_Tuning DSI PLL Tuning 984 * @{ 985 */ 986 #define DSI_PLL_LOOP_FILTER_2000HZ_4400HZ 0x00000000U /*!< 2.0 to 4.4 MHz */ 987 #define DSI_PLL_LOOP_FILTER_4400HZ_30900HZ 0x00000001U /*!< 4.4 to 30.9 MHz */ 988 #define DSI_PLL_LOOP_FILTER_30900HZ_50000HZ 0x00000002U /*!< 30.9 to 50 MHz */ 989 990 /** 991 * @} 992 */ 993 994 /** @defgroup DSI_PLL_Charge_Pump DSI PLL Charge pump 995 * @{ 996 */ 997 #define DSI_PLL_CHARGE_PUMP_2000HZ_4400HZ 0x00000000U /*!< 2.0 to 4.4 MHz */ 998 #define DSI_PLL_CHARGE_PUMP_4400HZ_14100HZ 0x00000001U /*!< 4.4 to 14.1 MHz */ 999 #define DSI_PLL_CHARGE_PUMP_14100HZ_30900HZ 0x00000000U /*!< 14.1 to 30.9 MHz */ 1000 #define DSI_PLL_CHARGE_PUMP_30900HZ_45700HZ 0x00000003U /*!< 30.9 to 45.7 MHz */ 1001 #define DSI_PLL_CHARGE_PUMP_45700HZ_50000HZ 0x00000002U /*!< 45.7 to 50 MHz */ 1002 /** 1003 * @} 1004 */ 1005 1006 /** 1007 * @} 1008 */ 1009 1010 /* Exported macros -----------------------------------------------------------*/ 1011 /** @defgroup DSI_Exported_Macros DSI Exported Macros 1012 * @{ 1013 */ 1014 1015 /** 1016 * @brief Reset DSI handle state. 1017 * @param __HANDLE__ DSI handle 1018 * @retval None 1019 */ 1020 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 1021 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1022 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ 1023 (__HANDLE__)->MspInitCallback = NULL; \ 1024 (__HANDLE__)->MspDeInitCallback = NULL; \ 1025 } while(0) 1026 #else 1027 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) 1028 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ 1029 1030 /** 1031 * @brief Enables the DSI host. 1032 * @param __HANDLE__ DSI handle 1033 * @retval None. 1034 */ 1035 #define __HAL_DSI_ENABLE(__HANDLE__) do { \ 1036 __IO uint32_t tmpreg = 0x00U; \ 1037 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 1038 /* Delay after an DSI Host enabling */ \ 1039 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 1040 UNUSED(tmpreg); \ 1041 } while(0U) 1042 1043 /** 1044 * @brief Disables the DSI host. 1045 * @param __HANDLE__ DSI handle 1046 * @retval None. 1047 */ 1048 #define __HAL_DSI_DISABLE(__HANDLE__) do { \ 1049 __IO uint32_t tmpreg = 0x00U; \ 1050 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 1051 /* Delay after an DSI Host disabling */ \ 1052 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 1053 UNUSED(tmpreg); \ 1054 } while(0U) 1055 1056 /** 1057 * @brief Enables the DSI wrapper. 1058 * @param __HANDLE__ DSI handle 1059 * @retval None. 1060 */ 1061 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ 1062 __IO uint32_t tmpreg = 0x00U; \ 1063 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 1064 /* Delay after an DSI wrapper enabling */ \ 1065 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 1066 UNUSED(tmpreg); \ 1067 } while(0U) 1068 1069 /** 1070 * @brief Disable the DSI wrapper. 1071 * @param __HANDLE__ DSI handle 1072 * @retval None. 1073 */ 1074 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ 1075 __IO uint32_t tmpreg = 0x00U; \ 1076 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 1077 /* Delay after an DSI wrapper disabling*/ \ 1078 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 1079 UNUSED(tmpreg); \ 1080 } while(0U) 1081 1082 /** 1083 * @brief Enables the DSI PLL. 1084 * @param __HANDLE__ DSI handle 1085 * @retval None. 1086 */ 1087 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ 1088 __IO uint32_t tmpreg = 0x00U; \ 1089 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1090 /* Delay after an DSI PLL enabling */ \ 1091 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1092 UNUSED(tmpreg); \ 1093 } while(0U) 1094 1095 /** 1096 * @brief Disables the DSI PLL. 1097 * @param __HANDLE__ DSI handle 1098 * @retval None. 1099 */ 1100 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ 1101 __IO uint32_t tmpreg = 0x00U; \ 1102 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1103 /* Delay after an DSI PLL disabling */ \ 1104 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1105 UNUSED(tmpreg); \ 1106 } while(0U) 1107 1108 1109 /** 1110 * @brief Get the DSI pending flags. 1111 * @param __HANDLE__ DSI handle. 1112 * @param __FLAG__ Get the specified flag. 1113 * This parameter can be any combination of the following values: 1114 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 1115 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 1116 * @arg DSI_FLAG_BUSY : Busy Flag 1117 * @arg DSI_FLAG_PLLLS: PLL Lock Status 1118 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 1119 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 1120 * @arg DSI_FLAG_RRS : Regulator Ready Flag 1121 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 1122 * @retval The state of FLAG (SET or RESET). 1123 */ 1124 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) 1125 1126 /** 1127 * @brief Clears the DSI pending flags. 1128 * @param __HANDLE__ DSI handle. 1129 * @param __FLAG__ specifies the flag to clear. 1130 * This parameter can be any combination of the following values: 1131 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 1132 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 1133 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 1134 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 1135 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 1136 * @retval None 1137 */ 1138 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) 1139 1140 /** 1141 * @brief Enables the specified DSI interrupts. 1142 * @param __HANDLE__ DSI handle. 1143 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. 1144 * This parameter can be any combination of the following values: 1145 * @arg DSI_IT_TE : Tearing Effect Interrupt 1146 * @arg DSI_IT_ER : End of Refresh Interrupt 1147 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1148 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1149 * @arg DSI_IT_RR : Regulator Ready Interrupt 1150 * @retval None 1151 */ 1152 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) 1153 1154 /** 1155 * @brief Disables the specified DSI interrupts. 1156 * @param __HANDLE__ DSI handle 1157 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. 1158 * This parameter can be any combination of the following values: 1159 * @arg DSI_IT_TE : Tearing Effect Interrupt 1160 * @arg DSI_IT_ER : End of Refresh Interrupt 1161 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1162 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1163 * @arg DSI_IT_RR : Regulator Ready Interrupt 1164 * @retval None 1165 */ 1166 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) 1167 1168 /** 1169 * @brief Checks whether the specified DSI interrupt source is enabled or not. 1170 * @param __HANDLE__ DSI handle 1171 * @param __INTERRUPT__ specifies the DSI interrupt source to check. 1172 * This parameter can be one of the following values: 1173 * @arg DSI_IT_TE : Tearing Effect Interrupt 1174 * @arg DSI_IT_ER : End of Refresh Interrupt 1175 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1176 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1177 * @arg DSI_IT_RR : Regulator Ready Interrupt 1178 * @retval The state of INTERRUPT (SET or RESET). 1179 */ 1180 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) 1181 1182 /** 1183 * @} 1184 */ 1185 1186 /* Exported functions --------------------------------------------------------*/ 1187 /** @defgroup DSI_Exported_Functions DSI Exported Functions 1188 * @{ 1189 */ 1190 /** @defgroup DSI_Group1 Initialization and Configuration functions 1191 * @brief Initialization and Configuration functions 1192 * @{ 1193 */ 1194 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); 1195 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); 1196 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); 1197 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); 1198 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); 1199 /* Callbacks Register/UnRegister functions ***********************************/ 1200 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 1201 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, 1202 pDSI_CallbackTypeDef pCallback); 1203 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); 1204 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 1205 /** 1206 * @} 1207 */ 1208 1209 /** @defgroup DSI_Group2 IO operation functions 1210 * @brief IO operation functions 1211 * @{ 1212 */ 1213 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); 1214 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); 1215 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); 1216 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); 1217 /** 1218 * @} 1219 */ 1220 1221 /** @defgroup DSI_Group3 Peripheral Control functions 1222 * @brief Peripheral Control functions 1223 * @{ 1224 */ 1225 HAL_StatusTypeDef HAL_DSI_SetGenericVCIDRX(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelIdRx); 1226 HAL_StatusTypeDef HAL_DSI_SetGenericVCIDTX(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelIdTx); 1227 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); 1228 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); 1229 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); 1230 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); 1231 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); 1232 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); 1233 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); 1234 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); 1235 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); 1236 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); 1237 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); 1238 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); 1239 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 1240 uint32_t ChannelID, 1241 uint32_t Mode, 1242 uint32_t Param1, 1243 uint32_t Param2); 1244 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 1245 uint32_t ChannelID, 1246 uint32_t Mode, 1247 uint32_t NbParams, 1248 uint32_t Param1, 1249 const uint8_t *ParametersTable); 1250 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 1251 uint32_t ChannelNbr, 1252 uint8_t *Array, 1253 uint32_t Size, 1254 uint32_t Mode, 1255 uint32_t DCSCmd, 1256 uint8_t *ParametersTable); 1257 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); 1258 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); 1259 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); 1260 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); 1261 1262 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); 1263 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); 1264 1265 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, 1266 FunctionalState State); 1267 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); 1268 1269 /** 1270 * @} 1271 */ 1272 1273 /** @defgroup DSI_Group4 Peripheral State and Errors functions 1274 * @brief Peripheral State and Errors functions 1275 * @{ 1276 */ 1277 uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi); 1278 HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi); 1279 1280 /** 1281 * @} 1282 */ 1283 1284 /** 1285 * @} 1286 */ 1287 1288 /* Private types -------------------------------------------------------------*/ 1289 /* Private defines -----------------------------------------------------------*/ 1290 /* Private variables ---------------------------------------------------------*/ 1291 /* Private constants ---------------------------------------------------------*/ 1292 /** @defgroup DSI_Private_Constants DSI Private Constants 1293 * @{ 1294 */ 1295 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ 1296 /** 1297 * @} 1298 */ 1299 1300 /* Private macros ------------------------------------------------------------*/ 1301 /** @defgroup DSI_Private_Macros DSI Private Macros 1302 * @{ 1303 */ 1304 #define IS_DSI_PLL_NDIV(NDIV) ((NDIV) <= 511U) 1305 #define IS_DSI_PLL_IDF(IDF) ((IDF) <= 511U) 1306 #define IS_DSI_PLL_ODF(ODF) ((ODF) <= 511U) 1307 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\ 1308 || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) 1309 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\ 1310 || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) 1311 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) 1312 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) 1313 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\ 1314 || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) 1315 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ 1316 || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) 1317 #define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\ 1318 || ((Vsync) == DSI_VSYNC_ACTIVE_LOW)) 1319 #define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\ 1320 || ((Hsync) == DSI_HSYNC_ACTIVE_LOW)) 1321 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ 1322 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ 1323 ((VideoModeType) == DSI_VID_MODE_BURST)) 1324 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\ 1325 || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) 1326 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) 1327 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\ 1328 || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) 1329 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) 1330 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) 1331 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\ 1332 || ((LPVActive) == DSI_LP_VACT_ENABLE)) 1333 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) 1334 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) 1335 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\ 1336 || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) 1337 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\ 1338 || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) 1339 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) 1340 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\ 1341 || ((TEPolarity) == DSI_TE_FALLING_EDGE)) 1342 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\ 1343 || ((AutomaticRefresh) == DSI_AR_ENABLE)) 1344 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\ 1345 || ((VSPolarity) == DSI_VSYNC_RISING)) 1346 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\ 1347 || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) 1348 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\ 1349 || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) 1350 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\ 1351 || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) 1352 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\ 1353 || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) 1354 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\ 1355 || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) 1356 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\ 1357 || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) 1358 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\ 1359 || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) 1360 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\ 1361 || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) 1362 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\ 1363 || ((LP_GLW) == DSI_LP_GLW_ENABLE)) 1364 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\ 1365 || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) 1366 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\ 1367 || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) 1368 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\ 1369 || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) 1370 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\ 1371 || ((LP_DLW) == DSI_LP_DLW_ENABLE)) 1372 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\ 1373 || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) 1374 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ 1375 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ 1376 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ 1377 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ 1378 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) 1379 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ 1380 ((MODE) == DSI_GEN_LONG_PKT_WRITE)) 1381 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ 1382 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ 1383 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ 1384 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) 1385 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) 1386 #define IS_DSI_CUSTOM_LANE(CustomLane) ((CustomLane) == DSI_SWAP_LANE_PINS) 1387 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \ 1388 ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) 1389 1390 #define IS_DSI_DPHY_VCO_FREQUENCY_RANGE(VCOFreqRange) (((VCOFreqRange) == DSI_DPHY_VCO_FRANGE_500MHZ_800MHZ) ||\ 1391 ((VCOFreqRange) == DSI_DPHY_VCO_FRANGE_800MHZ_1GHZ)) 1392 1393 #define IS_DSI_DPHY_BAND_CTL_FRANGE(PHYFrequencyRange) (((PHYFrequencyRange) == DSI_DPHY_FRANGE_80MHZ_100MHZ) ||\ 1394 ((PHYFrequencyRange) == DSI_DPHY_FRANGE_100MHZ_120MHZ) ||\ 1395 ((PHYFrequencyRange) == DSI_DPHY_FRANGE_120MHZ_160MHZ) ||\ 1396 ((PHYFrequencyRange) == DSI_DPHY_FRANGE_160MHZ_200MHZ) ||\ 1397 ((PHYFrequencyRange) == DSI_DPHY_FRANGE_200MHZ_240MHZ) ||\ 1398 ((PHYFrequencyRange) == DSI_DPHY_FRANGE_240MHZ_320MHZ) ||\ 1399 ((PHYFrequencyRange) == DSI_DPHY_FRANGE_320MHZ_390MHZ) ||\ 1400 ((PHYFrequencyRange) == DSI_DPHY_FRANGE_390MHZ_450MHZ) ||\ 1401 ((PHYFrequencyRange) == DSI_DPHY_FRANGE_450MHZ_510MHZ)) 1402 #define IS_DSI_DPHY_LOW_POWER_OFFSET(PHYLowPowerOffset)(((PHYLowPowerOffset) == PHY_LP_OFFSSET_0_CLKP) ||\ 1403 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_1_CLKP) ||\ 1404 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_2_CLKP) ||\ 1405 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_3_CLKP) ||\ 1406 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_4_CLKP) ||\ 1407 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_5_CLKP) ||\ 1408 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_6_CLKP) ||\ 1409 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_7_CLKP) ||\ 1410 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_1_CLKP) ||\ 1411 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_2_CLKP) ||\ 1412 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_3_CLKP) ||\ 1413 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_4_CLKP) ||\ 1414 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_5_CLKP) ||\ 1415 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_6_CLKP) ||\ 1416 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_7_CLKP) ||\ 1417 ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_8_CLKP)) 1418 #define IS_DSI_PLL_TUNING(PllTuning) (((PllTuning) == DSI_PLL_LOOP_FILTER_2000HZ_4400HZ) || \ 1419 ((PllTuning) == DSI_PLL_LOOP_FILTER_4400HZ_30900HZ) || \ 1420 ((PllTuning) == DSI_PLL_LOOP_FILTER_30900HZ_50000HZ)) 1421 1422 1423 #define IS_DSI_PLL_CHARGEPUMP(PllChargePump) (((PllChargePump) == DSI_PLL_CHARGE_PUMP_2000HZ_4400HZ) || \ 1424 ((PllChargePump) == DSI_PLL_CHARGE_PUMP_4400HZ_14100HZ) || \ 1425 ((PllChargePump) == DSI_PLL_CHARGE_PUMP_14100HZ_30900HZ) || \ 1426 ((PllChargePump) == DSI_PLL_CHARGE_PUMP_30900HZ_45700HZ) || \ 1427 ((PllChargePump) == DSI_PLL_CHARGE_PUMP_45700HZ_50000HZ)) 1428 /** 1429 * @} 1430 */ 1431 1432 /** 1433 * @} 1434 */ 1435 1436 /** 1437 * @} 1438 */ 1439 #endif /* DSI */ 1440 1441 #ifdef __cplusplus 1442 } 1443 #endif 1444 1445 #endif /* STM32U5xx_HAL_DSI_H */ 1446
