1 /** 2 ****************************************************************************** 3 * @file stm32h7rsxx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 * 8 ****************************************************************************** 9 * @attention 10 * 11 * Copyright (c) 2022 STMicroelectronics. 12 * All rights reserved. 13 * 14 * This software is licensed under terms that can be found in the LICENSE file 15 * in the root directory of this software component. 16 * If no LICENSE file comes with this software, it is provided AS-IS. 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32H7RSxx_HAL_H 23 #define STM32H7RSxx_HAL_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32h7rsxx_hal_conf.h" 31 32 /** @addtogroup STM32H7RSxx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup HAL_TICK_FREQ Tick Frequency 42 * @{ 43 */ 44 /** 45 * @brief HAL Tick frequency 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /* Exported constants --------------------------------------------------------*/ 59 /** @defgroup REV_ID device revision ID 60 * @{ 61 */ 62 #define REV_ID_A 0x1003U /*!< STM32H7Rx/Sx rev.A */ 63 /** 64 * @} 65 */ 66 67 /** @defgroup HAL_Exported_Constants HAL Exported Constants 68 * @{ 69 */ 70 /** 71 * @brief STM32H7RSxx HAL Driver version number 72 */ 73 #define STM32H7RSXX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 74 #define STM32H7RSXX_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ 75 #define STM32H7RSXX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ 76 #define STM32H7RSXX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 77 #define STM32H7RSXX_HAL_VERSION ((STM32H7RSXX_HAL_VERSION_MAIN << 24U)\ 78 |(STM32H7RSXX_HAL_VERSION_SUB1 << 16U)\ 79 |(STM32H7RSXX_HAL_VERSION_SUB2 << 8U )\ 80 |(STM32H7RSXX_HAL_VERSION_RC)) 81 /** 82 * @} 83 */ 84 85 /** @defgroup SBS_Exported_Constants SBS Exported Constants 86 * @{ 87 */ 88 89 /** @defgroup SBS_HDPL_Value HDPL Value 90 * @{ 91 */ 92 #define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ 93 #define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */ 94 #define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */ 95 #define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */ 96 /** 97 * @} 98 */ 99 100 /** @defgroup SBS_Timer_Break_Inputs Timer Break Inputs 101 * @{ 102 */ 103 #define SBS_TIMER_BREAK_LOCK_PVD SBS_BKLOCKR_PVD_BL /*!< PVD break lock */ 104 #define SBS_TIMER_BREAK_LOCK_FLASH SBS_BKLOCKR_FLASHECC_BL /*!< FLASH ECC error break lock */ 105 #define SBS_TIMER_BREAK_LOCK_CORE SBS_BKLOCKR_CM7LCKUP_BL /*!< Cortex-M7 lockup break lock */ 106 #define SBS_TIMER_BREAK_LOCK_BKPRAM SBS_BKLOCKR_BKRAMECC_BL /*!< Backup RAM ECC error break lock */ 107 #define SBS_TIMER_BREAK_LOCK_DTCM SBS_BKLOCKR_DTCMECC_BL /*!< DTCM ECC error break lock */ 108 #define SBS_TIMER_BREAK_LOCK_ITCM SBS_BKLOCKR_ITCMECC_BL /*!< ITCM ECC error break lock */ 109 #define SBS_TIMER_BREAK_LOCK_AXISRAM3 SBS_BKLOCKR_ARAM3ECC_BL /*!< AXISRAM3 ECC error break lock */ 110 #define SBS_TIMER_BREAK_LOCK_AXISRAM1 SBS_BKLOCKR_ARAM1ECC_BL /*!< AXISRAM1 ECC error break lock */ 111 /** 112 * @} 113 */ 114 115 /** @defgroup SBS_FPU_Interrupts FPU Interrupts 116 * @{ 117 */ 118 #define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 119 #define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 120 #define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 121 #define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 122 #define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 123 #define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 124 /** 125 * @} 126 */ 127 128 /** @defgroup SBS_Compensation_Cell_Selection Compensation Cell Selection 129 * @{ 130 */ 131 #define SBS_IO_ANALOG_CELL SBS_CCCSR_COMP_EN /*!< Compensation cell for the I/O analog switches */ 132 #define SBS_IO_XSPI1_CELL SBS_CCCSR_XSPI1_COMP_EN /*!< Compensation cell for the I/O of the XSPI1 */ 133 #define SBS_IO_XSPI2_CELL SBS_CCCSR_XSPI2_COMP_EN /*!< Compensation cell for the I/O of the XSPI2 */ 134 /** 135 * @} 136 */ 137 138 /** @defgroup SBS_Compensation_Cell_Ready_Selection Compensation Cell Ready Selection 139 * @{ 140 */ 141 #define SBS_IO_ANALOG_CELL_READY SBS_CCCSR_COMP_RDY /*!< Ready flag of compensation cell for the I/O analog switches */ 142 #define SBS_IO_XSPI1_CELL_READY SBS_CCCSR_XSPI1_COMP_RDY /*!< Ready flag of compensation cell for the I/O of the XSPI1 */ 143 #define SBS_IO_XSPI2_CELL_READY SBS_CCCSR_XSPI2_COMP_RDY /*!< Ready flag of compensation cell for the I/O of the XSPI2 */ 144 /** 145 * @} 146 */ 147 148 /** @defgroup SBS_IO_Compensation_Code_Config IO Compensation Code config 149 * @{ 150 */ 151 #define SBS_IO_CELL_CODE 0UL /*!< Code from the cell */ 152 #define SBS_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */ 153 /** 154 * @} 155 */ 156 157 /** @defgroup SBS_IO_HSLV_Selection IO High Speed at Low Voltage Selection 158 * @{ 159 */ 160 #define SBS_IO_ANALOG_HSLV SBS_CCCSR_IOHSLV /*!< High speed at low voltage for the I/O analog switches */ 161 #define SBS_IO_XSPI1_HSLV SBS_CCCSR_XSPI1_IOHSLV /*!< High speed at low voltage for the I/O of the XSPI1 */ 162 #define SBS_IO_XSPI2_HSLV SBS_CCCSR_XSPI2_IOHSLV /*!< High speed at low voltage for the I/O of the XSPI2 */ 163 /** 164 * @} 165 */ 166 167 /** @defgroup SBS_Ethernet_PHY_Config Ethernet PHY config 168 * @{ 169 */ 170 #define SBS_ETHERNET_PHY_GMII_OR_MII 0U /*!< GMII or MII */ 171 #define SBS_ETHERNET_PHY_RMII SBS_PMCR_ETH_PHYSEL_2 /*!< RMII */ 172 /** 173 * @} 174 */ 175 176 /** @defgroup SBS_ECC_AXISRAM_WS_Config ECC AXISRAMs Wait State when ECC=0 config 177 * @{ 178 */ 179 #define SBS_AXISRAM_WS_0 0U /*!< 0 Wait state */ 180 #define SBS_AXISRAM_WS_1 SBS_PMCR_AXISRAM_WS /*!< 1 Wait state */ 181 /** 182 * @} 183 */ 184 185 /** @defgroup SBS_EXTI_Port EXTI Port configuration 186 * @{ 187 */ 188 #define SBS_EXTI_PIN_PORTA 0x00UL /*!< Port A pin input of EXTI event detection */ 189 #define SBS_EXTI_PIN_PORTB 0x01UL /*!< Port B pin input of EXTI event detection */ 190 #define SBS_EXTI_PIN_PORTC 0x02UL /*!< Port C pin input of EXTI event detection */ 191 #define SBS_EXTI_PIN_PORTD 0x03UL /*!< Port D pin input of EXTI event detection */ 192 #define SBS_EXTI_PIN_PORTE 0x04UL /*!< Port E pin input of EXTI event detection */ 193 #define SBS_EXTI_PIN_PORTF 0x05UL /*!< Port F pin input of EXTI event detection */ 194 #define SBS_EXTI_PIN_PORTG 0x06UL /*!< Port G pin input of EXTI event detection */ 195 #define SBS_EXTI_PIN_PORTH 0x07UL /*!< Port H pin input of EXTI event detection */ 196 #define SBS_EXTI_PIN_PORTM 0x0CUL /*!< Port M pin input of EXTI event detection */ 197 #define SBS_EXTI_PIN_PORTN 0x0DUL /*!< Port N pin input of EXTI event detection */ 198 #define SBS_EXTI_PIN_PORTO 0x0EUL /*!< Port O pin input of EXTI event detection */ 199 #define SBS_EXTI_PIN_PORTP 0x0FUL /*!< Port P pin input of EXTI event detection */ 200 /** 201 * @} 202 */ 203 204 /** @defgroup AXIM_Exported_Constants AXIM Exported Constants 205 * @{ 206 */ 207 208 /** @defgroup AXIM_ASIB_READ_ISSUING_CAP AXIM ASIBs Read Issuing Capability 209 * @{ 210 */ 211 #define AXIM_ASIB_READ_ISS_NORMAL 0U /*!< Normal issuing capability */ 212 #define AXIM_ASIB_READ_ISS_FORCE_TO_1 AXIM_ASIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup AXIM_ASIB_WRITE_ISSUING_CAP AXIM ASIBs Write Issuing Capability 218 * @{ 219 */ 220 #define AXIM_ASIB_WRITE_ISS_NORMAL 0U /*!< Normal issuing capability */ 221 #define AXIM_ASIB_WRITE_ISS_FORCE_TO_1 AXIM_ASIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup AXIM_AMIB_READ_ISSUING_CAP AXIM AMIBs Read Issuing Capability 227 * @{ 228 */ 229 #define AXIM_AMIB_READ_ISS_NORMAL 0U /*!< Normal issuing capability */ 230 #define AXIM_AMIB_READ_ISS_FORCE_TO_1 AXIM_AMIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */ 231 /** 232 * @} 233 */ 234 235 /** @defgroup AXIM_AMIB_WRITE_ISSUING_CAP AXIM AMIBs Write Issuing Capability 236 * @{ 237 */ 238 #define AXIM_AMIB_WRITE_ISS_NORMAL 0U /*!< Normal issuing capability */ 239 #define AXIM_AMIB_WRITE_ISS_FORCE_TO_1 AXIM_AMIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */ 240 /** 241 * @} 242 */ 243 244 /** @defgroup AXIM_AMIB_READ_ISSUING_BM_CAP AXIM AMIBs Read Issuing Bus Matrix Capability 245 * @{ 246 */ 247 #define AXIM_AMIB_READ_ISS_BM_NORMAL 0U /*!< Normal issuing capability */ 248 #define AXIM_AMIB_READ_ISS_BM_FORCE_TO_1 AXIM_AMIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */ 249 /** 250 * @} 251 */ 252 253 /** @defgroup AXIM_AMIB_WRITE_ISSUING_BM_CAP AXIM AMIBs Write Issuing Bus Matrix Capability 254 * @{ 255 */ 256 #define AXIM_AMIB_WRITE_ISS_BM_NORMAL 0U /*!< Normal issuing capability */ 257 #define AXIM_AMIB_WRITE_ISS_BM_FORCE_TO_1 AXIM_AMIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */ 258 /** 259 * @} 260 */ 261 /** 262 * @} 263 */ 264 265 /* Exported macros -----------------------------------------------------------*/ 266 267 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 268 * @{ 269 */ 270 271 /** @brief Freeze/Unfreeze Peripherals in Debug mode 272 */ 273 #define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0) 274 #define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0) 275 276 #define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1) 277 #define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1) 278 279 #define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2) 280 #define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2) 281 282 #define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3) 283 #define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3) 284 285 #define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4) 286 #define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4) 287 288 #define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5) 289 #define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5) 290 291 #define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6) 292 #define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6) 293 294 #define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7) 295 #define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7) 296 297 #define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8) 298 #define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8) 299 300 #define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9) 301 #define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9) 302 303 #define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_10) 304 #define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_10) 305 306 #define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_11) 307 #define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_11) 308 309 #define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_12) 310 #define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_12) 311 312 #define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_13) 313 #define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_13) 314 315 #define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_14) 316 #define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_14) 317 318 #define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_15) 319 #define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_15) 320 321 #define __HAL_DBGMCU_FREEZE_HPDMA0() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_0) 322 #define __HAL_DBGMCU_UNFREEZE_HPDMA0() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_0) 323 324 #define __HAL_DBGMCU_FREEZE_HPDMA1() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_1) 325 #define __HAL_DBGMCU_UNFREEZE_HPDMA1() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_1) 326 327 #define __HAL_DBGMCU_FREEZE_HPDMA2() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_2) 328 #define __HAL_DBGMCU_UNFREEZE_HPDMA2() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_2) 329 330 #define __HAL_DBGMCU_FREEZE_HPDMA3() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_3) 331 #define __HAL_DBGMCU_UNFREEZE_HPDMA3() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_3) 332 333 #define __HAL_DBGMCU_FREEZE_HPDMA4() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_4) 334 #define __HAL_DBGMCU_UNFREEZE_HPDMA4() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_4) 335 336 #define __HAL_DBGMCU_FREEZE_HPDMA5() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_5) 337 #define __HAL_DBGMCU_UNFREEZE_HPDMA5() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_5) 338 339 #define __HAL_DBGMCU_FREEZE_HPDMA6() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_6) 340 #define __HAL_DBGMCU_UNFREEZE_HPDMA6() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_6) 341 342 #define __HAL_DBGMCU_FREEZE_HPDMA7() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_7) 343 #define __HAL_DBGMCU_UNFREEZE_HPDMA7() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_7) 344 345 #define __HAL_DBGMCU_FREEZE_HPDMA8() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_8) 346 #define __HAL_DBGMCU_UNFREEZE_HPDMA8() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_8) 347 348 #define __HAL_DBGMCU_FREEZE_HPDMA9() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_9) 349 #define __HAL_DBGMCU_UNFREEZE_HPDMA9() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_9) 350 351 #define __HAL_DBGMCU_FREEZE_HPDMA10() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_10) 352 #define __HAL_DBGMCU_UNFREEZE_HPDMA10() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_10) 353 354 #define __HAL_DBGMCU_FREEZE_HPDMA11() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_11) 355 #define __HAL_DBGMCU_UNFREEZE_HPDMA11() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_11) 356 357 #define __HAL_DBGMCU_FREEZE_HPDMA12() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_12) 358 #define __HAL_DBGMCU_UNFREEZE_HPDMA12() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_12) 359 360 #define __HAL_DBGMCU_FREEZE_HPDMA13() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_13) 361 #define __HAL_DBGMCU_UNFREEZE_HPDMA13() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_13) 362 363 #define __HAL_DBGMCU_FREEZE_HPDMA14() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_14) 364 #define __HAL_DBGMCU_UNFREEZE_HPDMA14() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_14) 365 366 #define __HAL_DBGMCU_FREEZE_HPDMA15() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_15) 367 #define __HAL_DBGMCU_UNFREEZE_HPDMA15() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_15) 368 369 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C1) 370 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C1) 371 372 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C2) 373 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C2) 374 375 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C3) 376 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C3) 377 378 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM2) 379 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM2) 380 381 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM3) 382 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM3) 383 384 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM4) 385 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM4) 386 387 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM5) 388 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM5) 389 390 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM6) 391 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM6) 392 393 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM7) 394 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM7) 395 396 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM9) 397 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM9) 398 399 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM12) 400 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM12) 401 402 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM13) 403 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM13) 404 405 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM14) 406 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM14) 407 408 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM1) 409 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM1) 410 411 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM15) 412 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM15) 413 414 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM16) 415 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM16) 416 417 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM17) 418 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM17) 419 420 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_LPTIM1) 421 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_LPTIM1) 422 423 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM2) 424 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM2) 425 426 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM3) 427 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM3) 428 429 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM4) 430 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM4) 431 432 #define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM5) 433 #define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM5) 434 435 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_IWDG) 436 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_IWDG) 437 438 #define __HAL_DBGMCU_FREEZE_PWM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_PWM1) 439 #define __HAL_DBGMCU_UNFREEZE_PWM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_PWM1) 440 441 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_RTC) 442 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_RTC) 443 444 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_WWDG) 445 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_WWDG) 446 447 /** 448 * @} 449 */ 450 451 /** @defgroup SBS_Exported_Macros SBS Exported Macros 452 * @{ 453 */ 454 455 /** @brief Floating Point Unit interrupt enable/disable macros 456 * @param __INTERRUPT__ This parameter can be a value of @ref SBS_FPU_Interrupts 457 */ 458 #define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do { \ 459 assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__))); \ 460 SET_BIT(SBS->FPUIMR, (__INTERRUPT__)); \ 461 } while(0) 462 463 #define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do { \ 464 assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__))); \ 465 CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__)); \ 466 } while(0) 467 468 /** @brief Check SBS Memories Erase Status Flags. 469 * @retval The state of memory erase. 470 */ 471 #define __HAL_SBS_GET_MEMORIES_ERASE_STATUS() ((SBS->MESR) & (SBS_MESR_MEF)) 472 473 /** 474 * @} 475 */ 476 477 478 /* Private macros ------------------------------------------------------------*/ 479 /** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale 480 * @{ 481 */ 482 #define VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ 483 #define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ 484 #define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ 485 #define VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ 486 487 488 #define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \ 489 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \ 490 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \ 491 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE3)) 492 493 494 /** 495 * @} 496 */ 497 498 /** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance 499 * @{ 500 */ 501 #define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 502 #define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 503 504 #define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 505 ((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE)) 506 507 #define IS_VREFBUF_TRIMMING(__VALUE__) ((__VALUE__) <= VREFBUF_CCR_TRIM) 508 509 /** 510 * @} 511 */ 512 513 /** @addtogroup SBS_Private_Macros 514 * @{ 515 */ 516 #define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \ 517 (((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \ 518 (((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \ 519 (((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \ 520 (((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \ 521 (((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC)) 522 523 #define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || \ 524 ((__LEVEL__) == SBS_HDPL_VALUE_1) || \ 525 ((__LEVEL__) == SBS_HDPL_VALUE_2) || \ 526 ((__LEVEL__) == SBS_HDPL_VALUE_3)) 527 528 #define IS_SBS_COMPENSATION_CELL(__CELL__) (((__CELL__) == SBS_IO_ANALOG_CELL) || \ 529 ((__CELL__) == SBS_IO_XSPI1_CELL) || \ 530 ((__CELL__) == SBS_IO_XSPI2_CELL)) 531 532 #define IS_SBS_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SBS_IO_ANALOG_CELL_READY) || \ 533 ((__CELL__) == SBS_IO_XSPI1_CELL_READY) || \ 534 ((__CELL__) == SBS_IO_XSPI2_CELL_READY)) 535 536 #define IS_SBS_IOHSLV(__HSLV__) (((__HSLV__) == SBS_IO_ANALOG_HSLV) || \ 537 ((__HSLV__) == SBS_IO_XSPI1_HSLV) || \ 538 ((__HSLV__) == SBS_IO_XSPI2_HSLV)) 539 540 #define IS_SBS_EXTI_INPUT(__INPUT__) ((__INPUT__) < 16U) 541 542 #define IS_SBS_EXTI_PIN(__PIN__) (((__PIN__) == SBS_EXTI_PIN_PORTA) || \ 543 ((__PIN__) == SBS_EXTI_PIN_PORTB) || \ 544 ((__PIN__) == SBS_EXTI_PIN_PORTC) || \ 545 ((__PIN__) == SBS_EXTI_PIN_PORTD) || \ 546 ((__PIN__) == SBS_EXTI_PIN_PORTE) || \ 547 ((__PIN__) == SBS_EXTI_PIN_PORTF) || \ 548 ((__PIN__) == SBS_EXTI_PIN_PORTG) || \ 549 ((__PIN__) == SBS_EXTI_PIN_PORTH) || \ 550 ((__PIN__) == SBS_EXTI_PIN_PORTM) || \ 551 ((__PIN__) == SBS_EXTI_PIN_PORTN) || \ 552 ((__PIN__) == SBS_EXTI_PIN_PORTO) || \ 553 ((__PIN__) == SBS_EXTI_PIN_PORTP)) 554 /** 555 * @} 556 */ 557 558 /** @addtogroup AXIM_Private_Macros 559 * @{ 560 */ 561 #define IS_AXIM_ASIB_READ_ISS(__ISS__) (((__ISS__) == AXIM_ASIB_READ_ISS_NORMAL) || \ 562 ((__ISS__) == AXIM_ASIB_READ_ISS_FORCE_TO_1)) 563 564 #define IS_AXIM_ASIB_WRITE_ISS(__ISS__) (((__ISS__) == AXIM_ASIB_WRITE_ISS_NORMAL) || \ 565 ((__ISS__) == AXIM_ASIB_WRITE_ISS_FORCE_TO_1)) 566 567 #define IS_AXIM_QOS(__QOS__) ((__QOS__) <= AXIM_ASIB_READQOS_AR_QOS) 568 569 #define IS_AXIM_AMIB_READ_ISS(__ISS__) (((__ISS__) == AXIM_AMIB_READ_ISS_NORMAL) || \ 570 ((__ISS__) == AXIM_AMIB_READ_ISS_FORCE_TO_1)) 571 572 #define IS_AXIM_AMIB_WRITE_ISS(__ISS__) (((__ISS__) == AXIM_AMIB_WRITE_ISS_NORMAL) || \ 573 ((__ISS__) == AXIM_AMIB_WRITE_ISS_FORCE_TO_1)) 574 575 #define IS_AXIM_AMIB_READ_ISS_BM(__ISS__) (((__ISS__) == AXIM_AMIB_READ_ISS_NORMAL) || \ 576 ((__ISS__) == AXIM_AMIB_READ_ISS_FORCE_TO_1)) 577 578 #define IS_AXIM_AMIB_WRITE_ISS_BM(__ISS__) (((__ISS__) == AXIM_AMIB_WRITE_ISS_BM_NORMAL) || \ 579 ((__ISS__) == AXIM_AMIB_WRITE_ISS_BM_FORCE_TO_1)) 580 581 /** 582 * @} 583 */ 584 585 /* Exported variables --------------------------------------------------------*/ 586 587 /** @addtogroup HAL_Exported_Variables 588 * @{ 589 */ 590 extern __IO uint32_t uwTick; 591 extern uint32_t uwTickPrio; 592 extern HAL_TickFreqTypeDef uwTickFreq; 593 /** 594 * @} 595 */ 596 597 /* Exported functions --------------------------------------------------------*/ 598 599 /** @addtogroup HAL_Exported_Functions 600 * @{ 601 */ 602 603 /** @addtogroup HAL_Exported_Functions_Group1 604 * @{ 605 */ 606 607 /* Initialization and de-initialization functions ****************************/ 608 HAL_StatusTypeDef HAL_Init(void); 609 HAL_StatusTypeDef HAL_DeInit(void); 610 void HAL_MspInit(void); 611 void HAL_MspDeInit(void); 612 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 613 614 /** 615 * @} 616 */ 617 618 /** @addtogroup HAL_Exported_Functions_Group2 619 * @{ 620 */ 621 622 /* Peripheral Control functions **********************************************/ 623 void HAL_IncTick(void); 624 void HAL_Delay(uint32_t Delay); 625 uint32_t HAL_GetTick(void); 626 uint32_t HAL_GetTickPrio(void); 627 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 628 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 629 void HAL_SuspendTick(void); 630 void HAL_ResumeTick(void); 631 uint32_t HAL_GetHalVersion(void); 632 uint32_t HAL_GetREVID(void); 633 uint32_t HAL_GetDEVID(void); 634 uint32_t HAL_GetUIDw0(void); 635 uint32_t HAL_GetUIDw1(void); 636 uint32_t HAL_GetUIDw2(void); 637 638 /** 639 * @} 640 */ 641 642 /** @addtogroup HAL_Exported_Functions_Group3 643 * @{ 644 */ 645 646 /* DBGMCU Peripheral Control functions ***************************************/ 647 void HAL_DBGMCU_EnableDBGSleepMode(void); 648 void HAL_DBGMCU_DisableDBGSleepMode(void); 649 void HAL_DBGMCU_EnableDBGStopMode(void); 650 void HAL_DBGMCU_DisableDBGStopMode(void); 651 void HAL_DBGMCU_EnableDBGStandbyMode(void); 652 void HAL_DBGMCU_DisableDBGStandbyMode(void); 653 654 /** 655 * @} 656 */ 657 658 /** @addtogroup HAL_Exported_Functions_Group4 659 * @{ 660 */ 661 662 /* SBS Control functions *****************************************************/ 663 uint32_t HAL_SBS_GetBootAddress(void); 664 665 void HAL_SBS_IncrementHDPLValue(void); 666 uint32_t HAL_SBS_GetHDPLValue(void); 667 668 void HAL_SBS_OpenAccessPort(void); 669 void HAL_SBS_OpenDebug(void); 670 HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level); 671 uint32_t HAL_SBS_GetDebugLevel(void); 672 void HAL_SBS_UnlockDebugConfig(void); 673 void HAL_SBS_LockDebugConfig(void); 674 675 void HAL_SBS_ConfigRSSCommand(uint32_t Cmd); 676 uint32_t HAL_SBS_GetRSSCommand(void); 677 678 void HAL_SBS_EnableIOAnalogBooster(void); 679 void HAL_SBS_DisableIOAnalogBooster(void); 680 void HAL_SBS_EnableIOAnalogSwitchVdd(void); 681 void HAL_SBS_DisableIOAnalogSwitchVdd(void); 682 void HAL_SBS_ConfigEthernetPHY(uint32_t Config); 683 void HAL_SBS_ConfigAXISRAMWaitState(uint32_t Config); 684 685 void HAL_SBS_EnableCompensationCell(uint32_t Selection); 686 void HAL_SBS_DisableCompensationCell(uint32_t Selection); 687 uint32_t HAL_SBS_GetCompensationCellReadyStatus(uint32_t Selection); 688 void HAL_SBS_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, 689 uint32_t PmosValue); 690 HAL_StatusTypeDef HAL_SBS_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue, 691 uint32_t *pPmosValue); 692 693 void HAL_SBS_EnableIOSpeedOptimize(uint32_t Selection); 694 void HAL_SBS_DisableIOSpeedOptimize(uint32_t Selection); 695 696 void HAL_SBS_ConfigTimerBreakInput(uint32_t Input); 697 uint32_t HAL_SBS_GetTimerBreakInputConfig(void); 698 699 void HAL_SBS_EXTIConfig(uint32_t Exti, uint32_t Port); 700 uint32_t HAL_SBS_GetEXTIConfig(uint32_t Exti); 701 /** 702 * @} 703 */ 704 705 /** @addtogroup HAL_Exported_Functions_Group5 706 * @{ 707 */ 708 709 /* VREFBUF Control functions *************************************************/ 710 void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 711 void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode); 712 void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 713 HAL_StatusTypeDef HAL_VREFBUF_Enable(void); 714 void HAL_VREFBUF_Disable(void); 715 716 717 /** 718 * @} 719 */ 720 721 /** @addtogroup HAL_Exported_Functions_Group6 722 * @{ 723 */ 724 725 /* AXIM Configuration functions *************************************************/ 726 void HAL_AXIM_ASIB_EnablePacking(AXIM_ASIB_TypeDef *AsibInstance); 727 void HAL_AXIM_ASIB_DisablePacking(AXIM_ASIB_TypeDef *AsibInstance); 728 void HAL_AXIM_ASIB_IssuingConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t ReadIssuing, 729 uint32_t WriteIssuing); 730 void HAL_AXIM_ASIB_ReadQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority); 731 void HAL_AXIM_ASIB_WriteQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority); 732 733 734 void HAL_AXIM_AMIB_EnablePacking(AXIM_AMIB_TypeDef *AmibInstance); 735 void HAL_AXIM_AMIB_DisablePacking(AXIM_AMIB_TypeDef *AmibInstance); 736 void HAL_AXIM_AMIB_IssuingConfig(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing, 737 uint32_t WriteIssuing); 738 void HAL_AXIM_AMIB_IssuingConfigBusMatrix(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing, 739 uint32_t WriteIssuing); 740 void HAL_AXIM_AMIB_EnableLongBurst(AXIM_AMIB_TypeDef *AmibInstance); 741 void HAL_AXIM_AMIB_DisableLongBurst(AXIM_AMIB_TypeDef *AmibInstance); 742 /** 743 * @} 744 */ 745 746 /** 747 * @} 748 */ 749 750 751 /** 752 * @} 753 */ 754 755 /** 756 * @} 757 */ 758 759 /** 760 * @} 761 */ 762 763 #ifdef __cplusplus 764 } 765 #endif 766 767 #endif /* STM32H7RSxx_HAL_H */ 768
