1 /** 2 ****************************************************************************** 3 * @file ism330is_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ism330is_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ISM330IS_REGS_H 23 #define ISM330IS_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ISM330IS 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ISM330IS_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define ISM330IS_I2C_ADD_L 0xD5U 173 #define ISM330IS_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define ISM330IS_ID 0x22U 177 178 /** 179 * @} 180 * 181 */ 182 183 /** @defgroup bitfields page main 184 * @{ 185 * 186 */ 187 188 #define ISM330IS_FUNC_CFG_ACCESS 0x1U 189 typedef struct 190 { 191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 192 uint8_t not_used0 : 1; 193 uint8_t sw_reset_ispu : 1; 194 uint8_t not_used1 : 4; 195 uint8_t shub_reg_access : 1; 196 uint8_t ispu_reg_access : 1; 197 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 198 uint8_t ispu_reg_access : 1; 199 uint8_t shub_reg_access : 1; 200 uint8_t not_used1 : 4; 201 uint8_t sw_reset_ispu : 1; 202 uint8_t not_used0 : 1; 203 #endif /* DRV_BYTE_ORDER */ 204 } ism330is_func_cfg_access_t; 205 206 #define ISM330IS_PIN_CTRL 0x2U 207 typedef struct 208 { 209 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 210 uint8_t not_used0 : 6; 211 uint8_t sdo_pu_en : 1; 212 uint8_t not_used1 : 1; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t not_used1 : 1; 215 uint8_t sdo_pu_en : 1; 216 uint8_t not_used0 : 6; 217 #endif /* DRV_BYTE_ORDER */ 218 } ism330is_pin_ctrl_t; 219 220 #define ISM330IS_DRDY_PULSED_REG 0x0BU 221 typedef struct 222 { 223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 224 uint8_t not_used0 : 7; 225 uint8_t drdy_pulsed : 1; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t drdy_pulsed : 1; 228 uint8_t not_used0 : 7; 229 #endif /* DRV_BYTE_ORDER */ 230 } ism330is_drdy_pulsed_reg_t; 231 232 #define ISM330IS_INT1_CTRL 0x0DU 233 typedef struct 234 { 235 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 236 uint8_t int1_drdy_xl : 1; 237 uint8_t int1_drdy_g : 1; 238 uint8_t int1_boot : 1; 239 uint8_t not_used0 : 5; 240 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 241 uint8_t not_used0 : 5; 242 uint8_t int1_boot : 1; 243 uint8_t int1_drdy_g : 1; 244 uint8_t int1_drdy_xl : 1; 245 #endif /* DRV_BYTE_ORDER */ 246 } ism330is_int1_ctrl_t; 247 248 #define ISM330IS_INT2_CTRL 0x0EU 249 typedef struct 250 { 251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 252 uint8_t int2_drdy_xl : 1; 253 uint8_t int2_drdy_g : 1; 254 uint8_t int2_drdy_temp : 1; 255 uint8_t not_used0 : 4; 256 uint8_t int2_sleep_ispu : 1; 257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 258 uint8_t int2_sleep_ispu : 1; 259 uint8_t not_used0 : 4; 260 uint8_t int2_drdy_temp : 1; 261 uint8_t int2_drdy_g : 1; 262 uint8_t int2_drdy_xl : 1; 263 #endif /* DRV_BYTE_ORDER */ 264 } ism330is_int2_ctrl_t; 265 266 #define ISM330IS_WHO_AM_I 0x0FU 267 typedef struct 268 { 269 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 270 uint8_t id : 8; 271 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 272 uint8_t id : 8; 273 #endif /* DRV_BYTE_ORDER */ 274 } ism330is_who_am_i_t; 275 276 #define ISM330IS_CTRL1_XL 0x10U 277 typedef struct 278 { 279 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 280 uint8_t not_used0 : 2; 281 uint8_t fs_xl : 2; 282 uint8_t odr_xl : 4; 283 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 284 uint8_t odr_xl : 4; 285 uint8_t fs_xl : 2; 286 uint8_t not_used0 : 2; 287 #endif /* DRV_BYTE_ORDER */ 288 } ism330is_ctrl1_xl_t; 289 290 #define ISM330IS_CTRL2_G 0x11U 291 typedef struct 292 { 293 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 294 uint8_t not_used0 : 1; 295 uint8_t fs_125 : 1; 296 uint8_t fs_g : 2; 297 uint8_t odr_g : 4; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t odr_g : 4; 300 uint8_t fs_g : 2; 301 uint8_t fs_125 : 1; 302 uint8_t not_used0 : 1; 303 #endif /* DRV_BYTE_ORDER */ 304 } ism330is_ctrl2_g_t; 305 306 #define ISM330IS_CTRL3_C 0x12U 307 typedef struct 308 { 309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 310 uint8_t sw_reset : 1; 311 uint8_t not_used0 : 1; 312 uint8_t if_inc : 1; 313 uint8_t sim : 1; 314 uint8_t pp_od : 1; 315 uint8_t h_lactive : 1; 316 uint8_t bdu : 1; 317 uint8_t boot : 1; 318 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 319 uint8_t boot : 1; 320 uint8_t bdu : 1; 321 uint8_t h_lactive : 1; 322 uint8_t pp_od : 1; 323 uint8_t sim : 1; 324 uint8_t if_inc : 1; 325 uint8_t not_used0 : 1; 326 uint8_t sw_reset : 1; 327 #endif /* DRV_BYTE_ORDER */ 328 } ism330is_ctrl3_c_t; 329 330 #define ISM330IS_CTRL4_C 0x13U 331 typedef struct 332 { 333 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 334 uint8_t not_used0 : 2; 335 uint8_t i2c_disable : 1; 336 uint8_t not_used1 : 2; 337 uint8_t int2_on_int1 : 1; 338 uint8_t sleep_g : 1; 339 uint8_t not_used2 : 1; 340 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 341 uint8_t not_used2 : 1; 342 uint8_t sleep_g : 1; 343 uint8_t int2_on_int1 : 1; 344 uint8_t not_used1 : 2; 345 uint8_t i2c_disable : 1; 346 uint8_t not_used0 : 2; 347 #endif /* DRV_BYTE_ORDER */ 348 } ism330is_ctrl4_c_t; 349 350 #define ISM330IS_CTRL5_C 0x14U 351 typedef struct 352 { 353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 354 uint8_t st_xl : 2; 355 uint8_t st_g : 2; 356 uint8_t not_used0 : 4; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t not_used0 : 4; 359 uint8_t st_g : 2; 360 uint8_t st_xl : 2; 361 #endif /* DRV_BYTE_ORDER */ 362 } ism330is_ctrl5_c_t; 363 364 #define ISM330IS_CTRL6_C 0x15U 365 typedef struct 366 { 367 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 368 uint8_t not_used0 : 4; 369 uint8_t xl_hm_mode : 1; 370 uint8_t not_used1 : 3; 371 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 372 uint8_t not_used1 : 3; 373 uint8_t xl_hm_mode : 1; 374 uint8_t not_used0 : 4; 375 #endif /* DRV_BYTE_ORDER */ 376 } ism330is_ctrl6_c_t; 377 378 #define ISM330IS_CTRL7_G 0x16U 379 typedef struct 380 { 381 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 382 uint8_t not_used0 : 7; 383 uint8_t g_hm_mode : 1; 384 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 385 uint8_t g_hm_mode : 1; 386 uint8_t not_used0 : 7; 387 #endif /* DRV_BYTE_ORDER */ 388 } ism330is_ctrl7_g_t; 389 390 #define ISM330IS_CTRL9_C 0x18U 391 typedef struct 392 { 393 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 394 uint8_t ispu_bdu : 2; 395 uint8_t not_used0 : 2; 396 uint8_t ispu_rate : 4; 397 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 398 uint8_t ispu_rate : 4; 399 uint8_t not_used0 : 2; 400 uint8_t ispu_bdu : 2; 401 #endif /* DRV_BYTE_ORDER */ 402 } ism330is_ctrl9_c_t; 403 404 #define ISM330IS_CTRL10_C 0x19U 405 typedef struct 406 { 407 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 408 uint8_t not_used0 : 2; 409 uint8_t ispu_clk_sel : 1; 410 uint8_t not_used1 : 2; 411 uint8_t timestamp_en : 1; 412 uint8_t not_used2 : 2; 413 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 414 uint8_t not_used2 : 2; 415 uint8_t timestamp_en : 1; 416 uint8_t not_used1 : 2; 417 uint8_t ispu_clk_sel : 1; 418 uint8_t not_used0 : 2; 419 #endif /* DRV_BYTE_ORDER */ 420 } ism330is_ctrl10_c_t; 421 422 #define ISM330IS_ISPU_INT_STATUS0_MAINPAGE 0x1AU 423 typedef struct 424 { 425 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 426 uint8_t ia_ispu : 8; 427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 428 uint8_t ia_ispu : 8; 429 #endif /* DRV_BYTE_ORDER */ 430 } ism330is_ispu_int_status0_mainpage_t; 431 432 #define ISM330IS_ISPU_INT_STATUS1_MAINPAGE 0x1BU 433 typedef struct 434 { 435 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 436 uint8_t ia_ispu : 8; 437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 438 uint8_t ia_ispu : 8; 439 #endif /* DRV_BYTE_ORDER */ 440 } ism330is_ispu_int_status1_mainpage_t; 441 442 #define ISM330IS_ISPU_INT_STATUS2_MAINPAGE 0x1CU 443 typedef struct 444 { 445 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 446 uint8_t ia_ispu : 8; 447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 448 uint8_t ia_ispu : 8; 449 #endif /* DRV_BYTE_ORDER */ 450 } ism330is_ispu_int_status2_mainpage_t; 451 452 #define ISM330IS_ISPU_INT_STATUS3_MAINPAGE 0x1DU 453 typedef struct 454 { 455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 456 uint8_t ia_ispu : 6; 457 uint8_t not_used0 : 2; 458 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 459 uint8_t not_used0 : 2; 460 uint8_t ia_ispu : 6; 461 #endif /* DRV_BYTE_ORDER */ 462 } ism330is_ispu_int_status3_mainpage_t; 463 464 #define ISM330IS_STATUS_REG 0x1EU 465 typedef struct 466 { 467 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 468 uint8_t xlda : 1; 469 uint8_t gda : 1; 470 uint8_t tda : 1; 471 uint8_t not_used0 : 4; 472 uint8_t timestamp_endcount : 1; 473 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 474 uint8_t timestamp_endcount : 1; 475 uint8_t not_used0 : 4; 476 uint8_t tda : 1; 477 uint8_t gda : 1; 478 uint8_t xlda : 1; 479 #endif /* DRV_BYTE_ORDER */ 480 } ism330is_status_reg_t; 481 482 #define ISM330IS_OUT_TEMP_L 0x20U 483 typedef struct 484 { 485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 486 uint8_t temp : 8; 487 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 488 uint8_t temp : 8; 489 #endif /* DRV_BYTE_ORDER */ 490 } ism330is_out_temp_l_t; 491 492 #define ISM330IS_OUT_TEMP_H 0x21U 493 typedef struct 494 { 495 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 496 uint8_t temp : 8; 497 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 498 uint8_t temp : 8; 499 #endif /* DRV_BYTE_ORDER */ 500 } ism330is_out_temp_h_t; 501 502 #define ISM330IS_OUTX_L_G 0x22U 503 typedef struct 504 { 505 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 506 uint8_t outx_g : 8; 507 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 508 uint8_t outx_g : 8; 509 #endif /* DRV_BYTE_ORDER */ 510 } ism330is_outx_l_g_t; 511 512 #define ISM330IS_OUTX_H_G 0x23U 513 typedef struct 514 { 515 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 516 uint8_t outx_g : 8; 517 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 518 uint8_t outx_g : 8; 519 #endif /* DRV_BYTE_ORDER */ 520 } ism330is_outx_h_g_t; 521 522 #define ISM330IS_OUTY_L_G 0x24U 523 typedef struct 524 { 525 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 526 uint8_t outy_g : 8; 527 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 528 uint8_t outy_g : 8; 529 #endif /* DRV_BYTE_ORDER */ 530 } ism330is_outy_l_g_t; 531 532 #define ISM330IS_OUTY_H_G 0x25U 533 typedef struct 534 { 535 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 536 uint8_t outy_g : 8; 537 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 538 uint8_t outy_g : 8; 539 #endif /* DRV_BYTE_ORDER */ 540 } ism330is_outy_h_g_t; 541 542 #define ISM330IS_OUTZ_L_G 0x26U 543 typedef struct 544 { 545 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 546 uint8_t outz_g : 8; 547 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 548 uint8_t outz_g : 8; 549 #endif /* DRV_BYTE_ORDER */ 550 } ism330is_outz_l_g_t; 551 552 #define ISM330IS_OUTZ_H_G 0x27U 553 typedef struct 554 { 555 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 556 uint8_t outz_g : 8; 557 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 558 uint8_t outz_g : 8; 559 #endif /* DRV_BYTE_ORDER */ 560 } ism330is_outz_h_g_t; 561 562 #define ISM330IS_OUTX_L_A 0x28U 563 typedef struct 564 { 565 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 566 uint8_t outx_a : 8; 567 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 568 uint8_t outx_a : 8; 569 #endif /* DRV_BYTE_ORDER */ 570 } ism330is_outx_l_a_t; 571 572 #define ISM330IS_OUTX_H_A 0x29U 573 typedef struct 574 { 575 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 576 uint8_t outx_a : 8; 577 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 578 uint8_t outx_a : 8; 579 #endif /* DRV_BYTE_ORDER */ 580 } ism330is_outx_h_a_t; 581 582 #define ISM330IS_OUTY_L_A 0x2AU 583 typedef struct 584 { 585 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 586 uint8_t outy_a : 8; 587 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 588 uint8_t outy_a : 8; 589 #endif /* DRV_BYTE_ORDER */ 590 } ism330is_outy_l_a_t; 591 592 #define ISM330IS_OUTY_H_A 0x2BU 593 typedef struct 594 { 595 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 596 uint8_t outy_a : 8; 597 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 598 uint8_t outy_a : 8; 599 #endif /* DRV_BYTE_ORDER */ 600 } ism330is_outy_h_a_t; 601 602 #define ISM330IS_OUTZ_L_A 0x2CU 603 typedef struct 604 { 605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 606 uint8_t outz_a : 8; 607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 608 uint8_t outz_a : 8; 609 #endif /* DRV_BYTE_ORDER */ 610 } ism330is_outz_l_a_t; 611 612 #define ISM330IS_OUTZ_H_A 0x2DU 613 typedef struct 614 { 615 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 616 uint8_t outz_a : 8; 617 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 618 uint8_t outz_a : 8; 619 #endif /* DRV_BYTE_ORDER */ 620 } ism330is_outz_h_a_t; 621 622 #define ISM330IS_STATUS_MASTER_MAINPAGE 0x39U 623 typedef struct 624 { 625 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 626 uint8_t sens_hub_endop : 1; 627 uint8_t not_used0 : 2; 628 uint8_t slave0_nack : 1; 629 uint8_t slave1_nack : 1; 630 uint8_t slave2_nack : 1; 631 uint8_t slave3_nack : 1; 632 uint8_t wr_once_done : 1; 633 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 634 uint8_t wr_once_done : 1; 635 uint8_t slave3_nack : 1; 636 uint8_t slave2_nack : 1; 637 uint8_t slave1_nack : 1; 638 uint8_t slave0_nack : 1; 639 uint8_t not_used0 : 2; 640 uint8_t sens_hub_endop : 1; 641 #endif /* DRV_BYTE_ORDER */ 642 } ism330is_status_master_mainpage_t; 643 644 #define ISM330IS_TIMESTAMP0 0x40U 645 typedef struct 646 { 647 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 648 uint8_t timestamp : 8; 649 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 650 uint8_t timestamp : 8; 651 #endif /* DRV_BYTE_ORDER */ 652 } ism330is_timestamp0_t; 653 654 #define ISM330IS_TIMESTAMP1 0x41U 655 typedef struct 656 { 657 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 658 uint8_t timestamp : 8; 659 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 660 uint8_t timestamp : 8; 661 #endif /* DRV_BYTE_ORDER */ 662 } ism330is_timestamp1_t; 663 664 #define ISM330IS_TIMESTAMP2 0x42U 665 typedef struct 666 { 667 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 668 uint8_t timestamp : 8; 669 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 670 uint8_t timestamp : 8; 671 #endif /* DRV_BYTE_ORDER */ 672 } ism330is_timestamp2_t; 673 674 #define ISM330IS_TIMESTAMP3 0x43U 675 typedef struct 676 { 677 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 678 uint8_t timestamp : 8; 679 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 680 uint8_t timestamp : 8; 681 #endif /* DRV_BYTE_ORDER */ 682 } ism330is_timestamp3_t; 683 684 #define ISM330IS_MD1_CFG 0x5EU 685 typedef struct 686 { 687 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 688 uint8_t int1_shub : 1; 689 uint8_t int1_ispu : 1; 690 uint8_t not_used0 : 6; 691 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 692 uint8_t not_used0 : 6; 693 uint8_t int1_ispu : 1; 694 uint8_t int1_shub : 1; 695 #endif /* DRV_BYTE_ORDER */ 696 } ism330is_md1_cfg_t; 697 698 #define ISM330IS_MD2_CFG 0x5FU 699 typedef struct 700 { 701 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 702 uint8_t int2_timestamp : 1; 703 uint8_t int2_ispu : 1; 704 uint8_t not_used0 : 6; 705 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 706 uint8_t not_used0 : 6; 707 uint8_t int2_ispu : 1; 708 uint8_t int2_timestamp : 1; 709 #endif /* DRV_BYTE_ORDER */ 710 } ism330is_md2_cfg_t; 711 712 #define ISM330IS_INTERNAL_FREQ_FINE 0x63U 713 typedef struct 714 { 715 uint8_t freq_fine : 8; 716 } ism330is_internal_freq_fine_t; 717 718 #define ISM330IS_ISPU_DUMMY_CFG_1_L 0x73U 719 typedef struct 720 { 721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 722 uint8_t ispu_dummy_cfg_1 : 8; 723 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 724 uint8_t ispu_dummy_cfg_1 : 8; 725 #endif /* DRV_BYTE_ORDER */ 726 } ism330is_ispu_dummy_cfg_1_l_t; 727 728 #define ISM330IS_ISPU_DUMMY_CFG_1_H 0x74U 729 typedef struct 730 { 731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 732 uint8_t ispu_dummy_cfg_1 : 8; 733 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 734 uint8_t ispu_dummy_cfg_1 : 8; 735 #endif /* DRV_BYTE_ORDER */ 736 } ism330is_ispu_dummy_cfg_1_h_t; 737 738 #define ISM330IS_ISPU_DUMMY_CFG_2_L 0x75U 739 typedef struct 740 { 741 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 742 uint8_t ispu_dummy_cfg_2 : 8; 743 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 744 uint8_t ispu_dummy_cfg_2 : 8; 745 #endif /* DRV_BYTE_ORDER */ 746 } ism330is_ispu_dummy_cfg_2_l_t; 747 748 #define ISM330IS_ISPU_DUMMY_CFG_2_H 0x76U 749 typedef struct 750 { 751 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 752 uint8_t ispu_dummy_cfg_2 : 8; 753 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 754 uint8_t ispu_dummy_cfg_2 : 8; 755 #endif /* DRV_BYTE_ORDER */ 756 } ism330is_ispu_dummy_cfg_2_h_t; 757 758 #define ISM330IS_ISPU_DUMMY_CFG_3_L 0x77U 759 typedef struct 760 { 761 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 762 uint8_t ispu_dummy_cfg_3 : 8; 763 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 764 uint8_t ispu_dummy_cfg_3 : 8; 765 #endif /* DRV_BYTE_ORDER */ 766 } ism330is_ispu_dummy_cfg_3_l_t; 767 768 #define ISM330IS_ISPU_DUMMY_CFG_3_H 0x78U 769 typedef struct 770 { 771 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 772 uint8_t ispu_dummy_cfg_3 : 8; 773 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 774 uint8_t ispu_dummy_cfg_3 : 8; 775 #endif /* DRV_BYTE_ORDER */ 776 } ism330is_ispu_dummy_cfg_3_h_t; 777 778 #define ISM330IS_ISPU_DUMMY_CFG_4_L 0x79U 779 typedef struct 780 { 781 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 782 uint8_t ispu_dummy_cfg_4 : 8; 783 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 784 uint8_t ispu_dummy_cfg_4 : 8; 785 #endif /* DRV_BYTE_ORDER */ 786 } ism330is_ispu_dummy_cfg_4_l_t; 787 788 #define ISM330IS_ISPU_DUMMY_CFG_4_H 0x7AU 789 typedef struct 790 { 791 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 792 uint8_t ispu_dummy_cfg_4 : 8; 793 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 794 uint8_t ispu_dummy_cfg_4 : 8; 795 #endif /* DRV_BYTE_ORDER */ 796 } ism330is_ispu_dummy_cfg_4_h_t; 797 798 /** 799 * @} 800 * 801 */ 802 803 /** @defgroup bitfields page sensor_hub 804 * @{ 805 * 806 */ 807 808 #define ISM330IS_SENSOR_HUB_1 0x2U 809 typedef struct 810 { 811 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 812 uint8_t sensorhub1 : 8; 813 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 814 uint8_t sensorhub1 : 8; 815 #endif /* DRV_BYTE_ORDER */ 816 } ism330is_sensor_hub_1_t; 817 818 #define ISM330IS_SENSOR_HUB_2 0x3U 819 typedef struct 820 { 821 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 822 uint8_t sensorhub2 : 8; 823 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 824 uint8_t sensorhub2 : 8; 825 #endif /* DRV_BYTE_ORDER */ 826 } ism330is_sensor_hub_2_t; 827 828 #define ISM330IS_SENSOR_HUB_3 0x4U 829 typedef struct 830 { 831 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 832 uint8_t sensorhub3 : 8; 833 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 834 uint8_t sensorhub3 : 8; 835 #endif /* DRV_BYTE_ORDER */ 836 } ism330is_sensor_hub_3_t; 837 838 #define ISM330IS_SENSOR_HUB_4 0x5U 839 typedef struct 840 { 841 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 842 uint8_t sensorhub4 : 8; 843 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 844 uint8_t sensorhub4 : 8; 845 #endif /* DRV_BYTE_ORDER */ 846 } ism330is_sensor_hub_4_t; 847 848 #define ISM330IS_SENSOR_HUB_5 0x6U 849 typedef struct 850 { 851 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 852 uint8_t sensorhub5 : 8; 853 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 854 uint8_t sensorhub5 : 8; 855 #endif /* DRV_BYTE_ORDER */ 856 } ism330is_sensor_hub_5_t; 857 858 #define ISM330IS_SENSOR_HUB_6 0x7U 859 typedef struct 860 { 861 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 862 uint8_t sensorhub6 : 8; 863 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 864 uint8_t sensorhub6 : 8; 865 #endif /* DRV_BYTE_ORDER */ 866 } ism330is_sensor_hub_6_t; 867 868 #define ISM330IS_SENSOR_HUB_7 0x8U 869 typedef struct 870 { 871 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 872 uint8_t sensorhub7 : 8; 873 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 874 uint8_t sensorhub7 : 8; 875 #endif /* DRV_BYTE_ORDER */ 876 } ism330is_sensor_hub_7_t; 877 878 #define ISM330IS_SENSOR_HUB_8 0x9U 879 typedef struct 880 { 881 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 882 uint8_t sensorhub8 : 8; 883 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 884 uint8_t sensorhub8 : 8; 885 #endif /* DRV_BYTE_ORDER */ 886 } ism330is_sensor_hub_8_t; 887 888 #define ISM330IS_SENSOR_HUB_9 0x0AU 889 typedef struct 890 { 891 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 892 uint8_t sensorhub9 : 8; 893 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 894 uint8_t sensorhub9 : 8; 895 #endif /* DRV_BYTE_ORDER */ 896 } ism330is_sensor_hub_9_t; 897 898 #define ISM330IS_SENSOR_HUB_10 0x0BU 899 typedef struct 900 { 901 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 902 uint8_t sensorhub10 : 8; 903 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 904 uint8_t sensorhub10 : 8; 905 #endif /* DRV_BYTE_ORDER */ 906 } ism330is_sensor_hub_10_t; 907 908 #define ISM330IS_SENSOR_HUB_11 0x0CU 909 typedef struct 910 { 911 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 912 uint8_t sensorhub11 : 8; 913 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 914 uint8_t sensorhub11 : 8; 915 #endif /* DRV_BYTE_ORDER */ 916 } ism330is_sensor_hub_11_t; 917 918 #define ISM330IS_SENSOR_HUB_12 0x0DU 919 typedef struct 920 { 921 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 922 uint8_t sensorhub12 : 8; 923 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 924 uint8_t sensorhub12 : 8; 925 #endif /* DRV_BYTE_ORDER */ 926 } ism330is_sensor_hub_12_t; 927 928 #define ISM330IS_SENSOR_HUB_13 0x0EU 929 typedef struct 930 { 931 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 932 uint8_t sensorhub13 : 8; 933 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 934 uint8_t sensorhub13 : 8; 935 #endif /* DRV_BYTE_ORDER */ 936 } ism330is_sensor_hub_13_t; 937 938 #define ISM330IS_SENSOR_HUB_14 0x0FU 939 typedef struct 940 { 941 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 942 uint8_t sensorhub14 : 8; 943 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 944 uint8_t sensorhub14 : 8; 945 #endif /* DRV_BYTE_ORDER */ 946 } ism330is_sensor_hub_14_t; 947 948 #define ISM330IS_SENSOR_HUB_15 0x10U 949 typedef struct 950 { 951 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 952 uint8_t sensorhub15 : 8; 953 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 954 uint8_t sensorhub15 : 8; 955 #endif /* DRV_BYTE_ORDER */ 956 } ism330is_sensor_hub_15_t; 957 958 #define ISM330IS_SENSOR_HUB_16 0x11U 959 typedef struct 960 { 961 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 962 uint8_t sensorhub16 : 8; 963 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 964 uint8_t sensorhub16 : 8; 965 #endif /* DRV_BYTE_ORDER */ 966 } ism330is_sensor_hub_16_t; 967 968 #define ISM330IS_SENSOR_HUB_17 0x12U 969 typedef struct 970 { 971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 972 uint8_t sensorhub17 : 8; 973 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 974 uint8_t sensorhub17 : 8; 975 #endif /* DRV_BYTE_ORDER */ 976 } ism330is_sensor_hub_17_t; 977 978 #define ISM330IS_SENSOR_HUB_18 0x13U 979 typedef struct 980 { 981 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 982 uint8_t sensorhub18 : 8; 983 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 984 uint8_t sensorhub18 : 8; 985 #endif /* DRV_BYTE_ORDER */ 986 } ism330is_sensor_hub_18_t; 987 988 #define ISM330IS_MASTER_CONFIG 0x14U 989 typedef struct 990 { 991 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 992 uint8_t aux_sens_on : 2; 993 uint8_t master_on : 1; 994 uint8_t shub_pu_en : 1; 995 uint8_t pass_through_mode : 1; 996 uint8_t start_config : 1; 997 uint8_t write_once : 1; 998 uint8_t rst_master_regs : 1; 999 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1000 uint8_t rst_master_regs : 1; 1001 uint8_t write_once : 1; 1002 uint8_t start_config : 1; 1003 uint8_t pass_through_mode : 1; 1004 uint8_t shub_pu_en : 1; 1005 uint8_t master_on : 1; 1006 uint8_t aux_sens_on : 2; 1007 #endif /* DRV_BYTE_ORDER */ 1008 } ism330is_master_config_t; 1009 1010 #define ISM330IS_SLV0_ADD 0x15U 1011 typedef struct 1012 { 1013 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1014 uint8_t rw_0 : 1; 1015 uint8_t slave0_add : 7; 1016 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1017 uint8_t slave0_add : 7; 1018 uint8_t rw_0 : 1; 1019 #endif /* DRV_BYTE_ORDER */ 1020 } ism330is_slv0_add_t; 1021 1022 #define ISM330IS_SLV0_SUBADD 0x16U 1023 typedef struct 1024 { 1025 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1026 uint8_t slave0_reg : 8; 1027 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1028 uint8_t slave0_reg : 8; 1029 #endif /* DRV_BYTE_ORDER */ 1030 } ism330is_slv0_subadd_t; 1031 1032 #define ISM330IS_SLV0_CONFIG 0x17U 1033 typedef struct 1034 { 1035 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1036 uint8_t slave0_numop : 3; 1037 uint8_t not_used0 : 3; 1038 uint8_t shub_odr : 2; 1039 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1040 uint8_t shub_odr : 2; 1041 uint8_t not_used0 : 3; 1042 uint8_t slave0_numop : 3; 1043 #endif /* DRV_BYTE_ORDER */ 1044 } ism330is_slv0_config_t; 1045 1046 #define ISM330IS_SLV1_ADD 0x18U 1047 typedef struct 1048 { 1049 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1050 uint8_t r_1 : 1; 1051 uint8_t slave1_add : 7; 1052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1053 uint8_t slave1_add : 7; 1054 uint8_t r_1 : 1; 1055 #endif /* DRV_BYTE_ORDER */ 1056 } ism330is_slv1_add_t; 1057 1058 #define ISM330IS_SLV1_SUBADD 0x19U 1059 typedef struct 1060 { 1061 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1062 uint8_t slave1_reg : 8; 1063 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1064 uint8_t slave1_reg : 8; 1065 #endif /* DRV_BYTE_ORDER */ 1066 } ism330is_slv1_subadd_t; 1067 1068 #define ISM330IS_SLV1_CONFIG 0x1AU 1069 typedef struct 1070 { 1071 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1072 uint8_t slave1_numop : 3; 1073 uint8_t not_used0 : 5; 1074 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1075 uint8_t not_used0 : 5; 1076 uint8_t slave1_numop : 3; 1077 #endif /* DRV_BYTE_ORDER */ 1078 } ism330is_slv1_config_t; 1079 1080 #define ISM330IS_SLV2_ADD 0x1BU 1081 typedef struct 1082 { 1083 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1084 uint8_t r_2 : 1; 1085 uint8_t slave2_add : 7; 1086 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1087 uint8_t slave2_add : 7; 1088 uint8_t r_2 : 1; 1089 #endif /* DRV_BYTE_ORDER */ 1090 } ism330is_slv2_add_t; 1091 1092 #define ISM330IS_SLV2_SUBADD 0x1CU 1093 typedef struct 1094 { 1095 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1096 uint8_t slave2_reg : 8; 1097 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1098 uint8_t slave2_reg : 8; 1099 #endif /* DRV_BYTE_ORDER */ 1100 } ism330is_slv2_subadd_t; 1101 1102 #define ISM330IS_SLV2_CONFIG 0x1DU 1103 typedef struct 1104 { 1105 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1106 uint8_t slave2_numop : 3; 1107 uint8_t not_used0 : 5; 1108 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1109 uint8_t not_used0 : 5; 1110 uint8_t slave2_numop : 3; 1111 #endif /* DRV_BYTE_ORDER */ 1112 } ism330is_slv2_config_t; 1113 1114 #define ISM330IS_SLV3_ADD 0x1EU 1115 typedef struct 1116 { 1117 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1118 uint8_t r_3 : 1; 1119 uint8_t slave3_add : 7; 1120 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1121 uint8_t slave3_add : 7; 1122 uint8_t r_3 : 1; 1123 #endif /* DRV_BYTE_ORDER */ 1124 } ism330is_slv3_add_t; 1125 1126 #define ISM330IS_SLV3_SUBADD 0x1FU 1127 typedef struct 1128 { 1129 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1130 uint8_t slave3_reg : 8; 1131 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1132 uint8_t slave3_reg : 8; 1133 #endif /* DRV_BYTE_ORDER */ 1134 } ism330is_slv3_subadd_t; 1135 1136 #define ISM330IS_SLV3_CONFIG 0x20U 1137 typedef struct 1138 { 1139 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1140 uint8_t slave3_numop : 3; 1141 uint8_t not_used0 : 5; 1142 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1143 uint8_t not_used0 : 5; 1144 uint8_t slave3_numop : 3; 1145 #endif /* DRV_BYTE_ORDER */ 1146 } ism330is_slv3_config_t; 1147 1148 #define ISM330IS_DATAWRITE_SLV0 0x21U 1149 typedef struct 1150 { 1151 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1152 uint8_t slave0_dataw : 8; 1153 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1154 uint8_t slave0_dataw : 8; 1155 #endif /* DRV_BYTE_ORDER */ 1156 } ism330is_datawrite_slv0_t; 1157 1158 #define ISM330IS_STATUS_MASTER 0x22U 1159 typedef struct 1160 { 1161 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1162 uint8_t sens_hub_endop : 1; 1163 uint8_t not_used0 : 2; 1164 uint8_t slave0_nack : 1; 1165 uint8_t slave1_nack : 1; 1166 uint8_t slave2_nack : 1; 1167 uint8_t slave3_nack : 1; 1168 uint8_t wr_once_done : 1; 1169 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1170 uint8_t wr_once_done : 1; 1171 uint8_t slave3_nack : 1; 1172 uint8_t slave2_nack : 1; 1173 uint8_t slave1_nack : 1; 1174 uint8_t slave0_nack : 1; 1175 uint8_t not_used0 : 2; 1176 uint8_t sens_hub_endop : 1; 1177 #endif /* DRV_BYTE_ORDER */ 1178 } ism330is_status_master_t; 1179 1180 /** 1181 * @} 1182 * 1183 */ 1184 1185 /** @defgroup bitfields page ispu 1186 * @{ 1187 * 1188 */ 1189 1190 #define ISM330IS_ISPU_CONFIG 0x2U 1191 typedef struct 1192 { 1193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1194 uint8_t ispu_rst_n : 1; 1195 uint8_t clk_dis : 1; 1196 uint8_t not_used0 : 2; 1197 uint8_t latched : 1; 1198 uint8_t not_used1 : 3; 1199 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1200 uint8_t not_used1 : 3; 1201 uint8_t latched : 1; 1202 uint8_t not_used0 : 2; 1203 uint8_t clk_dis : 1; 1204 uint8_t ispu_rst_n : 1; 1205 #endif /* DRV_BYTE_ORDER */ 1206 } ism330is_ispu_config_t; 1207 1208 #define ISM330IS_ISPU_STATUS 0x4U 1209 typedef struct 1210 { 1211 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1212 uint8_t not_used0 : 2; 1213 uint8_t boot_end : 1; 1214 uint8_t not_used1 : 5; 1215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1216 uint8_t not_used1 : 5; 1217 uint8_t boot_end : 1; 1218 uint8_t not_used0 : 2; 1219 #endif /* DRV_BYTE_ORDER */ 1220 } ism330is_ispu_status_t; 1221 1222 #define ISM330IS_ISPU_MEM_SEL 0x8U 1223 typedef struct 1224 { 1225 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1226 uint8_t mem_sel : 1; 1227 uint8_t not_used0 : 5; 1228 uint8_t read_mem_en : 1; 1229 uint8_t not_used1 : 1; 1230 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1231 uint8_t not_used1 : 1; 1232 uint8_t read_mem_en : 1; 1233 uint8_t not_used0 : 5; 1234 uint8_t mem_sel : 1; 1235 #endif /* DRV_BYTE_ORDER */ 1236 } ism330is_ispu_mem_sel_t; 1237 1238 #define ISM330IS_ISPU_MEM_ADDR1 0x9U 1239 typedef struct 1240 { 1241 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1242 uint8_t mem_addr : 8; 1243 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1244 uint8_t mem_addr : 8; 1245 #endif /* DRV_BYTE_ORDER */ 1246 } ism330is_ispu_mem_addr1_t; 1247 1248 #define ISM330IS_ISPU_MEM_ADDR0 0x0AU 1249 typedef struct 1250 { 1251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1252 uint8_t mem_addr : 8; 1253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1254 uint8_t mem_addr : 8; 1255 #endif /* DRV_BYTE_ORDER */ 1256 } ism330is_ispu_mem_addr0_t; 1257 1258 #define ISM330IS_ISPU_MEM_DATA 0x0BU 1259 typedef struct 1260 { 1261 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1262 uint8_t mem_data : 8; 1263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1264 uint8_t mem_data : 8; 1265 #endif /* DRV_BYTE_ORDER */ 1266 } ism330is_ispu_mem_data_t; 1267 1268 #define ISM330IS_ISPU_IF2S_FLAG_L 0x0CU 1269 typedef struct 1270 { 1271 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1272 uint8_t if2s : 8; 1273 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1274 uint8_t if2s : 8; 1275 #endif /* DRV_BYTE_ORDER */ 1276 } ism330is_ispu_if2s_flag_l_t; 1277 1278 #define ISM330IS_ISPU_IF2S_FLAG_H 0x0DU 1279 typedef struct 1280 { 1281 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1282 uint8_t if2s : 8; 1283 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1284 uint8_t if2s : 8; 1285 #endif /* DRV_BYTE_ORDER */ 1286 } ism330is_ispu_if2s_flag_h_t; 1287 1288 #define ISM330IS_ISPU_S2IF_FLAG_L 0x0EU 1289 typedef struct 1290 { 1291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1292 uint8_t s2if : 8; 1293 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1294 uint8_t s2if : 8; 1295 #endif /* DRV_BYTE_ORDER */ 1296 } ism330is_ispu_s2if_flag_l_t; 1297 1298 #define ISM330IS_ISPU_S2IF_FLAG_H 0x0FU 1299 typedef struct 1300 { 1301 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1302 uint8_t s2if : 8; 1303 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1304 uint8_t s2if : 8; 1305 #endif /* DRV_BYTE_ORDER */ 1306 } ism330is_ispu_s2if_flag_h_t; 1307 1308 #define ISM330IS_ISPU_DOUT_00_L 0x10U 1309 typedef struct 1310 { 1311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1312 uint8_t dout0 : 8; 1313 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1314 uint8_t dout0 : 8; 1315 #endif /* DRV_BYTE_ORDER */ 1316 } ism330is_ispu_dout_00_l_t; 1317 1318 #define ISM330IS_ISPU_DOUT_00_H 0x11U 1319 typedef struct 1320 { 1321 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1322 uint8_t dout0 : 8; 1323 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1324 uint8_t dout0 : 8; 1325 #endif /* DRV_BYTE_ORDER */ 1326 } ism330is_ispu_dout_00_h_t; 1327 1328 #define ISM330IS_ISPU_DOUT_01_L 0x12U 1329 typedef struct 1330 { 1331 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1332 uint8_t dout1 : 8; 1333 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1334 uint8_t dout1 : 8; 1335 #endif /* DRV_BYTE_ORDER */ 1336 } ism330is_ispu_dout_01_l_t; 1337 1338 #define ISM330IS_ISPU_DOUT_01_H 0x13U 1339 typedef struct 1340 { 1341 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1342 uint8_t dout1 : 8; 1343 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1344 uint8_t dout1 : 8; 1345 #endif /* DRV_BYTE_ORDER */ 1346 } ism330is_ispu_dout_01_h_t; 1347 1348 #define ISM330IS_ISPU_DOUT_02_L 0x14U 1349 typedef struct 1350 { 1351 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1352 uint8_t dout2 : 8; 1353 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1354 uint8_t dout2 : 8; 1355 #endif /* DRV_BYTE_ORDER */ 1356 } ism330is_ispu_dout_02_l_t; 1357 1358 #define ISM330IS_ISPU_DOUT_02_H 0x15U 1359 typedef struct 1360 { 1361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1362 uint8_t dout2 : 8; 1363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1364 uint8_t dout2 : 8; 1365 #endif /* DRV_BYTE_ORDER */ 1366 } ism330is_ispu_dout_02_h_t; 1367 1368 #define ISM330IS_ISPU_DOUT_03_L 0x16U 1369 typedef struct 1370 { 1371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1372 uint8_t dout3 : 8; 1373 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1374 uint8_t dout3 : 8; 1375 #endif /* DRV_BYTE_ORDER */ 1376 } ism330is_ispu_dout_03_l_t; 1377 1378 #define ISM330IS_ISPU_DOUT_03_H 0x17U 1379 typedef struct 1380 { 1381 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1382 uint8_t dout3 : 8; 1383 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1384 uint8_t dout3 : 8; 1385 #endif /* DRV_BYTE_ORDER */ 1386 } ism330is_ispu_dout_03_h_t; 1387 1388 #define ISM330IS_ISPU_DOUT_04_L 0x18U 1389 typedef struct 1390 { 1391 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1392 uint8_t dout4 : 8; 1393 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1394 uint8_t dout4 : 8; 1395 #endif /* DRV_BYTE_ORDER */ 1396 } ism330is_ispu_dout_04_l_t; 1397 1398 #define ISM330IS_ISPU_DOUT_04_H 0x19U 1399 typedef struct 1400 { 1401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1402 uint8_t dout4 : 8; 1403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1404 uint8_t dout4 : 8; 1405 #endif /* DRV_BYTE_ORDER */ 1406 } ism330is_ispu_dout_04_h_t; 1407 1408 #define ISM330IS_ISPU_DOUT_05_L 0x1AU 1409 typedef struct 1410 { 1411 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1412 uint8_t dout5 : 8; 1413 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1414 uint8_t dout5 : 8; 1415 #endif /* DRV_BYTE_ORDER */ 1416 } ism330is_ispu_dout_05_l_t; 1417 1418 #define ISM330IS_ISPU_DOUT_05_H 0x1BU 1419 typedef struct 1420 { 1421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1422 uint8_t dout5 : 8; 1423 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1424 uint8_t dout5 : 8; 1425 #endif /* DRV_BYTE_ORDER */ 1426 } ism330is_ispu_dout_05_h_t; 1427 1428 #define ISM330IS_ISPU_DOUT_06_L 0x1CU 1429 typedef struct 1430 { 1431 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1432 uint8_t dout6 : 8; 1433 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1434 uint8_t dout6 : 8; 1435 #endif /* DRV_BYTE_ORDER */ 1436 } ism330is_ispu_dout_06_l_t; 1437 1438 #define ISM330IS_ISPU_DOUT_06_H 0x1DU 1439 typedef struct 1440 { 1441 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1442 uint8_t dout6 : 8; 1443 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1444 uint8_t dout6 : 8; 1445 #endif /* DRV_BYTE_ORDER */ 1446 } ism330is_ispu_dout_06_h_t; 1447 1448 #define ISM330IS_ISPU_DOUT_07_L 0x1EU 1449 typedef struct 1450 { 1451 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1452 uint8_t dout7 : 8; 1453 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1454 uint8_t dout7 : 8; 1455 #endif /* DRV_BYTE_ORDER */ 1456 } ism330is_ispu_dout_07_l_t; 1457 1458 #define ISM330IS_ISPU_DOUT_07_H 0x1FU 1459 typedef struct 1460 { 1461 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1462 uint8_t dout7 : 8; 1463 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1464 uint8_t dout7 : 8; 1465 #endif /* DRV_BYTE_ORDER */ 1466 } ism330is_ispu_dout_07_h_t; 1467 1468 #define ISM330IS_ISPU_DOUT_08_L 0x20U 1469 typedef struct 1470 { 1471 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1472 uint8_t dout8 : 8; 1473 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1474 uint8_t dout8 : 8; 1475 #endif /* DRV_BYTE_ORDER */ 1476 } ism330is_ispu_dout_08_l_t; 1477 1478 #define ISM330IS_ISPU_DOUT_08_H 0x21U 1479 typedef struct 1480 { 1481 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1482 uint8_t dout8 : 8; 1483 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1484 uint8_t dout8 : 8; 1485 #endif /* DRV_BYTE_ORDER */ 1486 } ism330is_ispu_dout_08_h_t; 1487 1488 #define ISM330IS_ISPU_DOUT_09_L 0x22U 1489 typedef struct 1490 { 1491 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1492 uint8_t dout9 : 8; 1493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1494 uint8_t dout9 : 8; 1495 #endif /* DRV_BYTE_ORDER */ 1496 } ism330is_ispu_dout_09_l_t; 1497 1498 #define ISM330IS_ISPU_DOUT_09_H 0x23U 1499 typedef struct 1500 { 1501 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1502 uint8_t dout9 : 8; 1503 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1504 uint8_t dout9 : 8; 1505 #endif /* DRV_BYTE_ORDER */ 1506 } ism330is_ispu_dout_09_h_t; 1507 1508 #define ISM330IS_ISPU_DOUT_10_L 0x24U 1509 typedef struct 1510 { 1511 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1512 uint8_t dout10 : 8; 1513 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1514 uint8_t dout10 : 8; 1515 #endif /* DRV_BYTE_ORDER */ 1516 } ism330is_ispu_dout_10_l_t; 1517 1518 #define ISM330IS_ISPU_DOUT_10_H 0x25U 1519 typedef struct 1520 { 1521 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1522 uint8_t dout10 : 8; 1523 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1524 uint8_t dout10 : 8; 1525 #endif /* DRV_BYTE_ORDER */ 1526 } ism330is_ispu_dout_10_h_t; 1527 1528 #define ISM330IS_ISPU_DOUT_11_L 0x26U 1529 typedef struct 1530 { 1531 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1532 uint8_t dout11 : 8; 1533 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1534 uint8_t dout11 : 8; 1535 #endif /* DRV_BYTE_ORDER */ 1536 } ism330is_ispu_dout_11_l_t; 1537 1538 #define ISM330IS_ISPU_DOUT_11_H 0x27U 1539 typedef struct 1540 { 1541 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1542 uint8_t dout11 : 8; 1543 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1544 uint8_t dout11 : 8; 1545 #endif /* DRV_BYTE_ORDER */ 1546 } ism330is_ispu_dout_11_h_t; 1547 1548 #define ISM330IS_ISPU_DOUT_12_L 0x28U 1549 typedef struct 1550 { 1551 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1552 uint8_t dout12 : 8; 1553 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1554 uint8_t dout12 : 8; 1555 #endif /* DRV_BYTE_ORDER */ 1556 } ism330is_ispu_dout_12_l_t; 1557 1558 #define ISM330IS_ISPU_DOUT_12_H 0x29U 1559 typedef struct 1560 { 1561 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1562 uint8_t dout12 : 8; 1563 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1564 uint8_t dout12 : 8; 1565 #endif /* DRV_BYTE_ORDER */ 1566 } ism330is_ispu_dout_12_h_t; 1567 1568 #define ISM330IS_ISPU_DOUT_13_L 0x2AU 1569 typedef struct 1570 { 1571 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1572 uint8_t dout13 : 8; 1573 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1574 uint8_t dout13 : 8; 1575 #endif /* DRV_BYTE_ORDER */ 1576 } ism330is_ispu_dout_13_l_t; 1577 1578 #define ISM330IS_ISPU_DOUT_13_H 0x2BU 1579 typedef struct 1580 { 1581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1582 uint8_t dout13 : 8; 1583 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1584 uint8_t dout13 : 8; 1585 #endif /* DRV_BYTE_ORDER */ 1586 } ism330is_ispu_dout_13_h_t; 1587 1588 #define ISM330IS_ISPU_DOUT_14_L 0x2CU 1589 typedef struct 1590 { 1591 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1592 uint8_t dout14 : 8; 1593 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1594 uint8_t dout14 : 8; 1595 #endif /* DRV_BYTE_ORDER */ 1596 } ism330is_ispu_dout_14_l_t; 1597 1598 #define ISM330IS_ISPU_DOUT_14_H 0x2DU 1599 typedef struct 1600 { 1601 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1602 uint8_t dout14 : 8; 1603 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1604 uint8_t dout14 : 8; 1605 #endif /* DRV_BYTE_ORDER */ 1606 } ism330is_ispu_dout_14_h_t; 1607 1608 #define ISM330IS_ISPU_DOUT_15_L 0x2EU 1609 typedef struct 1610 { 1611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1612 uint8_t dout15 : 8; 1613 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1614 uint8_t dout15 : 8; 1615 #endif /* DRV_BYTE_ORDER */ 1616 } ism330is_ispu_dout_15_l_t; 1617 1618 #define ISM330IS_ISPU_DOUT_15_H 0x2FU 1619 typedef struct 1620 { 1621 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1622 uint8_t dout15 : 8; 1623 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1624 uint8_t dout15 : 8; 1625 #endif /* DRV_BYTE_ORDER */ 1626 } ism330is_ispu_dout_15_h_t; 1627 1628 #define ISM330IS_ISPU_DOUT_16_L 0x30U 1629 typedef struct 1630 { 1631 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1632 uint8_t dout16 : 8; 1633 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1634 uint8_t dout16 : 8; 1635 #endif /* DRV_BYTE_ORDER */ 1636 } ism330is_ispu_dout_16_l_t; 1637 1638 #define ISM330IS_ISPU_DOUT_16_H 0x31U 1639 typedef struct 1640 { 1641 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1642 uint8_t dout16 : 8; 1643 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1644 uint8_t dout16 : 8; 1645 #endif /* DRV_BYTE_ORDER */ 1646 } ism330is_ispu_dout_16_h_t; 1647 1648 #define ISM330IS_ISPU_DOUT_17_L 0x32U 1649 typedef struct 1650 { 1651 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1652 uint8_t dout17 : 8; 1653 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1654 uint8_t dout17 : 8; 1655 #endif /* DRV_BYTE_ORDER */ 1656 } ism330is_ispu_dout_17_l_t; 1657 1658 #define ISM330IS_ISPU_DOUT_17_H 0x33U 1659 typedef struct 1660 { 1661 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1662 uint8_t dout17 : 8; 1663 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1664 uint8_t dout17 : 8; 1665 #endif /* DRV_BYTE_ORDER */ 1666 } ism330is_ispu_dout_17_h_t; 1667 1668 #define ISM330IS_ISPU_DOUT_18_L 0x34U 1669 typedef struct 1670 { 1671 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1672 uint8_t dout18 : 8; 1673 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1674 uint8_t dout18 : 8; 1675 #endif /* DRV_BYTE_ORDER */ 1676 } ism330is_ispu_dout_18_l_t; 1677 1678 #define ISM330IS_ISPU_DOUT_18_H 0x35U 1679 typedef struct 1680 { 1681 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1682 uint8_t dout18 : 8; 1683 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1684 uint8_t dout18 : 8; 1685 #endif /* DRV_BYTE_ORDER */ 1686 } ism330is_ispu_dout_18_h_t; 1687 1688 #define ISM330IS_ISPU_DOUT_19_L 0x36U 1689 typedef struct 1690 { 1691 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1692 uint8_t dout19 : 8; 1693 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1694 uint8_t dout19 : 8; 1695 #endif /* DRV_BYTE_ORDER */ 1696 } ism330is_ispu_dout_19_l_t; 1697 1698 #define ISM330IS_ISPU_DOUT_19_H 0x37U 1699 typedef struct 1700 { 1701 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1702 uint8_t dout19 : 8; 1703 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1704 uint8_t dout19 : 8; 1705 #endif /* DRV_BYTE_ORDER */ 1706 } ism330is_ispu_dout_19_h_t; 1707 1708 #define ISM330IS_ISPU_DOUT_20_L 0x38U 1709 typedef struct 1710 { 1711 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1712 uint8_t dout20 : 8; 1713 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1714 uint8_t dout20 : 8; 1715 #endif /* DRV_BYTE_ORDER */ 1716 } ism330is_ispu_dout_20_l_t; 1717 1718 #define ISM330IS_ISPU_DOUT_20_H 0x39U 1719 typedef struct 1720 { 1721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1722 uint8_t dout20 : 8; 1723 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1724 uint8_t dout20 : 8; 1725 #endif /* DRV_BYTE_ORDER */ 1726 } ism330is_ispu_dout_20_h_t; 1727 1728 #define ISM330IS_ISPU_DOUT_21_L 0x3AU 1729 typedef struct 1730 { 1731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1732 uint8_t dout21 : 8; 1733 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1734 uint8_t dout21 : 8; 1735 #endif /* DRV_BYTE_ORDER */ 1736 } ism330is_ispu_dout_21_l_t; 1737 1738 #define ISM330IS_ISPU_DOUT_21_H 0x3BU 1739 typedef struct 1740 { 1741 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1742 uint8_t dout21 : 8; 1743 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1744 uint8_t dout21 : 8; 1745 #endif /* DRV_BYTE_ORDER */ 1746 } ism330is_ispu_dout_21_h_t; 1747 1748 #define ISM330IS_ISPU_DOUT_22_L 0x3CU 1749 typedef struct 1750 { 1751 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1752 uint8_t dout22 : 8; 1753 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1754 uint8_t dout22 : 8; 1755 #endif /* DRV_BYTE_ORDER */ 1756 } ism330is_ispu_dout_22_l_t; 1757 1758 #define ISM330IS_ISPU_DOUT_22_H 0x3DU 1759 typedef struct 1760 { 1761 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1762 uint8_t dout22 : 8; 1763 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1764 uint8_t dout22 : 8; 1765 #endif /* DRV_BYTE_ORDER */ 1766 } ism330is_ispu_dout_22_h_t; 1767 1768 #define ISM330IS_ISPU_DOUT_23_L 0x3EU 1769 typedef struct 1770 { 1771 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1772 uint8_t dout23 : 8; 1773 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1774 uint8_t dout23 : 8; 1775 #endif /* DRV_BYTE_ORDER */ 1776 } ism330is_ispu_dout_23_l_t; 1777 1778 #define ISM330IS_ISPU_DOUT_23_H 0x3FU 1779 typedef struct 1780 { 1781 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1782 uint8_t dout23 : 8; 1783 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1784 uint8_t dout23 : 8; 1785 #endif /* DRV_BYTE_ORDER */ 1786 } ism330is_ispu_dout_23_h_t; 1787 1788 #define ISM330IS_ISPU_DOUT_24_L 0x40U 1789 typedef struct 1790 { 1791 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1792 uint8_t dout24 : 8; 1793 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1794 uint8_t dout24 : 8; 1795 #endif /* DRV_BYTE_ORDER */ 1796 } ism330is_ispu_dout_24_l_t; 1797 1798 #define ISM330IS_ISPU_DOUT_24_H 0x41U 1799 typedef struct 1800 { 1801 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1802 uint8_t dout24 : 8; 1803 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1804 uint8_t dout24 : 8; 1805 #endif /* DRV_BYTE_ORDER */ 1806 } ism330is_ispu_dout_24_h_t; 1807 1808 #define ISM330IS_ISPU_DOUT_25_L 0x42U 1809 typedef struct 1810 { 1811 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1812 uint8_t dout25 : 8; 1813 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1814 uint8_t dout25 : 8; 1815 #endif /* DRV_BYTE_ORDER */ 1816 } ism330is_ispu_dout_25_l_t; 1817 1818 #define ISM330IS_ISPU_DOUT_25_H 0x43U 1819 typedef struct 1820 { 1821 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1822 uint8_t dout25 : 8; 1823 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1824 uint8_t dout25 : 8; 1825 #endif /* DRV_BYTE_ORDER */ 1826 } ism330is_ispu_dout_25_h_t; 1827 1828 #define ISM330IS_ISPU_DOUT_26_L 0x44U 1829 typedef struct 1830 { 1831 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1832 uint8_t dout26 : 8; 1833 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1834 uint8_t dout26 : 8; 1835 #endif /* DRV_BYTE_ORDER */ 1836 } ism330is_ispu_dout_26_l_t; 1837 1838 #define ISM330IS_ISPU_DOUT_26_H 0x45U 1839 typedef struct 1840 { 1841 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1842 uint8_t dout26 : 8; 1843 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1844 uint8_t dout26 : 8; 1845 #endif /* DRV_BYTE_ORDER */ 1846 } ism330is_ispu_dout_26_h_t; 1847 1848 #define ISM330IS_ISPU_DOUT_27_L 0x46U 1849 typedef struct 1850 { 1851 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1852 uint8_t dout27 : 8; 1853 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1854 uint8_t dout27 : 8; 1855 #endif /* DRV_BYTE_ORDER */ 1856 } ism330is_ispu_dout_27_l_t; 1857 1858 #define ISM330IS_ISPU_DOUT_27_H 0x47U 1859 typedef struct 1860 { 1861 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1862 uint8_t dout27 : 8; 1863 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1864 uint8_t dout27 : 8; 1865 #endif /* DRV_BYTE_ORDER */ 1866 } ism330is_ispu_dout_27_h_t; 1867 1868 #define ISM330IS_ISPU_DOUT_28_L 0x48U 1869 typedef struct 1870 { 1871 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1872 uint8_t dout28 : 8; 1873 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1874 uint8_t dout28 : 8; 1875 #endif /* DRV_BYTE_ORDER */ 1876 } ism330is_ispu_dout_28_l_t; 1877 1878 #define ISM330IS_ISPU_DOUT_28_H 0x49U 1879 typedef struct 1880 { 1881 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1882 uint8_t dout28 : 8; 1883 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1884 uint8_t dout28 : 8; 1885 #endif /* DRV_BYTE_ORDER */ 1886 } ism330is_ispu_dout_28_h_t; 1887 1888 #define ISM330IS_ISPU_DOUT_29_L 0x4AU 1889 typedef struct 1890 { 1891 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1892 uint8_t dout29 : 8; 1893 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1894 uint8_t dout29 : 8; 1895 #endif /* DRV_BYTE_ORDER */ 1896 } ism330is_ispu_dout_29_l_t; 1897 1898 #define ISM330IS_ISPU_DOUT_29_H 0x4BU 1899 typedef struct 1900 { 1901 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1902 uint8_t dout29 : 8; 1903 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1904 uint8_t dout29 : 8; 1905 #endif /* DRV_BYTE_ORDER */ 1906 } ism330is_ispu_dout_29_h_t; 1907 1908 #define ISM330IS_ISPU_DOUT_30_L 0x4CU 1909 typedef struct 1910 { 1911 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1912 uint8_t dout30 : 8; 1913 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1914 uint8_t dout30 : 8; 1915 #endif /* DRV_BYTE_ORDER */ 1916 } ism330is_ispu_dout_30_l_t; 1917 1918 #define ISM330IS_ISPU_DOUT_30_H 0x4DU 1919 typedef struct 1920 { 1921 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1922 uint8_t dout30 : 8; 1923 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1924 uint8_t dout30 : 8; 1925 #endif /* DRV_BYTE_ORDER */ 1926 } ism330is_ispu_dout_30_h_t; 1927 1928 #define ISM330IS_ISPU_DOUT_31_L 0x4EU 1929 typedef struct 1930 { 1931 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1932 uint8_t dout31 : 8; 1933 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1934 uint8_t dout31 : 8; 1935 #endif /* DRV_BYTE_ORDER */ 1936 } ism330is_ispu_dout_31_l_t; 1937 1938 #define ISM330IS_ISPU_DOUT_31_H 0x4FU 1939 typedef struct 1940 { 1941 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1942 uint8_t dout31 : 8; 1943 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1944 uint8_t dout31 : 8; 1945 #endif /* DRV_BYTE_ORDER */ 1946 } ism330is_ispu_dout_31_h_t; 1947 1948 #define ISM330IS_ISPU_INT1_CTRL0 0x50U 1949 typedef struct 1950 { 1951 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1952 uint8_t ispu_int1_ctrl : 8; 1953 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1954 uint8_t ispu_int1_ctrl : 8; 1955 #endif /* DRV_BYTE_ORDER */ 1956 } ism330is_ispu_int1_ctrl0_t; 1957 1958 #define ISM330IS_ISPU_INT1_CTRL1 0x51U 1959 typedef struct 1960 { 1961 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1962 uint8_t ispu_int1_ctrl : 8; 1963 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1964 uint8_t ispu_int1_ctrl : 8; 1965 #endif /* DRV_BYTE_ORDER */ 1966 } ism330is_ispu_int1_ctrl1_t; 1967 1968 #define ISM330IS_ISPU_INT1_CTRL2 0x52U 1969 typedef struct 1970 { 1971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1972 uint8_t ispu_int1_ctrl : 8; 1973 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1974 uint8_t ispu_int1_ctrl : 8; 1975 #endif /* DRV_BYTE_ORDER */ 1976 } ism330is_ispu_int1_ctrl2_t; 1977 1978 #define ISM330IS_ISPU_INT1_CTRL3 0x53U 1979 typedef struct 1980 { 1981 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1982 uint8_t ispu_int1_ctrl : 6; 1983 uint8_t not_used0 : 2; 1984 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1985 uint8_t not_used0 : 2; 1986 uint8_t ispu_int1_ctrl : 6; 1987 #endif /* DRV_BYTE_ORDER */ 1988 } ism330is_ispu_int1_ctrl3_t; 1989 1990 #define ISM330IS_ISPU_INT2_CTRL0 0x54U 1991 typedef struct 1992 { 1993 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1994 uint8_t ispu_int2_ctrl : 8; 1995 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1996 uint8_t ispu_int2_ctrl : 8; 1997 #endif /* DRV_BYTE_ORDER */ 1998 } ism330is_ispu_int2_ctrl0_t; 1999 2000 #define ISM330IS_ISPU_INT2_CTRL1 0x55U 2001 typedef struct 2002 { 2003 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2004 uint8_t ispu_int2_ctrl : 8; 2005 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2006 uint8_t ispu_int2_ctrl : 8; 2007 #endif /* DRV_BYTE_ORDER */ 2008 } ism330is_ispu_int2_ctrl1_t; 2009 2010 #define ISM330IS_ISPU_INT2_CTRL2 0x56U 2011 typedef struct 2012 { 2013 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2014 uint8_t ispu_int2_ctrl : 8; 2015 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2016 uint8_t ispu_int2_ctrl : 8; 2017 #endif /* DRV_BYTE_ORDER */ 2018 } ism330is_ispu_int2_ctrl2_t; 2019 2020 #define ISM330IS_ISPU_INT2_CTRL3 0x57U 2021 typedef struct 2022 { 2023 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2024 uint8_t ispu_int2_ctrl : 6; 2025 uint8_t not_used0 : 2; 2026 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2027 uint8_t not_used0 : 2; 2028 uint8_t ispu_int2_ctrl : 6; 2029 #endif /* DRV_BYTE_ORDER */ 2030 } ism330is_ispu_int2_ctrl3_t; 2031 2032 #define ISM330IS_ISPU_INT_STATUS0 0x58U 2033 typedef struct 2034 { 2035 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2036 uint8_t ispu_int_status : 8; 2037 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2038 uint8_t ispu_int_status : 8; 2039 #endif /* DRV_BYTE_ORDER */ 2040 } ism330is_ispu_int_status0_t; 2041 2042 #define ISM330IS_ISPU_INT_STATUS1 0x59U 2043 typedef struct 2044 { 2045 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2046 uint8_t ispu_int_status : 8; 2047 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2048 uint8_t ispu_int_status : 8; 2049 #endif /* DRV_BYTE_ORDER */ 2050 } ism330is_ispu_int_status1_t; 2051 2052 #define ISM330IS_ISPU_INT_STATUS2 0x5AU 2053 typedef struct 2054 { 2055 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2056 uint8_t ispu_int_status : 8; 2057 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2058 uint8_t ispu_int_status : 8; 2059 #endif /* DRV_BYTE_ORDER */ 2060 } ism330is_ispu_int_status2_t; 2061 2062 #define ISM330IS_ISPU_INT_STATUS3 0x5BU 2063 typedef struct 2064 { 2065 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2066 uint8_t ispu_int_status : 6; 2067 uint8_t not_used0 : 2; 2068 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2069 uint8_t not_used0 : 2; 2070 uint8_t ispu_int_status : 6; 2071 #endif /* DRV_BYTE_ORDER */ 2072 } ism330is_ispu_int_status3_t; 2073 2074 #define ISM330IS_ISPU_ALGO0 0x70U 2075 typedef struct 2076 { 2077 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2078 uint8_t ispu_algo : 8; 2079 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2080 uint8_t ispu_algo : 8; 2081 #endif /* DRV_BYTE_ORDER */ 2082 } ism330is_ispu_algo0_t; 2083 2084 #define ISM330IS_ISPU_ALGO1 0x71U 2085 typedef struct 2086 { 2087 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2088 uint8_t ispu_algo : 8; 2089 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2090 uint8_t ispu_algo : 8; 2091 #endif /* DRV_BYTE_ORDER */ 2092 } ism330is_ispu_algo1_t; 2093 2094 #define ISM330IS_ISPU_ALGO2 0x72U 2095 typedef struct 2096 { 2097 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2098 uint8_t ispu_algo : 8; 2099 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2100 uint8_t ispu_algo : 8; 2101 #endif /* DRV_BYTE_ORDER */ 2102 } ism330is_ispu_algo2_t; 2103 2104 #define ISM330IS_ISPU_ALGO3 0x73U 2105 typedef struct 2106 { 2107 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2108 uint8_t ispu_algo : 6; 2109 uint8_t not_used0 : 2; 2110 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2111 uint8_t not_used0 : 2; 2112 uint8_t ispu_algo : 6; 2113 #endif /* DRV_BYTE_ORDER */ 2114 } ism330is_ispu_algo3_t; 2115 2116 /** 2117 * @} 2118 * 2119 */ 2120 2121 typedef union 2122 { 2123 ism330is_func_cfg_access_t func_cfg_access; 2124 ism330is_pin_ctrl_t pin_ctrl; 2125 ism330is_drdy_pulsed_reg_t drdy_pulsed_reg; 2126 ism330is_int1_ctrl_t int1_ctrl; 2127 ism330is_int2_ctrl_t int2_ctrl; 2128 ism330is_who_am_i_t who_am_i; 2129 ism330is_ctrl1_xl_t ctrl1_xl; 2130 ism330is_ctrl2_g_t ctrl2_g; 2131 ism330is_ctrl3_c_t ctrl3_c; 2132 ism330is_ctrl4_c_t ctrl4_c; 2133 ism330is_ctrl5_c_t ctrl5_c; 2134 ism330is_ctrl6_c_t ctrl6_c; 2135 ism330is_ctrl7_g_t ctrl7_g; 2136 ism330is_ctrl9_c_t ctrl9_c; 2137 ism330is_ctrl10_c_t ctrl10_c; 2138 ism330is_ispu_int_status0_mainpage_t ispu_int_status0_mainpage; 2139 ism330is_ispu_int_status1_mainpage_t ispu_int_status1_mainpage; 2140 ism330is_ispu_int_status2_mainpage_t ispu_int_status2_mainpage; 2141 ism330is_ispu_int_status3_mainpage_t ispu_int_status3_mainpage; 2142 ism330is_status_reg_t status_reg; 2143 ism330is_out_temp_l_t out_temp_l; 2144 ism330is_out_temp_h_t out_temp_h; 2145 ism330is_outx_l_g_t outx_l_g; 2146 ism330is_outx_h_g_t outx_h_g; 2147 ism330is_outy_l_g_t outy_l_g; 2148 ism330is_outy_h_g_t outy_h_g; 2149 ism330is_outz_l_g_t outz_l_g; 2150 ism330is_outz_h_g_t outz_h_g; 2151 ism330is_outx_l_a_t outx_l_a; 2152 ism330is_outx_h_a_t outx_h_a; 2153 ism330is_outy_l_a_t outy_l_a; 2154 ism330is_outy_h_a_t outy_h_a; 2155 ism330is_outz_l_a_t outz_l_a; 2156 ism330is_outz_h_a_t outz_h_a; 2157 ism330is_status_master_mainpage_t status_master_mainpage; 2158 ism330is_timestamp0_t timestamp0; 2159 ism330is_timestamp1_t timestamp1; 2160 ism330is_timestamp2_t timestamp2; 2161 ism330is_timestamp3_t timestamp3; 2162 ism330is_md1_cfg_t md1_cfg; 2163 ism330is_md2_cfg_t md2_cfg; 2164 ism330is_internal_freq_fine_t internal_freq_fine; 2165 ism330is_ispu_dummy_cfg_1_l_t ispu_dummy_cfg_1_l; 2166 ism330is_ispu_dummy_cfg_1_h_t ispu_dummy_cfg_1_h; 2167 ism330is_ispu_dummy_cfg_2_l_t ispu_dummy_cfg_2_l; 2168 ism330is_ispu_dummy_cfg_2_h_t ispu_dummy_cfg_2_h; 2169 ism330is_ispu_dummy_cfg_3_l_t ispu_dummy_cfg_3_l; 2170 ism330is_ispu_dummy_cfg_3_h_t ispu_dummy_cfg_3_h; 2171 ism330is_ispu_dummy_cfg_4_l_t ispu_dummy_cfg_4_l; 2172 ism330is_ispu_dummy_cfg_4_h_t ispu_dummy_cfg_4_h; 2173 ism330is_sensor_hub_1_t sensor_hub_1; 2174 ism330is_sensor_hub_2_t sensor_hub_2; 2175 ism330is_sensor_hub_3_t sensor_hub_3; 2176 ism330is_sensor_hub_4_t sensor_hub_4; 2177 ism330is_sensor_hub_5_t sensor_hub_5; 2178 ism330is_sensor_hub_6_t sensor_hub_6; 2179 ism330is_sensor_hub_7_t sensor_hub_7; 2180 ism330is_sensor_hub_8_t sensor_hub_8; 2181 ism330is_sensor_hub_9_t sensor_hub_9; 2182 ism330is_sensor_hub_10_t sensor_hub_10; 2183 ism330is_sensor_hub_11_t sensor_hub_11; 2184 ism330is_sensor_hub_12_t sensor_hub_12; 2185 ism330is_sensor_hub_13_t sensor_hub_13; 2186 ism330is_sensor_hub_14_t sensor_hub_14; 2187 ism330is_sensor_hub_15_t sensor_hub_15; 2188 ism330is_sensor_hub_16_t sensor_hub_16; 2189 ism330is_sensor_hub_17_t sensor_hub_17; 2190 ism330is_sensor_hub_18_t sensor_hub_18; 2191 ism330is_master_config_t master_config; 2192 ism330is_slv0_add_t slv0_add; 2193 ism330is_slv0_subadd_t slv0_subadd; 2194 ism330is_slv0_config_t slv0_config; 2195 ism330is_slv1_add_t slv1_add; 2196 ism330is_slv1_subadd_t slv1_subadd; 2197 ism330is_slv1_config_t slv1_config; 2198 ism330is_slv2_add_t slv2_add; 2199 ism330is_slv2_subadd_t slv2_subadd; 2200 ism330is_slv2_config_t slv2_config; 2201 ism330is_slv3_add_t slv3_add; 2202 ism330is_slv3_subadd_t slv3_subadd; 2203 ism330is_slv3_config_t slv3_config; 2204 ism330is_datawrite_slv0_t datawrite_slv0; 2205 ism330is_status_master_t status_master; 2206 ism330is_ispu_config_t ispu_config; 2207 ism330is_ispu_status_t ispu_status; 2208 ism330is_ispu_mem_sel_t ispu_mem_sel; 2209 ism330is_ispu_mem_addr1_t ispu_mem_addr1; 2210 ism330is_ispu_mem_addr0_t ispu_mem_addr0; 2211 ism330is_ispu_mem_data_t ispu_mem_data; 2212 ism330is_ispu_if2s_flag_l_t ispu_if2s_flag_l; 2213 ism330is_ispu_if2s_flag_h_t ispu_if2s_flag_h; 2214 ism330is_ispu_s2if_flag_l_t ispu_s2if_flag_l; 2215 ism330is_ispu_s2if_flag_h_t ispu_s2if_flag_h; 2216 ism330is_ispu_dout_00_l_t ispu_dout_00_l; 2217 ism330is_ispu_dout_00_h_t ispu_dout_00_h; 2218 ism330is_ispu_dout_01_l_t ispu_dout_01_l; 2219 ism330is_ispu_dout_01_h_t ispu_dout_01_h; 2220 ism330is_ispu_dout_02_l_t ispu_dout_02_l; 2221 ism330is_ispu_dout_02_h_t ispu_dout_02_h; 2222 ism330is_ispu_dout_03_l_t ispu_dout_03_l; 2223 ism330is_ispu_dout_03_h_t ispu_dout_03_h; 2224 ism330is_ispu_dout_04_l_t ispu_dout_04_l; 2225 ism330is_ispu_dout_04_h_t ispu_dout_04_h; 2226 ism330is_ispu_dout_05_l_t ispu_dout_05_l; 2227 ism330is_ispu_dout_05_h_t ispu_dout_05_h; 2228 ism330is_ispu_dout_06_l_t ispu_dout_06_l; 2229 ism330is_ispu_dout_06_h_t ispu_dout_06_h; 2230 ism330is_ispu_dout_07_l_t ispu_dout_07_l; 2231 ism330is_ispu_dout_07_h_t ispu_dout_07_h; 2232 ism330is_ispu_dout_08_l_t ispu_dout_08_l; 2233 ism330is_ispu_dout_08_h_t ispu_dout_08_h; 2234 ism330is_ispu_dout_09_l_t ispu_dout_09_l; 2235 ism330is_ispu_dout_09_h_t ispu_dout_09_h; 2236 ism330is_ispu_dout_10_l_t ispu_dout_10_l; 2237 ism330is_ispu_dout_10_h_t ispu_dout_10_h; 2238 ism330is_ispu_dout_11_l_t ispu_dout_11_l; 2239 ism330is_ispu_dout_11_h_t ispu_dout_11_h; 2240 ism330is_ispu_dout_12_l_t ispu_dout_12_l; 2241 ism330is_ispu_dout_12_h_t ispu_dout_12_h; 2242 ism330is_ispu_dout_13_l_t ispu_dout_13_l; 2243 ism330is_ispu_dout_13_h_t ispu_dout_13_h; 2244 ism330is_ispu_dout_14_l_t ispu_dout_14_l; 2245 ism330is_ispu_dout_14_h_t ispu_dout_14_h; 2246 ism330is_ispu_dout_15_l_t ispu_dout_15_l; 2247 ism330is_ispu_dout_15_h_t ispu_dout_15_h; 2248 ism330is_ispu_dout_16_l_t ispu_dout_16_l; 2249 ism330is_ispu_dout_16_h_t ispu_dout_16_h; 2250 ism330is_ispu_dout_17_l_t ispu_dout_17_l; 2251 ism330is_ispu_dout_17_h_t ispu_dout_17_h; 2252 ism330is_ispu_dout_18_l_t ispu_dout_18_l; 2253 ism330is_ispu_dout_18_h_t ispu_dout_18_h; 2254 ism330is_ispu_dout_19_l_t ispu_dout_19_l; 2255 ism330is_ispu_dout_19_h_t ispu_dout_19_h; 2256 ism330is_ispu_dout_20_l_t ispu_dout_20_l; 2257 ism330is_ispu_dout_20_h_t ispu_dout_20_h; 2258 ism330is_ispu_dout_21_l_t ispu_dout_21_l; 2259 ism330is_ispu_dout_21_h_t ispu_dout_21_h; 2260 ism330is_ispu_dout_22_l_t ispu_dout_22_l; 2261 ism330is_ispu_dout_22_h_t ispu_dout_22_h; 2262 ism330is_ispu_dout_23_l_t ispu_dout_23_l; 2263 ism330is_ispu_dout_23_h_t ispu_dout_23_h; 2264 ism330is_ispu_dout_24_l_t ispu_dout_24_l; 2265 ism330is_ispu_dout_24_h_t ispu_dout_24_h; 2266 ism330is_ispu_dout_25_l_t ispu_dout_25_l; 2267 ism330is_ispu_dout_25_h_t ispu_dout_25_h; 2268 ism330is_ispu_dout_26_l_t ispu_dout_26_l; 2269 ism330is_ispu_dout_26_h_t ispu_dout_26_h; 2270 ism330is_ispu_dout_27_l_t ispu_dout_27_l; 2271 ism330is_ispu_dout_27_h_t ispu_dout_27_h; 2272 ism330is_ispu_dout_28_l_t ispu_dout_28_l; 2273 ism330is_ispu_dout_28_h_t ispu_dout_28_h; 2274 ism330is_ispu_dout_29_l_t ispu_dout_29_l; 2275 ism330is_ispu_dout_29_h_t ispu_dout_29_h; 2276 ism330is_ispu_dout_30_l_t ispu_dout_30_l; 2277 ism330is_ispu_dout_30_h_t ispu_dout_30_h; 2278 ism330is_ispu_dout_31_l_t ispu_dout_31_l; 2279 ism330is_ispu_dout_31_h_t ispu_dout_31_h; 2280 ism330is_ispu_int1_ctrl0_t ispu_int1_ctrl0; 2281 ism330is_ispu_int1_ctrl1_t ispu_int1_ctrl1; 2282 ism330is_ispu_int1_ctrl2_t ispu_int1_ctrl2; 2283 ism330is_ispu_int1_ctrl3_t ispu_int1_ctrl3; 2284 ism330is_ispu_int2_ctrl0_t ispu_int2_ctrl0; 2285 ism330is_ispu_int2_ctrl1_t ispu_int2_ctrl1; 2286 ism330is_ispu_int2_ctrl2_t ispu_int2_ctrl2; 2287 ism330is_ispu_int2_ctrl3_t ispu_int2_ctrl3; 2288 ism330is_ispu_int_status0_t ispu_int_status0; 2289 ism330is_ispu_int_status1_t ispu_int_status1; 2290 ism330is_ispu_int_status2_t ispu_int_status2; 2291 ism330is_ispu_int_status3_t ispu_int_status3; 2292 ism330is_ispu_algo0_t ispu_algo0; 2293 ism330is_ispu_algo1_t ispu_algo1; 2294 ism330is_ispu_algo2_t ispu_algo2; 2295 ism330is_ispu_algo3_t ispu_algo3; 2296 bitwise_t bitwise; 2297 uint8_t byte; 2298 } ism330is_reg_t; 2299 2300 /** 2301 * @} 2302 * 2303 */ 2304 2305 #ifndef __weak 2306 #define __weak __attribute__((weak)) 2307 #endif /* __weak */ 2308 2309 /* 2310 * These are the basic platform dependent I/O routines to read 2311 * and write device registers connected on a standard bus. 2312 * The driver keeps offering a default implementation based on function 2313 * pointers to read/write routines for backward compatibility. 2314 * The __weak directive allows the final application to overwrite 2315 * them with a custom implementation. 2316 */ 2317 2318 int32_t ism330is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 2319 uint8_t *data, 2320 uint16_t len); 2321 int32_t ism330is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 2322 uint8_t *data, 2323 uint16_t len); 2324 2325 float_t ism330is_from_fs2g_to_mg(int16_t lsb); 2326 float_t ism330is_from_fs4g_to_mg(int16_t lsb); 2327 float_t ism330is_from_fs8g_to_mg(int16_t lsb); 2328 float_t ism330is_from_fs16g_to_mg(int16_t lsb); 2329 2330 float_t ism330is_from_fs125dps_to_mdps(int16_t lsb); 2331 float_t ism330is_from_fs250dps_to_mdps(int16_t lsb); 2332 float_t ism330is_from_fs500dps_to_mdps(int16_t lsb); 2333 float_t ism330is_from_fs1000dps_to_mdps(int16_t lsb); 2334 float_t ism330is_from_fs2000dps_to_mdps(int16_t lsb); 2335 2336 float_t ism330is_from_lsb_to_celsius(int16_t lsb); 2337 2338 typedef enum 2339 { 2340 ISM330IS_MAIN_MEM_BANK = 0x0, 2341 ISM330IS_SENSOR_HUB_MEM_BANK = 0x2, 2342 ISM330IS_ISPU_MEM_BANK = 0x3, 2343 } ism330is_mem_bank_t; 2344 int32_t ism330is_mem_bank_set(stmdev_ctx_t *ctx, ism330is_mem_bank_t val); 2345 int32_t ism330is_mem_bank_get(stmdev_ctx_t *ctx, ism330is_mem_bank_t *val); 2346 2347 typedef enum 2348 { 2349 ISM330IS_DRDY_LATCHED = 0x0, 2350 ISM330IS_DRDY_PULSED = 0x1, 2351 } ism330is_data_ready_mode_t; 2352 int32_t ism330is_data_ready_mode_set(stmdev_ctx_t *ctx, 2353 ism330is_data_ready_mode_t val); 2354 int32_t ism330is_data_ready_mode_get(stmdev_ctx_t *ctx, 2355 ism330is_data_ready_mode_t *val); 2356 2357 int32_t ism330is_device_id_set(stmdev_ctx_t *ctx, uint8_t val); 2358 int32_t ism330is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); 2359 2360 int32_t ism330is_software_reset(stmdev_ctx_t *ctx); 2361 2362 int32_t ism330is_boot_set(stmdev_ctx_t *ctx, uint8_t val); 2363 int32_t ism330is_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 2364 2365 typedef enum 2366 { 2367 ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED = 0x0, 2368 ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED = 0x1, 2369 } ism330is_hm_mode_t; 2370 int32_t ism330is_xl_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val); 2371 int32_t ism330is_xl_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val); 2372 int32_t ism330is_gy_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val); 2373 int32_t ism330is_gy_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val); 2374 2375 typedef enum 2376 { 2377 ISM330IS_2g = 0x0, 2378 ISM330IS_16g = 0x1, 2379 ISM330IS_4g = 0x2, 2380 ISM330IS_8g = 0x3, 2381 } ism330is_xl_full_scale_t; 2382 int32_t ism330is_xl_full_scale_set(stmdev_ctx_t *ctx, 2383 ism330is_xl_full_scale_t val); 2384 int32_t ism330is_xl_full_scale_get(stmdev_ctx_t *ctx, 2385 ism330is_xl_full_scale_t *val); 2386 2387 typedef enum 2388 { 2389 ISM330IS_XL_ODR_OFF = 0x0, 2390 ISM330IS_XL_ODR_AT_12Hz5_HP = 0x1, 2391 ISM330IS_XL_ODR_AT_26H_HP = 0x2, 2392 ISM330IS_XL_ODR_AT_52Hz_HP = 0x3, 2393 ISM330IS_XL_ODR_AT_104Hz_HP = 0x4, 2394 ISM330IS_XL_ODR_AT_208Hz_HP = 0x5, 2395 ISM330IS_XL_ODR_AT_416Hz_HP = 0x6, 2396 ISM330IS_XL_ODR_AT_833Hz_HP = 0x7, 2397 ISM330IS_XL_ODR_AT_1667Hz_HP = 0x8, 2398 ISM330IS_XL_ODR_AT_3333Hz_HP = 0x9, 2399 ISM330IS_XL_ODR_AT_6667Hz_HP = 0xa, 2400 ISM330IS_XL_ODR_AT_12Hz5_LP = 0x11, 2401 ISM330IS_XL_ODR_AT_26H_LP = 0x12, 2402 ISM330IS_XL_ODR_AT_52Hz_LP = 0x13, 2403 ISM330IS_XL_ODR_AT_104Hz_LP = 0x14, 2404 ISM330IS_XL_ODR_AT_208Hz_LP = 0x15, 2405 ISM330IS_XL_ODR_AT_416Hz_LP = 0x16, 2406 ISM330IS_XL_ODR_AT_833Hz_LP = 0x17, 2407 ISM330IS_XL_ODR_AT_1667Hz_LP = 0x18, 2408 ISM330IS_XL_ODR_AT_3333Hz_LP = 0x19, 2409 ISM330IS_XL_ODR_AT_6667Hz_LP = 0x1a, 2410 ISM330IS_XL_ODR_AT_1Hz6_LP = 0x1b, 2411 } ism330is_xl_data_rate_t; 2412 int32_t ism330is_xl_data_rate_set(stmdev_ctx_t *ctx, 2413 ism330is_xl_data_rate_t val); 2414 int32_t ism330is_xl_data_rate_get(stmdev_ctx_t *ctx, 2415 ism330is_xl_data_rate_t *val); 2416 2417 typedef enum 2418 { 2419 ISM330IS_250dps = 0x0, 2420 ISM330IS_500dps = 0x1, 2421 ISM330IS_1000dps = 0x2, 2422 ISM330IS_2000dps = 0x3, 2423 ISM330IS_125dps = 0x10, 2424 } ism330is_gy_full_scale_t; 2425 int32_t ism330is_gy_full_scale_set(stmdev_ctx_t *ctx, 2426 ism330is_gy_full_scale_t val); 2427 int32_t ism330is_gy_full_scale_get(stmdev_ctx_t *ctx, 2428 ism330is_gy_full_scale_t *val); 2429 2430 typedef enum 2431 { 2432 ISM330IS_GY_ODR_OFF = 0x0, 2433 ISM330IS_GY_ODR_AT_12Hz5_HP = 0x1, 2434 ISM330IS_GY_ODR_AT_26H_HP = 0x2, 2435 ISM330IS_GY_ODR_AT_52Hz_HP = 0x3, 2436 ISM330IS_GY_ODR_AT_104Hz_HP = 0x4, 2437 ISM330IS_GY_ODR_AT_208Hz_HP = 0x5, 2438 ISM330IS_GY_ODR_AT_416Hz_HP = 0x6, 2439 ISM330IS_GY_ODR_AT_833Hz_HP = 0x7, 2440 ISM330IS_GY_ODR_AT_1667Hz_HP = 0x8, 2441 ISM330IS_GY_ODR_AT_3333Hz_HP = 0x9, 2442 ISM330IS_GY_ODR_AT_6667Hz_HP = 0xa, 2443 ISM330IS_GY_ODR_AT_12Hz5_LP = 0x11, 2444 ISM330IS_GY_ODR_AT_26H_LP = 0x12, 2445 ISM330IS_GY_ODR_AT_52Hz_LP = 0x13, 2446 ISM330IS_GY_ODR_AT_104Hz_LP = 0x14, 2447 ISM330IS_GY_ODR_AT_208Hz_LP = 0x15, 2448 ISM330IS_GY_ODR_AT_416Hz_LP = 0x16, 2449 ISM330IS_GY_ODR_AT_833Hz_LP = 0x17, 2450 ISM330IS_GY_ODR_AT_1667Hz_LP = 0x18, 2451 ISM330IS_GY_ODR_AT_3333Hz_LP = 0x19, 2452 ISM330IS_GY_ODR_AT_6667Hz_LP = 0x1a, 2453 } ism330is_gy_data_rate_t; 2454 int32_t ism330is_gy_data_rate_set(stmdev_ctx_t *ctx, 2455 ism330is_gy_data_rate_t val); 2456 int32_t ism330is_gy_data_rate_get(stmdev_ctx_t *ctx, 2457 ism330is_gy_data_rate_t *val); 2458 2459 int32_t ism330is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2460 int32_t ism330is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 2461 2462 int32_t ism330is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 2463 int32_t ism330is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 2464 2465 typedef enum 2466 { 2467 ISM330IS_SLEEP_G_ENABLE = 0x0, 2468 ISM330IS_SLEEP_G_DISABLE = 0x1, 2469 } ism330is_sleep_t; 2470 int32_t ism330is_sleep_set(stmdev_ctx_t *ctx, ism330is_sleep_t val); 2471 int32_t ism330is_sleep_get(stmdev_ctx_t *ctx, ism330is_sleep_t *val); 2472 2473 typedef enum 2474 { 2475 ISM330IS_XL_ST_DISABLE = 0x0, 2476 ISM330IS_XL_ST_POSITIVE = 0x1, 2477 ISM330IS_XL_ST_NEGATIVE = 0x2, 2478 } ism330is_xl_self_test_t; 2479 int32_t ism330is_xl_self_test_set(stmdev_ctx_t *ctx, 2480 ism330is_xl_self_test_t val); 2481 int32_t ism330is_xl_self_test_get(stmdev_ctx_t *ctx, 2482 ism330is_xl_self_test_t *val); 2483 2484 typedef enum 2485 { 2486 ISM330IS_GY_ST_DISABLE = 0x0, 2487 ISM330IS_GY_ST_POSITIVE = 0x1, 2488 ISM330IS_GY_ST_NEGATIVE = 0x3, 2489 } ism330is_gy_self_test_t; 2490 int32_t ism330is_gy_self_test_set(stmdev_ctx_t *ctx, 2491 ism330is_gy_self_test_t val); 2492 int32_t ism330is_gy_self_test_get(stmdev_ctx_t *ctx, 2493 ism330is_gy_self_test_t *val); 2494 2495 int32_t ism330is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); 2496 int32_t ism330is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); 2497 2498 typedef enum 2499 { 2500 ISM330IS_SPI_4_WIRE = 0x0, 2501 ISM330IS_SPI_3_WIRE = 0x1, 2502 } ism330is_spi_mode_t; 2503 int32_t ism330is_spi_mode_set(stmdev_ctx_t *ctx, ism330is_spi_mode_t val); 2504 int32_t ism330is_spi_mode_get(stmdev_ctx_t *ctx, ism330is_spi_mode_t *val); 2505 2506 typedef enum 2507 { 2508 ISM330IS_I2C_ENABLE = 0x0, 2509 ISM330IS_I2C_DISABLE = 0x1, 2510 } ism330is_ui_i2c_mode_t; 2511 int32_t ism330is_ui_i2c_mode_set(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val); 2512 int32_t ism330is_ui_i2c_mode_get(stmdev_ctx_t *ctx, 2513 ism330is_ui_i2c_mode_t *val); 2514 2515 2516 int32_t ism330is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 2517 int32_t ism330is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 2518 2519 int32_t ism330is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); 2520 2521 typedef struct 2522 { 2523 uint8_t drdy_xl : 1; 2524 uint8_t drdy_gy : 1; 2525 uint8_t boot : 1; 2526 uint8_t sh_endop : 1; 2527 uint8_t ispu : 1; 2528 } ism330is_pin_int1_route_t; 2529 int32_t ism330is_pin_int1_route_set(stmdev_ctx_t *ctx, 2530 ism330is_pin_int1_route_t val); 2531 int32_t ism330is_pin_int1_route_get(stmdev_ctx_t *ctx, 2532 ism330is_pin_int1_route_t *val); 2533 2534 typedef struct 2535 { 2536 uint8_t drdy_xl : 1; 2537 uint8_t drdy_gy : 1; 2538 uint8_t drdy_temp : 1; 2539 uint8_t timestamp : 1; 2540 uint8_t ispu_sleep : 1; 2541 uint8_t ispu : 1; 2542 } ism330is_pin_int2_route_t; 2543 int32_t ism330is_pin_int2_route_set(stmdev_ctx_t *ctx, 2544 ism330is_pin_int2_route_t val); 2545 int32_t ism330is_pin_int2_route_get(stmdev_ctx_t *ctx, 2546 ism330is_pin_int2_route_t *val); 2547 2548 typedef enum 2549 { 2550 ISM330IS_PUSH_PULL = 0x0, 2551 ISM330IS_OPEN_DRAIN = 0x1, 2552 } ism330is_int_pin_mode_t; 2553 int32_t ism330is_int_pin_mode_set(stmdev_ctx_t *ctx, 2554 ism330is_int_pin_mode_t val); 2555 int32_t ism330is_int_pin_mode_get(stmdev_ctx_t *ctx, 2556 ism330is_int_pin_mode_t *val); 2557 2558 typedef enum 2559 { 2560 ISM330IS_ACTIVE_HIGH = 0x0, 2561 ISM330IS_ACTIVE_LOW = 0x1, 2562 } ism330is_pin_polarity_t; 2563 int32_t ism330is_pin_polarity_set(stmdev_ctx_t *ctx, 2564 ism330is_pin_polarity_t val); 2565 int32_t ism330is_pin_polarity_get(stmdev_ctx_t *ctx, 2566 ism330is_pin_polarity_t *val); 2567 2568 typedef struct 2569 { 2570 uint8_t drdy_xl : 1; 2571 uint8_t drdy_gy : 1; 2572 uint8_t drdy_temp : 1; 2573 uint8_t sh_endop : 1; 2574 uint8_t sh_slave0_nack : 1; 2575 uint8_t sh_slave1_nack : 1; 2576 uint8_t sh_slave2_nack : 1; 2577 uint8_t sh_slave3_nack : 1; 2578 uint8_t sh_wr_once : 1; 2579 uint32_t ispu : 30; 2580 } ism330is_all_sources_t; 2581 int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, 2582 ism330is_all_sources_t *val); 2583 2584 int32_t ism330is_status_reg_get(stmdev_ctx_t *ctx, 2585 ism330is_status_reg_t *val); 2586 2587 int32_t ism330is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 2588 uint8_t *val); 2589 2590 int32_t ism330is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 2591 uint8_t *val); 2592 2593 int32_t ism330is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 2594 uint8_t *val); 2595 2596 int32_t ism330is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2597 2598 int32_t ism330is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2599 2600 int32_t ism330is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2601 2602 int32_t ism330is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); 2603 int32_t ism330is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); 2604 2605 int32_t ism330is_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, 2606 uint8_t len); 2607 2608 typedef enum 2609 { 2610 ISM330IS_SLV_0 = 0x0, 2611 ISM330IS_SLV_0_1 = 0x1, 2612 ISM330IS_SLV_0_1_2 = 0x2, 2613 ISM330IS_SLV_0_1_2_3 = 0x3, 2614 } ism330is_sh_slave_connected_t; 2615 int32_t ism330is_sh_slave_connected_set(stmdev_ctx_t *ctx, 2616 ism330is_sh_slave_connected_t val); 2617 int32_t ism330is_sh_slave_connected_get(stmdev_ctx_t *ctx, 2618 ism330is_sh_slave_connected_t *val); 2619 2620 int32_t ism330is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 2621 int32_t ism330is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 2622 2623 int32_t ism330is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, 2624 uint8_t val); 2625 int32_t ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, 2626 uint8_t *val); 2627 2628 int32_t ism330is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 2629 int32_t ism330is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); 2630 2631 typedef enum 2632 { 2633 ISM330IS_SH_TRG_XL_GY_DRDY = 0x0, 2634 ISM330IS_SH_TRIG_INT2 = 0x1, 2635 } ism330is_sh_syncro_mode_t; 2636 int32_t ism330is_sh_syncro_mode_set(stmdev_ctx_t *ctx, 2637 ism330is_sh_syncro_mode_t val); 2638 int32_t ism330is_sh_syncro_mode_get(stmdev_ctx_t *ctx, 2639 ism330is_sh_syncro_mode_t *val); 2640 2641 typedef enum 2642 { 2643 ISM330IS_EACH_SH_CYCLE = 0x0, 2644 ISM330IS_ONLY_FIRST_CYCLE = 0x1, 2645 } ism330is_sh_write_mode_t; 2646 int32_t ism330is_sh_write_mode_set(stmdev_ctx_t *ctx, 2647 ism330is_sh_write_mode_t val); 2648 int32_t ism330is_sh_write_mode_get(stmdev_ctx_t *ctx, 2649 ism330is_sh_write_mode_t *val); 2650 2651 int32_t ism330is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2652 int32_t ism330is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2653 2654 typedef struct 2655 { 2656 uint8_t slv0_add; 2657 uint8_t slv0_subadd; 2658 uint8_t slv0_data; 2659 } ism330is_sh_cfg_write_t; 2660 int32_t ism330is_sh_cfg_write(stmdev_ctx_t *ctx, 2661 ism330is_sh_cfg_write_t *val); 2662 typedef enum 2663 { 2664 ISM330IS_SH_104Hz = 0x0, 2665 ISM330IS_SH_52Hz = 0x1, 2666 ISM330IS_SH_26Hz = 0x2, 2667 ISM330IS_SH_12_5Hz = 0x3, 2668 } ism330is_sh_data_rate_t; 2669 int32_t ism330is_sh_data_rate_set(stmdev_ctx_t *ctx, 2670 ism330is_sh_data_rate_t val); 2671 int32_t ism330is_sh_data_rate_get(stmdev_ctx_t *ctx, 2672 ism330is_sh_data_rate_t *val); 2673 2674 typedef struct 2675 { 2676 uint8_t slv_add; 2677 uint8_t slv_subadd; 2678 uint8_t slv_len; 2679 } ism330is_sh_cfg_read_t; 2680 int32_t ism330is_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, 2681 ism330is_sh_cfg_read_t *val); 2682 2683 int32_t ism330is_sh_status_get(stmdev_ctx_t *ctx, 2684 ism330is_status_master_t *val); 2685 2686 int32_t ism330is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2687 int32_t ism330is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2688 2689 typedef enum 2690 { 2691 ISM330IS_ISPU_CLK_5MHz = 0x0, 2692 ISM330IS_ISPU_CLK_10MHz = 0x1, 2693 } ism330is_ispu_clock_sel_t; 2694 int32_t ism330is_ispu_clock_set(stmdev_ctx_t *ctx, 2695 ism330is_ispu_clock_sel_t val); 2696 int32_t ism330is_ispu_clock_get(stmdev_ctx_t *ctx, 2697 ism330is_ispu_clock_sel_t *val); 2698 2699 typedef enum 2700 { 2701 ISM330IS_ISPU_ODR_OFF = 0x0, 2702 ISM330IS_ISPU_ODR_AT_12Hz5 = 0x1, 2703 ISM330IS_ISPU_ODR_AT_26Hz = 0x2, 2704 ISM330IS_ISPU_ODR_AT_52Hz = 0x3, 2705 ISM330IS_ISPU_ODR_AT_104Hz = 0x4, 2706 ISM330IS_ISPU_ODR_AT_208Hz = 0x5, 2707 ISM330IS_ISPU_ODR_AT_416Hz = 0x6, 2708 ISM330IS_ISPU_ODR_AT_833Hz = 0x7, 2709 ISM330IS_ISPU_ODR_AT_1667Hz = 0x8, 2710 ISM330IS_ISPU_ODR_AT_3333Hz = 0x9, 2711 ISM330IS_ISPU_ODR_AT_6667Hz = 0xa, 2712 } ism330is_ispu_data_rate_t; 2713 int32_t ism330is_ispu_data_rate_set(stmdev_ctx_t *ctx, 2714 ism330is_ispu_data_rate_t val); 2715 int32_t ism330is_ispu_data_rate_get(stmdev_ctx_t *ctx, 2716 ism330is_ispu_data_rate_t *val); 2717 2718 typedef enum 2719 { 2720 ISM330IS_ISPU_BDU_OFF = 0x0, 2721 ISM330IS_ISPU_BDU_ON_2B_4B = 0x1, 2722 ISM330IS_ISPU_BDU_ON_2B_2B = 0x2, 2723 ISM330IS_ISPU_BDU_ON_4B_4B = 0x3, 2724 } ism330is_ispu_bdu_t; 2725 int32_t ism330is_ispu_bdu_set(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val); 2726 int32_t ism330is_ispu_bdu_get(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val); 2727 2728 int32_t ism330is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val); 2729 2730 int32_t ism330is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, 2731 uint8_t *val, uint8_t len); 2732 int32_t ism330is_ispu_read_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, 2733 uint8_t *val, uint8_t len); 2734 2735 typedef enum 2736 { 2737 ISM330IS_ISPU_TURN_ON = 0x0, 2738 ISM330IS_ISPU_TURN_OFF = 0x1, 2739 } ism330is_ispu_boot_latched_t; 2740 int32_t ism330is_ispu_boot_set(stmdev_ctx_t *ctx, 2741 ism330is_ispu_boot_latched_t val); 2742 int32_t ism330is_ispu_boot_get(stmdev_ctx_t *ctx, 2743 ism330is_ispu_boot_latched_t *val); 2744 2745 typedef enum 2746 { 2747 ISM330IS_ISPU_INT_PULSED = 0x0, 2748 ISM330IS_ISPU_INT_LATCHED = 0x1, 2749 } ism330is_ispu_int_latched_t; 2750 int32_t ism330is_ispu_int_latched_set(stmdev_ctx_t *ctx, 2751 ism330is_ispu_int_latched_t val); 2752 int32_t ism330is_ispu_int_latched_get(stmdev_ctx_t *ctx, 2753 ism330is_ispu_int_latched_t *val); 2754 2755 typedef enum 2756 { 2757 ISM330IS_ISPU_BOOT_IN_PROGRESS = 0x0, 2758 ISM330IS_ISPU_BOOT_ENDED = 0x1, 2759 } ism330is_ispu_boot_end_t; 2760 int32_t ism330is_ispu_get_boot_status(stmdev_ctx_t *ctx, 2761 ism330is_ispu_boot_end_t *val); 2762 2763 typedef enum 2764 { 2765 ISM330IS_ISPU_DATA_RAM_MEMORY = 0x0, 2766 ISM330IS_ISPU_PROGRAM_RAM_MEMORY = 0x1, 2767 } ism330is_ispu_memory_type_t; 2768 int32_t ism330is_ispu_read_memory_enable(stmdev_ctx_t *ctx, 2769 ism330is_ispu_memory_type_t val); 2770 int32_t ism330is_ispu_read_memory_disable(stmdev_ctx_t *ctx); 2771 2772 int32_t ism330is_ispu_write_memory(stmdev_ctx_t *ctx, 2773 ism330is_ispu_memory_type_t mem_sel, 2774 uint16_t mem_addr, uint8_t *mem_data, uint16_t len); 2775 int32_t ism330is_ispu_read_memory(stmdev_ctx_t *ctx, 2776 ism330is_ispu_memory_type_t mem_sel, 2777 uint16_t mem_addr, uint8_t *mem_data, uint16_t len); 2778 2779 int32_t ism330is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data); 2780 int32_t ism330is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data); 2781 int32_t ism330is_ispu_clear_flags(stmdev_ctx_t *ctx); 2782 2783 int32_t ism330is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, 2784 uint8_t *val, 2785 uint8_t len); 2786 2787 int32_t ism330is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); 2788 int32_t ism330is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); 2789 int32_t ism330is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); 2790 int32_t ism330is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); 2791 2792 int32_t ism330is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val); 2793 2794 int32_t ism330is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val); 2795 int32_t ism330is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val); 2796 /** 2797 * @} 2798 * 2799 */ 2800 2801 #ifdef __cplusplus 2802 } 2803 #endif 2804 2805 #endif /*ISM330IS_DRIVER_H */ 2806 2807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2808
