1 /** 2 ****************************************************************************** 3 * @file ism330bx_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ism330bx_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2024 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ISM330BX_REGS_H 23 #define ISM330BX_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ISM330BX 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ISM330BX_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define ISM330BX_I2C_ADD_L 0xD5U 173 #define ISM330BX_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define ISM330BX_ID 0x71U 177 178 /** 179 * @} 180 * 181 */ 182 183 /** @defgroup bitfields page main 184 * @{ 185 * 186 */ 187 188 #define ISM330BX_FUNC_CFG_ACCESS 0x1U 189 typedef struct 190 { 191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 192 uint8_t not_used0 : 2; 193 uint8_t sw_por : 1; 194 uint8_t fsm_wr_ctrl_en : 1; 195 uint8_t not_used1 : 3; 196 uint8_t emb_func_reg_access : 1; 197 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 198 uint8_t emb_func_reg_access : 1; 199 uint8_t not_used1 : 3; 200 uint8_t fsm_wr_ctrl_en : 1; 201 uint8_t sw_por : 1; 202 uint8_t not_used0 : 2; 203 #endif /* DRV_BYTE_ORDER */ 204 } ism330bx_func_cfg_access_t; 205 206 #define ISM330BX_PIN_CTRL 0x2U 207 typedef struct 208 { 209 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 210 uint8_t not_used0 : 5; 211 uint8_t ibhr_por_en : 1; 212 uint8_t sdo_pu_en : 1; 213 uint8_t tdm_wclk_pu_dis : 1; 214 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 215 uint8_t tdm_wclk_pu_dis : 1; 216 uint8_t sdo_pu_en : 1; 217 uint8_t ibhr_por_en : 1; 218 uint8_t not_used0 : 5; 219 #endif /* DRV_BYTE_ORDER */ 220 } ism330bx_pin_ctrl_t; 221 222 #define ISM330BX_IF_CFG 0x3U 223 typedef struct 224 { 225 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 226 uint8_t i2c_i3c_disable : 1; 227 uint8_t not_used0 : 1; 228 uint8_t sim : 1; 229 uint8_t pp_od : 1; 230 uint8_t h_lactive : 1; 231 uint8_t asf_ctrl : 1; 232 uint8_t tdm_out_pu_en : 1; 233 uint8_t sda_pu_en : 1; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t sda_pu_en : 1; 236 uint8_t tdm_out_pu_en : 1; 237 uint8_t asf_ctrl : 1; 238 uint8_t h_lactive : 1; 239 uint8_t pp_od : 1; 240 uint8_t sim : 1; 241 uint8_t not_used0 : 1; 242 uint8_t i2c_i3c_disable : 1; 243 #endif /* DRV_BYTE_ORDER */ 244 } ism330bx_if_cfg_t; 245 246 #define ISM330BX_FIFO_CTRL1 0x7U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t wtm : 8; 251 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 252 uint8_t wtm : 8; 253 #endif /* DRV_BYTE_ORDER */ 254 } ism330bx_fifo_ctrl1_t; 255 256 #define ISM330BX_FIFO_CTRL2 0x8U 257 typedef struct 258 { 259 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 260 uint8_t xl_dualc_batch_from_fsm : 1; 261 uint8_t uncompr_rate : 2; 262 uint8_t not_used0 : 1; 263 uint8_t odr_chg_en : 1; 264 uint8_t not_used1 : 1; 265 uint8_t fifo_compr_rt_en : 1; 266 uint8_t stop_on_wtm : 1; 267 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 268 uint8_t stop_on_wtm : 1; 269 uint8_t fifo_compr_rt_en : 1; 270 uint8_t not_used1 : 1; 271 uint8_t odr_chg_en : 1; 272 uint8_t not_used0 : 1; 273 uint8_t uncompr_rate : 2; 274 uint8_t xl_dualc_batch_from_fsm : 1; 275 #endif /* DRV_BYTE_ORDER */ 276 } ism330bx_fifo_ctrl2_t; 277 278 #define ISM330BX_FIFO_CTRL3 0x9U 279 typedef struct 280 { 281 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 282 uint8_t bdr_xl : 4; 283 uint8_t bdr_gy : 4; 284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 285 uint8_t bdr_gy : 4; 286 uint8_t bdr_xl : 4; 287 #endif /* DRV_BYTE_ORDER */ 288 } ism330bx_fifo_ctrl3_t; 289 290 #define ISM330BX_FIFO_CTRL4 0x0AU 291 typedef struct 292 { 293 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 294 uint8_t fifo_mode : 3; 295 uint8_t not_used0 : 1; 296 uint8_t odr_t_batch : 2; 297 uint8_t dec_ts_batch : 2; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t dec_ts_batch : 2; 300 uint8_t odr_t_batch : 2; 301 uint8_t not_used0 : 1; 302 uint8_t fifo_mode : 3; 303 #endif /* DRV_BYTE_ORDER */ 304 } ism330bx_fifo_ctrl4_t; 305 306 #define ISM330BX_COUNTER_BDR_REG1 0x0BU 307 typedef struct 308 { 309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 310 uint8_t cnt_bdr_th : 2; 311 uint8_t ah_qvar_batch_en : 1; 312 uint8_t not_used0 : 2; 313 uint8_t trig_counter_bdr : 2; 314 uint8_t not_used1 : 1; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t not_used1 : 1; 317 uint8_t trig_counter_bdr : 2; 318 uint8_t not_used0 : 2; 319 uint8_t ah_qvar_batch_en : 1; 320 uint8_t cnt_bdr_th : 2; 321 #endif /* DRV_BYTE_ORDER */ 322 } ism330bx_counter_bdr_reg1_t; 323 324 #define ISM330BX_COUNTER_BDR_REG2 0x0CU 325 typedef struct 326 { 327 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 328 uint8_t cnt_bdr_th : 8; 329 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 330 uint8_t cnt_bdr_th : 8; 331 #endif /* DRV_BYTE_ORDER */ 332 } ism330bx_counter_bdr_reg2_t; 333 334 #define ISM330BX_INT1_CTRL 0x0DU 335 typedef struct 336 { 337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 338 uint8_t int1_drdy_xl : 1; 339 uint8_t int1_drdy_g : 1; 340 uint8_t not_used0 : 1; 341 uint8_t int1_fifo_th : 1; 342 uint8_t int1_fifo_ovr : 1; 343 uint8_t int1_fifo_full : 1; 344 uint8_t int1_cnt_bdr : 1; 345 uint8_t not_used1 : 1; 346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 347 uint8_t not_used1 : 1; 348 uint8_t int1_cnt_bdr : 1; 349 uint8_t int1_fifo_full : 1; 350 uint8_t int1_fifo_ovr : 1; 351 uint8_t int1_fifo_th : 1; 352 uint8_t not_used0 : 1; 353 uint8_t int1_drdy_g : 1; 354 uint8_t int1_drdy_xl : 1; 355 #endif /* DRV_BYTE_ORDER */ 356 } ism330bx_int1_ctrl_t; 357 358 #define ISM330BX_INT2_CTRL 0x0EU 359 typedef struct 360 { 361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 362 uint8_t int2_drdy_xl : 1; 363 uint8_t int2_drdy_g : 1; 364 uint8_t not_used0 : 1; 365 uint8_t int2_fifo_th : 1; 366 uint8_t int2_fifo_ovr : 1; 367 uint8_t int2_fifo_full : 1; 368 uint8_t int2_cnt_bdr : 1; 369 uint8_t int2_emb_func_endop : 1; 370 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 371 uint8_t int2_emb_func_endop : 1; 372 uint8_t int2_cnt_bdr : 1; 373 uint8_t int2_fifo_full : 1; 374 uint8_t int2_fifo_ovr : 1; 375 uint8_t int2_fifo_th : 1; 376 uint8_t not_used0 : 1; 377 uint8_t int2_drdy_g : 1; 378 uint8_t int2_drdy_xl : 1; 379 #endif /* DRV_BYTE_ORDER */ 380 } ism330bx_int2_ctrl_t; 381 382 #define ISM330BX_WHO_AM_I 0x0FU 383 typedef struct 384 { 385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 386 uint8_t id : 8; 387 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 388 uint8_t id : 8; 389 #endif /* DRV_BYTE_ORDER */ 390 } ism330bx_who_am_i_t; 391 392 #define ISM330BX_CTRL1 0x10U 393 typedef struct 394 { 395 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 396 uint8_t odr_xl : 4; 397 uint8_t op_mode_xl : 3; 398 uint8_t not_used0 : 1; 399 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 400 uint8_t not_used0 : 1; 401 uint8_t op_mode_xl : 3; 402 uint8_t odr_xl : 4; 403 #endif /* DRV_BYTE_ORDER */ 404 } ism330bx_ctrl1_t; 405 406 #define ISM330BX_CTRL2 0x11U 407 typedef struct 408 { 409 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 410 uint8_t odr_g : 4; 411 uint8_t op_mode_g : 3; 412 uint8_t not_used0 : 1; 413 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 414 uint8_t not_used0 : 1; 415 uint8_t op_mode_g : 3; 416 uint8_t odr_g : 4; 417 #endif /* DRV_BYTE_ORDER */ 418 } ism330bx_ctrl2_t; 419 420 #define ISM330BX_CTRL3 0x12U 421 typedef struct 422 { 423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 424 uint8_t sw_reset : 1; 425 uint8_t not_used0 : 1; 426 uint8_t if_inc : 1; 427 uint8_t not_used1 : 3; 428 uint8_t bdu : 1; 429 uint8_t boot : 1; 430 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 431 uint8_t boot : 1; 432 uint8_t bdu : 1; 433 uint8_t not_used1 : 3; 434 uint8_t if_inc : 1; 435 uint8_t not_used0 : 1; 436 uint8_t sw_reset : 1; 437 #endif /* DRV_BYTE_ORDER */ 438 } ism330bx_ctrl3_t; 439 440 #define ISM330BX_CTRL4 0x13U 441 typedef struct 442 { 443 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 444 uint8_t not_used1 : 1; 445 uint8_t drdy_pulsed : 1; 446 uint8_t int2_drdy_temp : 1; 447 uint8_t drdy_mask : 1; 448 uint8_t int2_on_int1 : 1; 449 uint8_t not_used0 : 3; 450 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 451 uint8_t not_used0 : 3; 452 uint8_t int2_on_int1 : 1; 453 uint8_t drdy_mask : 1; 454 uint8_t int2_drdy_temp : 1; 455 uint8_t drdy_pulsed : 1; 456 uint8_t not_used1 : 1; 457 #endif /* DRV_BYTE_ORDER */ 458 } ism330bx_ctrl4_t; 459 460 #define ISM330BX_CTRL5 0x14U 461 typedef struct 462 { 463 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 464 uint8_t int_en_i3c : 1; 465 uint8_t bus_act_sel : 2; 466 uint8_t not_used0 : 5; 467 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 468 uint8_t not_used0 : 5; 469 uint8_t bus_act_sel : 2; 470 uint8_t int_en_i3c : 1; 471 #endif /* DRV_BYTE_ORDER */ 472 } ism330bx_ctrl5_t; 473 474 #define ISM330BX_CTRL6 0x15U 475 typedef struct 476 { 477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 478 uint8_t fs_g : 4; 479 uint8_t lpf1_g_bw : 3; 480 uint8_t not_used0 : 1; 481 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 482 uint8_t not_used0 : 1; 483 uint8_t lpf1_g_bw : 3; 484 uint8_t fs_g : 4; 485 #endif /* DRV_BYTE_ORDER */ 486 } ism330bx_ctrl6_t; 487 488 #define ISM330BX_CTRL7 0x16U 489 typedef struct 490 { 491 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 492 uint8_t lpf1_g_en : 1; 493 uint8_t not_used0 : 1; 494 uint8_t ah_qvar2_en : 1; 495 uint8_t ah_qvar1_en : 1; 496 uint8_t ah_qvar_c_zin : 2; 497 uint8_t int2_drdy_ah_qvar : 1; 498 uint8_t ah_qvar_en : 1; 499 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 500 uint8_t ah_qvar_en : 1; 501 uint8_t int2_drdy_ah_qvar : 1; 502 uint8_t ah_qvar_c_zin : 2; 503 uint8_t ah_qvar1_en : 1; 504 uint8_t ah_qvar2_en : 1; 505 uint8_t not_used0 : 1; 506 uint8_t lpf1_g_en : 1; 507 #endif /* DRV_BYTE_ORDER */ 508 } ism330bx_ctrl7_t; 509 510 #define ISM330BX_CTRL8 0x17U 511 typedef struct 512 { 513 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 514 uint8_t fs_xl : 2; 515 uint8_t not_used0 : 1; 516 uint8_t xl_dualc_en : 1; 517 uint8_t ah_qvar_hpf : 1; 518 uint8_t hp_lpf2_xl_bw : 3; 519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 520 uint8_t hp_lpf2_xl_bw : 3; 521 uint8_t ah_qvar_hpf : 1; 522 uint8_t xl_dualc_en : 1; 523 uint8_t not_used0 : 1; 524 uint8_t fs_xl : 2; 525 #endif /* DRV_BYTE_ORDER */ 526 } ism330bx_ctrl8_t; 527 528 #define ISM330BX_CTRL9 0x18U 529 typedef struct 530 { 531 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 532 uint8_t usr_off_on_out : 1; 533 uint8_t usr_off_w : 1; 534 uint8_t not_used0 : 1; 535 uint8_t lpf2_xl_en : 1; 536 uint8_t hp_slope_xl_en : 1; 537 uint8_t xl_fastsettl_mode : 1; 538 uint8_t hp_ref_mode_xl : 1; 539 uint8_t ah_qvar_lpf : 1; 540 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 541 uint8_t ah_qvar_lpf : 1; 542 uint8_t hp_ref_mode_xl : 1; 543 uint8_t xl_fastsettl_mode : 1; 544 uint8_t hp_slope_xl_en : 1; 545 uint8_t lpf2_xl_en : 1; 546 uint8_t not_used0 : 1; 547 uint8_t usr_off_w : 1; 548 uint8_t usr_off_on_out : 1; 549 #endif /* DRV_BYTE_ORDER */ 550 } ism330bx_ctrl9_t; 551 552 #define ISM330BX_CTRL10 0x19U 553 typedef struct 554 { 555 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 556 uint8_t st_xl : 2; 557 uint8_t st_g : 2; 558 uint8_t xl_st_offset : 1; 559 uint8_t ah_qvar_sw : 1; 560 uint8_t emb_func_debug : 1; 561 uint8_t not_used0 : 1; 562 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 563 uint8_t not_used0 : 1; 564 uint8_t emb_func_debug : 1; 565 uint8_t ah_qvar_sw : 1; 566 uint8_t xl_st_offset : 1; 567 uint8_t st_g : 2; 568 uint8_t st_xl : 2; 569 #endif /* DRV_BYTE_ORDER */ 570 } ism330bx_ctrl10_t; 571 572 #define ISM330BX_CTRL_STATUS 0x1AU 573 typedef struct 574 { 575 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 576 uint8_t not_used0 : 2; 577 uint8_t fsm_wr_ctrl_status : 1; 578 uint8_t not_used1 : 5; 579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 580 uint8_t not_used1 : 5; 581 uint8_t fsm_wr_ctrl_status : 1; 582 uint8_t not_used0 : 2; 583 #endif /* DRV_BYTE_ORDER */ 584 } ism330bx_ctrl_status_t; 585 586 #define ISM330BX_FIFO_STATUS1 0x1BU 587 typedef struct 588 { 589 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 590 uint8_t diff_fifo : 8; 591 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 592 uint8_t diff_fifo : 8; 593 #endif /* DRV_BYTE_ORDER */ 594 } ism330bx_fifo_status1_t; 595 596 #define ISM330BX_FIFO_STATUS2 0x1CU 597 typedef struct 598 { 599 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 600 uint8_t diff_fifo : 1; 601 uint8_t not_used0 : 2; 602 uint8_t fifo_ovr_latched : 1; 603 uint8_t counter_bdr_ia : 1; 604 uint8_t fifo_full_ia : 1; 605 uint8_t fifo_ovr_ia : 1; 606 uint8_t fifo_wtm_ia : 1; 607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 608 uint8_t fifo_wtm_ia : 1; 609 uint8_t fifo_ovr_ia : 1; 610 uint8_t fifo_full_ia : 1; 611 uint8_t counter_bdr_ia : 1; 612 uint8_t fifo_ovr_latched : 1; 613 uint8_t not_used0 : 2; 614 uint8_t diff_fifo : 1; 615 #endif /* DRV_BYTE_ORDER */ 616 } ism330bx_fifo_status2_t; 617 618 #define ISM330BX_ALL_INT_SRC 0x1DU 619 typedef struct 620 { 621 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 622 uint8_t ff_ia : 1; 623 uint8_t wu_ia : 1; 624 uint8_t tap_ia : 1; 625 uint8_t not_used0 : 1; 626 uint8_t d6d_ia : 1; 627 uint8_t sleep_change_ia : 1; 628 uint8_t not_used1 : 1; 629 uint8_t emb_func_ia : 1; 630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 631 uint8_t emb_func_ia : 1; 632 uint8_t not_used1 : 1; 633 uint8_t sleep_change_ia : 1; 634 uint8_t d6d_ia : 1; 635 uint8_t not_used0 : 1; 636 uint8_t tap_ia : 1; 637 uint8_t wu_ia : 1; 638 uint8_t ff_ia : 1; 639 #endif /* DRV_BYTE_ORDER */ 640 } ism330bx_all_int_src_t; 641 642 #define ISM330BX_STATUS_REG 0x1EU 643 typedef struct 644 { 645 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 646 uint8_t xlda : 1; 647 uint8_t gda : 1; 648 uint8_t tda : 1; 649 uint8_t ah_qvarda : 1; 650 uint8_t not_used0 : 3; 651 uint8_t timestamp_endcount : 1; 652 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 653 uint8_t timestamp_endcount : 1; 654 uint8_t not_used0 : 3; 655 uint8_t ah_qvarda : 1; 656 uint8_t tda : 1; 657 uint8_t gda : 1; 658 uint8_t xlda : 1; 659 #endif /* DRV_BYTE_ORDER */ 660 } ism330bx_status_reg_t; 661 662 #define ISM330BX_OUT_TEMP_L 0x20U 663 typedef struct 664 { 665 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 666 uint8_t temp : 8; 667 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 668 uint8_t temp : 8; 669 #endif /* DRV_BYTE_ORDER */ 670 } ism330bx_out_temp_l_t; 671 672 #define ISM330BX_OUT_TEMP_H 0x21U 673 typedef struct 674 { 675 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 676 uint8_t temp : 8; 677 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 678 uint8_t temp : 8; 679 #endif /* DRV_BYTE_ORDER */ 680 } ism330bx_out_temp_h_t; 681 682 #define ISM330BX_OUTX_L_G 0x22U 683 typedef struct 684 { 685 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 686 uint8_t outx_g : 8; 687 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 688 uint8_t outx_g : 8; 689 #endif /* DRV_BYTE_ORDER */ 690 } ism330bx_outx_l_g_t; 691 692 #define ISM330BX_OUTX_H_G 0x23U 693 typedef struct 694 { 695 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 696 uint8_t outx_g : 8; 697 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 698 uint8_t outx_g : 8; 699 #endif /* DRV_BYTE_ORDER */ 700 } ism330bx_outx_h_g_t; 701 702 #define ISM330BX_OUTY_L_G 0x24U 703 typedef struct 704 { 705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 706 uint8_t outy_g : 8; 707 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 708 uint8_t outy_g : 8; 709 #endif /* DRV_BYTE_ORDER */ 710 } ism330bx_outy_l_g_t; 711 712 #define ISM330BX_OUTY_H_G 0x25U 713 typedef struct 714 { 715 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 716 uint8_t outy_g : 8; 717 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 718 uint8_t outy_g : 8; 719 #endif /* DRV_BYTE_ORDER */ 720 } ism330bx_outy_h_g_t; 721 722 #define ISM330BX_OUTZ_L_G 0x26U 723 typedef struct 724 { 725 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 726 uint8_t outz_g : 8; 727 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 728 uint8_t outz_g : 8; 729 #endif /* DRV_BYTE_ORDER */ 730 } ism330bx_outz_l_g_t; 731 732 #define ISM330BX_OUTZ_H_G 0x27U 733 typedef struct 734 { 735 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 736 uint8_t outz_g : 8; 737 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 738 uint8_t outz_g : 8; 739 #endif /* DRV_BYTE_ORDER */ 740 } ism330bx_outz_h_g_t; 741 742 #define ISM330BX_OUTZ_L_A 0x28U 743 typedef struct 744 { 745 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 746 uint8_t outz_a : 8; 747 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 748 uint8_t outz_a : 8; 749 #endif /* DRV_BYTE_ORDER */ 750 } ism330bx_outz_l_a_t; 751 752 #define ISM330BX_OUTZ_H_A 0x29U 753 typedef struct 754 { 755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 756 uint8_t outz_a : 8; 757 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 758 uint8_t outz_a : 8; 759 #endif /* DRV_BYTE_ORDER */ 760 } ism330bx_outz_h_a_t; 761 762 #define ISM330BX_OUTY_L_A 0x2AU 763 typedef struct 764 { 765 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 766 uint8_t outy_a : 8; 767 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 768 uint8_t outy_a : 8; 769 #endif /* DRV_BYTE_ORDER */ 770 } ism330bx_outy_l_a_t; 771 772 #define ISM330BX_OUTY_H_A 0x2BU 773 typedef struct 774 { 775 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 776 uint8_t outy_a : 8; 777 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 778 uint8_t outy_a : 8; 779 #endif /* DRV_BYTE_ORDER */ 780 } ism330bx_outy_h_a_t; 781 782 #define ISM330BX_OUTX_L_A 0x2CU 783 typedef struct 784 { 785 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 786 uint8_t outx_a : 8; 787 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 788 uint8_t outx_a : 8; 789 #endif /* DRV_BYTE_ORDER */ 790 } ism330bx_outx_l_a_t; 791 792 #define ISM330BX_OUTX_H_A 0x2DU 793 typedef struct 794 { 795 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 796 uint8_t outx_a : 8; 797 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 798 uint8_t outx_a : 8; 799 #endif /* DRV_BYTE_ORDER */ 800 } ism330bx_outx_h_a_t; 801 802 #define ISM330BX_UI_OUTZ_L_A_DUALC 0x34U 803 typedef struct 804 { 805 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 806 uint8_t ui_outz_a_dualc : 8; 807 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 808 uint8_t ui_outz_a_dualc : 8; 809 #endif /* DRV_BYTE_ORDER */ 810 } ism330bx_ui_outz_l_a_dualc_t; 811 812 #define ISM330BX_UI_OUTZ_H_A_DUALC 0x35U 813 typedef struct 814 { 815 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 816 uint8_t ui_outz_a_dualc : 8; 817 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 818 uint8_t ui_outz_a_dualc : 8; 819 #endif /* DRV_BYTE_ORDER */ 820 } ism330bx_ui_outz_h_a_dualc_t; 821 822 #define ISM330BX_UI_OUTY_L_A_DUALC 0x36U 823 typedef struct 824 { 825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 826 uint8_t ui_outy_a_dualc : 8; 827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 828 uint8_t ui_outy_a_dualc : 8; 829 #endif /* DRV_BYTE_ORDER */ 830 } ism330bx_ui_outy_l_a_dualc_t; 831 832 #define ISM330BX_UI_OUTY_H_A_DUALC 0x37U 833 typedef struct 834 { 835 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 836 uint8_t ui_outy_a_dualc : 8; 837 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 838 uint8_t ui_outy_a_dualc : 8; 839 #endif /* DRV_BYTE_ORDER */ 840 } ism330bx_ui_outy_h_a_dualc_t; 841 842 #define ISM330BX_UI_OUTX_L_A_DUALC 0x38U 843 typedef struct 844 { 845 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 846 uint8_t ui_outx_a_dualc : 8; 847 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 848 uint8_t ui_outx_a_dualc : 8; 849 #endif /* DRV_BYTE_ORDER */ 850 } ism330bx_ui_outx_l_a_dualc_t; 851 852 #define ISM330BX_UI_OUTX_H_A_DUALC 0x39U 853 typedef struct 854 { 855 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 856 uint8_t ui_outx_a_dualc : 8; 857 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 858 uint8_t ui_outx_a_dualc : 8; 859 #endif /* DRV_BYTE_ORDER */ 860 } ism330bx_ui_outx_h_a_dualc_t; 861 862 #define ISM330BX_AH_QVAR_OUT_L 0x3AU 863 typedef struct 864 { 865 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 866 uint8_t ah_qvar : 8; 867 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 868 uint8_t ah_qvar : 8; 869 #endif /* DRV_BYTE_ORDER */ 870 } ism330bx_ah_qvar_out_l_t; 871 872 #define ISM330BX_AH_QVAR_OUT_H 0x3BU 873 typedef struct 874 { 875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 876 uint8_t ah_qvar : 8; 877 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 878 uint8_t ah_qvar : 8; 879 #endif /* DRV_BYTE_ORDER */ 880 } ism330bx_ah_qvar_out_h_t; 881 882 #define ISM330BX_TIMESTAMP0 0x40U 883 typedef struct 884 { 885 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 886 uint8_t timestamp : 8; 887 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 888 uint8_t timestamp : 8; 889 #endif /* DRV_BYTE_ORDER */ 890 } ism330bx_timestamp0_t; 891 892 #define ISM330BX_TIMESTAMP1 0x41U 893 typedef struct 894 { 895 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 896 uint8_t timestamp : 8; 897 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 898 uint8_t timestamp : 8; 899 #endif /* DRV_BYTE_ORDER */ 900 } ism330bx_timestamp1_t; 901 902 #define ISM330BX_TIMESTAMP2 0x42U 903 typedef struct 904 { 905 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 906 uint8_t timestamp : 8; 907 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 908 uint8_t timestamp : 8; 909 #endif /* DRV_BYTE_ORDER */ 910 } ism330bx_timestamp2_t; 911 912 #define ISM330BX_TIMESTAMP3 0x43U 913 typedef struct 914 { 915 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 916 uint8_t timestamp : 8; 917 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 918 uint8_t timestamp : 8; 919 #endif /* DRV_BYTE_ORDER */ 920 } ism330bx_timestamp3_t; 921 922 #define ISM330BX_WAKE_UP_SRC 0x45U 923 typedef struct 924 { 925 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 926 uint8_t x_wu : 1; 927 uint8_t y_wu : 1; 928 uint8_t z_wu : 1; 929 uint8_t wu_ia : 1; 930 uint8_t sleep_state : 1; 931 uint8_t ff_ia : 1; 932 uint8_t sleep_change_ia : 1; 933 uint8_t not_used0 : 1; 934 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 935 uint8_t not_used0 : 1; 936 uint8_t sleep_change_ia : 1; 937 uint8_t ff_ia : 1; 938 uint8_t sleep_state : 1; 939 uint8_t wu_ia : 1; 940 uint8_t z_wu : 1; 941 uint8_t y_wu : 1; 942 uint8_t x_wu : 1; 943 #endif /* DRV_BYTE_ORDER */ 944 } ism330bx_wake_up_src_t; 945 946 #define ISM330BX_TAP_SRC 0x46U 947 typedef struct 948 { 949 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 950 uint8_t x_tap : 1; 951 uint8_t y_tap : 1; 952 uint8_t z_tap : 1; 953 uint8_t tap_sign : 1; 954 uint8_t not_used0 : 1; 955 uint8_t double_tap : 1; 956 uint8_t single_tap : 1; 957 uint8_t tap_ia : 1; 958 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 959 uint8_t tap_ia : 1; 960 uint8_t single_tap : 1; 961 uint8_t double_tap : 1; 962 uint8_t not_used0 : 1; 963 uint8_t tap_sign : 1; 964 uint8_t z_tap : 1; 965 uint8_t y_tap : 1; 966 uint8_t x_tap : 1; 967 #endif /* DRV_BYTE_ORDER */ 968 } ism330bx_tap_src_t; 969 970 #define ISM330BX_D6D_SRC 0x47U 971 typedef struct 972 { 973 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 974 uint8_t zl : 1; 975 uint8_t zh : 1; 976 uint8_t yl : 1; 977 uint8_t yh : 1; 978 uint8_t xl : 1; 979 uint8_t xh : 1; 980 uint8_t d6d_ia : 1; 981 uint8_t not_used0 : 1; 982 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 983 uint8_t not_used0 : 1; 984 uint8_t d6d_ia : 1; 985 uint8_t xh : 1; 986 uint8_t xl : 1; 987 uint8_t yh : 1; 988 uint8_t yl : 1; 989 uint8_t zh : 1; 990 uint8_t zl : 1; 991 #endif /* DRV_BYTE_ORDER */ 992 } ism330bx_d6d_src_t; 993 994 #define ISM330BX_EMB_FUNC_STATUS_MAINPAGE 0x49U 995 typedef struct 996 { 997 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 998 uint8_t not_used0 : 3; 999 uint8_t is_step_det : 1; 1000 uint8_t is_tilt : 1; 1001 uint8_t is_sigmot : 1; 1002 uint8_t not_used1 : 1; 1003 uint8_t is_fsm_lc : 1; 1004 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1005 uint8_t is_fsm_lc : 1; 1006 uint8_t not_used1 : 1; 1007 uint8_t is_sigmot : 1; 1008 uint8_t is_tilt : 1; 1009 uint8_t is_step_det : 1; 1010 uint8_t not_used0 : 3; 1011 #endif /* DRV_BYTE_ORDER */ 1012 } ism330bx_emb_func_status_mainpage_t; 1013 1014 #define ISM330BX_FSM_STATUS_MAINPAGE 0x4AU 1015 typedef struct 1016 { 1017 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1018 uint8_t is_fsm1 : 1; 1019 uint8_t is_fsm2 : 1; 1020 uint8_t is_fsm3 : 1; 1021 uint8_t is_fsm4 : 1; 1022 uint8_t is_fsm5 : 1; 1023 uint8_t is_fsm6 : 1; 1024 uint8_t is_fsm7 : 1; 1025 uint8_t is_fsm8 : 1; 1026 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1027 uint8_t is_fsm8 : 1; 1028 uint8_t is_fsm7 : 1; 1029 uint8_t is_fsm6 : 1; 1030 uint8_t is_fsm5 : 1; 1031 uint8_t is_fsm4 : 1; 1032 uint8_t is_fsm3 : 1; 1033 uint8_t is_fsm2 : 1; 1034 uint8_t is_fsm1 : 1; 1035 #endif /* DRV_BYTE_ORDER */ 1036 } ism330bx_fsm_status_mainpage_t; 1037 1038 #define ISM330BX_MLC_STATUS_MAINPAGE 0x4BU 1039 typedef struct 1040 { 1041 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1042 uint8_t is_mlc1 : 1; 1043 uint8_t is_mlc2 : 1; 1044 uint8_t is_mlc3 : 1; 1045 uint8_t is_mlc4 : 1; 1046 uint8_t not_used0 : 4; 1047 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1048 uint8_t not_used0 : 4; 1049 uint8_t is_mlc4 : 1; 1050 uint8_t is_mlc3 : 1; 1051 uint8_t is_mlc2 : 1; 1052 uint8_t is_mlc1 : 1; 1053 #endif /* DRV_BYTE_ORDER */ 1054 } ism330bx_mlc_status_mainpage_t; 1055 1056 #define ISM330BX_INTERNAL_FREQ 0x4FU 1057 typedef struct 1058 { 1059 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1060 uint8_t freq_fine : 8; 1061 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1062 uint8_t freq_fine : 8; 1063 #endif /* DRV_BYTE_ORDER */ 1064 } ism330bx_internal_freq_t; 1065 1066 #define ISM330BX_FUNCTIONS_ENABLE 0x50U 1067 typedef struct 1068 { 1069 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1070 uint8_t inact_en : 2; 1071 uint8_t not_used0 : 1; 1072 uint8_t dis_rst_lir_all_int : 1; 1073 uint8_t not_used1 : 2; 1074 uint8_t timestamp_en : 1; 1075 uint8_t interrupts_enable : 1; 1076 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1077 uint8_t interrupts_enable : 1; 1078 uint8_t timestamp_en : 1; 1079 uint8_t not_used1 : 2; 1080 uint8_t dis_rst_lir_all_int : 1; 1081 uint8_t not_used0 : 1; 1082 uint8_t inact_en : 2; 1083 #endif /* DRV_BYTE_ORDER */ 1084 } ism330bx_functions_enable_t; 1085 1086 #define ISM330BX_INACTIVITY_DUR 0x54U 1087 typedef struct 1088 { 1089 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1090 uint8_t inact_dur : 2; 1091 uint8_t xl_inact_odr : 2; 1092 uint8_t wu_inact_ths_w : 3; 1093 uint8_t sleep_status_on_int : 1; 1094 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1095 uint8_t sleep_status_on_int : 1; 1096 uint8_t wu_inact_ths_w : 3; 1097 uint8_t xl_inact_odr : 2; 1098 uint8_t inact_dur : 2; 1099 #endif /* DRV_BYTE_ORDER */ 1100 } ism330bx_inactivity_dur_t; 1101 1102 #define ISM330BX_INACTIVITY_THS 0x55U 1103 typedef struct 1104 { 1105 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1106 uint8_t inact_ths : 6; 1107 uint8_t not_used0 : 2; 1108 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1109 uint8_t not_used0 : 2; 1110 uint8_t inact_ths : 6; 1111 #endif /* DRV_BYTE_ORDER */ 1112 } ism330bx_inactivity_ths_t; 1113 1114 #define ISM330BX_TAP_CFG0 0x56U 1115 typedef struct 1116 { 1117 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1118 uint8_t lir : 1; 1119 uint8_t tap_x_en : 1; 1120 uint8_t tap_y_en : 1; 1121 uint8_t tap_z_en : 1; 1122 uint8_t slope_fds : 1; 1123 uint8_t hw_func_mask_xl_settl : 1; 1124 uint8_t low_pass_on_6d : 1; 1125 uint8_t not_used1 : 1; 1126 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1127 uint8_t not_used1 : 1; 1128 uint8_t low_pass_on_6d : 1; 1129 uint8_t hw_func_mask_xl_settl : 1; 1130 uint8_t slope_fds : 1; 1131 uint8_t tap_z_en : 1; 1132 uint8_t tap_y_en : 1; 1133 uint8_t tap_x_en : 1; 1134 uint8_t lir : 1; 1135 #endif /* DRV_BYTE_ORDER */ 1136 } ism330bx_tap_cfg0_t; 1137 1138 #define ISM330BX_TAP_CFG1 0x57U 1139 typedef struct 1140 { 1141 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1142 uint8_t tap_ths_z : 5; 1143 uint8_t tap_priority : 3; 1144 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1145 uint8_t tap_priority : 3; 1146 uint8_t tap_ths_z : 5; 1147 #endif /* DRV_BYTE_ORDER */ 1148 } ism330bx_tap_cfg1_t; 1149 1150 #define ISM330BX_TAP_CFG2 0x58U 1151 typedef struct 1152 { 1153 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1154 uint8_t tap_ths_y : 5; 1155 uint8_t not_used0 : 3; 1156 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1157 uint8_t not_used0 : 3; 1158 uint8_t tap_ths_y : 5; 1159 #endif /* DRV_BYTE_ORDER */ 1160 } ism330bx_tap_cfg2_t; 1161 1162 #define ISM330BX_TAP_THS_6D 0x59U 1163 typedef struct 1164 { 1165 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1166 uint8_t tap_ths_x : 5; 1167 uint8_t sixd_ths : 2; 1168 uint8_t not_used0 : 1; 1169 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1170 uint8_t not_used0 : 1; 1171 uint8_t sixd_ths : 2; 1172 uint8_t tap_ths_x : 5; 1173 #endif /* DRV_BYTE_ORDER */ 1174 } ism330bx_tap_ths_6d_t; 1175 1176 #define ISM330BX_TAP_DUR 0x5AU 1177 typedef struct 1178 { 1179 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1180 uint8_t shock : 2; 1181 uint8_t quiet : 2; 1182 uint8_t dur : 4; 1183 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1184 uint8_t dur : 4; 1185 uint8_t quiet : 2; 1186 uint8_t shock : 2; 1187 #endif /* DRV_BYTE_ORDER */ 1188 } ism330bx_tap_dur_t; 1189 1190 #define ISM330BX_WAKE_UP_THS 0x5BU 1191 typedef struct 1192 { 1193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1194 uint8_t wk_ths : 6; 1195 uint8_t usr_off_on_wu : 1; 1196 uint8_t single_double_tap : 1; 1197 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1198 uint8_t single_double_tap : 1; 1199 uint8_t usr_off_on_wu : 1; 1200 uint8_t wk_ths : 6; 1201 #endif /* DRV_BYTE_ORDER */ 1202 } ism330bx_wake_up_ths_t; 1203 1204 #define ISM330BX_WAKE_UP_DUR 0x5CU 1205 typedef struct 1206 { 1207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1208 uint8_t sleep_dur : 4; 1209 uint8_t not_used0 : 1; 1210 uint8_t wake_dur : 2; 1211 uint8_t ff_dur : 1; 1212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1213 uint8_t ff_dur : 1; 1214 uint8_t wake_dur : 2; 1215 uint8_t not_used0 : 1; 1216 uint8_t sleep_dur : 4; 1217 #endif /* DRV_BYTE_ORDER */ 1218 } ism330bx_wake_up_dur_t; 1219 1220 #define ISM330BX_FREE_FALL 0x5DU 1221 typedef struct 1222 { 1223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1224 uint8_t ff_ths : 3; 1225 uint8_t ff_dur : 5; 1226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1227 uint8_t ff_dur : 5; 1228 uint8_t ff_ths : 3; 1229 #endif /* DRV_BYTE_ORDER */ 1230 } ism330bx_free_fall_t; 1231 1232 #define ISM330BX_MD1_CFG 0x5EU 1233 typedef struct 1234 { 1235 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1236 uint8_t not_used0 : 1; 1237 uint8_t int1_emb_func : 1; 1238 uint8_t int1_6d : 1; 1239 uint8_t int1_double_tap : 1; 1240 uint8_t int1_ff : 1; 1241 uint8_t int1_wu : 1; 1242 uint8_t int1_single_tap : 1; 1243 uint8_t int1_sleep_change : 1; 1244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1245 uint8_t int1_sleep_change : 1; 1246 uint8_t int1_single_tap : 1; 1247 uint8_t int1_wu : 1; 1248 uint8_t int1_ff : 1; 1249 uint8_t int1_double_tap : 1; 1250 uint8_t int1_6d : 1; 1251 uint8_t int1_emb_func : 1; 1252 uint8_t not_used0 : 1; 1253 #endif /* DRV_BYTE_ORDER */ 1254 } ism330bx_md1_cfg_t; 1255 1256 #define ISM330BX_MD2_CFG 0x5FU 1257 typedef struct 1258 { 1259 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1260 uint8_t int2_timestamp : 1; 1261 uint8_t int2_emb_func : 1; 1262 uint8_t int2_6d : 1; 1263 uint8_t int2_double_tap : 1; 1264 uint8_t int2_ff : 1; 1265 uint8_t int2_wu : 1; 1266 uint8_t int2_single_tap : 1; 1267 uint8_t int2_sleep_change : 1; 1268 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1269 uint8_t int2_sleep_change : 1; 1270 uint8_t int2_single_tap : 1; 1271 uint8_t int2_wu : 1; 1272 uint8_t int2_ff : 1; 1273 uint8_t int2_double_tap : 1; 1274 uint8_t int2_6d : 1; 1275 uint8_t int2_emb_func : 1; 1276 uint8_t int2_timestamp : 1; 1277 #endif /* DRV_BYTE_ORDER */ 1278 } ism330bx_md2_cfg_t; 1279 1280 #define ISM330BX_EMB_FUNC_CFG 0x63U 1281 typedef struct 1282 { 1283 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1284 uint8_t not_used0 : 3; 1285 uint8_t emb_func_disable : 1; 1286 uint8_t emb_func_irq_mask_xl_settl : 1; 1287 uint8_t emb_func_irq_mask_g_settl : 1; 1288 uint8_t not_used1 : 1; 1289 uint8_t xl_dualc_batch_from_if : 1; 1290 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1291 uint8_t xl_dualc_batch_from_if : 1; 1292 uint8_t not_used1 : 1; 1293 uint8_t emb_func_irq_mask_g_settl : 1; 1294 uint8_t emb_func_irq_mask_xl_settl : 1; 1295 uint8_t emb_func_disable : 1; 1296 uint8_t not_used0 : 3; 1297 #endif /* DRV_BYTE_ORDER */ 1298 } ism330bx_emb_func_cfg_t; 1299 1300 #define ISM330BX_TDM_CFG0 0x6CU 1301 typedef struct 1302 { 1303 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1304 uint8_t tdm_wclk_bclk_sel : 1; 1305 uint8_t tdm_wclk : 2; 1306 uint8_t not_used0 : 1; 1307 uint8_t tdm_slot_sel : 1; 1308 uint8_t tdm_bclk_edge_sel : 1; 1309 uint8_t tdm_delayed_cfg : 1; 1310 uint8_t not_used1 : 1; 1311 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1312 uint8_t not_used1 : 1; 1313 uint8_t tdm_delayed_cfg : 1; 1314 uint8_t tdm_bclk_edge_sel : 1; 1315 uint8_t tdm_slot_sel : 1; 1316 uint8_t not_used0 : 1; 1317 uint8_t tdm_wclk : 2; 1318 uint8_t tdm_wclk_bclk_sel : 1; 1319 #endif /* DRV_BYTE_ORDER */ 1320 } ism330bx_tdm_cfg0_t; 1321 1322 #define ISM330BX_TDM_CFG1 0x6DU 1323 typedef struct 1324 { 1325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1326 uint8_t not_used0 : 3; 1327 uint8_t tdm_axes_ord_sel : 2; 1328 uint8_t tdm_xl_z_en : 1; 1329 uint8_t tdm_xl_y_en : 1; 1330 uint8_t tdm_xl_x_en : 1; 1331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1332 uint8_t tdm_xl_x_en : 1; 1333 uint8_t tdm_xl_y_en : 1; 1334 uint8_t tdm_xl_z_en : 1; 1335 uint8_t tdm_axes_ord_sel : 2; 1336 uint8_t not_used0 : 3; 1337 #endif /* DRV_BYTE_ORDER */ 1338 } ism330bx_tdm_cfg1_t; 1339 1340 #define ISM330BX_TDM_CFG2 0x6EU 1341 typedef struct 1342 { 1343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1344 uint8_t tdm_fs_xl : 2; 1345 uint8_t not_used0 : 1; 1346 uint8_t tdm_data_mask : 1; 1347 uint8_t not_used1 : 4; 1348 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1349 uint8_t not_used1 : 4; 1350 uint8_t tdm_data_mask : 1; 1351 uint8_t not_used0 : 1; 1352 uint8_t tdm_fs_xl : 2; 1353 #endif /* DRV_BYTE_ORDER */ 1354 } ism330bx_tdm_cfg2_t; 1355 1356 #define ISM330BX_Z_OFS_USR 0x73U 1357 typedef struct 1358 { 1359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1360 uint8_t z_ofs_usr : 8; 1361 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1362 uint8_t z_ofs_usr : 8; 1363 #endif /* DRV_BYTE_ORDER */ 1364 } ism330bx_z_ofs_usr_t; 1365 1366 #define ISM330BX_Y_OFS_USR 0x74U 1367 typedef struct 1368 { 1369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1370 uint8_t y_ofs_usr : 8; 1371 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1372 uint8_t y_ofs_usr : 8; 1373 #endif /* DRV_BYTE_ORDER */ 1374 } ism330bx_y_ofs_usr_t; 1375 1376 #define ISM330BX_X_OFS_USR 0x75U 1377 typedef struct 1378 { 1379 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1380 uint8_t x_ofs_usr : 8; 1381 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1382 uint8_t x_ofs_usr : 8; 1383 #endif /* DRV_BYTE_ORDER */ 1384 } ism330bx_x_ofs_usr_t; 1385 1386 #define ISM330BX_FIFO_DATA_OUT_TAG 0x78U 1387 typedef struct 1388 { 1389 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1390 uint8_t not_used0 : 1; 1391 uint8_t tag_cnt : 2; 1392 uint8_t tag_sensor : 5; 1393 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1394 uint8_t tag_sensor : 5; 1395 uint8_t tag_cnt : 2; 1396 uint8_t not_used0 : 1; 1397 #endif /* DRV_BYTE_ORDER */ 1398 } ism330bx_fifo_data_out_tag_t; 1399 1400 #define ISM330BX_FIFO_DATA_OUT_BYTE_0 0x79U 1401 typedef struct 1402 { 1403 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1404 uint8_t fifo_data_out : 8; 1405 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1406 uint8_t fifo_data_out : 8; 1407 #endif /* DRV_BYTE_ORDER */ 1408 } ism330bx_fifo_data_out_byte_0_t; 1409 1410 #define ISM330BX_FIFO_DATA_OUT_BYTE_1 0x7AU 1411 typedef struct 1412 { 1413 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1414 uint8_t fifo_data_out : 8; 1415 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1416 uint8_t fifo_data_out : 8; 1417 #endif /* DRV_BYTE_ORDER */ 1418 } ism330bx_fifo_data_out_byte_1_t; 1419 1420 #define ISM330BX_FIFO_DATA_OUT_BYTE_2 0x7BU 1421 typedef struct 1422 { 1423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1424 uint8_t fifo_data_out : 8; 1425 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1426 uint8_t fifo_data_out : 8; 1427 #endif /* DRV_BYTE_ORDER */ 1428 } ism330bx_fifo_data_out_byte_2_t; 1429 1430 #define ISM330BX_FIFO_DATA_OUT_BYTE_3 0x7CU 1431 typedef struct 1432 { 1433 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1434 uint8_t fifo_data_out : 8; 1435 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1436 uint8_t fifo_data_out : 8; 1437 #endif /* DRV_BYTE_ORDER */ 1438 } ism330bx_fifo_data_out_byte_3_t; 1439 1440 #define ISM330BX_FIFO_DATA_OUT_BYTE_4 0x7DU 1441 typedef struct 1442 { 1443 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1444 uint8_t fifo_data_out : 8; 1445 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1446 uint8_t fifo_data_out : 8; 1447 #endif /* DRV_BYTE_ORDER */ 1448 } ism330bx_fifo_data_out_byte_4_t; 1449 1450 #define ISM330BX_FIFO_DATA_OUT_BYTE_5 0x7EU 1451 typedef struct 1452 { 1453 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1454 uint8_t fifo_data_out : 8; 1455 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1456 uint8_t fifo_data_out : 8; 1457 #endif /* DRV_BYTE_ORDER */ 1458 } ism330bx_fifo_data_out_byte_5_t; 1459 1460 /** 1461 * @} 1462 * 1463 */ 1464 1465 /** @defgroup bitfields page embedded 1466 * @{ 1467 * 1468 */ 1469 1470 #define ISM330BX_PAGE_SEL 0x2U 1471 typedef struct 1472 { 1473 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1474 uint8_t not_used0 : 4; 1475 uint8_t page_sel : 4; 1476 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1477 uint8_t page_sel : 4; 1478 uint8_t not_used0 : 4; 1479 #endif /* DRV_BYTE_ORDER */ 1480 } ism330bx_page_sel_t; 1481 1482 #define ISM330BX_EMB_FUNC_EN_A 0x4U 1483 typedef struct 1484 { 1485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1486 uint8_t not_used2 : 1; 1487 uint8_t sflp_game_en : 1; 1488 uint8_t not_used0 : 1; 1489 uint8_t pedo_en : 1; 1490 uint8_t tilt_en : 1; 1491 uint8_t sign_motion_en : 1; 1492 uint8_t not_used1 : 1; 1493 uint8_t mlc_before_fsm_en : 1; 1494 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1495 uint8_t mlc_before_fsm_en : 1; 1496 uint8_t not_used1 : 1; 1497 uint8_t sign_motion_en : 1; 1498 uint8_t tilt_en : 1; 1499 uint8_t pedo_en : 1; 1500 uint8_t not_used0 : 1; 1501 uint8_t sflp_game_en : 1; 1502 uint8_t not_used2 : 1; 1503 #endif /* DRV_BYTE_ORDER */ 1504 } ism330bx_emb_func_en_a_t; 1505 1506 #define ISM330BX_EMB_FUNC_EN_B 0x5U 1507 typedef struct 1508 { 1509 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1510 uint8_t fsm_en : 1; 1511 uint8_t not_used0 : 2; 1512 uint8_t fifo_compr_en : 1; 1513 uint8_t mlc_en : 1; 1514 uint8_t not_used1 : 3; 1515 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1516 uint8_t not_used1 : 3; 1517 uint8_t mlc_en : 1; 1518 uint8_t fifo_compr_en : 1; 1519 uint8_t not_used0 : 2; 1520 uint8_t fsm_en : 1; 1521 #endif /* DRV_BYTE_ORDER */ 1522 } ism330bx_emb_func_en_b_t; 1523 1524 #define ISM330BX_EMB_FUNC_EXEC_STATUS 0x7U 1525 typedef struct 1526 { 1527 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1528 uint8_t emb_func_endop : 1; 1529 uint8_t emb_func_exec_ovr : 1; 1530 uint8_t not_used0 : 6; 1531 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1532 uint8_t not_used0 : 6; 1533 uint8_t emb_func_exec_ovr : 1; 1534 uint8_t emb_func_endop : 1; 1535 #endif /* DRV_BYTE_ORDER */ 1536 } ism330bx_emb_func_exec_status_t; 1537 1538 #define ISM330BX_PAGE_ADDRESS 0x8U 1539 typedef struct 1540 { 1541 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1542 uint8_t page_addr : 8; 1543 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1544 uint8_t page_addr : 8; 1545 #endif /* DRV_BYTE_ORDER */ 1546 } ism330bx_page_address_t; 1547 1548 #define ISM330BX_PAGE_VALUE 0x9U 1549 typedef struct 1550 { 1551 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1552 uint8_t page_value : 8; 1553 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1554 uint8_t page_value : 8; 1555 #endif /* DRV_BYTE_ORDER */ 1556 } ism330bx_page_value_t; 1557 1558 #define ISM330BX_EMB_FUNC_INT1 0x0AU 1559 typedef struct 1560 { 1561 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1562 uint8_t not_used0 : 3; 1563 uint8_t int1_step_detector : 1; 1564 uint8_t int1_tilt : 1; 1565 uint8_t int1_sig_mot : 1; 1566 uint8_t not_used1 : 1; 1567 uint8_t int1_fsm_lc : 1; 1568 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1569 uint8_t int1_fsm_lc : 1; 1570 uint8_t not_used1 : 1; 1571 uint8_t int1_sig_mot : 1; 1572 uint8_t int1_tilt : 1; 1573 uint8_t int1_step_detector : 1; 1574 uint8_t not_used0 : 3; 1575 #endif /* DRV_BYTE_ORDER */ 1576 } ism330bx_emb_func_int1_t; 1577 1578 #define ISM330BX_FSM_INT1 0x0BU 1579 typedef struct 1580 { 1581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1582 uint8_t int1_fsm1 : 1; 1583 uint8_t int1_fsm2 : 1; 1584 uint8_t int1_fsm3 : 1; 1585 uint8_t int1_fsm4 : 1; 1586 uint8_t int1_fsm5 : 1; 1587 uint8_t int1_fsm6 : 1; 1588 uint8_t int1_fsm7 : 1; 1589 uint8_t int1_fsm8 : 1; 1590 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1591 uint8_t int1_fsm8 : 1; 1592 uint8_t int1_fsm7 : 1; 1593 uint8_t int1_fsm6 : 1; 1594 uint8_t int1_fsm5 : 1; 1595 uint8_t int1_fsm4 : 1; 1596 uint8_t int1_fsm3 : 1; 1597 uint8_t int1_fsm2 : 1; 1598 uint8_t int1_fsm1 : 1; 1599 #endif /* DRV_BYTE_ORDER */ 1600 } ism330bx_fsm_int1_t; 1601 1602 #define ISM330BX_MLC_INT1 0x0DU 1603 typedef struct 1604 { 1605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1606 uint8_t int1_mlc1 : 1; 1607 uint8_t int1_mlc2 : 1; 1608 uint8_t int1_mlc3 : 1; 1609 uint8_t int1_mlc4 : 1; 1610 uint8_t not_used0 : 4; 1611 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1612 uint8_t not_used0 : 4; 1613 uint8_t int1_mlc4 : 1; 1614 uint8_t int1_mlc3 : 1; 1615 uint8_t int1_mlc2 : 1; 1616 uint8_t int1_mlc1 : 1; 1617 #endif /* DRV_BYTE_ORDER */ 1618 } ism330bx_mlc_int1_t; 1619 1620 #define ISM330BX_EMB_FUNC_INT2 0x0EU 1621 typedef struct 1622 { 1623 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1624 uint8_t not_used0 : 3; 1625 uint8_t int2_step_detector : 1; 1626 uint8_t int2_tilt : 1; 1627 uint8_t int2_sig_mot : 1; 1628 uint8_t not_used1 : 1; 1629 uint8_t int2_fsm_lc : 1; 1630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1631 uint8_t int2_fsm_lc : 1; 1632 uint8_t not_used1 : 1; 1633 uint8_t int2_sig_mot : 1; 1634 uint8_t int2_tilt : 1; 1635 uint8_t int2_step_detector : 1; 1636 uint8_t not_used0 : 3; 1637 #endif /* DRV_BYTE_ORDER */ 1638 } ism330bx_emb_func_int2_t; 1639 1640 #define ISM330BX_FSM_INT2 0x0FU 1641 typedef struct 1642 { 1643 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1644 uint8_t int2_fsm1 : 1; 1645 uint8_t int2_fsm2 : 1; 1646 uint8_t int2_fsm3 : 1; 1647 uint8_t int2_fsm4 : 1; 1648 uint8_t int2_fsm5 : 1; 1649 uint8_t int2_fsm6 : 1; 1650 uint8_t int2_fsm7 : 1; 1651 uint8_t int2_fsm8 : 1; 1652 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1653 uint8_t int2_fsm8 : 1; 1654 uint8_t int2_fsm7 : 1; 1655 uint8_t int2_fsm6 : 1; 1656 uint8_t int2_fsm5 : 1; 1657 uint8_t int2_fsm4 : 1; 1658 uint8_t int2_fsm3 : 1; 1659 uint8_t int2_fsm2 : 1; 1660 uint8_t int2_fsm1 : 1; 1661 #endif /* DRV_BYTE_ORDER */ 1662 } ism330bx_fsm_int2_t; 1663 1664 #define ISM330BX_MLC_INT2 0x11U 1665 typedef struct 1666 { 1667 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1668 uint8_t int2_mlc1 : 1; 1669 uint8_t int2_mlc2 : 1; 1670 uint8_t int2_mlc3 : 1; 1671 uint8_t int2_mlc4 : 1; 1672 uint8_t not_used0 : 4; 1673 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1674 uint8_t not_used0 : 4; 1675 uint8_t int2_mlc4 : 1; 1676 uint8_t int2_mlc3 : 1; 1677 uint8_t int2_mlc2 : 1; 1678 uint8_t int2_mlc1 : 1; 1679 #endif /* DRV_BYTE_ORDER */ 1680 } ism330bx_mlc_int2_t; 1681 1682 #define ISM330BX_EMB_FUNC_STATUS 0x12U 1683 typedef struct 1684 { 1685 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1686 uint8_t not_used0 : 3; 1687 uint8_t is_step_det : 1; 1688 uint8_t is_tilt : 1; 1689 uint8_t is_sigmot : 1; 1690 uint8_t not_used1 : 1; 1691 uint8_t is_fsm_lc : 1; 1692 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1693 uint8_t is_fsm_lc : 1; 1694 uint8_t not_used1 : 1; 1695 uint8_t is_sigmot : 1; 1696 uint8_t is_tilt : 1; 1697 uint8_t is_step_det : 1; 1698 uint8_t not_used0 : 3; 1699 #endif /* DRV_BYTE_ORDER */ 1700 } ism330bx_emb_func_status_t; 1701 1702 #define ISM330BX_FSM_STATUS 0x13U 1703 typedef struct 1704 { 1705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1706 uint8_t is_fsm1 : 1; 1707 uint8_t is_fsm2 : 1; 1708 uint8_t is_fsm3 : 1; 1709 uint8_t is_fsm4 : 1; 1710 uint8_t is_fsm5 : 1; 1711 uint8_t is_fsm6 : 1; 1712 uint8_t is_fsm7 : 1; 1713 uint8_t is_fsm8 : 1; 1714 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1715 uint8_t is_fsm8 : 1; 1716 uint8_t is_fsm7 : 1; 1717 uint8_t is_fsm6 : 1; 1718 uint8_t is_fsm5 : 1; 1719 uint8_t is_fsm4 : 1; 1720 uint8_t is_fsm3 : 1; 1721 uint8_t is_fsm2 : 1; 1722 uint8_t is_fsm1 : 1; 1723 #endif /* DRV_BYTE_ORDER */ 1724 } ism330bx_fsm_status_t; 1725 1726 #define ISM330BX_MLC_STATUS 0x15U 1727 typedef struct 1728 { 1729 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1730 uint8_t is_mlc1 : 1; 1731 uint8_t is_mlc2 : 1; 1732 uint8_t is_mlc3 : 1; 1733 uint8_t is_mlc4 : 1; 1734 uint8_t not_used0 : 4; 1735 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1736 uint8_t not_used0 : 4; 1737 uint8_t is_mlc4 : 1; 1738 uint8_t is_mlc3 : 1; 1739 uint8_t is_mlc2 : 1; 1740 uint8_t is_mlc1 : 1; 1741 #endif /* DRV_BYTE_ORDER */ 1742 } ism330bx_mlc_status_t; 1743 1744 #define ISM330BX_PAGE_RW 0x17U 1745 typedef struct 1746 { 1747 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1748 uint8_t not_used0 : 5; 1749 uint8_t page_read : 1; 1750 uint8_t page_write : 1; 1751 uint8_t emb_func_lir : 1; 1752 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1753 uint8_t emb_func_lir : 1; 1754 uint8_t page_write : 1; 1755 uint8_t page_read : 1; 1756 uint8_t not_used0 : 5; 1757 #endif /* DRV_BYTE_ORDER */ 1758 } ism330bx_page_rw_t; 1759 1760 #define ISM330BX_EMB_FUNC_FIFO_EN_A 0x44U 1761 typedef struct 1762 { 1763 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1764 uint8_t not_used0 : 1; 1765 uint8_t sflp_game_fifo_en : 1; 1766 uint8_t not_used1 : 2; 1767 uint8_t sflp_gravity_fifo_en : 1; 1768 uint8_t sflp_gbias_fifo_en : 1; 1769 uint8_t step_counter_fifo_en : 1; 1770 uint8_t mlc_fifo_en : 1; 1771 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1772 uint8_t mlc_fifo_en : 1; 1773 uint8_t step_counter_fifo_en : 1; 1774 uint8_t sflp_gbias_fifo_en : 1; 1775 uint8_t sflp_gravity_fifo_en : 1; 1776 uint8_t not_used1 : 2; 1777 uint8_t sflp_game_fifo_en : 1; 1778 uint8_t not_used0 : 1; 1779 #endif /* DRV_BYTE_ORDER */ 1780 } ism330bx_emb_func_fifo_en_a_t; 1781 1782 #define ISM330BX_EMB_FUNC_FIFO_EN_B 0x45U 1783 typedef struct 1784 { 1785 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1786 uint8_t not_used0 : 1; 1787 uint8_t mlc_filter_feature_fifo_en : 1; 1788 uint8_t not_used1 : 6; 1789 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1790 uint8_t not_used1 : 6; 1791 uint8_t mlc_filter_feature_fifo_en : 1; 1792 uint8_t not_used0 : 1; 1793 #endif /* DRV_BYTE_ORDER */ 1794 } ism330bx_emb_func_fifo_en_b_t; 1795 1796 #define ISM330BX_FSM_ENABLE 0x46U 1797 typedef struct 1798 { 1799 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1800 uint8_t fsm1_en : 1; 1801 uint8_t fsm2_en : 1; 1802 uint8_t fsm3_en : 1; 1803 uint8_t fsm4_en : 1; 1804 uint8_t fsm5_en : 1; 1805 uint8_t fsm6_en : 1; 1806 uint8_t fsm7_en : 1; 1807 uint8_t fsm8_en : 1; 1808 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1809 uint8_t fsm8_en : 1; 1810 uint8_t fsm7_en : 1; 1811 uint8_t fsm6_en : 1; 1812 uint8_t fsm5_en : 1; 1813 uint8_t fsm4_en : 1; 1814 uint8_t fsm3_en : 1; 1815 uint8_t fsm2_en : 1; 1816 uint8_t fsm1_en : 1; 1817 #endif /* DRV_BYTE_ORDER */ 1818 } ism330bx_fsm_enable_t; 1819 1820 #define ISM330BX_FSM_LONG_COUNTER_L 0x48U 1821 typedef struct 1822 { 1823 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1824 uint8_t fsm_lc : 8; 1825 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1826 uint8_t fsm_lc : 8; 1827 #endif /* DRV_BYTE_ORDER */ 1828 } ism330bx_fsm_long_counter_l_t; 1829 1830 #define ISM330BX_FSM_LONG_COUNTER_H 0x49U 1831 typedef struct 1832 { 1833 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1834 uint8_t fsm_lc : 8; 1835 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1836 uint8_t fsm_lc : 8; 1837 #endif /* DRV_BYTE_ORDER */ 1838 } ism330bx_fsm_long_counter_h_t; 1839 1840 #define ISM330BX_INT_ACK_MASK 0x4BU 1841 typedef struct 1842 { 1843 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1844 uint8_t iack_mask : 8; 1845 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1846 uint8_t iack_mask : 8; 1847 #endif /* DRV_BYTE_ORDER */ 1848 } ism330bx_int_ack_mask_t; 1849 1850 #define ISM330BX_FSM_OUTS1 0x4CU 1851 typedef struct 1852 { 1853 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1854 uint8_t fsm1_n_v : 1; 1855 uint8_t fsm1_p_v : 1; 1856 uint8_t fsm1_n_3 : 1; 1857 uint8_t fsm1_p_3 : 1; 1858 uint8_t fsm1_n_2 : 1; 1859 uint8_t fsm1_p_2 : 1; 1860 uint8_t fsm1_n_1 : 1; 1861 uint8_t fsm1_p_1 : 1; 1862 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1863 uint8_t fsm1_p_1 : 1; 1864 uint8_t fsm1_n_1 : 1; 1865 uint8_t fsm1_p_2 : 1; 1866 uint8_t fsm1_n_2 : 1; 1867 uint8_t fsm1_p_3 : 1; 1868 uint8_t fsm1_n_3 : 1; 1869 uint8_t fsm1_p_v : 1; 1870 uint8_t fsm1_n_v : 1; 1871 #endif /* DRV_BYTE_ORDER */ 1872 } ism330bx_fsm_outs1_t; 1873 1874 #define ISM330BX_FSM_OUTS2 0x4DU 1875 typedef struct 1876 { 1877 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1878 uint8_t fsm2_n_v : 1; 1879 uint8_t fsm2_p_v : 1; 1880 uint8_t fsm2_n_3 : 1; 1881 uint8_t fsm2_p_3 : 1; 1882 uint8_t fsm2_n_2 : 1; 1883 uint8_t fsm2_p_2 : 1; 1884 uint8_t fsm2_n_1 : 1; 1885 uint8_t fsm2_p_1 : 1; 1886 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1887 uint8_t fsm2_p_1 : 1; 1888 uint8_t fsm2_n_1 : 1; 1889 uint8_t fsm2_p_2 : 1; 1890 uint8_t fsm2_n_2 : 1; 1891 uint8_t fsm2_p_3 : 1; 1892 uint8_t fsm2_n_3 : 1; 1893 uint8_t fsm2_p_v : 1; 1894 uint8_t fsm2_n_v : 1; 1895 #endif /* DRV_BYTE_ORDER */ 1896 } ism330bx_fsm_outs2_t; 1897 1898 #define ISM330BX_FSM_OUTS3 0x4EU 1899 typedef struct 1900 { 1901 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1902 uint8_t fsm3_n_v : 1; 1903 uint8_t fsm3_p_v : 1; 1904 uint8_t fsm3_n_3 : 1; 1905 uint8_t fsm3_p_3 : 1; 1906 uint8_t fsm3_n_2 : 1; 1907 uint8_t fsm3_p_2 : 1; 1908 uint8_t fsm3_n_1 : 1; 1909 uint8_t fsm3_p_1 : 1; 1910 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1911 uint8_t fsm3_p_1 : 1; 1912 uint8_t fsm3_n_1 : 1; 1913 uint8_t fsm3_p_2 : 1; 1914 uint8_t fsm3_n_2 : 1; 1915 uint8_t fsm3_p_3 : 1; 1916 uint8_t fsm3_n_3 : 1; 1917 uint8_t fsm3_p_v : 1; 1918 uint8_t fsm3_n_v : 1; 1919 #endif /* DRV_BYTE_ORDER */ 1920 } ism330bx_fsm_outs3_t; 1921 1922 #define ISM330BX_FSM_OUTS4 0x4FU 1923 typedef struct 1924 { 1925 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1926 uint8_t fsm4_n_v : 1; 1927 uint8_t fsm4_p_v : 1; 1928 uint8_t fsm4_n_3 : 1; 1929 uint8_t fsm4_p_3 : 1; 1930 uint8_t fsm4_n_2 : 1; 1931 uint8_t fsm4_p_2 : 1; 1932 uint8_t fsm4_n_1 : 1; 1933 uint8_t fsm4_p_1 : 1; 1934 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1935 uint8_t fsm4_p_1 : 1; 1936 uint8_t fsm4_n_1 : 1; 1937 uint8_t fsm4_p_2 : 1; 1938 uint8_t fsm4_n_2 : 1; 1939 uint8_t fsm4_p_3 : 1; 1940 uint8_t fsm4_n_3 : 1; 1941 uint8_t fsm4_p_v : 1; 1942 uint8_t fsm4_n_v : 1; 1943 #endif /* DRV_BYTE_ORDER */ 1944 } ism330bx_fsm_outs4_t; 1945 1946 #define ISM330BX_FSM_OUTS5 0x50U 1947 typedef struct 1948 { 1949 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1950 uint8_t fsm5_n_v : 1; 1951 uint8_t fsm5_p_v : 1; 1952 uint8_t fsm5_n_3 : 1; 1953 uint8_t fsm5_p_3 : 1; 1954 uint8_t fsm5_n_2 : 1; 1955 uint8_t fsm5_p_2 : 1; 1956 uint8_t fsm5_n_1 : 1; 1957 uint8_t fsm5_p_1 : 1; 1958 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1959 uint8_t fsm5_p_1 : 1; 1960 uint8_t fsm5_n_1 : 1; 1961 uint8_t fsm5_p_2 : 1; 1962 uint8_t fsm5_n_2 : 1; 1963 uint8_t fsm5_p_3 : 1; 1964 uint8_t fsm5_n_3 : 1; 1965 uint8_t fsm5_p_v : 1; 1966 uint8_t fsm5_n_v : 1; 1967 #endif /* DRV_BYTE_ORDER */ 1968 } ism330bx_fsm_outs5_t; 1969 1970 #define ISM330BX_FSM_OUTS6 0x51U 1971 typedef struct 1972 { 1973 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1974 uint8_t fsm6_n_v : 1; 1975 uint8_t fsm6_p_v : 1; 1976 uint8_t fsm6_n_3 : 1; 1977 uint8_t fsm6_p_3 : 1; 1978 uint8_t fsm6_n_2 : 1; 1979 uint8_t fsm6_p_2 : 1; 1980 uint8_t fsm6_n_1 : 1; 1981 uint8_t fsm6_p_1 : 1; 1982 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1983 uint8_t fsm6_p_1 : 1; 1984 uint8_t fsm6_n_1 : 1; 1985 uint8_t fsm6_p_2 : 1; 1986 uint8_t fsm6_n_2 : 1; 1987 uint8_t fsm6_p_3 : 1; 1988 uint8_t fsm6_n_3 : 1; 1989 uint8_t fsm6_p_v : 1; 1990 uint8_t fsm6_n_v : 1; 1991 #endif /* DRV_BYTE_ORDER */ 1992 } ism330bx_fsm_outs6_t; 1993 1994 #define ISM330BX_FSM_OUTS7 0x52U 1995 typedef struct 1996 { 1997 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1998 uint8_t fsm7_n_v : 1; 1999 uint8_t fsm7_p_v : 1; 2000 uint8_t fsm7_n_3 : 1; 2001 uint8_t fsm7_p_3 : 1; 2002 uint8_t fsm7_n_2 : 1; 2003 uint8_t fsm7_p_2 : 1; 2004 uint8_t fsm7_n_1 : 1; 2005 uint8_t fsm7_p_1 : 1; 2006 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2007 uint8_t fsm7_p_1 : 1; 2008 uint8_t fsm7_n_1 : 1; 2009 uint8_t fsm7_p_2 : 1; 2010 uint8_t fsm7_n_2 : 1; 2011 uint8_t fsm7_p_3 : 1; 2012 uint8_t fsm7_n_3 : 1; 2013 uint8_t fsm7_p_v : 1; 2014 uint8_t fsm7_n_v : 1; 2015 #endif /* DRV_BYTE_ORDER */ 2016 } ism330bx_fsm_outs7_t; 2017 2018 #define ISM330BX_FSM_OUTS8 0x53U 2019 typedef struct 2020 { 2021 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2022 uint8_t fsm8_n_v : 1; 2023 uint8_t fsm8_p_v : 1; 2024 uint8_t fsm8_n_3 : 1; 2025 uint8_t fsm8_p_3 : 1; 2026 uint8_t fsm8_n_2 : 1; 2027 uint8_t fsm8_p_2 : 1; 2028 uint8_t fsm8_n_1 : 1; 2029 uint8_t fsm8_p_1 : 1; 2030 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2031 uint8_t fsm8_p_1 : 1; 2032 uint8_t fsm8_n_1 : 1; 2033 uint8_t fsm8_p_2 : 1; 2034 uint8_t fsm8_n_2 : 1; 2035 uint8_t fsm8_p_3 : 1; 2036 uint8_t fsm8_n_3 : 1; 2037 uint8_t fsm8_p_v : 1; 2038 uint8_t fsm8_n_v : 1; 2039 #endif /* DRV_BYTE_ORDER */ 2040 } ism330bx_fsm_outs8_t; 2041 2042 #define ISM330BX_SFLP_ODR 0x5EU 2043 typedef struct 2044 { 2045 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2046 uint8_t not_used0 : 3; 2047 uint8_t sflp_game_odr : 3; 2048 uint8_t not_used1 : 2; 2049 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2050 uint8_t not_used1 : 2; 2051 uint8_t sflp_game_odr : 3; 2052 uint8_t not_used0 : 3; 2053 #endif /* DRV_BYTE_ORDER */ 2054 } ism330bx_sflp_odr_t; 2055 2056 #define ISM330BX_FSM_ODR 0x5FU 2057 typedef struct 2058 { 2059 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2060 uint8_t not_used0 : 3; 2061 uint8_t fsm_odr : 3; 2062 uint8_t not_used1 : 2; 2063 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2064 uint8_t not_used1 : 2; 2065 uint8_t fsm_odr : 3; 2066 uint8_t not_used0 : 3; 2067 #endif /* DRV_BYTE_ORDER */ 2068 } ism330bx_fsm_odr_t; 2069 2070 #define ISM330BX_MLC_ODR 0x60U 2071 typedef struct 2072 { 2073 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2074 uint8_t not_used0 : 4; 2075 uint8_t mlc_odr : 3; 2076 uint8_t not_used1 : 1; 2077 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2078 uint8_t not_used1 : 1; 2079 uint8_t mlc_odr : 3; 2080 uint8_t not_used0 : 4; 2081 #endif /* DRV_BYTE_ORDER */ 2082 } ism330bx_mlc_odr_t; 2083 2084 #define ISM330BX_STEP_COUNTER_L 0x62U 2085 typedef struct 2086 { 2087 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2088 uint8_t step : 8; 2089 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2090 uint8_t step : 8; 2091 #endif /* DRV_BYTE_ORDER */ 2092 } ism330bx_step_counter_l_t; 2093 2094 #define ISM330BX_STEP_COUNTER_H 0x63U 2095 typedef struct 2096 { 2097 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2098 uint8_t step : 8; 2099 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2100 uint8_t step : 8; 2101 #endif /* DRV_BYTE_ORDER */ 2102 } ism330bx_step_counter_h_t; 2103 2104 #define ISM330BX_EMB_FUNC_SRC 0x64U 2105 typedef struct 2106 { 2107 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2108 uint8_t not_used0 : 2; 2109 uint8_t stepcounter_bit_set : 1; 2110 uint8_t step_overflow : 1; 2111 uint8_t step_count_delta_ia : 1; 2112 uint8_t step_detected : 1; 2113 uint8_t not_used1 : 1; 2114 uint8_t pedo_rst_step : 1; 2115 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2116 uint8_t pedo_rst_step : 1; 2117 uint8_t not_used1 : 1; 2118 uint8_t step_detected : 1; 2119 uint8_t step_count_delta_ia : 1; 2120 uint8_t step_overflow : 1; 2121 uint8_t stepcounter_bit_set : 1; 2122 uint8_t not_used0 : 2; 2123 #endif /* DRV_BYTE_ORDER */ 2124 } ism330bx_emb_func_src_t; 2125 2126 #define ISM330BX_EMB_FUNC_INIT_A 0x66U 2127 typedef struct 2128 { 2129 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2130 uint8_t not_used0 : 1; 2131 uint8_t sflp_game_init : 1; 2132 uint8_t not_used2 : 1; 2133 uint8_t step_det_init : 1; 2134 uint8_t tilt_init : 1; 2135 uint8_t sig_mot_init : 1; 2136 uint8_t not_used1 : 1; 2137 uint8_t mlc_before_fsm_init : 1; 2138 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2139 uint8_t mlc_before_fsm_init : 1; 2140 uint8_t not_used1 : 1; 2141 uint8_t sig_mot_init : 1; 2142 uint8_t tilt_init : 1; 2143 uint8_t step_det_init : 1; 2144 uint8_t not_used2 : 1; 2145 uint8_t sflp_game_init : 1; 2146 uint8_t not_used0 : 1; 2147 #endif /* DRV_BYTE_ORDER */ 2148 } ism330bx_emb_func_init_a_t; 2149 2150 #define ISM330BX_EMB_FUNC_INIT_B 0x67U 2151 typedef struct 2152 { 2153 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2154 uint8_t fsm_init : 1; 2155 uint8_t not_used0 : 2; 2156 uint8_t fifo_compr_init : 1; 2157 uint8_t mlc_init : 1; 2158 uint8_t not_used1 : 3; 2159 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2160 uint8_t not_used1 : 3; 2161 uint8_t mlc_init : 1; 2162 uint8_t fifo_compr_init : 1; 2163 uint8_t not_used0 : 2; 2164 uint8_t fsm_init : 1; 2165 #endif /* DRV_BYTE_ORDER */ 2166 } ism330bx_emb_func_init_b_t; 2167 2168 #define ISM330BX_MLC1_SRC 0x70U 2169 typedef struct 2170 { 2171 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2172 uint8_t mlc1_src : 8; 2173 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2174 uint8_t mlc1_src : 8; 2175 #endif /* DRV_BYTE_ORDER */ 2176 } ism330bx_mlc1_src_t; 2177 2178 #define ISM330BX_MLC2_SRC 0x71U 2179 typedef struct 2180 { 2181 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2182 uint8_t mlc2_src : 8; 2183 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2184 uint8_t mlc2_src : 8; 2185 #endif /* DRV_BYTE_ORDER */ 2186 } ism330bx_mlc2_src_t; 2187 2188 #define ISM330BX_MLC3_SRC 0x72U 2189 typedef struct 2190 { 2191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2192 uint8_t mlc3_src : 8; 2193 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2194 uint8_t mlc3_src : 8; 2195 #endif /* DRV_BYTE_ORDER */ 2196 } ism330bx_mlc3_src_t; 2197 2198 #define ISM330BX_MLC4_SRC 0x73U 2199 typedef struct 2200 { 2201 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2202 uint8_t mlc4_src : 8; 2203 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2204 uint8_t mlc4_src : 8; 2205 #endif /* DRV_BYTE_ORDER */ 2206 } ism330bx_mlc4_src_t; 2207 2208 /** 2209 * @} 2210 * 2211 */ 2212 2213 /** @defgroup bitfields page pg0_emb_adv 2214 * @{ 2215 * 2216 */ 2217 #define ISM330BX_EMB_ADV_PG_0 0x000 2218 2219 #define ISM330BX_SFLP_GAME_GBIASX_L 0x6EU 2220 typedef struct 2221 { 2222 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2223 uint8_t gbiasx : 8; 2224 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2225 uint8_t gbiasx : 8; 2226 #endif /* DRV_BYTE_ORDER */ 2227 } ism330bx_sflp_game_gbiasx_l_t; 2228 2229 #define ISM330BX_SFLP_GAME_GBIASX_H 0x6FU 2230 typedef struct 2231 { 2232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2233 uint8_t gbiasx : 8; 2234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2235 uint8_t gbiasx : 8; 2236 #endif /* DRV_BYTE_ORDER */ 2237 } ism330bx_sflp_game_gbiasx_h_t; 2238 2239 #define ISM330BX_SFLP_GAME_GBIASY_L 0x70U 2240 typedef struct 2241 { 2242 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2243 uint8_t gbiasy : 8; 2244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2245 uint8_t gbiasy : 8; 2246 #endif /* DRV_BYTE_ORDER */ 2247 } ism330bx_sflp_game_gbiasy_l_t; 2248 2249 #define ISM330BX_SFLP_GAME_GBIASY_H 0x71U 2250 typedef struct 2251 { 2252 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2253 uint8_t gbiasy : 8; 2254 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2255 uint8_t gbiasy : 8; 2256 #endif /* DRV_BYTE_ORDER */ 2257 } ism330bx_sflp_game_gbiasy_h_t; 2258 2259 #define ISM330BX_SFLP_GAME_GBIASZ_L 0x72U 2260 typedef struct 2261 { 2262 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2263 uint8_t gbiasz : 8; 2264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2265 uint8_t gbiasz : 8; 2266 #endif /* DRV_BYTE_ORDER */ 2267 } ism330bx_sflp_game_gbiasz_l_t; 2268 2269 #define ISM330BX_SFLP_GAME_GBIASZ_H 0x73U 2270 typedef struct 2271 { 2272 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2273 uint8_t gbiasz : 8; 2274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2275 uint8_t gbiasz : 8; 2276 #endif /* DRV_BYTE_ORDER */ 2277 } ism330bx_sflp_game_gbiasz_h_t; 2278 2279 #define ISM330BX_FSM_QVAR_SENSITIVITY_L 0xBAU 2280 typedef struct 2281 { 2282 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2283 uint8_t fsm_qvar_s : 8; 2284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2285 uint8_t fsm_qvar_s : 8; 2286 #endif /* DRV_BYTE_ORDER */ 2287 } ism330bx_fsm_qvar_sensitivity_l_t; 2288 2289 #define ISM330BX_FSM_QVAR_SENSITIVITY_H 0xBBU 2290 typedef struct 2291 { 2292 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2293 uint8_t fsm_qvar_s : 8; 2294 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2295 uint8_t fsm_qvar_s : 8; 2296 #endif /* DRV_BYTE_ORDER */ 2297 } ism330bx_fsm_qvar_sensitivity_h_t; 2298 2299 /** 2300 * @} 2301 * 2302 */ 2303 2304 /** @defgroup bitfields page pg1_emb_adv 2305 * @{ 2306 * 2307 */ 2308 2309 #define ISM330BX_EMB_ADV_PG_1 0x001 2310 2311 #define ISM330BX_FSM_LC_TIMEOUT_L 0x17AU 2312 typedef struct 2313 { 2314 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2315 uint8_t fsm_lc_timeout : 8; 2316 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2317 uint8_t fsm_lc_timeout : 8; 2318 #endif /* DRV_BYTE_ORDER */ 2319 } ism330bx_fsm_lc_timeout_l_t; 2320 2321 #define ISM330BX_FSM_LC_TIMEOUT_H 0x17BU 2322 typedef struct 2323 { 2324 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2325 uint8_t fsm_lc_timeout : 8; 2326 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2327 uint8_t fsm_lc_timeout : 8; 2328 #endif /* DRV_BYTE_ORDER */ 2329 } ism330bx_fsm_lc_timeout_h_t; 2330 2331 #define ISM330BX_FSM_PROGRAMS 0x17CU 2332 typedef struct 2333 { 2334 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2335 uint8_t fsm_n_prog : 8; 2336 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2337 uint8_t fsm_n_prog : 8; 2338 #endif /* DRV_BYTE_ORDER */ 2339 } ism330bx_fsm_programs_t; 2340 2341 #define ISM330BX_FSM_START_ADD_L 0x17EU 2342 typedef struct 2343 { 2344 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2345 uint8_t fsm_start : 8; 2346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2347 uint8_t fsm_start : 8; 2348 #endif /* DRV_BYTE_ORDER */ 2349 } ism330bx_fsm_start_add_l_t; 2350 2351 #define ISM330BX_FSM_START_ADD_H 0x17FU 2352 typedef struct 2353 { 2354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2355 uint8_t fsm_start : 8; 2356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2357 uint8_t fsm_start : 8; 2358 #endif /* DRV_BYTE_ORDER */ 2359 } ism330bx_fsm_start_add_h_t; 2360 2361 #define ISM330BX_PEDO_CMD_REG 0x183U 2362 typedef struct 2363 { 2364 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2365 uint8_t not_used0 : 2; 2366 uint8_t fp_rejection_en : 1; 2367 uint8_t carry_count_en : 1; 2368 uint8_t not_used1 : 4; 2369 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2370 uint8_t not_used1 : 4; 2371 uint8_t carry_count_en : 1; 2372 uint8_t fp_rejection_en : 1; 2373 uint8_t not_used0 : 2; 2374 #endif /* DRV_BYTE_ORDER */ 2375 } ism330bx_pedo_cmd_reg_t; 2376 2377 #define ISM330BX_PEDO_DEB_STEPS_CONF 0x184U 2378 typedef struct 2379 { 2380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2381 uint8_t deb_step : 8; 2382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2383 uint8_t deb_step : 8; 2384 #endif /* DRV_BYTE_ORDER */ 2385 } ism330bx_pedo_deb_steps_conf_t; 2386 2387 #define ISM330BX_PEDO_SC_DELTAT_L 0x1D0U 2388 typedef struct 2389 { 2390 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2391 uint8_t pd_sc : 8; 2392 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2393 uint8_t pd_sc : 8; 2394 #endif /* DRV_BYTE_ORDER */ 2395 } ism330bx_pedo_sc_deltat_l_t; 2396 2397 #define ISM330BX_PEDO_SC_DELTAT_H 0x1D1U 2398 typedef struct 2399 { 2400 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2401 uint8_t pd_sc : 8; 2402 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2403 uint8_t pd_sc : 8; 2404 #endif /* DRV_BYTE_ORDER */ 2405 } ism330bx_pedo_sc_deltat_h_t; 2406 2407 #define ISM330BX_MLC_QVAR_SENSITIVITY_L 0x1E8U 2408 typedef struct 2409 { 2410 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2411 uint8_t mlc_qvar_s : 8; 2412 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2413 uint8_t mlc_qvar_s : 8; 2414 #endif /* DRV_BYTE_ORDER */ 2415 } ism330bx_mlc_qvar_sensitivity_l_t; 2416 2417 #define ISM330BX_MLC_QVAR_SENSITIVITY_H 0x1E9U 2418 typedef struct 2419 { 2420 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2421 uint8_t mlc_qvar_s : 8; 2422 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2423 uint8_t mlc_qvar_s : 8; 2424 #endif /* DRV_BYTE_ORDER */ 2425 } ism330bx_mlc_qvar_sensitivity_h_t; 2426 2427 /** 2428 * @} 2429 * 2430 */ 2431 2432 #define ISM330BX_START_FSM_ADD 0x035CU 2433 2434 /** 2435 * @defgroup ISM330BX_Register_Union 2436 * @brief These unions group all the registers having a bit-field 2437 * description. 2438 * These unions are useful but it's not needed by the driver. 2439 * 2440 * REMOVING this unions you are compliant with: 2441 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2442 * 2443 * @{ 2444 * 2445 */ 2446 typedef union 2447 { 2448 ism330bx_func_cfg_access_t func_cfg_access; 2449 ism330bx_pin_ctrl_t pin_ctrl; 2450 ism330bx_if_cfg_t if_cfg; 2451 ism330bx_fifo_ctrl1_t fifo_ctrl1; 2452 ism330bx_fifo_ctrl2_t fifo_ctrl2; 2453 ism330bx_fifo_ctrl3_t fifo_ctrl3; 2454 ism330bx_fifo_ctrl4_t fifo_ctrl4; 2455 ism330bx_counter_bdr_reg1_t counter_bdr_reg1; 2456 ism330bx_counter_bdr_reg2_t counter_bdr_reg2; 2457 ism330bx_int1_ctrl_t int1_ctrl; 2458 ism330bx_int2_ctrl_t int2_ctrl; 2459 ism330bx_who_am_i_t who_am_i; 2460 ism330bx_ctrl1_t ctrl1; 2461 ism330bx_ctrl2_t ctrl2; 2462 ism330bx_ctrl3_t ctrl3; 2463 ism330bx_ctrl4_t ctrl4; 2464 ism330bx_ctrl5_t ctrl5; 2465 ism330bx_ctrl6_t ctrl6; 2466 ism330bx_ctrl7_t ctrl7; 2467 ism330bx_ctrl8_t ctrl8; 2468 ism330bx_ctrl9_t ctrl9; 2469 ism330bx_ctrl10_t ctrl10; 2470 ism330bx_fifo_status1_t fifo_status1; 2471 ism330bx_fifo_status2_t fifo_status2; 2472 ism330bx_all_int_src_t all_int_src; 2473 ism330bx_status_reg_t status_reg; 2474 ism330bx_out_temp_l_t out_temp_l; 2475 ism330bx_out_temp_h_t out_temp_h; 2476 ism330bx_outx_l_g_t outx_l_g; 2477 ism330bx_outx_h_g_t outx_h_g; 2478 ism330bx_outy_l_g_t outy_l_g; 2479 ism330bx_outy_h_g_t outy_h_g; 2480 ism330bx_outz_l_g_t outz_l_g; 2481 ism330bx_outz_h_g_t outz_h_g; 2482 ism330bx_outz_l_a_t outz_l_a; 2483 ism330bx_outz_h_a_t outz_h_a; 2484 ism330bx_outy_l_a_t outy_l_a; 2485 ism330bx_outy_h_a_t outy_h_a; 2486 ism330bx_outx_l_a_t outx_l_a; 2487 ism330bx_outx_h_a_t outx_h_a; 2488 ism330bx_ui_outz_l_a_dualc_t ui_outz_l_a_dualc; 2489 ism330bx_ui_outz_h_a_dualc_t ui_outz_h_a_dualc; 2490 ism330bx_ui_outy_l_a_dualc_t ui_outy_l_a_dualc; 2491 ism330bx_ui_outy_h_a_dualc_t ui_outy_h_a_dualc; 2492 ism330bx_ui_outx_l_a_dualc_t ui_outx_l_a_dualc; 2493 ism330bx_ui_outx_h_a_dualc_t ui_outx_h_a_dualc; 2494 ism330bx_ah_qvar_out_l_t ah_qvar_out_l; 2495 ism330bx_ah_qvar_out_h_t ah_qvar_out_h; 2496 ism330bx_timestamp0_t timestamp0; 2497 ism330bx_timestamp1_t timestamp1; 2498 ism330bx_timestamp2_t timestamp2; 2499 ism330bx_timestamp3_t timestamp3; 2500 ism330bx_wake_up_src_t wake_up_src; 2501 ism330bx_tap_src_t tap_src; 2502 ism330bx_d6d_src_t d6d_src; 2503 ism330bx_emb_func_status_mainpage_t emb_func_status_mainpage; 2504 ism330bx_fsm_status_mainpage_t fsm_status_mainpage; 2505 ism330bx_mlc_status_mainpage_t mlc_status_mainpage; 2506 ism330bx_internal_freq_t internal_freq; 2507 ism330bx_functions_enable_t functions_enable; 2508 ism330bx_inactivity_dur_t inactivity_dur; 2509 ism330bx_inactivity_ths_t inactivity_ths; 2510 ism330bx_tap_cfg0_t tap_cfg0; 2511 ism330bx_tap_cfg1_t tap_cfg1; 2512 ism330bx_tap_cfg2_t tap_cfg2; 2513 ism330bx_tap_ths_6d_t tap_ths_6d; 2514 ism330bx_tap_dur_t int_dur2; 2515 ism330bx_wake_up_ths_t wake_up_ths; 2516 ism330bx_wake_up_dur_t wake_up_dur; 2517 ism330bx_free_fall_t free_fall; 2518 ism330bx_md1_cfg_t md1_cfg; 2519 ism330bx_md2_cfg_t md2_cfg; 2520 ism330bx_emb_func_cfg_t emb_func_cfg; 2521 ism330bx_tdm_cfg0_t tdm_cfg0; 2522 ism330bx_tdm_cfg1_t tdm_cfg1; 2523 ism330bx_tdm_cfg2_t tdm_cfg2; 2524 ism330bx_z_ofs_usr_t z_ofs_usr; 2525 ism330bx_y_ofs_usr_t y_ofs_usr; 2526 ism330bx_x_ofs_usr_t x_ofs_usr; 2527 ism330bx_fifo_data_out_tag_t fifo_data_out_tag; 2528 ism330bx_fifo_data_out_byte_0_t fifo_data_out_byte_0; 2529 ism330bx_fifo_data_out_byte_1_t fifo_data_out_byte_1; 2530 ism330bx_fifo_data_out_byte_2_t fifo_data_out_byte_2; 2531 ism330bx_fifo_data_out_byte_3_t fifo_data_out_byte_3; 2532 ism330bx_fifo_data_out_byte_4_t fifo_data_out_byte_4; 2533 ism330bx_fifo_data_out_byte_5_t fifo_data_out_byte_5; 2534 ism330bx_page_sel_t page_sel; 2535 ism330bx_emb_func_en_a_t emb_func_en_a; 2536 ism330bx_emb_func_en_b_t emb_func_en_b; 2537 ism330bx_emb_func_exec_status_t emb_func_exec_status; 2538 ism330bx_page_address_t page_address; 2539 ism330bx_page_value_t page_value; 2540 ism330bx_emb_func_int1_t emb_func_int1; 2541 ism330bx_fsm_int1_t fsm_int1; 2542 ism330bx_mlc_int1_t mlc_int1; 2543 ism330bx_emb_func_int2_t emb_func_int2; 2544 ism330bx_fsm_int2_t fsm_int2; 2545 ism330bx_mlc_int2_t mlc_int2; 2546 ism330bx_emb_func_status_t emb_func_status; 2547 ism330bx_fsm_status_t fsm_status; 2548 ism330bx_mlc_status_t mlc_status; 2549 ism330bx_page_rw_t page_rw; 2550 ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; 2551 ism330bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; 2552 ism330bx_fsm_enable_t fsm_enable; 2553 ism330bx_fsm_long_counter_l_t fsm_long_counter_l; 2554 ism330bx_fsm_long_counter_h_t fsm_long_counter_h; 2555 ism330bx_fsm_outs1_t fsm_outs1; 2556 ism330bx_fsm_outs2_t fsm_outs2; 2557 ism330bx_fsm_outs3_t fsm_outs3; 2558 ism330bx_fsm_outs4_t fsm_outs4; 2559 ism330bx_fsm_outs5_t fsm_outs5; 2560 ism330bx_fsm_outs6_t fsm_outs6; 2561 ism330bx_fsm_outs7_t fsm_outs7; 2562 ism330bx_fsm_outs8_t fsm_outs8; 2563 ism330bx_fsm_odr_t fsm_odr; 2564 ism330bx_mlc_odr_t mlc_odr; 2565 ism330bx_step_counter_l_t step_counter_l; 2566 ism330bx_step_counter_h_t step_counter_h; 2567 ism330bx_emb_func_src_t emb_func_src; 2568 ism330bx_emb_func_init_a_t emb_func_init_a; 2569 ism330bx_emb_func_init_b_t emb_func_init_b; 2570 ism330bx_mlc1_src_t mlc1_src; 2571 ism330bx_mlc2_src_t mlc2_src; 2572 ism330bx_mlc3_src_t mlc3_src; 2573 ism330bx_mlc4_src_t mlc4_src; 2574 ism330bx_fsm_qvar_sensitivity_l_t fsm_qvar_sensitivity_l; 2575 ism330bx_fsm_qvar_sensitivity_h_t fsm_qvar_sensitivity_h; 2576 ism330bx_fsm_lc_timeout_l_t fsm_lc_timeout_l; 2577 ism330bx_fsm_lc_timeout_h_t fsm_lc_timeout_h; 2578 ism330bx_fsm_programs_t fsm_programs; 2579 ism330bx_fsm_start_add_l_t fsm_start_add_l; 2580 ism330bx_fsm_start_add_h_t fsm_start_add_h; 2581 ism330bx_pedo_cmd_reg_t pedo_cmd_reg; 2582 ism330bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; 2583 ism330bx_pedo_sc_deltat_l_t pedo_sc_deltat_l; 2584 ism330bx_pedo_sc_deltat_h_t pedo_sc_deltat_h; 2585 ism330bx_mlc_qvar_sensitivity_l_t mlc_qvar_sensitivity_l; 2586 ism330bx_mlc_qvar_sensitivity_h_t mlc_qvar_sensitivity_h; 2587 bitwise_t bitwise; 2588 uint8_t byte; 2589 } ism330bx_reg_t; 2590 2591 2592 /** 2593 * @} 2594 * 2595 */ 2596 2597 #ifndef __weak 2598 #define __weak __attribute__((weak)) 2599 #endif /* __weak */ 2600 2601 /* 2602 * These are the basic platform dependent I/O routines to read 2603 * and write device registers connected on a standard bus. 2604 * The driver keeps offering a default implementation based on function 2605 * pointers to read/write routines for backward compatibility. 2606 * The __weak directive allows the final application to overwrite 2607 * them with a custom implementation. 2608 */ 2609 2610 int32_t ism330bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2611 uint8_t *data, 2612 uint16_t len); 2613 int32_t ism330bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2614 uint8_t *data, 2615 uint16_t len); 2616 2617 float_t ism330bx_from_sflp_to_mg(int16_t lsb); 2618 float_t ism330bx_from_fs2_to_mg(int16_t lsb); 2619 float_t ism330bx_from_fs4_to_mg(int16_t lsb); 2620 float_t ism330bx_from_fs8_to_mg(int16_t lsb); 2621 float_t ism330bx_from_fs16_to_mg(int16_t lsb); 2622 2623 float_t ism330bx_from_fs125_to_mdps(int16_t lsb); 2624 float_t ism330bx_from_fs500_to_mdps(int16_t lsb); 2625 float_t ism330bx_from_fs250_to_mdps(int16_t lsb); 2626 float_t ism330bx_from_fs1000_to_mdps(int16_t lsb); 2627 float_t ism330bx_from_fs2000_to_mdps(int16_t lsb); 2628 float_t ism330bx_from_fs4000_to_mdps(int16_t lsb); 2629 2630 float_t ism330bx_from_lsb_to_celsius(int16_t lsb); 2631 2632 uint64_t ism330bx_from_lsb_to_nsec(uint32_t lsb); 2633 2634 float_t ism330bx_from_lsb_to_mv(int16_t lsb); 2635 2636 typedef enum 2637 { 2638 ISM330BX_READY = 0x0, 2639 ISM330BX_GLOBAL_RST = 0x1, 2640 ISM330BX_RESTORE_CAL_PARAM = 0x2, 2641 ISM330BX_RESTORE_CTRL_REGS = 0x4, 2642 } ism330bx_reset_t; 2643 int32_t ism330bx_reset_set(const stmdev_ctx_t *ctx, ism330bx_reset_t val); 2644 int32_t ism330bx_reset_get(const stmdev_ctx_t *ctx, ism330bx_reset_t *val); 2645 2646 typedef enum 2647 { 2648 ISM330BX_MAIN_MEM_BANK = 0x0, 2649 ISM330BX_EMBED_FUNC_MEM_BANK = 0x1, 2650 } ism330bx_mem_bank_t; 2651 int32_t ism330bx_mem_bank_set(const stmdev_ctx_t *ctx, ism330bx_mem_bank_t val); 2652 int32_t ism330bx_mem_bank_get(const stmdev_ctx_t *ctx, 2653 ism330bx_mem_bank_t *val); 2654 2655 int32_t ism330bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 2656 2657 typedef enum 2658 { 2659 ISM330BX_XL_ODR_OFF = 0x0, 2660 ISM330BX_XL_ODR_AT_1Hz875 = 0x1, 2661 ISM330BX_XL_ODR_AT_7Hz5 = 0x2, 2662 ISM330BX_XL_ODR_AT_15Hz = 0x3, 2663 ISM330BX_XL_ODR_AT_30Hz = 0x4, 2664 ISM330BX_XL_ODR_AT_60Hz = 0x5, 2665 ISM330BX_XL_ODR_AT_120Hz = 0x6, 2666 ISM330BX_XL_ODR_AT_240Hz = 0x7, 2667 ISM330BX_XL_ODR_AT_480Hz = 0x8, 2668 ISM330BX_XL_ODR_AT_960Hz = 0x9, 2669 ISM330BX_XL_ODR_AT_1920Hz = 0xA, 2670 ISM330BX_XL_ODR_AT_3840Hz = 0xB, 2671 } ism330bx_xl_data_rate_t; 2672 int32_t ism330bx_xl_data_rate_set(const stmdev_ctx_t *ctx, 2673 ism330bx_xl_data_rate_t val); 2674 int32_t ism330bx_xl_data_rate_get(const stmdev_ctx_t *ctx, 2675 ism330bx_xl_data_rate_t *val); 2676 2677 typedef enum 2678 { 2679 ISM330BX_XL_HIGH_PERFORMANCE_MD = 0x0, 2680 ISM330BX_XL_HIGH_PERFORMANCE_TDM_MD = 0x2, 2681 ISM330BX_XL_LOW_POWER_2_AVG_MD = 0x4, 2682 ISM330BX_XL_LOW_POWER_4_AVG_MD = 0x5, 2683 ISM330BX_XL_LOW_POWER_8_AVG_MD = 0x6, 2684 } ism330bx_xl_mode_t; 2685 int32_t ism330bx_xl_mode_set(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t val); 2686 int32_t ism330bx_xl_mode_get(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t *val); 2687 2688 typedef enum 2689 { 2690 ISM330BX_GY_ODR_OFF = 0x0, 2691 ISM330BX_GY_ODR_AT_7Hz5 = 0x2, 2692 ISM330BX_GY_ODR_AT_15Hz = 0x3, 2693 ISM330BX_GY_ODR_AT_30Hz = 0x4, 2694 ISM330BX_GY_ODR_AT_60Hz = 0x5, 2695 ISM330BX_GY_ODR_AT_120Hz = 0x6, 2696 ISM330BX_GY_ODR_AT_240Hz = 0x7, 2697 ISM330BX_GY_ODR_AT_480Hz = 0x8, 2698 ISM330BX_GY_ODR_AT_960Hz = 0x9, 2699 ISM330BX_GY_ODR_AT_1920Hz = 0xa, 2700 ISM330BX_GY_ODR_AT_3840Hz = 0xb, 2701 } ism330bx_gy_data_rate_t; 2702 int32_t ism330bx_gy_data_rate_set(const stmdev_ctx_t *ctx, 2703 ism330bx_gy_data_rate_t val); 2704 int32_t ism330bx_gy_data_rate_get(const stmdev_ctx_t *ctx, 2705 ism330bx_gy_data_rate_t *val); 2706 2707 typedef enum 2708 { 2709 ISM330BX_GY_HIGH_PERFORMANCE_MD = 0x0, 2710 ISM330BX_GY_SLEEP_MD = 0x4, 2711 ISM330BX_GY_LOW_POWER_MD = 0x5, 2712 } ism330bx_gy_mode_t; 2713 int32_t ism330bx_gy_mode_set(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t val); 2714 int32_t ism330bx_gy_mode_get(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t *val); 2715 2716 int32_t ism330bx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 2717 int32_t ism330bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 2718 2719 int32_t ism330bx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 2720 int32_t ism330bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); 2721 2722 typedef enum 2723 { 2724 ISM330BX_DRDY_LATCHED = 0x0, 2725 ISM330BX_DRDY_PULSED = 0x1, 2726 } ism330bx_data_ready_mode_t; 2727 int32_t ism330bx_data_ready_mode_set(const stmdev_ctx_t *ctx, 2728 ism330bx_data_ready_mode_t val); 2729 int32_t ism330bx_data_ready_mode_get(const stmdev_ctx_t *ctx, 2730 ism330bx_data_ready_mode_t *val); 2731 2732 typedef enum 2733 { 2734 ISM330BX_125dps = 0x0, 2735 ISM330BX_250dps = 0x1, 2736 ISM330BX_500dps = 0x2, 2737 ISM330BX_1000dps = 0x3, 2738 ISM330BX_2000dps = 0x4, 2739 ISM330BX_4000dps = 0xc, 2740 } ism330bx_gy_full_scale_t; 2741 int32_t ism330bx_gy_full_scale_set(const stmdev_ctx_t *ctx, 2742 ism330bx_gy_full_scale_t val); 2743 int32_t ism330bx_gy_full_scale_get(const stmdev_ctx_t *ctx, 2744 ism330bx_gy_full_scale_t *val); 2745 2746 typedef enum 2747 { 2748 ISM330BX_2g = 0x0, 2749 ISM330BX_4g = 0x1, 2750 ISM330BX_8g = 0x2, 2751 } ism330bx_xl_full_scale_t; 2752 int32_t ism330bx_xl_full_scale_set(const stmdev_ctx_t *ctx, 2753 ism330bx_xl_full_scale_t val); 2754 int32_t ism330bx_xl_full_scale_get(const stmdev_ctx_t *ctx, 2755 ism330bx_xl_full_scale_t *val); 2756 2757 int32_t ism330bx_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); 2758 int32_t ism330bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); 2759 2760 typedef enum 2761 { 2762 ISM330BX_XL_ST_DISABLE = 0x0, 2763 ISM330BX_XL_ST_POSITIVE = 0x1, 2764 ISM330BX_XL_ST_NEGATIVE = 0x2, 2765 ISM330BX_XL_ST_OFFSET_POS = 0x5, 2766 ISM330BX_XL_ST_OFFSET_NEG = 0x6, 2767 } ism330bx_xl_self_test_t; 2768 int32_t ism330bx_xl_self_test_set(const stmdev_ctx_t *ctx, 2769 ism330bx_xl_self_test_t val); 2770 int32_t ism330bx_xl_self_test_get(const stmdev_ctx_t *ctx, 2771 ism330bx_xl_self_test_t *val); 2772 2773 typedef enum 2774 { 2775 ISM330BX_GY_ST_DISABLE = 0x0, 2776 ISM330BX_GY_ST_POSITIVE = 0x1, 2777 ISM330BX_GY_ST_NEGATIVE = 0x2, 2778 } ism330bx_gy_self_test_t; 2779 int32_t ism330bx_gy_self_test_set(const stmdev_ctx_t *ctx, 2780 ism330bx_gy_self_test_t val); 2781 int32_t ism330bx_gy_self_test_get(const stmdev_ctx_t *ctx, 2782 ism330bx_gy_self_test_t *val); 2783 2784 typedef struct 2785 { 2786 uint8_t drdy_xl : 1; 2787 uint8_t drdy_gy : 1; 2788 uint8_t drdy_temp : 1; 2789 uint8_t drdy_ah_qvar : 1; 2790 uint8_t gy_settling : 1; 2791 uint8_t den_flag : 1; 2792 uint8_t timestamp : 1; 2793 uint8_t free_fall : 1; 2794 uint8_t wake_up : 1; 2795 uint8_t wake_up_z : 1; 2796 uint8_t wake_up_y : 1; 2797 uint8_t wake_up_x : 1; 2798 uint8_t single_tap : 1; 2799 uint8_t double_tap : 1; 2800 uint8_t tap_z : 1; 2801 uint8_t tap_y : 1; 2802 uint8_t tap_x : 1; 2803 uint8_t tap_sign : 1; 2804 uint8_t six_d : 1; 2805 uint8_t six_d_xl : 1; 2806 uint8_t six_d_xh : 1; 2807 uint8_t six_d_yl : 1; 2808 uint8_t six_d_yh : 1; 2809 uint8_t six_d_zl : 1; 2810 uint8_t six_d_zh : 1; 2811 uint8_t sleep_change : 1; 2812 uint8_t sleep_state : 1; 2813 uint8_t step_detector : 1; 2814 uint8_t step_count_inc : 1; 2815 uint8_t step_count_overflow : 1; 2816 uint8_t step_on_delta_time : 1; 2817 uint8_t emb_func_stand_by : 1; 2818 uint8_t emb_func_time_exceed: 1; 2819 uint8_t tilt : 1; 2820 uint8_t sig_mot : 1; 2821 uint8_t fsm_lc : 1; 2822 uint8_t fsm1 : 1; 2823 uint8_t fsm2 : 1; 2824 uint8_t fsm3 : 1; 2825 uint8_t fsm4 : 1; 2826 uint8_t fsm5 : 1; 2827 uint8_t fsm6 : 1; 2828 uint8_t fsm7 : 1; 2829 uint8_t fsm8 : 1; 2830 uint8_t mlc1 : 1; 2831 uint8_t mlc2 : 1; 2832 uint8_t mlc3 : 1; 2833 uint8_t mlc4 : 1; 2834 uint8_t fifo_bdr : 1; 2835 uint8_t fifo_full : 1; 2836 uint8_t fifo_ovr : 1; 2837 uint8_t fifo_th : 1; 2838 } ism330bx_all_sources_t; 2839 int32_t ism330bx_all_sources_get(const stmdev_ctx_t *ctx, 2840 ism330bx_all_sources_t *val); 2841 2842 typedef struct 2843 { 2844 uint8_t drdy_xl : 1; 2845 uint8_t drdy_gy : 1; 2846 uint8_t drdy_temp : 1; 2847 uint8_t drdy_ah_qvar : 1; 2848 } ism330bx_data_ready_t; 2849 int32_t ism330bx_flag_data_ready_get(const stmdev_ctx_t *ctx, 2850 ism330bx_data_ready_t *val); 2851 2852 int32_t ism330bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2853 2854 int32_t ism330bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2855 2856 int32_t ism330bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2857 2858 int32_t ism330bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2859 2860 int32_t ism330bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, 2861 int16_t *val); 2862 2863 int32_t ism330bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2864 2865 int32_t ism330bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); 2866 2867 typedef struct 2868 { 2869 uint8_t x : 1; 2870 uint8_t y : 1; 2871 uint8_t z : 1; 2872 } ism330bx_tdm_xl_axis_t; 2873 int32_t ism330bx_tdm_xl_axis_set(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t val); 2874 int32_t ism330bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t *val); 2875 2876 int32_t ism330bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 2877 uint8_t *buf, uint8_t len); 2878 int32_t ism330bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 2879 uint8_t *buf, uint8_t len); 2880 2881 int32_t ism330bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 2882 int32_t ism330bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2883 2884 int32_t ism330bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 2885 2886 typedef enum 2887 { 2888 ISM330BX_AUTO = 0x0, 2889 ISM330BX_ALWAYS_ACTIVE = 0x1, 2890 } ism330bx_filt_anti_spike_t; 2891 int32_t ism330bx_filt_anti_spike_set(const stmdev_ctx_t *ctx, 2892 ism330bx_filt_anti_spike_t val); 2893 int32_t ism330bx_filt_anti_spike_get(const stmdev_ctx_t *ctx, 2894 ism330bx_filt_anti_spike_t *val); 2895 2896 typedef struct 2897 { 2898 uint8_t drdy : 1; 2899 uint8_t irq_xl : 1; 2900 uint8_t irq_g : 1; 2901 uint8_t tdm_excep_code : 1; 2902 } ism330bx_filt_settling_mask_t; 2903 int32_t ism330bx_filt_settling_mask_set(const stmdev_ctx_t *ctx, 2904 ism330bx_filt_settling_mask_t val); 2905 int32_t ism330bx_filt_settling_mask_get(const stmdev_ctx_t *ctx, 2906 ism330bx_filt_settling_mask_t *val); 2907 2908 typedef enum 2909 { 2910 ISM330BX_GY_ULTRA_LIGHT = 0x0, 2911 ISM330BX_GY_VERY_LIGHT = 0x1, 2912 ISM330BX_GY_LIGHT = 0x2, 2913 ISM330BX_GY_MEDIUM = 0x3, 2914 ISM330BX_GY_STRONG = 0x4, 2915 ISM330BX_GY_VERY_STRONG = 0x5, 2916 ISM330BX_GY_AGGRESSIVE = 0x6, 2917 ISM330BX_GY_XTREME = 0x7, 2918 } ism330bx_filt_gy_lp1_bandwidth_t; 2919 int32_t ism330bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 2920 ism330bx_filt_gy_lp1_bandwidth_t val); 2921 int32_t ism330bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 2922 ism330bx_filt_gy_lp1_bandwidth_t *val); 2923 2924 int32_t ism330bx_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 2925 int32_t ism330bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2926 2927 typedef struct 2928 { 2929 uint8_t hpf : 1; 2930 uint8_t lpf : 1; 2931 } ism330bx_filt_ah_qvar_conf_t; 2932 int32_t ism330bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx, 2933 ism330bx_filt_ah_qvar_conf_t val); 2934 int32_t ism330bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx, 2935 ism330bx_filt_ah_qvar_conf_t *val); 2936 2937 typedef enum 2938 { 2939 ISM330BX_XL_ULTRA_LIGHT = 0x0, 2940 ISM330BX_XL_VERY_LIGHT = 0x1, 2941 ISM330BX_XL_LIGHT = 0x2, 2942 ISM330BX_XL_MEDIUM = 0x3, 2943 ISM330BX_XL_STRONG = 0x4, 2944 ISM330BX_XL_VERY_STRONG = 0x5, 2945 ISM330BX_XL_AGGRESSIVE = 0x6, 2946 ISM330BX_XL_XTREME = 0x7, 2947 } ism330bx_filt_xl_lp2_bandwidth_t; 2948 int32_t ism330bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, 2949 ism330bx_filt_xl_lp2_bandwidth_t val); 2950 int32_t ism330bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, 2951 ism330bx_filt_xl_lp2_bandwidth_t *val); 2952 2953 int32_t ism330bx_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 2954 int32_t ism330bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 2955 2956 int32_t ism330bx_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); 2957 int32_t ism330bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2958 2959 int32_t ism330bx_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 2960 int32_t ism330bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 2961 2962 typedef enum 2963 { 2964 ISM330BX_HP_MD_NORMAL = 0x0, 2965 ISM330BX_HP_MD_REFERENCE = 0x1, 2966 } ism330bx_filt_xl_hp_mode_t; 2967 int32_t ism330bx_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, 2968 ism330bx_filt_xl_hp_mode_t val); 2969 int32_t ism330bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, 2970 ism330bx_filt_xl_hp_mode_t *val); 2971 2972 typedef enum 2973 { 2974 ISM330BX_WK_FEED_SLOPE = 0x0, 2975 ISM330BX_WK_FEED_HIGH_PASS = 0x1, 2976 ISM330BX_WK_FEED_LP_WITH_OFFSET = 0x2, 2977 } ism330bx_filt_wkup_act_feed_t; 2978 int32_t ism330bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, 2979 ism330bx_filt_wkup_act_feed_t val); 2980 int32_t ism330bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, 2981 ism330bx_filt_wkup_act_feed_t *val); 2982 2983 int32_t ism330bx_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); 2984 int32_t ism330bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); 2985 2986 typedef enum 2987 { 2988 ISM330BX_SIXD_FEED_ODR_DIV_2 = 0x0, 2989 ISM330BX_SIXD_FEED_LOW_PASS = 0x1, 2990 } ism330bx_filt_sixd_feed_t; 2991 int32_t ism330bx_filt_sixd_feed_set(const stmdev_ctx_t *ctx, 2992 ism330bx_filt_sixd_feed_t val); 2993 int32_t ism330bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx, 2994 ism330bx_filt_sixd_feed_t *val); 2995 2996 int32_t ism330bx_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 2997 int32_t ism330bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 2998 2999 typedef enum 3000 { 3001 ISM330BX_I2C_I3C_ENABLE = 0x0, 3002 ISM330BX_I2C_I3C_DISABLE = 0x1, 3003 } ism330bx_ui_i2c_i3c_mode_t; 3004 int32_t ism330bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, 3005 ism330bx_ui_i2c_i3c_mode_t val); 3006 int32_t ism330bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, 3007 ism330bx_ui_i2c_i3c_mode_t *val); 3008 3009 typedef enum 3010 { 3011 ISM330BX_SPI_4_WIRE = 0x0, 3012 ISM330BX_SPI_3_WIRE = 0x1, 3013 } ism330bx_spi_mode_t; 3014 int32_t ism330bx_spi_mode_set(const stmdev_ctx_t *ctx, ism330bx_spi_mode_t val); 3015 int32_t ism330bx_spi_mode_get(const stmdev_ctx_t *ctx, 3016 ism330bx_spi_mode_t *val); 3017 3018 int32_t ism330bx_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 3019 int32_t ism330bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 3020 3021 typedef enum 3022 { 3023 ISM330BX_IBI_2us = 0x0, 3024 ISM330BX_IBI_50us = 0x1, 3025 ISM330BX_IBI_1ms = 0x2, 3026 ISM330BX_IBI_25ms = 0x3, 3027 } ism330bx_i3c_ibi_time_t; 3028 int32_t ism330bx_i3c_ibi_time_set(const stmdev_ctx_t *ctx, 3029 ism330bx_i3c_ibi_time_t val); 3030 int32_t ism330bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx, 3031 ism330bx_i3c_ibi_time_t *val); 3032 3033 typedef enum 3034 { 3035 ISM330BX_PUSH_PULL = 0x0, 3036 ISM330BX_OPEN_DRAIN = 0x1, 3037 } ism330bx_int_pin_mode_t; 3038 int32_t ism330bx_int_pin_mode_set(const stmdev_ctx_t *ctx, 3039 ism330bx_int_pin_mode_t val); 3040 int32_t ism330bx_int_pin_mode_get(const stmdev_ctx_t *ctx, 3041 ism330bx_int_pin_mode_t *val); 3042 3043 typedef enum 3044 { 3045 ISM330BX_ACTIVE_HIGH = 0x0, 3046 ISM330BX_ACTIVE_LOW = 0x1, 3047 } ism330bx_pin_polarity_t; 3048 int32_t ism330bx_pin_polarity_set(const stmdev_ctx_t *ctx, 3049 ism330bx_pin_polarity_t val); 3050 int32_t ism330bx_pin_polarity_get(const stmdev_ctx_t *ctx, 3051 ism330bx_pin_polarity_t *val); 3052 3053 typedef struct 3054 { 3055 uint8_t boot : 1; 3056 uint8_t drdy_xl : 1; 3057 uint8_t drdy_gy : 1; 3058 uint8_t drdy_temp : 1; 3059 uint8_t drdy_ah_qvar : 1; 3060 uint8_t fifo_th : 1; 3061 uint8_t fifo_ovr : 1; 3062 uint8_t fifo_full : 1; 3063 uint8_t fifo_bdr : 1; 3064 uint8_t den_flag : 1; 3065 uint8_t timestamp : 1; // impact on int2 signals 3066 uint8_t six_d : 1; 3067 uint8_t double_tap : 1; 3068 uint8_t free_fall : 1; 3069 uint8_t wake_up : 1; 3070 uint8_t single_tap : 1; 3071 uint8_t sleep_change : 1; 3072 uint8_t sleep_status : 1; 3073 uint8_t step_detector : 1; 3074 uint8_t step_count_overflow : 1; 3075 uint8_t tilt : 1; 3076 uint8_t sig_mot : 1; 3077 uint8_t emb_func_stand_by : 1; // impact on int2 signals 3078 uint8_t fsm_lc : 1; 3079 uint8_t fsm1 : 1; 3080 uint8_t fsm2 : 1; 3081 uint8_t fsm3 : 1; 3082 uint8_t fsm4 : 1; 3083 uint8_t fsm5 : 1; 3084 uint8_t fsm6 : 1; 3085 uint8_t fsm7 : 1; 3086 uint8_t fsm8 : 1; 3087 uint8_t mlc1 : 1; 3088 uint8_t mlc2 : 1; 3089 uint8_t mlc3 : 1; 3090 uint8_t mlc4 : 1; 3091 } ism330bx_pin_int_route_t; 3092 int32_t ism330bx_pin_int1_route_set(const stmdev_ctx_t *ctx, 3093 ism330bx_pin_int_route_t val); 3094 int32_t ism330bx_pin_int1_route_get(const stmdev_ctx_t *ctx, 3095 ism330bx_pin_int_route_t *val); 3096 int32_t ism330bx_pin_int2_route_set(const stmdev_ctx_t *ctx, 3097 ism330bx_pin_int_route_t val); 3098 int32_t ism330bx_pin_int2_route_get(const stmdev_ctx_t *ctx, 3099 ism330bx_pin_int_route_t *val); 3100 3101 int32_t ism330bx_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val); 3102 int32_t ism330bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val); 3103 3104 typedef enum 3105 { 3106 ISM330BX_ALL_INT_PULSED = 0x0, 3107 ISM330BX_BASE_LATCHED_EMB_PULSED = 0x1, 3108 ISM330BX_BASE_PULSED_EMB_LATCHED = 0x2, 3109 ISM330BX_ALL_INT_LATCHED = 0x3, 3110 } ism330bx_int_notification_t; 3111 int32_t ism330bx_int_notification_set(const stmdev_ctx_t *ctx, 3112 ism330bx_int_notification_t val); 3113 int32_t ism330bx_int_notification_get(const stmdev_ctx_t *ctx, 3114 ism330bx_int_notification_t *val); 3115 3116 typedef enum 3117 { 3118 ISM330BX_XL_AND_GY_NOT_AFFECTED = 0x0, 3119 ISM330BX_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, 3120 ISM330BX_XL_LOW_POWER_GY_SLEEP = 0x2, 3121 ISM330BX_XL_LOW_POWER_GY_POWER_DOWN = 0x3, 3122 } ism330bx_act_mode_t; 3123 int32_t ism330bx_act_mode_set(const stmdev_ctx_t *ctx, ism330bx_act_mode_t val); 3124 int32_t ism330bx_act_mode_get(const stmdev_ctx_t *ctx, 3125 ism330bx_act_mode_t *val); 3126 3127 typedef enum 3128 { 3129 ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, 3130 ISM330BX_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, 3131 ISM330BX_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, 3132 ISM330BX_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, 3133 } ism330bx_act_from_sleep_to_act_dur_t; 3134 int32_t ism330bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, 3135 ism330bx_act_from_sleep_to_act_dur_t val); 3136 int32_t ism330bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, 3137 ism330bx_act_from_sleep_to_act_dur_t *val); 3138 3139 typedef enum 3140 { 3141 ISM330BX_1Hz875 = 0x0, 3142 ISM330BX_15Hz = 0x1, 3143 ISM330BX_30Hz = 0x2, 3144 ISM330BX_60Hz = 0x3, 3145 } ism330bx_act_sleep_xl_odr_t; 3146 int32_t ism330bx_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, 3147 ism330bx_act_sleep_xl_odr_t val); 3148 int32_t ism330bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, 3149 ism330bx_act_sleep_xl_odr_t *val); 3150 3151 typedef struct 3152 { 3153 uint32_t wk_ths_mg; 3154 uint32_t inact_ths_mg; 3155 } ism330bx_act_thresholds_t; 3156 int32_t ism330bx_act_thresholds_set(const stmdev_ctx_t *ctx, 3157 ism330bx_act_thresholds_t val); 3158 int32_t ism330bx_act_thresholds_get(const stmdev_ctx_t *ctx, 3159 ism330bx_act_thresholds_t *val); 3160 3161 typedef struct 3162 { 3163 uint8_t shock : 2; 3164 uint8_t quiet : 4; 3165 } ism330bx_act_wkup_time_windows_t; 3166 int32_t ism330bx_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, 3167 ism330bx_act_wkup_time_windows_t val); 3168 int32_t ism330bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, 3169 ism330bx_act_wkup_time_windows_t *val); 3170 3171 typedef struct 3172 { 3173 uint8_t tap_x_en : 1; 3174 uint8_t tap_y_en : 1; 3175 uint8_t tap_z_en : 1; 3176 } ism330bx_tap_detection_t; 3177 int32_t ism330bx_tap_detection_set(const stmdev_ctx_t *ctx, 3178 ism330bx_tap_detection_t val); 3179 int32_t ism330bx_tap_detection_get(const stmdev_ctx_t *ctx, 3180 ism330bx_tap_detection_t *val); 3181 3182 typedef struct 3183 { 3184 uint8_t x : 1; 3185 uint8_t y : 1; 3186 uint8_t z : 1; 3187 } ism330bx_tap_thresholds_t; 3188 int32_t ism330bx_tap_thresholds_set(const stmdev_ctx_t *ctx, 3189 ism330bx_tap_thresholds_t val); 3190 int32_t ism330bx_tap_thresholds_get(const stmdev_ctx_t *ctx, 3191 ism330bx_tap_thresholds_t *val); 3192 3193 3194 typedef enum 3195 { 3196 ISM330BX_XYZ = 0x3, 3197 ISM330BX_YXZ = 0x5, 3198 ISM330BX_XZY = 0x6, 3199 ISM330BX_ZYX = 0x0, 3200 ISM330BX_YZX = 0x1, 3201 ISM330BX_ZXY = 0x2, 3202 } ism330bx_tap_axis_priority_t; 3203 int32_t ism330bx_tap_axis_priority_set(const stmdev_ctx_t *ctx, 3204 ism330bx_tap_axis_priority_t val); 3205 int32_t ism330bx_tap_axis_priority_get(const stmdev_ctx_t *ctx, 3206 ism330bx_tap_axis_priority_t *val); 3207 3208 typedef struct 3209 { 3210 uint8_t shock : 1; 3211 uint8_t quiet : 1; 3212 uint8_t tap_gap : 1; 3213 } ism330bx_tap_time_windows_t; 3214 int32_t ism330bx_tap_time_windows_set(const stmdev_ctx_t *ctx, 3215 ism330bx_tap_time_windows_t val); 3216 int32_t ism330bx_tap_time_windows_get(const stmdev_ctx_t *ctx, 3217 ism330bx_tap_time_windows_t *val); 3218 3219 typedef enum 3220 { 3221 ISM330BX_ONLY_SINGLE = 0x0, 3222 ISM330BX_BOTH_SINGLE_DOUBLE = 0x1, 3223 } ism330bx_tap_mode_t; 3224 int32_t ism330bx_tap_mode_set(const stmdev_ctx_t *ctx, ism330bx_tap_mode_t val); 3225 int32_t ism330bx_tap_mode_get(const stmdev_ctx_t *ctx, 3226 ism330bx_tap_mode_t *val); 3227 3228 typedef enum 3229 { 3230 ISM330BX_DEG_80 = 0x0, 3231 ISM330BX_DEG_70 = 0x1, 3232 ISM330BX_DEG_60 = 0x2, 3233 ISM330BX_DEG_50 = 0x3, 3234 } ism330bx_6d_threshold_t; 3235 int32_t ism330bx_6d_threshold_set(const stmdev_ctx_t *ctx, 3236 ism330bx_6d_threshold_t val); 3237 int32_t ism330bx_6d_threshold_get(const stmdev_ctx_t *ctx, 3238 ism330bx_6d_threshold_t *val); 3239 3240 int32_t ism330bx_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); 3241 int32_t ism330bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); 3242 3243 typedef enum 3244 { 3245 ISM330BX_156_mg = 0x0, 3246 ISM330BX_219_mg = 0x1, 3247 ISM330BX_250_mg = 0x2, 3248 ISM330BX_312_mg = 0x3, 3249 ISM330BX_344_mg = 0x4, 3250 ISM330BX_406_mg = 0x5, 3251 ISM330BX_469_mg = 0x6, 3252 ISM330BX_500_mg = 0x7, 3253 } ism330bx_ff_thresholds_t; 3254 int32_t ism330bx_ff_thresholds_set(const stmdev_ctx_t *ctx, 3255 ism330bx_ff_thresholds_t val); 3256 int32_t ism330bx_ff_thresholds_get(const stmdev_ctx_t *ctx, 3257 ism330bx_ff_thresholds_t *val); 3258 3259 int32_t ism330bx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 3260 int32_t ism330bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 3261 3262 int32_t ism330bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 3263 int32_t ism330bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 3264 3265 typedef enum 3266 { 3267 ISM330BX_CMP_DISABLE = 0x0, 3268 ISM330BX_CMP_8_TO_1 = 0x1, 3269 ISM330BX_CMP_16_TO_1 = 0x2, 3270 ISM330BX_CMP_32_TO_1 = 0x3, 3271 } ism330bx_fifo_compress_algo_t; 3272 int32_t ism330bx_fifo_compress_algo_set(const stmdev_ctx_t *ctx, 3273 ism330bx_fifo_compress_algo_t val); 3274 int32_t ism330bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx, 3275 ism330bx_fifo_compress_algo_t *val); 3276 3277 int32_t ism330bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 3278 uint8_t val); 3279 int32_t ism330bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 3280 uint8_t *val); 3281 3282 int32_t ism330bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, 3283 uint8_t val); 3284 int32_t ism330bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, 3285 uint8_t *val); 3286 3287 int32_t ism330bx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 3288 int32_t ism330bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 3289 3290 typedef enum 3291 { 3292 ISM330BX_XL_NOT_BATCHED = 0x0, 3293 ISM330BX_XL_BATCHED_AT_1Hz875 = 0x1, 3294 ISM330BX_XL_BATCHED_AT_7Hz5 = 0x2, 3295 ISM330BX_XL_BATCHED_AT_15Hz = 0x3, 3296 ISM330BX_XL_BATCHED_AT_30Hz = 0x4, 3297 ISM330BX_XL_BATCHED_AT_60Hz = 0x5, 3298 ISM330BX_XL_BATCHED_AT_120Hz = 0x6, 3299 ISM330BX_XL_BATCHED_AT_240Hz = 0x7, 3300 ISM330BX_XL_BATCHED_AT_480Hz = 0x8, 3301 ISM330BX_XL_BATCHED_AT_960Hz = 0x9, 3302 ISM330BX_XL_BATCHED_AT_1920Hz = 0xA, 3303 ISM330BX_XL_BATCHED_AT_3840Hz = 0xB, 3304 } ism330bx_fifo_xl_batch_t; 3305 int32_t ism330bx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 3306 ism330bx_fifo_xl_batch_t val); 3307 int32_t ism330bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 3308 ism330bx_fifo_xl_batch_t *val); 3309 3310 typedef enum 3311 { 3312 ISM330BX_GY_NOT_BATCHED = 0x0, 3313 ISM330BX_GY_BATCHED_AT_1Hz875 = 0x1, 3314 ISM330BX_GY_BATCHED_AT_7Hz5 = 0x2, 3315 ISM330BX_GY_BATCHED_AT_15Hz = 0x3, 3316 ISM330BX_GY_BATCHED_AT_30Hz = 0x4, 3317 ISM330BX_GY_BATCHED_AT_60Hz = 0x5, 3318 ISM330BX_GY_BATCHED_AT_120Hz = 0x6, 3319 ISM330BX_GY_BATCHED_AT_240Hz = 0x7, 3320 ISM330BX_GY_BATCHED_AT_480Hz = 0x8, 3321 ISM330BX_GY_BATCHED_AT_960Hz = 0x9, 3322 ISM330BX_GY_BATCHED_AT_1920Hz = 0xa, 3323 ISM330BX_GY_BATCHED_AT_3840Hz = 0xb, 3324 } ism330bx_fifo_gy_batch_t; 3325 int32_t ism330bx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 3326 ism330bx_fifo_gy_batch_t val); 3327 int32_t ism330bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 3328 ism330bx_fifo_gy_batch_t *val); 3329 3330 typedef enum 3331 { 3332 ISM330BX_BYPASS_MODE = 0x0, 3333 ISM330BX_FIFO_MODE = 0x1, 3334 ISM330BX_STREAM_WTM_TO_FULL_MODE = 0x2, 3335 ISM330BX_STREAM_TO_FIFO_MODE = 0x3, 3336 ISM330BX_BYPASS_TO_STREAM_MODE = 0x4, 3337 ISM330BX_STREAM_MODE = 0x6, 3338 ISM330BX_BYPASS_TO_FIFO_MODE = 0x7, 3339 } ism330bx_fifo_mode_t; 3340 int32_t ism330bx_fifo_mode_set(const stmdev_ctx_t *ctx, 3341 ism330bx_fifo_mode_t val); 3342 int32_t ism330bx_fifo_mode_get(const stmdev_ctx_t *ctx, 3343 ism330bx_fifo_mode_t *val); 3344 3345 typedef enum 3346 { 3347 ISM330BX_TEMP_NOT_BATCHED = 0x0, 3348 ISM330BX_TEMP_BATCHED_AT_1Hz875 = 0x1, 3349 ISM330BX_TEMP_BATCHED_AT_15Hz = 0x2, 3350 ISM330BX_TEMP_BATCHED_AT_60Hz = 0x3, 3351 } ism330bx_fifo_temp_batch_t; 3352 int32_t ism330bx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 3353 ism330bx_fifo_temp_batch_t val); 3354 int32_t ism330bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 3355 ism330bx_fifo_temp_batch_t *val); 3356 3357 typedef enum 3358 { 3359 ISM330BX_TMSTMP_NOT_BATCHED = 0x0, 3360 ISM330BX_TMSTMP_DEC_1 = 0x1, 3361 ISM330BX_TMSTMP_DEC_8 = 0x2, 3362 ISM330BX_TMSTMP_DEC_32 = 0x3, 3363 } ism330bx_fifo_timestamp_batch_t; 3364 int32_t ism330bx_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, 3365 ism330bx_fifo_timestamp_batch_t val); 3366 int32_t ism330bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, 3367 ism330bx_fifo_timestamp_batch_t *val); 3368 3369 int32_t ism330bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 3370 uint16_t val); 3371 int32_t ism330bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 3372 uint16_t *val); 3373 3374 int32_t ism330bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t *ctx, uint8_t val); 3375 int32_t ism330bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val); 3376 3377 typedef enum 3378 { 3379 ISM330BX_XL_BATCH_EVENT = 0x0, 3380 ISM330BX_GY_BATCH_EVENT = 0x1, 3381 } ism330bx_fifo_batch_cnt_event_t; 3382 int32_t ism330bx_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, 3383 ism330bx_fifo_batch_cnt_event_t val); 3384 int32_t ism330bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, 3385 ism330bx_fifo_batch_cnt_event_t *val); 3386 3387 typedef struct 3388 { 3389 uint8_t game_rotation : 1; 3390 uint8_t gravity : 1; 3391 uint8_t gbias : 1; 3392 } ism330bx_fifo_sflp_raw_t; 3393 int32_t ism330bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, 3394 ism330bx_fifo_sflp_raw_t val); 3395 int32_t ism330bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, 3396 ism330bx_fifo_sflp_raw_t *val); 3397 3398 typedef struct 3399 { 3400 uint16_t fifo_level : 9; 3401 uint8_t fifo_bdr : 1; 3402 uint8_t fifo_full : 1; 3403 uint8_t fifo_ovr : 1; 3404 uint8_t fifo_th : 1; 3405 } ism330bx_fifo_status_t; 3406 3407 int32_t ism330bx_fifo_status_get(const stmdev_ctx_t *ctx, 3408 ism330bx_fifo_status_t *val); 3409 3410 typedef struct 3411 { 3412 enum 3413 { 3414 ISM330BX_FIFO_EMPTY = 0x0, 3415 ISM330BX_GY_NC_TAG = 0x1, 3416 ISM330BX_XL_NC_TAG = 0x2, 3417 ISM330BX_TEMPERATURE_TAG = 0x3, 3418 ISM330BX_TIMESTAMP_TAG = 0x4, 3419 ISM330BX_CFG_CHANGE_TAG = 0x5, 3420 ISM330BX_XL_NC_T_2_TAG = 0x6, 3421 ISM330BX_XL_NC_T_1_TAG = 0x7, 3422 ISM330BX_XL_2XC_TAG = 0x8, 3423 ISM330BX_XL_3XC_TAG = 0x9, 3424 ISM330BX_GY_NC_T_2_TAG = 0xA, 3425 ISM330BX_GY_NC_T_1_TAG = 0xB, 3426 ISM330BX_GY_2XC_TAG = 0xC, 3427 ISM330BX_GY_3XC_TAG = 0xD, 3428 ISM330BX_STEP_COUNTER_TAG = 0x12, 3429 ISM330BX_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, 3430 ISM330BX_SFLP_GYROSCOPE_BIAS_TAG = 0x16, 3431 ISM330BX_SFLP_GRAVITY_VECTOR_TAG = 0x17, 3432 ISM330BX_MLC_RESULT_TAG = 0x1A, 3433 ISM330BX_MLC_FILTER = 0x1B, 3434 ISM330BX_MLC_FEATURE = 0x1C, 3435 ISM330BX_XL_DUAL_CORE = 0x1D, 3436 ISM330BX_AH_QVAR = 0x1F, 3437 } tag; 3438 uint8_t cnt; 3439 uint8_t data[6]; 3440 } ism330bx_fifo_out_raw_t; 3441 int32_t ism330bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, 3442 ism330bx_fifo_out_raw_t *val); 3443 3444 int32_t ism330bx_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 3445 int32_t ism330bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 3446 3447 int32_t ism330bx_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 3448 int32_t ism330bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 3449 3450 int32_t ism330bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 3451 int32_t ism330bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 3452 3453 typedef struct 3454 { 3455 uint8_t step_counter_enable : 1; 3456 uint8_t false_step_rej : 1; 3457 } ism330bx_stpcnt_mode_t; 3458 int32_t ism330bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, 3459 ism330bx_stpcnt_mode_t val); 3460 int32_t ism330bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, 3461 ism330bx_stpcnt_mode_t *val); 3462 3463 int32_t ism330bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 3464 3465 int32_t ism330bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); 3466 int32_t ism330bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); 3467 3468 int32_t ism330bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); 3469 int32_t ism330bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); 3470 3471 int32_t ism330bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); 3472 int32_t ism330bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); 3473 3474 int32_t ism330bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3475 int32_t ism330bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3476 3477 int32_t ism330bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3478 int32_t ism330bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3479 3480 int32_t ism330bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val); 3481 int32_t ism330bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val); 3482 3483 typedef struct 3484 { 3485 float_t gbias_x; /* dps */ 3486 float_t gbias_y; /* dps */ 3487 float_t gbias_z; /* dps */ 3488 } ism330bx_sflp_gbias_t; 3489 int32_t ism330bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, 3490 ism330bx_sflp_gbias_t *val); 3491 3492 int32_t ism330bx_sflp_configure(const stmdev_ctx_t *ctx); 3493 3494 typedef enum 3495 { 3496 ISM330BX_SFLP_15Hz = 0x0, 3497 ISM330BX_SFLP_30Hz = 0x1, 3498 ISM330BX_SFLP_60Hz = 0x2, 3499 ISM330BX_SFLP_120Hz = 0x3, 3500 ISM330BX_SFLP_240Hz = 0x4, 3501 ISM330BX_SFLP_480Hz = 0x5, 3502 } ism330bx_sflp_data_rate_t; 3503 int32_t ism330bx_sflp_data_rate_set(const stmdev_ctx_t *ctx, 3504 ism330bx_sflp_data_rate_t val); 3505 int32_t ism330bx_sflp_data_rate_get(const stmdev_ctx_t *ctx, 3506 ism330bx_sflp_data_rate_t *val); 3507 3508 typedef enum 3509 { 3510 ISM330BX_PROTECT_CTRL_REGS = 0x0, 3511 ISM330BX_WRITE_CTRL_REG = 0x1, 3512 } ism330bx_fsm_permission_t; 3513 int32_t ism330bx_fsm_permission_set(const stmdev_ctx_t *ctx, 3514 ism330bx_fsm_permission_t val); 3515 int32_t ism330bx_fsm_permission_get(const stmdev_ctx_t *ctx, 3516 ism330bx_fsm_permission_t *val); 3517 3518 typedef enum 3519 { 3520 ISM330BX_STD_IF_CONTROL = 0x0, 3521 ISM330BX_FSM_CONTROL = 0x1, 3522 } ism330bx_fsm_permission_status_t; 3523 int32_t ism330bx_fsm_permission_status(const stmdev_ctx_t *ctx, 3524 ism330bx_fsm_permission_status_t *val); 3525 3526 typedef struct 3527 { 3528 uint8_t fsm1_en : 1; 3529 uint8_t fsm2_en : 1; 3530 uint8_t fsm3_en : 1; 3531 uint8_t fsm4_en : 1; 3532 uint8_t fsm5_en : 1; 3533 uint8_t fsm6_en : 1; 3534 uint8_t fsm7_en : 1; 3535 uint8_t fsm8_en : 1; 3536 } ism330bx_fsm_mode_t; 3537 int32_t ism330bx_fsm_mode_set(const stmdev_ctx_t *ctx, ism330bx_fsm_mode_t val); 3538 int32_t ism330bx_fsm_mode_get(const stmdev_ctx_t *ctx, 3539 ism330bx_fsm_mode_t *val); 3540 3541 int32_t ism330bx_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 3542 int32_t ism330bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 3543 3544 typedef struct 3545 { 3546 uint8_t fsm_outs1; 3547 uint8_t fsm_outs2; 3548 uint8_t fsm_outs3; 3549 uint8_t fsm_outs4; 3550 uint8_t fsm_outs5; 3551 uint8_t fsm_outs6; 3552 uint8_t fsm_outs7; 3553 uint8_t fsm_outs8; 3554 } ism330bx_fsm_out_t; 3555 int32_t ism330bx_fsm_out_get(const stmdev_ctx_t *ctx, ism330bx_fsm_out_t *val); 3556 3557 typedef enum 3558 { 3559 ISM330BX_FSM_15Hz = 0x0, 3560 ISM330BX_FSM_30Hz = 0x1, 3561 ISM330BX_FSM_60Hz = 0x2, 3562 ISM330BX_FSM_120Hz = 0x3, 3563 ISM330BX_FSM_240Hz = 0x4, 3564 ISM330BX_FSM_480Hz = 0x5, 3565 ISM330BX_FSM_960Hz = 0x6, 3566 } ism330bx_fsm_data_rate_t; 3567 int32_t ism330bx_fsm_data_rate_set(const stmdev_ctx_t *ctx, 3568 ism330bx_fsm_data_rate_t val); 3569 int32_t ism330bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, 3570 ism330bx_fsm_data_rate_t *val); 3571 3572 int32_t ism330bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); 3573 int32_t ism330bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); 3574 3575 int32_t ism330bx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); 3576 int32_t ism330bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); 3577 3578 int32_t ism330bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); 3579 int32_t ism330bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); 3580 3581 typedef enum 3582 { 3583 ISM330BX_MLC_OFF = 0x0, 3584 ISM330BX_MLC_ON = 0x1, 3585 ISM330BX_MLC_ON_BEFORE_FSM = 0x2, 3586 } ism330bx_mlc_mode_t; 3587 int32_t ism330bx_mlc_set(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t val); 3588 int32_t ism330bx_mlc_get(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t *val); 3589 3590 typedef enum 3591 { 3592 ISM330BX_MLC_15Hz = 0x0, 3593 ISM330BX_MLC_30Hz = 0x1, 3594 ISM330BX_MLC_60Hz = 0x2, 3595 ISM330BX_MLC_120Hz = 0x3, 3596 ISM330BX_MLC_240Hz = 0x4, 3597 ISM330BX_MLC_480Hz = 0x5, 3598 ISM330BX_MLC_960Hz = 0x6, 3599 } ism330bx_mlc_data_rate_t; 3600 int32_t ism330bx_mlc_data_rate_set(const stmdev_ctx_t *ctx, 3601 ism330bx_mlc_data_rate_t val); 3602 int32_t ism330bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, 3603 ism330bx_mlc_data_rate_t *val); 3604 3605 typedef struct 3606 { 3607 uint8_t mlc1_src; 3608 uint8_t mlc2_src; 3609 uint8_t mlc3_src; 3610 uint8_t mlc4_src; 3611 } ism330bx_mlc_out_t; 3612 int32_t ism330bx_mlc_out_get(const stmdev_ctx_t *ctx, ism330bx_mlc_out_t *val); 3613 3614 int32_t ism330bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); 3615 int32_t ism330bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); 3616 3617 int32_t ism330bx_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); 3618 int32_t ism330bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); 3619 3620 typedef struct 3621 { 3622 float_t z_mg; 3623 float_t y_mg; 3624 float_t x_mg; 3625 } ism330bx_xl_offset_mg_t; 3626 int32_t ism330bx_xl_offset_mg_set(const stmdev_ctx_t *ctx, 3627 ism330bx_xl_offset_mg_t val); 3628 int32_t ism330bx_xl_offset_mg_get(const stmdev_ctx_t *ctx, 3629 ism330bx_xl_offset_mg_t *val); 3630 3631 typedef struct 3632 { 3633 uint8_t ah_qvar1_en : 1; 3634 uint8_t ah_qvar2_en : 1; 3635 uint8_t swaps : 1; 3636 } ism330bx_ah_qvar_mode_t; 3637 int32_t ism330bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx, 3638 ism330bx_ah_qvar_mode_t val); 3639 int32_t ism330bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx, 3640 ism330bx_ah_qvar_mode_t *val); 3641 3642 typedef enum 3643 { 3644 ISM330BX_2400MOhm = 0x0, 3645 ISM330BX_730MOhm = 0x1, 3646 ISM330BX_300MOhm = 0x2, 3647 ISM330BX_255MOhm = 0x3, 3648 } ism330bx_ah_qvar_zin_t; 3649 int32_t ism330bx_ah_qvar_zin_set(const stmdev_ctx_t *ctx, 3650 ism330bx_ah_qvar_zin_t val); 3651 int32_t ism330bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx, 3652 ism330bx_ah_qvar_zin_t *val); 3653 3654 int32_t ism330bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); 3655 int32_t ism330bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); 3656 3657 typedef enum 3658 { 3659 ISM330BX_SW_RST_DYN_ADDRESS_RST = 0x0, 3660 ISM330BX_I3C_GLOBAL_RST = 0x1, 3661 } ism330bx_i3c_reset_mode_t; 3662 int32_t ism330bx_i3c_reset_mode_set(const stmdev_ctx_t *ctx, 3663 ism330bx_i3c_reset_mode_t val); 3664 int32_t ism330bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx, 3665 ism330bx_i3c_reset_mode_t *val); 3666 3667 int32_t ism330bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 3668 int32_t ism330bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 3669 3670 int32_t ism330bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 3671 int32_t ism330bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 3672 3673 typedef enum 3674 { 3675 ISM330BX_WCLK_16kHZ_BCLK_2048kHz = 0x1, 3676 ISM330BX_WCLK_8kHZ_BCLK_2048kHz = 0x4, 3677 } ism330bx_tdm_wclk_bclk_t; 3678 int32_t ism330bx_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx, 3679 ism330bx_tdm_wclk_bclk_t val); 3680 int32_t ism330bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, 3681 ism330bx_tdm_wclk_bclk_t *val); 3682 3683 typedef enum 3684 { 3685 ISM330BX_SLOT_012 = 0x0, 3686 ISM330BX_SLOT_456 = 0x1, 3687 } ism330bx_tdm_slot_t; 3688 int32_t ism330bx_tdm_slot_set(const stmdev_ctx_t *ctx, ism330bx_tdm_slot_t val); 3689 int32_t ism330bx_tdm_slot_get(const stmdev_ctx_t *ctx, 3690 ism330bx_tdm_slot_t *val); 3691 3692 typedef enum 3693 { 3694 ISM330BX_BCLK_RISING = 0x0, 3695 ISM330BX_BCLK_FALLING = 0x1, 3696 } ism330bx_tdm_bclk_edge_t; 3697 int32_t ism330bx_tdm_bclk_edge_set(const stmdev_ctx_t *ctx, 3698 ism330bx_tdm_bclk_edge_t val); 3699 int32_t ism330bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, 3700 ism330bx_tdm_bclk_edge_t *val); 3701 3702 int32_t ism330bx_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val); 3703 int32_t ism330bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); 3704 3705 typedef enum 3706 { 3707 ISM330BX_TDM_ORDER_ZYX = 0x0, 3708 ISM330BX_TDM_ORDER_XZY = 0x1, 3709 ISM330BX_TDM_ORDER_XYZ = 0x2, 3710 } ism330bx_tdm_axis_order_t; 3711 int32_t ism330bx_tdm_axis_order_set(const stmdev_ctx_t *ctx, 3712 ism330bx_tdm_axis_order_t val); 3713 int32_t ism330bx_tdm_axis_order_get(const stmdev_ctx_t *ctx, 3714 ism330bx_tdm_axis_order_t *val); 3715 3716 typedef enum 3717 { 3718 ISM330BX_TDM_2g = 0x0, 3719 ISM330BX_TDM_4g = 0x1, 3720 ISM330BX_TDM_8g = 0x2, 3721 } ism330bx_tdm_xl_full_scale_t; 3722 int32_t ism330bx_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx, 3723 ism330bx_tdm_xl_full_scale_t val); 3724 int32_t ism330bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, 3725 ism330bx_tdm_xl_full_scale_t *val); 3726 3727 /** 3728 * @} 3729 * 3730 */ 3731 3732 #ifdef __cplusplus 3733 } 3734 #endif 3735 3736 #endif /*ISM330BX_DRIVER_H */ 3737 3738 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3739
