1 /*
2 * Copyright (c) 2023 Intel Corporation
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef _ISH_PM_H_
8 #define _ISH_PM_H_
9
10 #include <sedi_driver_common.h>
11 #include "pm_regs.h"
12
13 #define FABRIC_IDLE_COUNT 50
14 #define TRUNK_CLKGATE_COUNT 0xf
15
16 /* power states for ISH */
17 enum ish_pm_state {
18 /* D0 state: active mode */
19 ISH_PM_STATE_D0 = 0,
20 /* sleep state: cpu halt */
21 ISH_PM_STATE_D0I0,
22 /* deep sleep state 1: Trunk Clock Gating(TCG), cpu halt*/
23 ISH_PM_STATE_D0I1,
24 /* deep sleep state 2: TCG, SRAM retention, cpu halt */
25 ISH_PM_STATE_D0I2,
26 /* deep sleep state 3: TCG, SRAM power off, cpu halt*/
27 ISH_PM_STATE_D0I3,
28 /**
29 * D3 state: power off state, on ISH5.0, can't do real power off,
30 * similar to D0I3, but will reset ISH
31 */
32 ISH_PM_STATE_D3,
33 /**
34 * reset ISH, main FW received 'reboot' command
35 */
36 ISH_PM_STATE_RESET,
37 /**
38 * reset ISH, main FW received reset_prep interrupt during
39 * S0->Sx transition.
40 */
41 ISH_PM_STATE_RESET_PREP,
42 ISH_PM_STATE_NUM
43 };
44
45 /* halt ISH minute-ia cpu core */
ish_mia_halt(void)46 static inline void ish_mia_halt(void)
47 {
48 /* make sure interrupts are enabled before halting */
49 __asm__ volatile("sti;\n"
50 "hlt;");
51 }
52
53 /* reset ISH mintue-ia cpu core */
ish_mia_reset(void)54 static inline void ish_mia_reset(void)
55 {
56 /**
57 * ISH HW looks at the rising edge of this bit to
58 * trigger a MIA reset.
59 */
60 write32(ISH_RST_REG, 0);
61 write32(ISH_RST_REG, 1);
62
63 __builtin_unreachable();
64 }
65
66 /* Initialize power management module. */
67 void ish_pm_init(void);
68
69 /**
70 * reset ISH (reset minute-ia cpu core, and power off main SRAM)
71 */
72 void ish_pm_reset(enum ish_pm_state pm_state);
73
74 #endif
75
