Searched defs:IRQ_MASK_SET (Results 1 – 12 of 12) sorted by relevance
| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 14504 …__IO uint32_t IRQ_MASK_SET; /**< EPDC IRQ Mask Register, offset: 0x404 … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/ |
| D | MIMX8UD7_dsp1.h | 48453 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| D | MIMX8UD7_dsp0.h | 49157 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| D | MIMX8UD7_cm33.h | 50836 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/ |
| D | MIMX8UD3_cm33.h | 50836 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| D | MIMX8UD3_dsp0.h | 49157 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/ |
| D | MIMX8UD5_cm33.h | 49228 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| D | MIMX8UD5_dsp0.h | 47570 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/ |
| D | MIMX8US5_dsp0.h | 47570 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| D | MIMX8US5_cm33.h | 49228 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/ |
| D | MIMX8US3_dsp0.h | 49157 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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| D | MIMX8US3_cm33.h | 50836 __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ member
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