1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_SWT.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_SWT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_SWT_H_) /* Check if memory map has not been already included */ 58 #define S32K344_SWT_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SWT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SWT_Peripheral_Access_Layer SWT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SWT - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CR; /**< Control, offset: 0x0 */ 74 __IO uint32_t IR; /**< Interrupt, offset: 0x4 */ 75 __IO uint32_t TO; /**< Timeout, offset: 0x8 */ 76 __IO uint32_t WN; /**< Window, offset: 0xC */ 77 __O uint32_t SR; /**< Service, offset: 0x10 */ 78 __I uint32_t CO; /**< Counter Output, offset: 0x14 */ 79 __IO uint32_t SK; /**< Service Key, offset: 0x18 */ 80 __IO uint32_t RRR; /**< Event Request, offset: 0x1C */ 81 } SWT_Type, *SWT_MemMapPtr; 82 83 /** Number of instances of the SWT module. */ 84 #define SWT_INSTANCE_COUNT (1u) 85 86 /* SWT - Peripheral instance base addresses */ 87 /** Peripheral SWT_0 base address */ 88 #define IP_SWT_0_BASE (0x40270000u) 89 /** Peripheral SWT_0 base pointer */ 90 #define IP_SWT_0 ((SWT_Type *)IP_SWT_0_BASE) 91 /** Array initializer of SWT peripheral base addresses */ 92 #define IP_SWT_BASE_ADDRS { IP_SWT_0_BASE } 93 /** Array initializer of SWT peripheral base pointers */ 94 #define IP_SWT_BASE_PTRS { IP_SWT_0 } 95 96 /* ---------------------------------------------------------------------------- 97 -- SWT Register Masks 98 ---------------------------------------------------------------------------- */ 99 100 /*! 101 * @addtogroup SWT_Register_Masks SWT Register Masks 102 * @{ 103 */ 104 105 /*! @name CR - Control */ 106 /*! @{ */ 107 108 #define SWT_CR_WEN_MASK (0x1U) 109 #define SWT_CR_WEN_SHIFT (0U) 110 #define SWT_CR_WEN_WIDTH (1U) 111 #define SWT_CR_WEN(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_WEN_SHIFT)) & SWT_CR_WEN_MASK) 112 113 #define SWT_CR_FRZ_MASK (0x2U) 114 #define SWT_CR_FRZ_SHIFT (1U) 115 #define SWT_CR_FRZ_WIDTH (1U) 116 #define SWT_CR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_FRZ_SHIFT)) & SWT_CR_FRZ_MASK) 117 118 #define SWT_CR_STP_MASK (0x4U) 119 #define SWT_CR_STP_SHIFT (2U) 120 #define SWT_CR_STP_WIDTH (1U) 121 #define SWT_CR_STP(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_STP_SHIFT)) & SWT_CR_STP_MASK) 122 123 #define SWT_CR_SLK_MASK (0x10U) 124 #define SWT_CR_SLK_SHIFT (4U) 125 #define SWT_CR_SLK_WIDTH (1U) 126 #define SWT_CR_SLK(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_SLK_SHIFT)) & SWT_CR_SLK_MASK) 127 128 #define SWT_CR_HLK_MASK (0x20U) 129 #define SWT_CR_HLK_SHIFT (5U) 130 #define SWT_CR_HLK_WIDTH (1U) 131 #define SWT_CR_HLK(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_HLK_SHIFT)) & SWT_CR_HLK_MASK) 132 133 #define SWT_CR_ITR_MASK (0x40U) 134 #define SWT_CR_ITR_SHIFT (6U) 135 #define SWT_CR_ITR_WIDTH (1U) 136 #define SWT_CR_ITR(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_ITR_SHIFT)) & SWT_CR_ITR_MASK) 137 138 #define SWT_CR_WND_MASK (0x80U) 139 #define SWT_CR_WND_SHIFT (7U) 140 #define SWT_CR_WND_WIDTH (1U) 141 #define SWT_CR_WND(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_WND_SHIFT)) & SWT_CR_WND_MASK) 142 143 #define SWT_CR_RIA_MASK (0x100U) 144 #define SWT_CR_RIA_SHIFT (8U) 145 #define SWT_CR_RIA_WIDTH (1U) 146 #define SWT_CR_RIA(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_RIA_SHIFT)) & SWT_CR_RIA_MASK) 147 148 #define SWT_CR_SMD_MASK (0x600U) 149 #define SWT_CR_SMD_SHIFT (9U) 150 #define SWT_CR_SMD_WIDTH (2U) 151 #define SWT_CR_SMD(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_SMD_SHIFT)) & SWT_CR_SMD_MASK) 152 153 #define SWT_CR_MAP7_MASK (0x1000000U) 154 #define SWT_CR_MAP7_SHIFT (24U) 155 #define SWT_CR_MAP7_WIDTH (1U) 156 #define SWT_CR_MAP7(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP7_SHIFT)) & SWT_CR_MAP7_MASK) 157 158 #define SWT_CR_MAP6_MASK (0x2000000U) 159 #define SWT_CR_MAP6_SHIFT (25U) 160 #define SWT_CR_MAP6_WIDTH (1U) 161 #define SWT_CR_MAP6(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP6_SHIFT)) & SWT_CR_MAP6_MASK) 162 163 #define SWT_CR_MAP5_MASK (0x4000000U) 164 #define SWT_CR_MAP5_SHIFT (26U) 165 #define SWT_CR_MAP5_WIDTH (1U) 166 #define SWT_CR_MAP5(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP5_SHIFT)) & SWT_CR_MAP5_MASK) 167 168 #define SWT_CR_MAP4_MASK (0x8000000U) 169 #define SWT_CR_MAP4_SHIFT (27U) 170 #define SWT_CR_MAP4_WIDTH (1U) 171 #define SWT_CR_MAP4(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP4_SHIFT)) & SWT_CR_MAP4_MASK) 172 173 #define SWT_CR_MAP3_MASK (0x10000000U) 174 #define SWT_CR_MAP3_SHIFT (28U) 175 #define SWT_CR_MAP3_WIDTH (1U) 176 #define SWT_CR_MAP3(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP3_SHIFT)) & SWT_CR_MAP3_MASK) 177 178 #define SWT_CR_MAP2_MASK (0x20000000U) 179 #define SWT_CR_MAP2_SHIFT (29U) 180 #define SWT_CR_MAP2_WIDTH (1U) 181 #define SWT_CR_MAP2(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP2_SHIFT)) & SWT_CR_MAP2_MASK) 182 183 #define SWT_CR_MAP1_MASK (0x40000000U) 184 #define SWT_CR_MAP1_SHIFT (30U) 185 #define SWT_CR_MAP1_WIDTH (1U) 186 #define SWT_CR_MAP1(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP1_SHIFT)) & SWT_CR_MAP1_MASK) 187 188 #define SWT_CR_MAP0_MASK (0x80000000U) 189 #define SWT_CR_MAP0_SHIFT (31U) 190 #define SWT_CR_MAP0_WIDTH (1U) 191 #define SWT_CR_MAP0(x) (((uint32_t)(((uint32_t)(x)) << SWT_CR_MAP0_SHIFT)) & SWT_CR_MAP0_MASK) 192 /*! @} */ 193 194 /*! @name IR - Interrupt */ 195 /*! @{ */ 196 197 #define SWT_IR_TIF_MASK (0x1U) 198 #define SWT_IR_TIF_SHIFT (0U) 199 #define SWT_IR_TIF_WIDTH (1U) 200 #define SWT_IR_TIF(x) (((uint32_t)(((uint32_t)(x)) << SWT_IR_TIF_SHIFT)) & SWT_IR_TIF_MASK) 201 /*! @} */ 202 203 /*! @name TO - Timeout */ 204 /*! @{ */ 205 206 #define SWT_TO_WTO_MASK (0xFFFFFFFFU) 207 #define SWT_TO_WTO_SHIFT (0U) 208 #define SWT_TO_WTO_WIDTH (32U) 209 #define SWT_TO_WTO(x) (((uint32_t)(((uint32_t)(x)) << SWT_TO_WTO_SHIFT)) & SWT_TO_WTO_MASK) 210 /*! @} */ 211 212 /*! @name WN - Window */ 213 /*! @{ */ 214 215 #define SWT_WN_WST_MASK (0xFFFFFFFFU) 216 #define SWT_WN_WST_SHIFT (0U) 217 #define SWT_WN_WST_WIDTH (32U) 218 #define SWT_WN_WST(x) (((uint32_t)(((uint32_t)(x)) << SWT_WN_WST_SHIFT)) & SWT_WN_WST_MASK) 219 /*! @} */ 220 221 /*! @name SR - Service */ 222 /*! @{ */ 223 224 #define SWT_SR_WSC_MASK (0xFFFFU) 225 #define SWT_SR_WSC_SHIFT (0U) 226 #define SWT_SR_WSC_WIDTH (16U) 227 #define SWT_SR_WSC(x) (((uint32_t)(((uint32_t)(x)) << SWT_SR_WSC_SHIFT)) & SWT_SR_WSC_MASK) 228 /*! @} */ 229 230 /*! @name CO - Counter Output */ 231 /*! @{ */ 232 233 #define SWT_CO_CNT_MASK (0xFFFFFFFFU) 234 #define SWT_CO_CNT_SHIFT (0U) 235 #define SWT_CO_CNT_WIDTH (32U) 236 #define SWT_CO_CNT(x) (((uint32_t)(((uint32_t)(x)) << SWT_CO_CNT_SHIFT)) & SWT_CO_CNT_MASK) 237 /*! @} */ 238 239 /*! @name SK - Service Key */ 240 /*! @{ */ 241 242 #define SWT_SK_SK_MASK (0xFFFFU) 243 #define SWT_SK_SK_SHIFT (0U) 244 #define SWT_SK_SK_WIDTH (16U) 245 #define SWT_SK_SK(x) (((uint32_t)(((uint32_t)(x)) << SWT_SK_SK_SHIFT)) & SWT_SK_SK_MASK) 246 /*! @} */ 247 248 /*! @name RRR - Event Request */ 249 /*! @{ */ 250 251 #define SWT_RRR_RRF_MASK (0x1U) 252 #define SWT_RRR_RRF_SHIFT (0U) 253 #define SWT_RRR_RRF_WIDTH (1U) 254 #define SWT_RRR_RRF(x) (((uint32_t)(((uint32_t)(x)) << SWT_RRR_RRF_SHIFT)) & SWT_RRR_RRF_MASK) 255 /*! @} */ 256 257 /*! 258 * @} 259 */ /* end of group SWT_Register_Masks */ 260 261 /*! 262 * @} 263 */ /* end of group SWT_Peripheral_Access_Layer */ 264 265 #endif /* #if !defined(S32K344_SWT_H_) */ 266
