1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SIUL2.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_SIUL2 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SIUL2_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SIUL2_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SIUL2 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SIUL2_Peripheral_Access_Layer SIUL2 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SIUL2 - Size of Registers Arrays */ 72 #define SIUL2_IFMCR_COUNT 20u 73 #define SIUL2_MSCR_COUNT 504u 74 #define SIUL2_IMCR_COUNT 496u 75 #define SIUL2_MPGPDO_COUNT 11u 76 77 /** SIUL2 - Register Layout Typedef */ 78 typedef struct { 79 uint8_t RESERVED_0[4]; 80 __I uint32_t MIDR1; /**< SIUL2 MCU ID Register #1, offset: 0x4 */ 81 __I uint32_t MIDR2; /**< SIUL2 MCU ID Register #2, offset: 0x8 */ 82 uint8_t RESERVED_1[4]; 83 __IO uint32_t DISR0; /**< SIUL2 DMA/Interrupt Status Flag Register0, offset: 0x10 */ 84 uint8_t RESERVED_2[4]; 85 __IO uint32_t DIRER0; /**< SIUL2 DMA/Interrupt Request Enable Register0, offset: 0x18 */ 86 uint8_t RESERVED_3[4]; 87 __IO uint32_t DIRSR0; /**< SIUL2 DMA/Interrupt Request Select Register0, offset: 0x20 */ 88 uint8_t RESERVED_4[4]; 89 __IO uint32_t IREER0; /**< SIUL2 Interrupt Rising-Edge Event Enable Register 0, offset: 0x28 */ 90 uint8_t RESERVED_5[4]; 91 __IO uint32_t IFEER0; /**< SIUL2 Interrupt Falling-Edge Event Enable Register 0, offset: 0x30 */ 92 uint8_t RESERVED_6[4]; 93 __IO uint32_t IFER0; /**< SIUL2 Interrupt Filter Enable Register 0, offset: 0x38 */ 94 uint8_t RESERVED_7[4]; 95 __IO uint32_t IFMCR[SIUL2_IFMCR_COUNT]; /**< SIUL2 Interrupt Filter Maximum Counter Register, array offset: 0x40, array step: 0x4 */ 96 uint8_t RESERVED_8[48]; 97 __IO uint32_t IFCPR; /**< SIUL2 Interrupt Filter Clock Prescaler Register, offset: 0xC0 */ 98 uint8_t RESERVED_9[316]; 99 __I uint32_t MIDR3; /**< SIUL2 MCU ID Register #3, offset: 0x200 */ 100 __I uint32_t MIDR4; /**< SIUL2 MCU ID Register #4, offset: 0x204 */ 101 uint8_t RESERVED_10[56]; 102 __IO uint32_t MSCR[SIUL2_MSCR_COUNT]; /**< SIUL2 Multiplexed Signal Configuration Register, array offset: 0x240, array step: 0x4 */ 103 uint8_t RESERVED_11[32]; 104 __IO uint32_t IMCR[SIUL2_IMCR_COUNT]; /**< SIUL2 Input Multiplexed Signal Configuration Register, array offset: 0xA40, array step: 0x4 */ 105 uint8_t RESERVED_12[256]; 106 __IO uint8_t GPDO3; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1300 */ 107 __IO uint8_t GPDO2; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1301 */ 108 __IO uint8_t GPDO1; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1302 */ 109 __IO uint8_t GPDO0; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1303 */ 110 __IO uint8_t GPDO7; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1304 */ 111 __IO uint8_t GPDO6; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1305 */ 112 __IO uint8_t GPDO5; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1306 */ 113 __IO uint8_t GPDO4; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1307 */ 114 __IO uint8_t GPDO11; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1308 */ 115 __IO uint8_t GPDO10; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1309 */ 116 __IO uint8_t GPDO9; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130A */ 117 __IO uint8_t GPDO8; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130B */ 118 __IO uint8_t GPDO15; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130C */ 119 __IO uint8_t GPDO14; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130D */ 120 __IO uint8_t GPDO13; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130E */ 121 __IO uint8_t GPDO12; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x130F */ 122 __IO uint8_t GPDO19; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1310 */ 123 __IO uint8_t GPDO18; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1311 */ 124 __IO uint8_t GPDO17; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1312 */ 125 __IO uint8_t GPDO16; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1313 */ 126 __IO uint8_t GPDO23; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1314 */ 127 __IO uint8_t GPDO22; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1315 */ 128 __IO uint8_t GPDO21; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1316 */ 129 __IO uint8_t GPDO20; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1317 */ 130 __IO uint8_t GPDO27; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1318 */ 131 __IO uint8_t GPDO26; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1319 */ 132 __IO uint8_t GPDO25; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131A */ 133 __IO uint8_t GPDO24; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131B */ 134 __IO uint8_t GPDO31; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131C */ 135 __IO uint8_t GPDO30; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131D */ 136 __IO uint8_t GPDO29; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131E */ 137 __IO uint8_t GPDO28; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x131F */ 138 __IO uint8_t GPDO35; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1320 */ 139 __IO uint8_t GPDO34; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1321 */ 140 __IO uint8_t GPDO33; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1322 */ 141 __IO uint8_t GPDO32; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1323 */ 142 __IO uint8_t GPDO39; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1324 */ 143 __IO uint8_t GPDO38; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1325 */ 144 __IO uint8_t GPDO37; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1326 */ 145 __IO uint8_t GPDO36; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1327 */ 146 __IO uint8_t GPDO43; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1328 */ 147 __IO uint8_t GPDO42; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1329 */ 148 __IO uint8_t GPDO41; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132A */ 149 __IO uint8_t GPDO40; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132B */ 150 __IO uint8_t GPDO47; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132C */ 151 __IO uint8_t GPDO46; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132D */ 152 __IO uint8_t GPDO45; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132E */ 153 __IO uint8_t GPDO44; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x132F */ 154 __IO uint8_t GPDO51; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1330 */ 155 __IO uint8_t GPDO50; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1331 */ 156 __IO uint8_t GPDO49; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1332 */ 157 __IO uint8_t GPDO48; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1333 */ 158 __IO uint8_t GPDO55; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1334 */ 159 __IO uint8_t GPDO54; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1335 */ 160 __IO uint8_t GPDO53; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1336 */ 161 __IO uint8_t GPDO52; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1337 */ 162 __IO uint8_t GPDO59; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1338 */ 163 __IO uint8_t GPDO58; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1339 */ 164 __IO uint8_t GPDO57; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133A */ 165 __IO uint8_t GPDO56; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133B */ 166 __IO uint8_t GPDO63; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133C */ 167 __IO uint8_t GPDO62; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133D */ 168 __IO uint8_t GPDO61; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133E */ 169 __IO uint8_t GPDO60; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x133F */ 170 __IO uint8_t GPDO67; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1340 */ 171 __IO uint8_t GPDO66; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1341 */ 172 __IO uint8_t GPDO65; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1342 */ 173 __IO uint8_t GPDO64; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1343 */ 174 __IO uint8_t GPDO71; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1344 */ 175 __IO uint8_t GPDO70; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1345 */ 176 __IO uint8_t GPDO69; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1346 */ 177 __IO uint8_t GPDO68; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1347 */ 178 __IO uint8_t GPDO75; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1348 */ 179 __IO uint8_t GPDO74; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1349 */ 180 __IO uint8_t GPDO73; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134A */ 181 __IO uint8_t GPDO72; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134B */ 182 __IO uint8_t GPDO79; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134C */ 183 __IO uint8_t GPDO78; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134D */ 184 __IO uint8_t GPDO77; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134E */ 185 __IO uint8_t GPDO76; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x134F */ 186 __IO uint8_t GPDO83; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1350 */ 187 __IO uint8_t GPDO82; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1351 */ 188 __IO uint8_t GPDO81; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1352 */ 189 __IO uint8_t GPDO80; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1353 */ 190 __IO uint8_t GPDO87; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1354 */ 191 __IO uint8_t GPDO86; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1355 */ 192 __IO uint8_t GPDO85; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1356 */ 193 __IO uint8_t GPDO84; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1357 */ 194 __IO uint8_t GPDO91; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1358 */ 195 __IO uint8_t GPDO90; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1359 */ 196 __IO uint8_t GPDO89; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135A */ 197 __IO uint8_t GPDO88; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135B */ 198 __IO uint8_t GPDO95; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135C */ 199 __IO uint8_t GPDO94; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135D */ 200 __IO uint8_t GPDO93; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135E */ 201 __IO uint8_t GPDO92; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x135F */ 202 __IO uint8_t GPDO99; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1360 */ 203 __IO uint8_t GPDO98; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1361 */ 204 __IO uint8_t GPDO97; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1362 */ 205 __IO uint8_t GPDO96; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1363 */ 206 __IO uint8_t GPDO103; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1364 */ 207 __IO uint8_t GPDO102; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1365 */ 208 __IO uint8_t GPDO101; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1366 */ 209 __IO uint8_t GPDO100; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1367 */ 210 __IO uint8_t GPDO107; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1368 */ 211 __IO uint8_t GPDO106; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1369 */ 212 __IO uint8_t GPDO105; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136A */ 213 __IO uint8_t GPDO104; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136B */ 214 __IO uint8_t GPDO111; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136C */ 215 __IO uint8_t GPDO110; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136D */ 216 __IO uint8_t GPDO109; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136E */ 217 __IO uint8_t GPDO108; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x136F */ 218 __IO uint8_t GPDO115; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1370 */ 219 __IO uint8_t GPDO114; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1371 */ 220 __IO uint8_t GPDO113; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1372 */ 221 __IO uint8_t GPDO112; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1373 */ 222 __IO uint8_t GPDO119; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1374 */ 223 __IO uint8_t GPDO118; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1375 */ 224 __IO uint8_t GPDO117; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1376 */ 225 __IO uint8_t GPDO116; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1377 */ 226 __IO uint8_t GPDO123; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1378 */ 227 __IO uint8_t GPDO122; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1379 */ 228 __IO uint8_t GPDO121; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137A */ 229 __IO uint8_t GPDO120; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137B */ 230 __IO uint8_t GPDO127; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137C */ 231 __IO uint8_t GPDO126; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137D */ 232 __IO uint8_t GPDO125; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137E */ 233 __IO uint8_t GPDO124; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x137F */ 234 __IO uint8_t GPDO131; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1380 */ 235 __IO uint8_t GPDO130; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1381 */ 236 __IO uint8_t GPDO129; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1382 */ 237 __IO uint8_t GPDO128; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1383 */ 238 __IO uint8_t GPDO135; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1384 */ 239 __IO uint8_t GPDO134; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1385 */ 240 __IO uint8_t GPDO133; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1386 */ 241 __IO uint8_t GPDO132; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1387 */ 242 __IO uint8_t GPDO139; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1388 */ 243 __IO uint8_t GPDO138; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1389 */ 244 __IO uint8_t GPDO137; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138A */ 245 __IO uint8_t GPDO136; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138B */ 246 __IO uint8_t GPDO143; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138C */ 247 __IO uint8_t GPDO142; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138D */ 248 __IO uint8_t GPDO141; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138E */ 249 __IO uint8_t GPDO140; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x138F */ 250 __IO uint8_t GPDO147; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1390 */ 251 __IO uint8_t GPDO146; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1391 */ 252 __IO uint8_t GPDO145; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1392 */ 253 __IO uint8_t GPDO144; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1393 */ 254 __IO uint8_t GPDO151; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1394 */ 255 __IO uint8_t GPDO150; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1395 */ 256 __IO uint8_t GPDO149; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1396 */ 257 __IO uint8_t GPDO148; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1397 */ 258 __IO uint8_t GPDO155; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1398 */ 259 __IO uint8_t GPDO154; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x1399 */ 260 __IO uint8_t GPDO153; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139A */ 261 __IO uint8_t GPDO152; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139B */ 262 __IO uint8_t GPDO159; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139C */ 263 __IO uint8_t GPDO158; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139D */ 264 __IO uint8_t GPDO157; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139E */ 265 __IO uint8_t GPDO156; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x139F */ 266 __IO uint8_t GPDO163; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A0 */ 267 __IO uint8_t GPDO162; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A1 */ 268 __IO uint8_t GPDO161; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A2 */ 269 __IO uint8_t GPDO160; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A3 */ 270 __IO uint8_t GPDO167; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A4 */ 271 __IO uint8_t GPDO166; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A5 */ 272 __IO uint8_t GPDO165; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A6 */ 273 __IO uint8_t GPDO164; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A7 */ 274 __IO uint8_t GPDO171; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A8 */ 275 __IO uint8_t GPDO170; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13A9 */ 276 __IO uint8_t GPDO169; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AA */ 277 __IO uint8_t GPDO168; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AB */ 278 uint8_t RESERVED_13[2]; 279 __IO uint8_t GPDO173; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AE */ 280 __IO uint8_t GPDO172; /**< SIUL2 GPIO Pad Data Output Register, offset: 0x13AF */ 281 uint8_t RESERVED_14[336]; 282 __I uint8_t GPDI3; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1500 */ 283 __I uint8_t GPDI2; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1501 */ 284 __I uint8_t GPDI1; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1502 */ 285 __I uint8_t GPDI0; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1503 */ 286 __I uint8_t GPDI7; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1504 */ 287 __I uint8_t GPDI6; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1505 */ 288 __I uint8_t GPDI5; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1506 */ 289 __I uint8_t GPDI4; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1507 */ 290 __I uint8_t GPDI11; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1508 */ 291 __I uint8_t GPDI10; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1509 */ 292 __I uint8_t GPDI9; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150A */ 293 __I uint8_t GPDI8; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150B */ 294 __I uint8_t GPDI15; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150C */ 295 __I uint8_t GPDI14; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150D */ 296 __I uint8_t GPDI13; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150E */ 297 __I uint8_t GPDI12; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x150F */ 298 __I uint8_t GPDI19; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1510 */ 299 __I uint8_t GPDI18; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1511 */ 300 __I uint8_t GPDI17; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1512 */ 301 __I uint8_t GPDI16; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1513 */ 302 __I uint8_t GPDI23; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1514 */ 303 __I uint8_t GPDI22; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1515 */ 304 __I uint8_t GPDI21; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1516 */ 305 __I uint8_t GPDI20; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1517 */ 306 __I uint8_t GPDI27; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1518 */ 307 __I uint8_t GPDI26; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1519 */ 308 __I uint8_t GPDI25; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151A */ 309 __I uint8_t GPDI24; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151B */ 310 __I uint8_t GPDI31; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151C */ 311 __I uint8_t GPDI30; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151D */ 312 __I uint8_t GPDI29; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151E */ 313 __I uint8_t GPDI28; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x151F */ 314 __I uint8_t GPDI35; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1520 */ 315 __I uint8_t GPDI34; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1521 */ 316 __I uint8_t GPDI33; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1522 */ 317 __I uint8_t GPDI32; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1523 */ 318 __I uint8_t GPDI39; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1524 */ 319 __I uint8_t GPDI38; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1525 */ 320 __I uint8_t GPDI37; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1526 */ 321 __I uint8_t GPDI36; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1527 */ 322 __I uint8_t GPDI43; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1528 */ 323 __I uint8_t GPDI42; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1529 */ 324 __I uint8_t GPDI41; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152A */ 325 __I uint8_t GPDI40; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152B */ 326 __I uint8_t GPDI47; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152C */ 327 __I uint8_t GPDI46; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152D */ 328 __I uint8_t GPDI45; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152E */ 329 __I uint8_t GPDI44; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x152F */ 330 __I uint8_t GPDI51; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1530 */ 331 __I uint8_t GPDI50; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1531 */ 332 __I uint8_t GPDI49; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1532 */ 333 __I uint8_t GPDI48; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1533 */ 334 __I uint8_t GPDI55; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1534 */ 335 __I uint8_t GPDI54; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1535 */ 336 __I uint8_t GPDI53; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1536 */ 337 __I uint8_t GPDI52; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1537 */ 338 __I uint8_t GPDI59; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1538 */ 339 __I uint8_t GPDI58; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1539 */ 340 __I uint8_t GPDI57; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153A */ 341 __I uint8_t GPDI56; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153B */ 342 __I uint8_t GPDI63; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153C */ 343 __I uint8_t GPDI62; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153D */ 344 __I uint8_t GPDI61; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153E */ 345 __I uint8_t GPDI60; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x153F */ 346 __I uint8_t GPDI67; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1540 */ 347 __I uint8_t GPDI66; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1541 */ 348 __I uint8_t GPDI65; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1542 */ 349 __I uint8_t GPDI64; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1543 */ 350 __I uint8_t GPDI71; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1544 */ 351 __I uint8_t GPDI70; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1545 */ 352 __I uint8_t GPDI69; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1546 */ 353 __I uint8_t GPDI68; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1547 */ 354 __I uint8_t GPDI75; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1548 */ 355 __I uint8_t GPDI74; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1549 */ 356 __I uint8_t GPDI73; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154A */ 357 __I uint8_t GPDI72; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154B */ 358 __I uint8_t GPDI79; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154C */ 359 __I uint8_t GPDI78; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154D */ 360 __I uint8_t GPDI77; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154E */ 361 __I uint8_t GPDI76; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x154F */ 362 __I uint8_t GPDI83; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1550 */ 363 __I uint8_t GPDI82; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1551 */ 364 __I uint8_t GPDI81; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1552 */ 365 __I uint8_t GPDI80; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1553 */ 366 __I uint8_t GPDI87; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1554 */ 367 __I uint8_t GPDI86; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1555 */ 368 __I uint8_t GPDI85; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1556 */ 369 __I uint8_t GPDI84; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1557 */ 370 __I uint8_t GPDI91; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1558 */ 371 __I uint8_t GPDI90; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1559 */ 372 __I uint8_t GPDI89; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155A */ 373 __I uint8_t GPDI88; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155B */ 374 __I uint8_t GPDI95; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155C */ 375 __I uint8_t GPDI94; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155D */ 376 __I uint8_t GPDI93; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155E */ 377 __I uint8_t GPDI92; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x155F */ 378 __I uint8_t GPDI99; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1560 */ 379 __I uint8_t GPDI98; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1561 */ 380 __I uint8_t GPDI97; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1562 */ 381 __I uint8_t GPDI96; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1563 */ 382 __I uint8_t GPDI103; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1564 */ 383 __I uint8_t GPDI102; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1565 */ 384 __I uint8_t GPDI101; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1566 */ 385 __I uint8_t GPDI100; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1567 */ 386 __I uint8_t GPDI107; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1568 */ 387 __I uint8_t GPDI106; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1569 */ 388 __I uint8_t GPDI105; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156A */ 389 __I uint8_t GPDI104; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156B */ 390 __I uint8_t GPDI111; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156C */ 391 __I uint8_t GPDI110; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156D */ 392 __I uint8_t GPDI109; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156E */ 393 __I uint8_t GPDI108; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x156F */ 394 __I uint8_t GPDI115; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1570 */ 395 __I uint8_t GPDI114; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1571 */ 396 __I uint8_t GPDI113; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1572 */ 397 __I uint8_t GPDI112; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1573 */ 398 __I uint8_t GPDI119; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1574 */ 399 __I uint8_t GPDI118; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1575 */ 400 __I uint8_t GPDI117; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1576 */ 401 __I uint8_t GPDI116; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1577 */ 402 __I uint8_t GPDI123; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1578 */ 403 __I uint8_t GPDI122; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1579 */ 404 __I uint8_t GPDI121; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157A */ 405 __I uint8_t GPDI120; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157B */ 406 __I uint8_t GPDI127; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157C */ 407 __I uint8_t GPDI126; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157D */ 408 __I uint8_t GPDI125; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157E */ 409 __I uint8_t GPDI124; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x157F */ 410 __I uint8_t GPDI131; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1580 */ 411 __I uint8_t GPDI130; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1581 */ 412 __I uint8_t GPDI129; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1582 */ 413 __I uint8_t GPDI128; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1583 */ 414 __I uint8_t GPDI135; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1584 */ 415 __I uint8_t GPDI134; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1585 */ 416 __I uint8_t GPDI133; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1586 */ 417 __I uint8_t GPDI132; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1587 */ 418 __I uint8_t GPDI139; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1588 */ 419 __I uint8_t GPDI138; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1589 */ 420 __I uint8_t GPDI137; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158A */ 421 __I uint8_t GPDI136; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158B */ 422 __I uint8_t GPDI143; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158C */ 423 __I uint8_t GPDI142; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158D */ 424 __I uint8_t GPDI141; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158E */ 425 __I uint8_t GPDI140; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x158F */ 426 __I uint8_t GPDI147; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1590 */ 427 __I uint8_t GPDI146; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1591 */ 428 __I uint8_t GPDI145; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1592 */ 429 __I uint8_t GPDI144; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1593 */ 430 __I uint8_t GPDI151; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1594 */ 431 __I uint8_t GPDI150; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1595 */ 432 __I uint8_t GPDI149; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1596 */ 433 __I uint8_t GPDI148; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1597 */ 434 __I uint8_t GPDI155; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1598 */ 435 __I uint8_t GPDI154; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x1599 */ 436 __I uint8_t GPDI153; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159A */ 437 __I uint8_t GPDI152; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159B */ 438 __I uint8_t GPDI159; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159C */ 439 __I uint8_t GPDI158; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159D */ 440 __I uint8_t GPDI157; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159E */ 441 __I uint8_t GPDI156; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x159F */ 442 __I uint8_t GPDI163; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A0 */ 443 __I uint8_t GPDI162; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A1 */ 444 __I uint8_t GPDI161; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A2 */ 445 __I uint8_t GPDI160; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A3 */ 446 __I uint8_t GPDI167; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A4 */ 447 __I uint8_t GPDI166; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A5 */ 448 __I uint8_t GPDI165; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A6 */ 449 __I uint8_t GPDI164; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A7 */ 450 __I uint8_t GPDI171; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A8 */ 451 __I uint8_t GPDI170; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15A9 */ 452 __I uint8_t GPDI169; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AA */ 453 __I uint8_t GPDI168; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AB */ 454 uint8_t RESERVED_15[2]; 455 __I uint8_t GPDI173; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AE */ 456 __I uint8_t GPDI172; /**< SIUL2 GPIO Pad Data Input Register, offset: 0x15AF */ 457 uint8_t RESERVED_16[336]; 458 __IO uint16_t PGPDO1; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1700 */ 459 __IO uint16_t PGPDO0; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1702 */ 460 __IO uint16_t PGPDO3; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1704 */ 461 __IO uint16_t PGPDO2; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1706 */ 462 __IO uint16_t PGPDO5; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1708 */ 463 __IO uint16_t PGPDO4; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x170A */ 464 __IO uint16_t PGPDO7; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x170C */ 465 __IO uint16_t PGPDO6; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x170E */ 466 __IO uint16_t PGPDO9; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1710 */ 467 __IO uint16_t PGPDO8; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1712 */ 468 uint8_t RESERVED_17[2]; 469 __IO uint16_t PGPDO10; /**< SIUL2 Parallel GPIO Pad Data Out Register, offset: 0x1716 */ 470 uint8_t RESERVED_18[40]; 471 __I uint16_t PGPDI1; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1740 */ 472 __I uint16_t PGPDI0; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1742 */ 473 __I uint16_t PGPDI3; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1744 */ 474 __I uint16_t PGPDI2; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1746 */ 475 __I uint16_t PGPDI5; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1748 */ 476 __I uint16_t PGPDI4; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x174A */ 477 __I uint16_t PGPDI7; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x174C */ 478 __I uint16_t PGPDI6; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x174E */ 479 __I uint16_t PGPDI9; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1750 */ 480 __I uint16_t PGPDI8; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1752 */ 481 uint8_t RESERVED_19[2]; 482 __I uint16_t PGPDI10; /**< SIUL2 Parallel GPIO Pad Data In Register, offset: 0x1756 */ 483 uint8_t RESERVED_20[40]; 484 __O uint32_t MPGPDO[SIUL2_MPGPDO_COUNT]; /**< SIUL2 Masked Parallel GPIO Pad Data Out Register, array offset: 0x1780, array step: 0x4 */ 485 } SIUL2_Type, *SIUL2_MemMapPtr; 486 487 /** Number of instances of the SIUL2 module. */ 488 #define SIUL2_INSTANCE_COUNT (5u) 489 490 /* SIUL2 - Peripheral instance base addresses */ 491 /** Peripheral SIUL2_0 base address */ 492 #define IP_SIUL2_0_BASE (0x40520000u) 493 /** Peripheral SIUL2_0 base pointer */ 494 #define IP_SIUL2_0 ((SIUL2_Type *)IP_SIUL2_0_BASE) 495 /** Peripheral SIUL2_1 base address */ 496 #define IP_SIUL2_1_BASE (0x40D20000u) 497 /** Peripheral SIUL2_1 base pointer */ 498 #define IP_SIUL2_1 ((SIUL2_Type *)IP_SIUL2_1_BASE) 499 /** Peripheral SIUL2_3 base address */ 500 #define IP_SIUL2_3_BASE (0x41D20000u) 501 /** Peripheral SIUL2_3 base pointer */ 502 #define IP_SIUL2_3 ((SIUL2_Type *)IP_SIUL2_3_BASE) 503 /** Peripheral SIUL2_4 base address */ 504 #define IP_SIUL2_4_BASE (0x42520000u) 505 /** Peripheral SIUL2_4 base pointer */ 506 #define IP_SIUL2_4 ((SIUL2_Type *)IP_SIUL2_4_BASE) 507 /** Peripheral SIUL2_5 base address */ 508 #define IP_SIUL2_5_BASE (0x42D20000u) 509 /** Peripheral SIUL2_5 base pointer */ 510 #define IP_SIUL2_5 ((SIUL2_Type *)IP_SIUL2_5_BASE) 511 /** Array initializer of SIUL2 peripheral base addresses */ 512 #define IP_SIUL2_BASE_ADDRS { IP_SIUL2_0_BASE, IP_SIUL2_1_BASE, IP_SIUL2_3_BASE, IP_SIUL2_4_BASE, IP_SIUL2_5_BASE } 513 /** Array initializer of SIUL2 peripheral base pointers */ 514 #define IP_SIUL2_BASE_PTRS { IP_SIUL2_0, IP_SIUL2_1, IP_SIUL2_3, IP_SIUL2_4, IP_SIUL2_5 } 515 516 /* ---------------------------------------------------------------------------- 517 -- SIUL2 Register Masks 518 ---------------------------------------------------------------------------- */ 519 520 /*! 521 * @addtogroup SIUL2_Register_Masks SIUL2 Register Masks 522 * @{ 523 */ 524 525 /*! @name MIDR1 - SIUL2 MCU ID Register #1 */ 526 /*! @{ */ 527 528 #define SIUL2_MIDR1_MINOR_MASK_MASK (0xFU) 529 #define SIUL2_MIDR1_MINOR_MASK_SHIFT (0U) 530 #define SIUL2_MIDR1_MINOR_MASK_WIDTH (4U) 531 #define SIUL2_MIDR1_MINOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR1_MINOR_MASK_SHIFT)) & SIUL2_MIDR1_MINOR_MASK_MASK) 532 533 #define SIUL2_MIDR1_MAJOR_MASK_MASK (0xF0U) 534 #define SIUL2_MIDR1_MAJOR_MASK_SHIFT (4U) 535 #define SIUL2_MIDR1_MAJOR_MASK_WIDTH (4U) 536 #define SIUL2_MIDR1_MAJOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR1_MAJOR_MASK_SHIFT)) & SIUL2_MIDR1_MAJOR_MASK_MASK) 537 538 #define SIUL2_MIDR1_PART_NO_MASK (0x3FF0000U) 539 #define SIUL2_MIDR1_PART_NO_SHIFT (16U) 540 #define SIUL2_MIDR1_PART_NO_WIDTH (10U) 541 #define SIUL2_MIDR1_PART_NO(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR1_PART_NO_SHIFT)) & SIUL2_MIDR1_PART_NO_MASK) 542 543 #define SIUL2_MIDR1_PRODUCT_LINE_LETTER_MASK (0xFC000000U) 544 #define SIUL2_MIDR1_PRODUCT_LINE_LETTER_SHIFT (26U) 545 #define SIUL2_MIDR1_PRODUCT_LINE_LETTER_WIDTH (6U) 546 #define SIUL2_MIDR1_PRODUCT_LINE_LETTER(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR1_PRODUCT_LINE_LETTER_SHIFT)) & SIUL2_MIDR1_PRODUCT_LINE_LETTER_MASK) 547 /*! @} */ 548 549 /*! @name MIDR2 - SIUL2 MCU ID Register #2 */ 550 /*! @{ */ 551 552 #define SIUL2_MIDR2_FLASH_SIZE_CODE_MASK (0xFFU) 553 #define SIUL2_MIDR2_FLASH_SIZE_CODE_SHIFT (0U) 554 #define SIUL2_MIDR2_FLASH_SIZE_CODE_WIDTH (8U) 555 #define SIUL2_MIDR2_FLASH_SIZE_CODE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FLASH_SIZE_CODE_SHIFT)) & SIUL2_MIDR2_FLASH_SIZE_CODE_MASK) 556 557 #define SIUL2_MIDR2_FLASH_SIZE_DATA_MASK (0xF00U) 558 #define SIUL2_MIDR2_FLASH_SIZE_DATA_SHIFT (8U) 559 #define SIUL2_MIDR2_FLASH_SIZE_DATA_WIDTH (4U) 560 #define SIUL2_MIDR2_FLASH_SIZE_DATA(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FLASH_SIZE_DATA_SHIFT)) & SIUL2_MIDR2_FLASH_SIZE_DATA_MASK) 561 562 #define SIUL2_MIDR2_FLASH_DATA_MASK (0x3000U) 563 #define SIUL2_MIDR2_FLASH_DATA_SHIFT (12U) 564 #define SIUL2_MIDR2_FLASH_DATA_WIDTH (2U) 565 #define SIUL2_MIDR2_FLASH_DATA(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FLASH_DATA_SHIFT)) & SIUL2_MIDR2_FLASH_DATA_MASK) 566 567 #define SIUL2_MIDR2_FLASH_CODE_MASK (0xC000U) 568 #define SIUL2_MIDR2_FLASH_CODE_SHIFT (14U) 569 #define SIUL2_MIDR2_FLASH_CODE_WIDTH (2U) 570 #define SIUL2_MIDR2_FLASH_CODE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FLASH_CODE_SHIFT)) & SIUL2_MIDR2_FLASH_CODE_MASK) 571 572 #define SIUL2_MIDR2_FREQUENCY_MASK (0xF0000U) 573 #define SIUL2_MIDR2_FREQUENCY_SHIFT (16U) 574 #define SIUL2_MIDR2_FREQUENCY_WIDTH (4U) 575 #define SIUL2_MIDR2_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_FREQUENCY_SHIFT)) & SIUL2_MIDR2_FREQUENCY_MASK) 576 577 #define SIUL2_MIDR2_PACKAGE_MASK (0x3F00000U) 578 #define SIUL2_MIDR2_PACKAGE_SHIFT (20U) 579 #define SIUL2_MIDR2_PACKAGE_WIDTH (6U) 580 #define SIUL2_MIDR2_PACKAGE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_PACKAGE_SHIFT)) & SIUL2_MIDR2_PACKAGE_MASK) 581 582 #define SIUL2_MIDR2_TEMPERATURE_MASK (0x1C000000U) 583 #define SIUL2_MIDR2_TEMPERATURE_SHIFT (26U) 584 #define SIUL2_MIDR2_TEMPERATURE_WIDTH (3U) 585 #define SIUL2_MIDR2_TEMPERATURE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_TEMPERATURE_SHIFT)) & SIUL2_MIDR2_TEMPERATURE_MASK) 586 587 #define SIUL2_MIDR2_TECHNOLOGY_MASK (0xE0000000U) 588 #define SIUL2_MIDR2_TECHNOLOGY_SHIFT (29U) 589 #define SIUL2_MIDR2_TECHNOLOGY_WIDTH (3U) 590 #define SIUL2_MIDR2_TECHNOLOGY(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR2_TECHNOLOGY_SHIFT)) & SIUL2_MIDR2_TECHNOLOGY_MASK) 591 /*! @} */ 592 593 /*! @name DISR0 - SIUL2 DMA/Interrupt Status Flag Register0 */ 594 /*! @{ */ 595 596 #define SIUL2_DISR0_EIF0_MASK (0x1U) 597 #define SIUL2_DISR0_EIF0_SHIFT (0U) 598 #define SIUL2_DISR0_EIF0_WIDTH (1U) 599 #define SIUL2_DISR0_EIF0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF0_SHIFT)) & SIUL2_DISR0_EIF0_MASK) 600 601 #define SIUL2_DISR0_EIF1_MASK (0x2U) 602 #define SIUL2_DISR0_EIF1_SHIFT (1U) 603 #define SIUL2_DISR0_EIF1_WIDTH (1U) 604 #define SIUL2_DISR0_EIF1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF1_SHIFT)) & SIUL2_DISR0_EIF1_MASK) 605 606 #define SIUL2_DISR0_EIF2_MASK (0x4U) 607 #define SIUL2_DISR0_EIF2_SHIFT (2U) 608 #define SIUL2_DISR0_EIF2_WIDTH (1U) 609 #define SIUL2_DISR0_EIF2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF2_SHIFT)) & SIUL2_DISR0_EIF2_MASK) 610 611 #define SIUL2_DISR0_EIF3_MASK (0x8U) 612 #define SIUL2_DISR0_EIF3_SHIFT (3U) 613 #define SIUL2_DISR0_EIF3_WIDTH (1U) 614 #define SIUL2_DISR0_EIF3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF3_SHIFT)) & SIUL2_DISR0_EIF3_MASK) 615 616 #define SIUL2_DISR0_EIF4_MASK (0x10U) 617 #define SIUL2_DISR0_EIF4_SHIFT (4U) 618 #define SIUL2_DISR0_EIF4_WIDTH (1U) 619 #define SIUL2_DISR0_EIF4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF4_SHIFT)) & SIUL2_DISR0_EIF4_MASK) 620 621 #define SIUL2_DISR0_EIF5_MASK (0x20U) 622 #define SIUL2_DISR0_EIF5_SHIFT (5U) 623 #define SIUL2_DISR0_EIF5_WIDTH (1U) 624 #define SIUL2_DISR0_EIF5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF5_SHIFT)) & SIUL2_DISR0_EIF5_MASK) 625 626 #define SIUL2_DISR0_EIF6_MASK (0x40U) 627 #define SIUL2_DISR0_EIF6_SHIFT (6U) 628 #define SIUL2_DISR0_EIF6_WIDTH (1U) 629 #define SIUL2_DISR0_EIF6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF6_SHIFT)) & SIUL2_DISR0_EIF6_MASK) 630 631 #define SIUL2_DISR0_EIF7_MASK (0x80U) 632 #define SIUL2_DISR0_EIF7_SHIFT (7U) 633 #define SIUL2_DISR0_EIF7_WIDTH (1U) 634 #define SIUL2_DISR0_EIF7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF7_SHIFT)) & SIUL2_DISR0_EIF7_MASK) 635 636 #define SIUL2_DISR0_EIF8_MASK (0x100U) 637 #define SIUL2_DISR0_EIF8_SHIFT (8U) 638 #define SIUL2_DISR0_EIF8_WIDTH (1U) 639 #define SIUL2_DISR0_EIF8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF8_SHIFT)) & SIUL2_DISR0_EIF8_MASK) 640 641 #define SIUL2_DISR0_EIF9_MASK (0x200U) 642 #define SIUL2_DISR0_EIF9_SHIFT (9U) 643 #define SIUL2_DISR0_EIF9_WIDTH (1U) 644 #define SIUL2_DISR0_EIF9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF9_SHIFT)) & SIUL2_DISR0_EIF9_MASK) 645 646 #define SIUL2_DISR0_EIF10_MASK (0x400U) 647 #define SIUL2_DISR0_EIF10_SHIFT (10U) 648 #define SIUL2_DISR0_EIF10_WIDTH (1U) 649 #define SIUL2_DISR0_EIF10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF10_SHIFT)) & SIUL2_DISR0_EIF10_MASK) 650 651 #define SIUL2_DISR0_EIF11_MASK (0x800U) 652 #define SIUL2_DISR0_EIF11_SHIFT (11U) 653 #define SIUL2_DISR0_EIF11_WIDTH (1U) 654 #define SIUL2_DISR0_EIF11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF11_SHIFT)) & SIUL2_DISR0_EIF11_MASK) 655 656 #define SIUL2_DISR0_EIF12_MASK (0x1000U) 657 #define SIUL2_DISR0_EIF12_SHIFT (12U) 658 #define SIUL2_DISR0_EIF12_WIDTH (1U) 659 #define SIUL2_DISR0_EIF12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF12_SHIFT)) & SIUL2_DISR0_EIF12_MASK) 660 661 #define SIUL2_DISR0_EIF13_MASK (0x2000U) 662 #define SIUL2_DISR0_EIF13_SHIFT (13U) 663 #define SIUL2_DISR0_EIF13_WIDTH (1U) 664 #define SIUL2_DISR0_EIF13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF13_SHIFT)) & SIUL2_DISR0_EIF13_MASK) 665 666 #define SIUL2_DISR0_EIF14_MASK (0x4000U) 667 #define SIUL2_DISR0_EIF14_SHIFT (14U) 668 #define SIUL2_DISR0_EIF14_WIDTH (1U) 669 #define SIUL2_DISR0_EIF14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF14_SHIFT)) & SIUL2_DISR0_EIF14_MASK) 670 671 #define SIUL2_DISR0_EIF15_MASK (0x8000U) 672 #define SIUL2_DISR0_EIF15_SHIFT (15U) 673 #define SIUL2_DISR0_EIF15_WIDTH (1U) 674 #define SIUL2_DISR0_EIF15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF15_SHIFT)) & SIUL2_DISR0_EIF15_MASK) 675 676 #define SIUL2_DISR0_EIF16_MASK (0x10000U) 677 #define SIUL2_DISR0_EIF16_SHIFT (16U) 678 #define SIUL2_DISR0_EIF16_WIDTH (1U) 679 #define SIUL2_DISR0_EIF16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF16_SHIFT)) & SIUL2_DISR0_EIF16_MASK) 680 681 #define SIUL2_DISR0_EIF17_MASK (0x20000U) 682 #define SIUL2_DISR0_EIF17_SHIFT (17U) 683 #define SIUL2_DISR0_EIF17_WIDTH (1U) 684 #define SIUL2_DISR0_EIF17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF17_SHIFT)) & SIUL2_DISR0_EIF17_MASK) 685 686 #define SIUL2_DISR0_EIF18_MASK (0x40000U) 687 #define SIUL2_DISR0_EIF18_SHIFT (18U) 688 #define SIUL2_DISR0_EIF18_WIDTH (1U) 689 #define SIUL2_DISR0_EIF18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF18_SHIFT)) & SIUL2_DISR0_EIF18_MASK) 690 691 #define SIUL2_DISR0_EIF19_MASK (0x80000U) 692 #define SIUL2_DISR0_EIF19_SHIFT (19U) 693 #define SIUL2_DISR0_EIF19_WIDTH (1U) 694 #define SIUL2_DISR0_EIF19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DISR0_EIF19_SHIFT)) & SIUL2_DISR0_EIF19_MASK) 695 /*! @} */ 696 697 /*! @name DIRER0 - SIUL2 DMA/Interrupt Request Enable Register0 */ 698 /*! @{ */ 699 700 #define SIUL2_DIRER0_EIRE0_MASK (0x1U) 701 #define SIUL2_DIRER0_EIRE0_SHIFT (0U) 702 #define SIUL2_DIRER0_EIRE0_WIDTH (1U) 703 #define SIUL2_DIRER0_EIRE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE0_SHIFT)) & SIUL2_DIRER0_EIRE0_MASK) 704 705 #define SIUL2_DIRER0_EIRE1_MASK (0x2U) 706 #define SIUL2_DIRER0_EIRE1_SHIFT (1U) 707 #define SIUL2_DIRER0_EIRE1_WIDTH (1U) 708 #define SIUL2_DIRER0_EIRE1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE1_SHIFT)) & SIUL2_DIRER0_EIRE1_MASK) 709 710 #define SIUL2_DIRER0_EIRE2_MASK (0x4U) 711 #define SIUL2_DIRER0_EIRE2_SHIFT (2U) 712 #define SIUL2_DIRER0_EIRE2_WIDTH (1U) 713 #define SIUL2_DIRER0_EIRE2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE2_SHIFT)) & SIUL2_DIRER0_EIRE2_MASK) 714 715 #define SIUL2_DIRER0_EIRE3_MASK (0x8U) 716 #define SIUL2_DIRER0_EIRE3_SHIFT (3U) 717 #define SIUL2_DIRER0_EIRE3_WIDTH (1U) 718 #define SIUL2_DIRER0_EIRE3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE3_SHIFT)) & SIUL2_DIRER0_EIRE3_MASK) 719 720 #define SIUL2_DIRER0_EIRE4_MASK (0x10U) 721 #define SIUL2_DIRER0_EIRE4_SHIFT (4U) 722 #define SIUL2_DIRER0_EIRE4_WIDTH (1U) 723 #define SIUL2_DIRER0_EIRE4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE4_SHIFT)) & SIUL2_DIRER0_EIRE4_MASK) 724 725 #define SIUL2_DIRER0_EIRE5_MASK (0x20U) 726 #define SIUL2_DIRER0_EIRE5_SHIFT (5U) 727 #define SIUL2_DIRER0_EIRE5_WIDTH (1U) 728 #define SIUL2_DIRER0_EIRE5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE5_SHIFT)) & SIUL2_DIRER0_EIRE5_MASK) 729 730 #define SIUL2_DIRER0_EIRE6_MASK (0x40U) 731 #define SIUL2_DIRER0_EIRE6_SHIFT (6U) 732 #define SIUL2_DIRER0_EIRE6_WIDTH (1U) 733 #define SIUL2_DIRER0_EIRE6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE6_SHIFT)) & SIUL2_DIRER0_EIRE6_MASK) 734 735 #define SIUL2_DIRER0_EIRE7_MASK (0x80U) 736 #define SIUL2_DIRER0_EIRE7_SHIFT (7U) 737 #define SIUL2_DIRER0_EIRE7_WIDTH (1U) 738 #define SIUL2_DIRER0_EIRE7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE7_SHIFT)) & SIUL2_DIRER0_EIRE7_MASK) 739 740 #define SIUL2_DIRER0_EIRE8_MASK (0x100U) 741 #define SIUL2_DIRER0_EIRE8_SHIFT (8U) 742 #define SIUL2_DIRER0_EIRE8_WIDTH (1U) 743 #define SIUL2_DIRER0_EIRE8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE8_SHIFT)) & SIUL2_DIRER0_EIRE8_MASK) 744 745 #define SIUL2_DIRER0_EIRE9_MASK (0x200U) 746 #define SIUL2_DIRER0_EIRE9_SHIFT (9U) 747 #define SIUL2_DIRER0_EIRE9_WIDTH (1U) 748 #define SIUL2_DIRER0_EIRE9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE9_SHIFT)) & SIUL2_DIRER0_EIRE9_MASK) 749 750 #define SIUL2_DIRER0_EIRE10_MASK (0x400U) 751 #define SIUL2_DIRER0_EIRE10_SHIFT (10U) 752 #define SIUL2_DIRER0_EIRE10_WIDTH (1U) 753 #define SIUL2_DIRER0_EIRE10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE10_SHIFT)) & SIUL2_DIRER0_EIRE10_MASK) 754 755 #define SIUL2_DIRER0_EIRE11_MASK (0x800U) 756 #define SIUL2_DIRER0_EIRE11_SHIFT (11U) 757 #define SIUL2_DIRER0_EIRE11_WIDTH (1U) 758 #define SIUL2_DIRER0_EIRE11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE11_SHIFT)) & SIUL2_DIRER0_EIRE11_MASK) 759 760 #define SIUL2_DIRER0_EIRE12_MASK (0x1000U) 761 #define SIUL2_DIRER0_EIRE12_SHIFT (12U) 762 #define SIUL2_DIRER0_EIRE12_WIDTH (1U) 763 #define SIUL2_DIRER0_EIRE12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE12_SHIFT)) & SIUL2_DIRER0_EIRE12_MASK) 764 765 #define SIUL2_DIRER0_EIRE13_MASK (0x2000U) 766 #define SIUL2_DIRER0_EIRE13_SHIFT (13U) 767 #define SIUL2_DIRER0_EIRE13_WIDTH (1U) 768 #define SIUL2_DIRER0_EIRE13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE13_SHIFT)) & SIUL2_DIRER0_EIRE13_MASK) 769 770 #define SIUL2_DIRER0_EIRE14_MASK (0x4000U) 771 #define SIUL2_DIRER0_EIRE14_SHIFT (14U) 772 #define SIUL2_DIRER0_EIRE14_WIDTH (1U) 773 #define SIUL2_DIRER0_EIRE14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE14_SHIFT)) & SIUL2_DIRER0_EIRE14_MASK) 774 775 #define SIUL2_DIRER0_EIRE15_MASK (0x8000U) 776 #define SIUL2_DIRER0_EIRE15_SHIFT (15U) 777 #define SIUL2_DIRER0_EIRE15_WIDTH (1U) 778 #define SIUL2_DIRER0_EIRE15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE15_SHIFT)) & SIUL2_DIRER0_EIRE15_MASK) 779 780 #define SIUL2_DIRER0_EIRE16_MASK (0x10000U) 781 #define SIUL2_DIRER0_EIRE16_SHIFT (16U) 782 #define SIUL2_DIRER0_EIRE16_WIDTH (1U) 783 #define SIUL2_DIRER0_EIRE16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE16_SHIFT)) & SIUL2_DIRER0_EIRE16_MASK) 784 785 #define SIUL2_DIRER0_EIRE17_MASK (0x20000U) 786 #define SIUL2_DIRER0_EIRE17_SHIFT (17U) 787 #define SIUL2_DIRER0_EIRE17_WIDTH (1U) 788 #define SIUL2_DIRER0_EIRE17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE17_SHIFT)) & SIUL2_DIRER0_EIRE17_MASK) 789 790 #define SIUL2_DIRER0_EIRE18_MASK (0x40000U) 791 #define SIUL2_DIRER0_EIRE18_SHIFT (18U) 792 #define SIUL2_DIRER0_EIRE18_WIDTH (1U) 793 #define SIUL2_DIRER0_EIRE18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE18_SHIFT)) & SIUL2_DIRER0_EIRE18_MASK) 794 795 #define SIUL2_DIRER0_EIRE19_MASK (0x80000U) 796 #define SIUL2_DIRER0_EIRE19_SHIFT (19U) 797 #define SIUL2_DIRER0_EIRE19_WIDTH (1U) 798 #define SIUL2_DIRER0_EIRE19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRER0_EIRE19_SHIFT)) & SIUL2_DIRER0_EIRE19_MASK) 799 /*! @} */ 800 801 /*! @name DIRSR0 - SIUL2 DMA/Interrupt Request Select Register0 */ 802 /*! @{ */ 803 804 #define SIUL2_DIRSR0_DIRSR0_MASK (0x1U) 805 #define SIUL2_DIRSR0_DIRSR0_SHIFT (0U) 806 #define SIUL2_DIRSR0_DIRSR0_WIDTH (1U) 807 #define SIUL2_DIRSR0_DIRSR0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR0_SHIFT)) & SIUL2_DIRSR0_DIRSR0_MASK) 808 809 #define SIUL2_DIRSR0_DIRSR1_MASK (0x2U) 810 #define SIUL2_DIRSR0_DIRSR1_SHIFT (1U) 811 #define SIUL2_DIRSR0_DIRSR1_WIDTH (1U) 812 #define SIUL2_DIRSR0_DIRSR1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR1_SHIFT)) & SIUL2_DIRSR0_DIRSR1_MASK) 813 814 #define SIUL2_DIRSR0_DIRSR2_MASK (0x4U) 815 #define SIUL2_DIRSR0_DIRSR2_SHIFT (2U) 816 #define SIUL2_DIRSR0_DIRSR2_WIDTH (1U) 817 #define SIUL2_DIRSR0_DIRSR2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR2_SHIFT)) & SIUL2_DIRSR0_DIRSR2_MASK) 818 819 #define SIUL2_DIRSR0_DIRSR3_MASK (0x8U) 820 #define SIUL2_DIRSR0_DIRSR3_SHIFT (3U) 821 #define SIUL2_DIRSR0_DIRSR3_WIDTH (1U) 822 #define SIUL2_DIRSR0_DIRSR3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR3_SHIFT)) & SIUL2_DIRSR0_DIRSR3_MASK) 823 824 #define SIUL2_DIRSR0_DIRSR4_MASK (0x10U) 825 #define SIUL2_DIRSR0_DIRSR4_SHIFT (4U) 826 #define SIUL2_DIRSR0_DIRSR4_WIDTH (1U) 827 #define SIUL2_DIRSR0_DIRSR4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR4_SHIFT)) & SIUL2_DIRSR0_DIRSR4_MASK) 828 829 #define SIUL2_DIRSR0_DIRSR5_MASK (0x20U) 830 #define SIUL2_DIRSR0_DIRSR5_SHIFT (5U) 831 #define SIUL2_DIRSR0_DIRSR5_WIDTH (1U) 832 #define SIUL2_DIRSR0_DIRSR5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR5_SHIFT)) & SIUL2_DIRSR0_DIRSR5_MASK) 833 834 #define SIUL2_DIRSR0_DIRSR6_MASK (0x40U) 835 #define SIUL2_DIRSR0_DIRSR6_SHIFT (6U) 836 #define SIUL2_DIRSR0_DIRSR6_WIDTH (1U) 837 #define SIUL2_DIRSR0_DIRSR6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR6_SHIFT)) & SIUL2_DIRSR0_DIRSR6_MASK) 838 839 #define SIUL2_DIRSR0_DIRSR7_MASK (0x80U) 840 #define SIUL2_DIRSR0_DIRSR7_SHIFT (7U) 841 #define SIUL2_DIRSR0_DIRSR7_WIDTH (1U) 842 #define SIUL2_DIRSR0_DIRSR7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR7_SHIFT)) & SIUL2_DIRSR0_DIRSR7_MASK) 843 844 #define SIUL2_DIRSR0_DIRSR8_MASK (0x100U) 845 #define SIUL2_DIRSR0_DIRSR8_SHIFT (8U) 846 #define SIUL2_DIRSR0_DIRSR8_WIDTH (1U) 847 #define SIUL2_DIRSR0_DIRSR8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR8_SHIFT)) & SIUL2_DIRSR0_DIRSR8_MASK) 848 849 #define SIUL2_DIRSR0_DIRSR9_MASK (0x200U) 850 #define SIUL2_DIRSR0_DIRSR9_SHIFT (9U) 851 #define SIUL2_DIRSR0_DIRSR9_WIDTH (1U) 852 #define SIUL2_DIRSR0_DIRSR9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR9_SHIFT)) & SIUL2_DIRSR0_DIRSR9_MASK) 853 854 #define SIUL2_DIRSR0_DIRSR10_MASK (0x400U) 855 #define SIUL2_DIRSR0_DIRSR10_SHIFT (10U) 856 #define SIUL2_DIRSR0_DIRSR10_WIDTH (1U) 857 #define SIUL2_DIRSR0_DIRSR10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR10_SHIFT)) & SIUL2_DIRSR0_DIRSR10_MASK) 858 859 #define SIUL2_DIRSR0_DIRSR11_MASK (0x800U) 860 #define SIUL2_DIRSR0_DIRSR11_SHIFT (11U) 861 #define SIUL2_DIRSR0_DIRSR11_WIDTH (1U) 862 #define SIUL2_DIRSR0_DIRSR11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR11_SHIFT)) & SIUL2_DIRSR0_DIRSR11_MASK) 863 864 #define SIUL2_DIRSR0_DIRSR12_MASK (0x1000U) 865 #define SIUL2_DIRSR0_DIRSR12_SHIFT (12U) 866 #define SIUL2_DIRSR0_DIRSR12_WIDTH (1U) 867 #define SIUL2_DIRSR0_DIRSR12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR12_SHIFT)) & SIUL2_DIRSR0_DIRSR12_MASK) 868 869 #define SIUL2_DIRSR0_DIRSR13_MASK (0x2000U) 870 #define SIUL2_DIRSR0_DIRSR13_SHIFT (13U) 871 #define SIUL2_DIRSR0_DIRSR13_WIDTH (1U) 872 #define SIUL2_DIRSR0_DIRSR13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR13_SHIFT)) & SIUL2_DIRSR0_DIRSR13_MASK) 873 874 #define SIUL2_DIRSR0_DIRSR14_MASK (0x4000U) 875 #define SIUL2_DIRSR0_DIRSR14_SHIFT (14U) 876 #define SIUL2_DIRSR0_DIRSR14_WIDTH (1U) 877 #define SIUL2_DIRSR0_DIRSR14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR14_SHIFT)) & SIUL2_DIRSR0_DIRSR14_MASK) 878 879 #define SIUL2_DIRSR0_DIRSR15_MASK (0x8000U) 880 #define SIUL2_DIRSR0_DIRSR15_SHIFT (15U) 881 #define SIUL2_DIRSR0_DIRSR15_WIDTH (1U) 882 #define SIUL2_DIRSR0_DIRSR15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR15_SHIFT)) & SIUL2_DIRSR0_DIRSR15_MASK) 883 884 #define SIUL2_DIRSR0_DIRSR16_MASK (0x10000U) 885 #define SIUL2_DIRSR0_DIRSR16_SHIFT (16U) 886 #define SIUL2_DIRSR0_DIRSR16_WIDTH (1U) 887 #define SIUL2_DIRSR0_DIRSR16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR16_SHIFT)) & SIUL2_DIRSR0_DIRSR16_MASK) 888 889 #define SIUL2_DIRSR0_DIRSR17_MASK (0x20000U) 890 #define SIUL2_DIRSR0_DIRSR17_SHIFT (17U) 891 #define SIUL2_DIRSR0_DIRSR17_WIDTH (1U) 892 #define SIUL2_DIRSR0_DIRSR17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR17_SHIFT)) & SIUL2_DIRSR0_DIRSR17_MASK) 893 894 #define SIUL2_DIRSR0_DIRSR18_MASK (0x40000U) 895 #define SIUL2_DIRSR0_DIRSR18_SHIFT (18U) 896 #define SIUL2_DIRSR0_DIRSR18_WIDTH (1U) 897 #define SIUL2_DIRSR0_DIRSR18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR18_SHIFT)) & SIUL2_DIRSR0_DIRSR18_MASK) 898 899 #define SIUL2_DIRSR0_DIRSR19_MASK (0x80000U) 900 #define SIUL2_DIRSR0_DIRSR19_SHIFT (19U) 901 #define SIUL2_DIRSR0_DIRSR19_WIDTH (1U) 902 #define SIUL2_DIRSR0_DIRSR19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_DIRSR0_DIRSR19_SHIFT)) & SIUL2_DIRSR0_DIRSR19_MASK) 903 /*! @} */ 904 905 /*! @name IREER0 - SIUL2 Interrupt Rising-Edge Event Enable Register 0 */ 906 /*! @{ */ 907 908 #define SIUL2_IREER0_IREE0_MASK (0x1U) 909 #define SIUL2_IREER0_IREE0_SHIFT (0U) 910 #define SIUL2_IREER0_IREE0_WIDTH (1U) 911 #define SIUL2_IREER0_IREE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE0_SHIFT)) & SIUL2_IREER0_IREE0_MASK) 912 913 #define SIUL2_IREER0_IREE1_MASK (0x2U) 914 #define SIUL2_IREER0_IREE1_SHIFT (1U) 915 #define SIUL2_IREER0_IREE1_WIDTH (1U) 916 #define SIUL2_IREER0_IREE1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE1_SHIFT)) & SIUL2_IREER0_IREE1_MASK) 917 918 #define SIUL2_IREER0_IREE2_MASK (0x4U) 919 #define SIUL2_IREER0_IREE2_SHIFT (2U) 920 #define SIUL2_IREER0_IREE2_WIDTH (1U) 921 #define SIUL2_IREER0_IREE2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE2_SHIFT)) & SIUL2_IREER0_IREE2_MASK) 922 923 #define SIUL2_IREER0_IREE3_MASK (0x8U) 924 #define SIUL2_IREER0_IREE3_SHIFT (3U) 925 #define SIUL2_IREER0_IREE3_WIDTH (1U) 926 #define SIUL2_IREER0_IREE3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE3_SHIFT)) & SIUL2_IREER0_IREE3_MASK) 927 928 #define SIUL2_IREER0_IREE4_MASK (0x10U) 929 #define SIUL2_IREER0_IREE4_SHIFT (4U) 930 #define SIUL2_IREER0_IREE4_WIDTH (1U) 931 #define SIUL2_IREER0_IREE4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE4_SHIFT)) & SIUL2_IREER0_IREE4_MASK) 932 933 #define SIUL2_IREER0_IREE5_MASK (0x20U) 934 #define SIUL2_IREER0_IREE5_SHIFT (5U) 935 #define SIUL2_IREER0_IREE5_WIDTH (1U) 936 #define SIUL2_IREER0_IREE5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE5_SHIFT)) & SIUL2_IREER0_IREE5_MASK) 937 938 #define SIUL2_IREER0_IREE6_MASK (0x40U) 939 #define SIUL2_IREER0_IREE6_SHIFT (6U) 940 #define SIUL2_IREER0_IREE6_WIDTH (1U) 941 #define SIUL2_IREER0_IREE6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE6_SHIFT)) & SIUL2_IREER0_IREE6_MASK) 942 943 #define SIUL2_IREER0_IREE7_MASK (0x80U) 944 #define SIUL2_IREER0_IREE7_SHIFT (7U) 945 #define SIUL2_IREER0_IREE7_WIDTH (1U) 946 #define SIUL2_IREER0_IREE7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE7_SHIFT)) & SIUL2_IREER0_IREE7_MASK) 947 948 #define SIUL2_IREER0_IREE8_MASK (0x100U) 949 #define SIUL2_IREER0_IREE8_SHIFT (8U) 950 #define SIUL2_IREER0_IREE8_WIDTH (1U) 951 #define SIUL2_IREER0_IREE8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE8_SHIFT)) & SIUL2_IREER0_IREE8_MASK) 952 953 #define SIUL2_IREER0_IREE9_MASK (0x200U) 954 #define SIUL2_IREER0_IREE9_SHIFT (9U) 955 #define SIUL2_IREER0_IREE9_WIDTH (1U) 956 #define SIUL2_IREER0_IREE9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE9_SHIFT)) & SIUL2_IREER0_IREE9_MASK) 957 958 #define SIUL2_IREER0_IREE10_MASK (0x400U) 959 #define SIUL2_IREER0_IREE10_SHIFT (10U) 960 #define SIUL2_IREER0_IREE10_WIDTH (1U) 961 #define SIUL2_IREER0_IREE10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE10_SHIFT)) & SIUL2_IREER0_IREE10_MASK) 962 963 #define SIUL2_IREER0_IREE11_MASK (0x800U) 964 #define SIUL2_IREER0_IREE11_SHIFT (11U) 965 #define SIUL2_IREER0_IREE11_WIDTH (1U) 966 #define SIUL2_IREER0_IREE11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE11_SHIFT)) & SIUL2_IREER0_IREE11_MASK) 967 968 #define SIUL2_IREER0_IREE12_MASK (0x1000U) 969 #define SIUL2_IREER0_IREE12_SHIFT (12U) 970 #define SIUL2_IREER0_IREE12_WIDTH (1U) 971 #define SIUL2_IREER0_IREE12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE12_SHIFT)) & SIUL2_IREER0_IREE12_MASK) 972 973 #define SIUL2_IREER0_IREE13_MASK (0x2000U) 974 #define SIUL2_IREER0_IREE13_SHIFT (13U) 975 #define SIUL2_IREER0_IREE13_WIDTH (1U) 976 #define SIUL2_IREER0_IREE13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE13_SHIFT)) & SIUL2_IREER0_IREE13_MASK) 977 978 #define SIUL2_IREER0_IREE14_MASK (0x4000U) 979 #define SIUL2_IREER0_IREE14_SHIFT (14U) 980 #define SIUL2_IREER0_IREE14_WIDTH (1U) 981 #define SIUL2_IREER0_IREE14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE14_SHIFT)) & SIUL2_IREER0_IREE14_MASK) 982 983 #define SIUL2_IREER0_IREE15_MASK (0x8000U) 984 #define SIUL2_IREER0_IREE15_SHIFT (15U) 985 #define SIUL2_IREER0_IREE15_WIDTH (1U) 986 #define SIUL2_IREER0_IREE15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE15_SHIFT)) & SIUL2_IREER0_IREE15_MASK) 987 988 #define SIUL2_IREER0_IREE16_MASK (0x10000U) 989 #define SIUL2_IREER0_IREE16_SHIFT (16U) 990 #define SIUL2_IREER0_IREE16_WIDTH (1U) 991 #define SIUL2_IREER0_IREE16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE16_SHIFT)) & SIUL2_IREER0_IREE16_MASK) 992 993 #define SIUL2_IREER0_IREE17_MASK (0x20000U) 994 #define SIUL2_IREER0_IREE17_SHIFT (17U) 995 #define SIUL2_IREER0_IREE17_WIDTH (1U) 996 #define SIUL2_IREER0_IREE17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE17_SHIFT)) & SIUL2_IREER0_IREE17_MASK) 997 998 #define SIUL2_IREER0_IREE18_MASK (0x40000U) 999 #define SIUL2_IREER0_IREE18_SHIFT (18U) 1000 #define SIUL2_IREER0_IREE18_WIDTH (1U) 1001 #define SIUL2_IREER0_IREE18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE18_SHIFT)) & SIUL2_IREER0_IREE18_MASK) 1002 1003 #define SIUL2_IREER0_IREE19_MASK (0x80000U) 1004 #define SIUL2_IREER0_IREE19_SHIFT (19U) 1005 #define SIUL2_IREER0_IREE19_WIDTH (1U) 1006 #define SIUL2_IREER0_IREE19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IREER0_IREE19_SHIFT)) & SIUL2_IREER0_IREE19_MASK) 1007 /*! @} */ 1008 1009 /*! @name IFEER0 - SIUL2 Interrupt Falling-Edge Event Enable Register 0 */ 1010 /*! @{ */ 1011 1012 #define SIUL2_IFEER0_IFEE0_MASK (0x1U) 1013 #define SIUL2_IFEER0_IFEE0_SHIFT (0U) 1014 #define SIUL2_IFEER0_IFEE0_WIDTH (1U) 1015 #define SIUL2_IFEER0_IFEE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE0_SHIFT)) & SIUL2_IFEER0_IFEE0_MASK) 1016 1017 #define SIUL2_IFEER0_IFEE1_MASK (0x2U) 1018 #define SIUL2_IFEER0_IFEE1_SHIFT (1U) 1019 #define SIUL2_IFEER0_IFEE1_WIDTH (1U) 1020 #define SIUL2_IFEER0_IFEE1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE1_SHIFT)) & SIUL2_IFEER0_IFEE1_MASK) 1021 1022 #define SIUL2_IFEER0_IFEE2_MASK (0x4U) 1023 #define SIUL2_IFEER0_IFEE2_SHIFT (2U) 1024 #define SIUL2_IFEER0_IFEE2_WIDTH (1U) 1025 #define SIUL2_IFEER0_IFEE2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE2_SHIFT)) & SIUL2_IFEER0_IFEE2_MASK) 1026 1027 #define SIUL2_IFEER0_IFEE3_MASK (0x8U) 1028 #define SIUL2_IFEER0_IFEE3_SHIFT (3U) 1029 #define SIUL2_IFEER0_IFEE3_WIDTH (1U) 1030 #define SIUL2_IFEER0_IFEE3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE3_SHIFT)) & SIUL2_IFEER0_IFEE3_MASK) 1031 1032 #define SIUL2_IFEER0_IFEE4_MASK (0x10U) 1033 #define SIUL2_IFEER0_IFEE4_SHIFT (4U) 1034 #define SIUL2_IFEER0_IFEE4_WIDTH (1U) 1035 #define SIUL2_IFEER0_IFEE4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE4_SHIFT)) & SIUL2_IFEER0_IFEE4_MASK) 1036 1037 #define SIUL2_IFEER0_IFEE5_MASK (0x20U) 1038 #define SIUL2_IFEER0_IFEE5_SHIFT (5U) 1039 #define SIUL2_IFEER0_IFEE5_WIDTH (1U) 1040 #define SIUL2_IFEER0_IFEE5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE5_SHIFT)) & SIUL2_IFEER0_IFEE5_MASK) 1041 1042 #define SIUL2_IFEER0_IFEE6_MASK (0x40U) 1043 #define SIUL2_IFEER0_IFEE6_SHIFT (6U) 1044 #define SIUL2_IFEER0_IFEE6_WIDTH (1U) 1045 #define SIUL2_IFEER0_IFEE6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE6_SHIFT)) & SIUL2_IFEER0_IFEE6_MASK) 1046 1047 #define SIUL2_IFEER0_IFEE7_MASK (0x80U) 1048 #define SIUL2_IFEER0_IFEE7_SHIFT (7U) 1049 #define SIUL2_IFEER0_IFEE7_WIDTH (1U) 1050 #define SIUL2_IFEER0_IFEE7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE7_SHIFT)) & SIUL2_IFEER0_IFEE7_MASK) 1051 1052 #define SIUL2_IFEER0_IFEE8_MASK (0x100U) 1053 #define SIUL2_IFEER0_IFEE8_SHIFT (8U) 1054 #define SIUL2_IFEER0_IFEE8_WIDTH (1U) 1055 #define SIUL2_IFEER0_IFEE8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE8_SHIFT)) & SIUL2_IFEER0_IFEE8_MASK) 1056 1057 #define SIUL2_IFEER0_IFEE9_MASK (0x200U) 1058 #define SIUL2_IFEER0_IFEE9_SHIFT (9U) 1059 #define SIUL2_IFEER0_IFEE9_WIDTH (1U) 1060 #define SIUL2_IFEER0_IFEE9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE9_SHIFT)) & SIUL2_IFEER0_IFEE9_MASK) 1061 1062 #define SIUL2_IFEER0_IFEE10_MASK (0x400U) 1063 #define SIUL2_IFEER0_IFEE10_SHIFT (10U) 1064 #define SIUL2_IFEER0_IFEE10_WIDTH (1U) 1065 #define SIUL2_IFEER0_IFEE10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE10_SHIFT)) & SIUL2_IFEER0_IFEE10_MASK) 1066 1067 #define SIUL2_IFEER0_IFEE11_MASK (0x800U) 1068 #define SIUL2_IFEER0_IFEE11_SHIFT (11U) 1069 #define SIUL2_IFEER0_IFEE11_WIDTH (1U) 1070 #define SIUL2_IFEER0_IFEE11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE11_SHIFT)) & SIUL2_IFEER0_IFEE11_MASK) 1071 1072 #define SIUL2_IFEER0_IFEE12_MASK (0x1000U) 1073 #define SIUL2_IFEER0_IFEE12_SHIFT (12U) 1074 #define SIUL2_IFEER0_IFEE12_WIDTH (1U) 1075 #define SIUL2_IFEER0_IFEE12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE12_SHIFT)) & SIUL2_IFEER0_IFEE12_MASK) 1076 1077 #define SIUL2_IFEER0_IFEE13_MASK (0x2000U) 1078 #define SIUL2_IFEER0_IFEE13_SHIFT (13U) 1079 #define SIUL2_IFEER0_IFEE13_WIDTH (1U) 1080 #define SIUL2_IFEER0_IFEE13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE13_SHIFT)) & SIUL2_IFEER0_IFEE13_MASK) 1081 1082 #define SIUL2_IFEER0_IFEE14_MASK (0x4000U) 1083 #define SIUL2_IFEER0_IFEE14_SHIFT (14U) 1084 #define SIUL2_IFEER0_IFEE14_WIDTH (1U) 1085 #define SIUL2_IFEER0_IFEE14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE14_SHIFT)) & SIUL2_IFEER0_IFEE14_MASK) 1086 1087 #define SIUL2_IFEER0_IFEE15_MASK (0x8000U) 1088 #define SIUL2_IFEER0_IFEE15_SHIFT (15U) 1089 #define SIUL2_IFEER0_IFEE15_WIDTH (1U) 1090 #define SIUL2_IFEER0_IFEE15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE15_SHIFT)) & SIUL2_IFEER0_IFEE15_MASK) 1091 1092 #define SIUL2_IFEER0_IFEE16_MASK (0x10000U) 1093 #define SIUL2_IFEER0_IFEE16_SHIFT (16U) 1094 #define SIUL2_IFEER0_IFEE16_WIDTH (1U) 1095 #define SIUL2_IFEER0_IFEE16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE16_SHIFT)) & SIUL2_IFEER0_IFEE16_MASK) 1096 1097 #define SIUL2_IFEER0_IFEE17_MASK (0x20000U) 1098 #define SIUL2_IFEER0_IFEE17_SHIFT (17U) 1099 #define SIUL2_IFEER0_IFEE17_WIDTH (1U) 1100 #define SIUL2_IFEER0_IFEE17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE17_SHIFT)) & SIUL2_IFEER0_IFEE17_MASK) 1101 1102 #define SIUL2_IFEER0_IFEE18_MASK (0x40000U) 1103 #define SIUL2_IFEER0_IFEE18_SHIFT (18U) 1104 #define SIUL2_IFEER0_IFEE18_WIDTH (1U) 1105 #define SIUL2_IFEER0_IFEE18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE18_SHIFT)) & SIUL2_IFEER0_IFEE18_MASK) 1106 1107 #define SIUL2_IFEER0_IFEE19_MASK (0x80000U) 1108 #define SIUL2_IFEER0_IFEE19_SHIFT (19U) 1109 #define SIUL2_IFEER0_IFEE19_WIDTH (1U) 1110 #define SIUL2_IFEER0_IFEE19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFEER0_IFEE19_SHIFT)) & SIUL2_IFEER0_IFEE19_MASK) 1111 /*! @} */ 1112 1113 /*! @name IFER0 - SIUL2 Interrupt Filter Enable Register 0 */ 1114 /*! @{ */ 1115 1116 #define SIUL2_IFER0_IFE0_MASK (0x1U) 1117 #define SIUL2_IFER0_IFE0_SHIFT (0U) 1118 #define SIUL2_IFER0_IFE0_WIDTH (1U) 1119 #define SIUL2_IFER0_IFE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE0_SHIFT)) & SIUL2_IFER0_IFE0_MASK) 1120 1121 #define SIUL2_IFER0_IFE1_MASK (0x2U) 1122 #define SIUL2_IFER0_IFE1_SHIFT (1U) 1123 #define SIUL2_IFER0_IFE1_WIDTH (1U) 1124 #define SIUL2_IFER0_IFE1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE1_SHIFT)) & SIUL2_IFER0_IFE1_MASK) 1125 1126 #define SIUL2_IFER0_IFE2_MASK (0x4U) 1127 #define SIUL2_IFER0_IFE2_SHIFT (2U) 1128 #define SIUL2_IFER0_IFE2_WIDTH (1U) 1129 #define SIUL2_IFER0_IFE2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE2_SHIFT)) & SIUL2_IFER0_IFE2_MASK) 1130 1131 #define SIUL2_IFER0_IFE3_MASK (0x8U) 1132 #define SIUL2_IFER0_IFE3_SHIFT (3U) 1133 #define SIUL2_IFER0_IFE3_WIDTH (1U) 1134 #define SIUL2_IFER0_IFE3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE3_SHIFT)) & SIUL2_IFER0_IFE3_MASK) 1135 1136 #define SIUL2_IFER0_IFE4_MASK (0x10U) 1137 #define SIUL2_IFER0_IFE4_SHIFT (4U) 1138 #define SIUL2_IFER0_IFE4_WIDTH (1U) 1139 #define SIUL2_IFER0_IFE4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE4_SHIFT)) & SIUL2_IFER0_IFE4_MASK) 1140 1141 #define SIUL2_IFER0_IFE5_MASK (0x20U) 1142 #define SIUL2_IFER0_IFE5_SHIFT (5U) 1143 #define SIUL2_IFER0_IFE5_WIDTH (1U) 1144 #define SIUL2_IFER0_IFE5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE5_SHIFT)) & SIUL2_IFER0_IFE5_MASK) 1145 1146 #define SIUL2_IFER0_IFE6_MASK (0x40U) 1147 #define SIUL2_IFER0_IFE6_SHIFT (6U) 1148 #define SIUL2_IFER0_IFE6_WIDTH (1U) 1149 #define SIUL2_IFER0_IFE6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE6_SHIFT)) & SIUL2_IFER0_IFE6_MASK) 1150 1151 #define SIUL2_IFER0_IFE7_MASK (0x80U) 1152 #define SIUL2_IFER0_IFE7_SHIFT (7U) 1153 #define SIUL2_IFER0_IFE7_WIDTH (1U) 1154 #define SIUL2_IFER0_IFE7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE7_SHIFT)) & SIUL2_IFER0_IFE7_MASK) 1155 1156 #define SIUL2_IFER0_IFE8_MASK (0x100U) 1157 #define SIUL2_IFER0_IFE8_SHIFT (8U) 1158 #define SIUL2_IFER0_IFE8_WIDTH (1U) 1159 #define SIUL2_IFER0_IFE8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE8_SHIFT)) & SIUL2_IFER0_IFE8_MASK) 1160 1161 #define SIUL2_IFER0_IFE9_MASK (0x200U) 1162 #define SIUL2_IFER0_IFE9_SHIFT (9U) 1163 #define SIUL2_IFER0_IFE9_WIDTH (1U) 1164 #define SIUL2_IFER0_IFE9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE9_SHIFT)) & SIUL2_IFER0_IFE9_MASK) 1165 1166 #define SIUL2_IFER0_IFE10_MASK (0x400U) 1167 #define SIUL2_IFER0_IFE10_SHIFT (10U) 1168 #define SIUL2_IFER0_IFE10_WIDTH (1U) 1169 #define SIUL2_IFER0_IFE10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE10_SHIFT)) & SIUL2_IFER0_IFE10_MASK) 1170 1171 #define SIUL2_IFER0_IFE11_MASK (0x800U) 1172 #define SIUL2_IFER0_IFE11_SHIFT (11U) 1173 #define SIUL2_IFER0_IFE11_WIDTH (1U) 1174 #define SIUL2_IFER0_IFE11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE11_SHIFT)) & SIUL2_IFER0_IFE11_MASK) 1175 1176 #define SIUL2_IFER0_IFE12_MASK (0x1000U) 1177 #define SIUL2_IFER0_IFE12_SHIFT (12U) 1178 #define SIUL2_IFER0_IFE12_WIDTH (1U) 1179 #define SIUL2_IFER0_IFE12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE12_SHIFT)) & SIUL2_IFER0_IFE12_MASK) 1180 1181 #define SIUL2_IFER0_IFE13_MASK (0x2000U) 1182 #define SIUL2_IFER0_IFE13_SHIFT (13U) 1183 #define SIUL2_IFER0_IFE13_WIDTH (1U) 1184 #define SIUL2_IFER0_IFE13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE13_SHIFT)) & SIUL2_IFER0_IFE13_MASK) 1185 1186 #define SIUL2_IFER0_IFE14_MASK (0x4000U) 1187 #define SIUL2_IFER0_IFE14_SHIFT (14U) 1188 #define SIUL2_IFER0_IFE14_WIDTH (1U) 1189 #define SIUL2_IFER0_IFE14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE14_SHIFT)) & SIUL2_IFER0_IFE14_MASK) 1190 1191 #define SIUL2_IFER0_IFE15_MASK (0x8000U) 1192 #define SIUL2_IFER0_IFE15_SHIFT (15U) 1193 #define SIUL2_IFER0_IFE15_WIDTH (1U) 1194 #define SIUL2_IFER0_IFE15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE15_SHIFT)) & SIUL2_IFER0_IFE15_MASK) 1195 1196 #define SIUL2_IFER0_IFE16_MASK (0x10000U) 1197 #define SIUL2_IFER0_IFE16_SHIFT (16U) 1198 #define SIUL2_IFER0_IFE16_WIDTH (1U) 1199 #define SIUL2_IFER0_IFE16(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE16_SHIFT)) & SIUL2_IFER0_IFE16_MASK) 1200 1201 #define SIUL2_IFER0_IFE17_MASK (0x20000U) 1202 #define SIUL2_IFER0_IFE17_SHIFT (17U) 1203 #define SIUL2_IFER0_IFE17_WIDTH (1U) 1204 #define SIUL2_IFER0_IFE17(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE17_SHIFT)) & SIUL2_IFER0_IFE17_MASK) 1205 1206 #define SIUL2_IFER0_IFE18_MASK (0x40000U) 1207 #define SIUL2_IFER0_IFE18_SHIFT (18U) 1208 #define SIUL2_IFER0_IFE18_WIDTH (1U) 1209 #define SIUL2_IFER0_IFE18(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE18_SHIFT)) & SIUL2_IFER0_IFE18_MASK) 1210 1211 #define SIUL2_IFER0_IFE19_MASK (0x80000U) 1212 #define SIUL2_IFER0_IFE19_SHIFT (19U) 1213 #define SIUL2_IFER0_IFE19_WIDTH (1U) 1214 #define SIUL2_IFER0_IFE19(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFER0_IFE19_SHIFT)) & SIUL2_IFER0_IFE19_MASK) 1215 /*! @} */ 1216 1217 /*! @name IFMCR - SIUL2 Interrupt Filter Maximum Counter Register */ 1218 /*! @{ */ 1219 1220 #define SIUL2_IFMCR_MAXCNT_MASK (0xFU) 1221 #define SIUL2_IFMCR_MAXCNT_SHIFT (0U) 1222 #define SIUL2_IFMCR_MAXCNT_WIDTH (4U) 1223 #define SIUL2_IFMCR_MAXCNT(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFMCR_MAXCNT_SHIFT)) & SIUL2_IFMCR_MAXCNT_MASK) 1224 /*! @} */ 1225 1226 /*! @name IFCPR - SIUL2 Interrupt Filter Clock Prescaler Register */ 1227 /*! @{ */ 1228 1229 #define SIUL2_IFCPR_IFCP_MASK (0xFU) 1230 #define SIUL2_IFCPR_IFCP_SHIFT (0U) 1231 #define SIUL2_IFCPR_IFCP_WIDTH (4U) 1232 #define SIUL2_IFCPR_IFCP(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IFCPR_IFCP_SHIFT)) & SIUL2_IFCPR_IFCP_MASK) 1233 /*! @} */ 1234 1235 /*! @name MIDR3 - SIUL2 MCU ID Register #3 */ 1236 /*! @{ */ 1237 1238 #define SIUL2_MIDR3_SYSTEM_RAM_SIZE_MASK (0x3FU) 1239 #define SIUL2_MIDR3_SYSTEM_RAM_SIZE_SHIFT (0U) 1240 #define SIUL2_MIDR3_SYSTEM_RAM_SIZE_WIDTH (6U) 1241 #define SIUL2_MIDR3_SYSTEM_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR3_SYSTEM_RAM_SIZE_SHIFT)) & SIUL2_MIDR3_SYSTEM_RAM_SIZE_MASK) 1242 1243 #define SIUL2_MIDR3_PART_NO_LETTER_MASK (0xFC00U) 1244 #define SIUL2_MIDR3_PART_NO_LETTER_SHIFT (10U) 1245 #define SIUL2_MIDR3_PART_NO_LETTER_WIDTH (6U) 1246 #define SIUL2_MIDR3_PART_NO_LETTER(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR3_PART_NO_LETTER_SHIFT)) & SIUL2_MIDR3_PART_NO_LETTER_MASK) 1247 1248 #define SIUL2_MIDR3_PRODUCT_FAMILY_NO_MASK (0x3FF0000U) 1249 #define SIUL2_MIDR3_PRODUCT_FAMILY_NO_SHIFT (16U) 1250 #define SIUL2_MIDR3_PRODUCT_FAMILY_NO_WIDTH (10U) 1251 #define SIUL2_MIDR3_PRODUCT_FAMILY_NO(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR3_PRODUCT_FAMILY_NO_SHIFT)) & SIUL2_MIDR3_PRODUCT_FAMILY_NO_MASK) 1252 1253 #define SIUL2_MIDR3_PRODUCT_FAMILY_LETTER_MASK (0xFC000000U) 1254 #define SIUL2_MIDR3_PRODUCT_FAMILY_LETTER_SHIFT (26U) 1255 #define SIUL2_MIDR3_PRODUCT_FAMILY_LETTER_WIDTH (6U) 1256 #define SIUL2_MIDR3_PRODUCT_FAMILY_LETTER(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR3_PRODUCT_FAMILY_LETTER_SHIFT)) & SIUL2_MIDR3_PRODUCT_FAMILY_LETTER_MASK) 1257 /*! @} */ 1258 1259 /*! @name MIDR4 - SIUL2 MCU ID Register #4 */ 1260 /*! @{ */ 1261 1262 #define SIUL2_MIDR4_AE0_MASK (0x1U) 1263 #define SIUL2_MIDR4_AE0_SHIFT (0U) 1264 #define SIUL2_MIDR4_AE0_WIDTH (1U) 1265 #define SIUL2_MIDR4_AE0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_AE0_SHIFT)) & SIUL2_MIDR4_AE0_MASK) 1266 1267 #define SIUL2_MIDR4_AE_RC_MASK (0x2U) 1268 #define SIUL2_MIDR4_AE_RC_SHIFT (1U) 1269 #define SIUL2_MIDR4_AE_RC_WIDTH (1U) 1270 #define SIUL2_MIDR4_AE_RC(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_AE_RC_SHIFT)) & SIUL2_MIDR4_AE_RC_MASK) 1271 1272 #define SIUL2_MIDR4_DIP_MASK (0x4U) 1273 #define SIUL2_MIDR4_DIP_SHIFT (2U) 1274 #define SIUL2_MIDR4_DIP_WIDTH (1U) 1275 #define SIUL2_MIDR4_DIP(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_DIP_SHIFT)) & SIUL2_MIDR4_DIP_MASK) 1276 1277 #define SIUL2_MIDR4_GTM_MASK (0x200U) 1278 #define SIUL2_MIDR4_GTM_SHIFT (9U) 1279 #define SIUL2_MIDR4_GTM_WIDTH (1U) 1280 #define SIUL2_MIDR4_GTM(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_GTM_SHIFT)) & SIUL2_MIDR4_GTM_MASK) 1281 1282 #define SIUL2_MIDR4_CANXL_FUNC_MASK (0x400U) 1283 #define SIUL2_MIDR4_CANXL_FUNC_SHIFT (10U) 1284 #define SIUL2_MIDR4_CANXL_FUNC_WIDTH (1U) 1285 #define SIUL2_MIDR4_CANXL_FUNC(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_CANXL_FUNC_SHIFT)) & SIUL2_MIDR4_CANXL_FUNC_MASK) 1286 1287 #define SIUL2_MIDR4_CANXL_INST_MASK (0x800U) 1288 #define SIUL2_MIDR4_CANXL_INST_SHIFT (11U) 1289 #define SIUL2_MIDR4_CANXL_INST_WIDTH (1U) 1290 #define SIUL2_MIDR4_CANXL_INST(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_CANXL_INST_SHIFT)) & SIUL2_MIDR4_CANXL_INST_MASK) 1291 1292 #define SIUL2_MIDR4_MCP_MASK (0x1000U) 1293 #define SIUL2_MIDR4_MCP_SHIFT (12U) 1294 #define SIUL2_MIDR4_MCP_WIDTH (1U) 1295 #define SIUL2_MIDR4_MCP(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_MCP_SHIFT)) & SIUL2_MIDR4_MCP_MASK) 1296 1297 #define SIUL2_MIDR4_HPBF_MASK (0x2000U) 1298 #define SIUL2_MIDR4_HPBF_SHIFT (13U) 1299 #define SIUL2_MIDR4_HPBF_WIDTH (1U) 1300 #define SIUL2_MIDR4_HPBF(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_HPBF_SHIFT)) & SIUL2_MIDR4_HPBF_MASK) 1301 1302 #define SIUL2_MIDR4_OTA_MASK (0x4000U) 1303 #define SIUL2_MIDR4_OTA_SHIFT (14U) 1304 #define SIUL2_MIDR4_OTA_WIDTH (1U) 1305 #define SIUL2_MIDR4_OTA(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_OTA_SHIFT)) & SIUL2_MIDR4_OTA_MASK) 1306 1307 #define SIUL2_MIDR4_SERDES_MASK (0x8000U) 1308 #define SIUL2_MIDR4_SERDES_SHIFT (15U) 1309 #define SIUL2_MIDR4_SERDES_WIDTH (1U) 1310 #define SIUL2_MIDR4_SERDES(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_SERDES_SHIFT)) & SIUL2_MIDR4_SERDES_MASK) 1311 1312 #define SIUL2_MIDR4_COMPUTE_DIE_PART_NUMBER_MASK (0x3FF0000U) 1313 #define SIUL2_MIDR4_COMPUTE_DIE_PART_NUMBER_SHIFT (16U) 1314 #define SIUL2_MIDR4_COMPUTE_DIE_PART_NUMBER_WIDTH (10U) 1315 #define SIUL2_MIDR4_COMPUTE_DIE_PART_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_COMPUTE_DIE_PART_NUMBER_SHIFT)) & SIUL2_MIDR4_COMPUTE_DIE_PART_NUMBER_MASK) 1316 1317 #define SIUL2_MIDR4_FLASH_CONFIG_MASK (0x30000000U) 1318 #define SIUL2_MIDR4_FLASH_CONFIG_SHIFT (28U) 1319 #define SIUL2_MIDR4_FLASH_CONFIG_WIDTH (2U) 1320 #define SIUL2_MIDR4_FLASH_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_FLASH_CONFIG_SHIFT)) & SIUL2_MIDR4_FLASH_CONFIG_MASK) 1321 1322 #define SIUL2_MIDR4_FLASH_VENDOR_MASK (0xC0000000U) 1323 #define SIUL2_MIDR4_FLASH_VENDOR_SHIFT (30U) 1324 #define SIUL2_MIDR4_FLASH_VENDOR_WIDTH (2U) 1325 #define SIUL2_MIDR4_FLASH_VENDOR(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MIDR4_FLASH_VENDOR_SHIFT)) & SIUL2_MIDR4_FLASH_VENDOR_MASK) 1326 /*! @} */ 1327 1328 /*! @name MSCR - SIUL2 Multiplexed Signal Configuration Register */ 1329 /*! @{ */ 1330 1331 #define SIUL2_MSCR_SSS_MASK (0x7U) 1332 #define SIUL2_MSCR_SSS_SHIFT (0U) 1333 #define SIUL2_MSCR_SSS_WIDTH (3U) 1334 #define SIUL2_MSCR_SSS(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SSS_SHIFT)) & SIUL2_MSCR_SSS_MASK) 1335 1336 #define SIUL2_MSCR_SMC_MASK (0xF0U) 1337 #define SIUL2_MSCR_SMC_SHIFT (4U) 1338 #define SIUL2_MSCR_SMC_WIDTH (4U) 1339 #define SIUL2_MSCR_SMC(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SMC_SHIFT)) & SIUL2_MSCR_SMC_MASK) 1340 1341 #define SIUL2_MSCR_TRC_MASK (0x100U) 1342 #define SIUL2_MSCR_TRC_SHIFT (8U) 1343 #define SIUL2_MSCR_TRC_WIDTH (1U) 1344 #define SIUL2_MSCR_TRC(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_TRC_SHIFT)) & SIUL2_MSCR_TRC_MASK) 1345 1346 #define SIUL2_MSCR_RCVR_MASK (0x400U) 1347 #define SIUL2_MSCR_RCVR_SHIFT (10U) 1348 #define SIUL2_MSCR_RCVR_WIDTH (1U) 1349 #define SIUL2_MSCR_RCVR(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_RCVR_SHIFT)) & SIUL2_MSCR_RCVR_MASK) 1350 1351 #define SIUL2_MSCR_CREF_MASK (0x800U) 1352 #define SIUL2_MSCR_CREF_SHIFT (11U) 1353 #define SIUL2_MSCR_CREF_WIDTH (1U) 1354 #define SIUL2_MSCR_CREF(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_CREF_SHIFT)) & SIUL2_MSCR_CREF_MASK) 1355 1356 #define SIUL2_MSCR_PUS_MASK (0x1000U) 1357 #define SIUL2_MSCR_PUS_SHIFT (12U) 1358 #define SIUL2_MSCR_PUS_WIDTH (1U) 1359 #define SIUL2_MSCR_PUS(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_PUS_SHIFT)) & SIUL2_MSCR_PUS_MASK) 1360 1361 #define SIUL2_MSCR_PUE_MASK (0x2000U) 1362 #define SIUL2_MSCR_PUE_SHIFT (13U) 1363 #define SIUL2_MSCR_PUE_WIDTH (1U) 1364 #define SIUL2_MSCR_PUE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_PUE_SHIFT)) & SIUL2_MSCR_PUE_MASK) 1365 1366 #define SIUL2_MSCR_SRE_MASK (0x1C000U) 1367 #define SIUL2_MSCR_SRE_SHIFT (14U) 1368 #define SIUL2_MSCR_SRE_WIDTH (3U) 1369 #define SIUL2_MSCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SRE_SHIFT)) & SIUL2_MSCR_SRE_MASK) 1370 1371 #define SIUL2_MSCR_RXCB_MASK (0x20000U) 1372 #define SIUL2_MSCR_RXCB_SHIFT (17U) 1373 #define SIUL2_MSCR_RXCB_WIDTH (1U) 1374 #define SIUL2_MSCR_RXCB(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_RXCB_SHIFT)) & SIUL2_MSCR_RXCB_MASK) 1375 1376 #define SIUL2_MSCR_IBE_MASK (0x80000U) 1377 #define SIUL2_MSCR_IBE_SHIFT (19U) 1378 #define SIUL2_MSCR_IBE_WIDTH (1U) 1379 #define SIUL2_MSCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_IBE_SHIFT)) & SIUL2_MSCR_IBE_MASK) 1380 1381 #define SIUL2_MSCR_ODE_MASK (0x100000U) 1382 #define SIUL2_MSCR_ODE_SHIFT (20U) 1383 #define SIUL2_MSCR_ODE_WIDTH (1U) 1384 #define SIUL2_MSCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_ODE_SHIFT)) & SIUL2_MSCR_ODE_MASK) 1385 1386 #define SIUL2_MSCR_OBE_MASK (0x200000U) 1387 #define SIUL2_MSCR_OBE_SHIFT (21U) 1388 #define SIUL2_MSCR_OBE_WIDTH (1U) 1389 #define SIUL2_MSCR_OBE(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_OBE_SHIFT)) & SIUL2_MSCR_OBE_MASK) 1390 /*! @} */ 1391 1392 /*! @name IMCR - SIUL2 Input Multiplexed Signal Configuration Register */ 1393 /*! @{ */ 1394 1395 #define SIUL2_IMCR_SSS_MASK (0x7U) 1396 #define SIUL2_IMCR_SSS_SHIFT (0U) 1397 #define SIUL2_IMCR_SSS_WIDTH (3U) 1398 #define SIUL2_IMCR_SSS(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_IMCR_SSS_SHIFT)) & SIUL2_IMCR_SSS_MASK) 1399 /*! @} */ 1400 1401 /*! @name GPDO3 - SIUL2 GPIO Pad Data Output Register */ 1402 /*! @{ */ 1403 1404 #define SIUL2_GPDO3_PDO_n_MASK (0x1U) 1405 #define SIUL2_GPDO3_PDO_n_SHIFT (0U) 1406 #define SIUL2_GPDO3_PDO_n_WIDTH (1U) 1407 #define SIUL2_GPDO3_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO3_PDO_n_SHIFT)) & SIUL2_GPDO3_PDO_n_MASK) 1408 /*! @} */ 1409 1410 /*! @name GPDO2 - SIUL2 GPIO Pad Data Output Register */ 1411 /*! @{ */ 1412 1413 #define SIUL2_GPDO2_PDO_n_MASK (0x1U) 1414 #define SIUL2_GPDO2_PDO_n_SHIFT (0U) 1415 #define SIUL2_GPDO2_PDO_n_WIDTH (1U) 1416 #define SIUL2_GPDO2_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO2_PDO_n_SHIFT)) & SIUL2_GPDO2_PDO_n_MASK) 1417 /*! @} */ 1418 1419 /*! @name GPDO1 - SIUL2 GPIO Pad Data Output Register */ 1420 /*! @{ */ 1421 1422 #define SIUL2_GPDO1_PDO_n_MASK (0x1U) 1423 #define SIUL2_GPDO1_PDO_n_SHIFT (0U) 1424 #define SIUL2_GPDO1_PDO_n_WIDTH (1U) 1425 #define SIUL2_GPDO1_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO1_PDO_n_SHIFT)) & SIUL2_GPDO1_PDO_n_MASK) 1426 /*! @} */ 1427 1428 /*! @name GPDO0 - SIUL2 GPIO Pad Data Output Register */ 1429 /*! @{ */ 1430 1431 #define SIUL2_GPDO0_PDO_n_MASK (0x1U) 1432 #define SIUL2_GPDO0_PDO_n_SHIFT (0U) 1433 #define SIUL2_GPDO0_PDO_n_WIDTH (1U) 1434 #define SIUL2_GPDO0_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO0_PDO_n_SHIFT)) & SIUL2_GPDO0_PDO_n_MASK) 1435 /*! @} */ 1436 1437 /*! @name GPDO7 - SIUL2 GPIO Pad Data Output Register */ 1438 /*! @{ */ 1439 1440 #define SIUL2_GPDO7_PDO_n_MASK (0x1U) 1441 #define SIUL2_GPDO7_PDO_n_SHIFT (0U) 1442 #define SIUL2_GPDO7_PDO_n_WIDTH (1U) 1443 #define SIUL2_GPDO7_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO7_PDO_n_SHIFT)) & SIUL2_GPDO7_PDO_n_MASK) 1444 /*! @} */ 1445 1446 /*! @name GPDO6 - SIUL2 GPIO Pad Data Output Register */ 1447 /*! @{ */ 1448 1449 #define SIUL2_GPDO6_PDO_n_MASK (0x1U) 1450 #define SIUL2_GPDO6_PDO_n_SHIFT (0U) 1451 #define SIUL2_GPDO6_PDO_n_WIDTH (1U) 1452 #define SIUL2_GPDO6_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO6_PDO_n_SHIFT)) & SIUL2_GPDO6_PDO_n_MASK) 1453 /*! @} */ 1454 1455 /*! @name GPDO5 - SIUL2 GPIO Pad Data Output Register */ 1456 /*! @{ */ 1457 1458 #define SIUL2_GPDO5_PDO_n_MASK (0x1U) 1459 #define SIUL2_GPDO5_PDO_n_SHIFT (0U) 1460 #define SIUL2_GPDO5_PDO_n_WIDTH (1U) 1461 #define SIUL2_GPDO5_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO5_PDO_n_SHIFT)) & SIUL2_GPDO5_PDO_n_MASK) 1462 /*! @} */ 1463 1464 /*! @name GPDO4 - SIUL2 GPIO Pad Data Output Register */ 1465 /*! @{ */ 1466 1467 #define SIUL2_GPDO4_PDO_n_MASK (0x1U) 1468 #define SIUL2_GPDO4_PDO_n_SHIFT (0U) 1469 #define SIUL2_GPDO4_PDO_n_WIDTH (1U) 1470 #define SIUL2_GPDO4_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO4_PDO_n_SHIFT)) & SIUL2_GPDO4_PDO_n_MASK) 1471 /*! @} */ 1472 1473 /*! @name GPDO11 - SIUL2 GPIO Pad Data Output Register */ 1474 /*! @{ */ 1475 1476 #define SIUL2_GPDO11_PDO_n_MASK (0x1U) 1477 #define SIUL2_GPDO11_PDO_n_SHIFT (0U) 1478 #define SIUL2_GPDO11_PDO_n_WIDTH (1U) 1479 #define SIUL2_GPDO11_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO11_PDO_n_SHIFT)) & SIUL2_GPDO11_PDO_n_MASK) 1480 /*! @} */ 1481 1482 /*! @name GPDO10 - SIUL2 GPIO Pad Data Output Register */ 1483 /*! @{ */ 1484 1485 #define SIUL2_GPDO10_PDO_n_MASK (0x1U) 1486 #define SIUL2_GPDO10_PDO_n_SHIFT (0U) 1487 #define SIUL2_GPDO10_PDO_n_WIDTH (1U) 1488 #define SIUL2_GPDO10_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO10_PDO_n_SHIFT)) & SIUL2_GPDO10_PDO_n_MASK) 1489 /*! @} */ 1490 1491 /*! @name GPDO9 - SIUL2 GPIO Pad Data Output Register */ 1492 /*! @{ */ 1493 1494 #define SIUL2_GPDO9_PDO_n_MASK (0x1U) 1495 #define SIUL2_GPDO9_PDO_n_SHIFT (0U) 1496 #define SIUL2_GPDO9_PDO_n_WIDTH (1U) 1497 #define SIUL2_GPDO9_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO9_PDO_n_SHIFT)) & SIUL2_GPDO9_PDO_n_MASK) 1498 /*! @} */ 1499 1500 /*! @name GPDO8 - SIUL2 GPIO Pad Data Output Register */ 1501 /*! @{ */ 1502 1503 #define SIUL2_GPDO8_PDO_n_MASK (0x1U) 1504 #define SIUL2_GPDO8_PDO_n_SHIFT (0U) 1505 #define SIUL2_GPDO8_PDO_n_WIDTH (1U) 1506 #define SIUL2_GPDO8_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO8_PDO_n_SHIFT)) & SIUL2_GPDO8_PDO_n_MASK) 1507 /*! @} */ 1508 1509 /*! @name GPDO15 - SIUL2 GPIO Pad Data Output Register */ 1510 /*! @{ */ 1511 1512 #define SIUL2_GPDO15_PDO_n_MASK (0x1U) 1513 #define SIUL2_GPDO15_PDO_n_SHIFT (0U) 1514 #define SIUL2_GPDO15_PDO_n_WIDTH (1U) 1515 #define SIUL2_GPDO15_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO15_PDO_n_SHIFT)) & SIUL2_GPDO15_PDO_n_MASK) 1516 /*! @} */ 1517 1518 /*! @name GPDO14 - SIUL2 GPIO Pad Data Output Register */ 1519 /*! @{ */ 1520 1521 #define SIUL2_GPDO14_PDO_n_MASK (0x1U) 1522 #define SIUL2_GPDO14_PDO_n_SHIFT (0U) 1523 #define SIUL2_GPDO14_PDO_n_WIDTH (1U) 1524 #define SIUL2_GPDO14_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO14_PDO_n_SHIFT)) & SIUL2_GPDO14_PDO_n_MASK) 1525 /*! @} */ 1526 1527 /*! @name GPDO13 - SIUL2 GPIO Pad Data Output Register */ 1528 /*! @{ */ 1529 1530 #define SIUL2_GPDO13_PDO_n_MASK (0x1U) 1531 #define SIUL2_GPDO13_PDO_n_SHIFT (0U) 1532 #define SIUL2_GPDO13_PDO_n_WIDTH (1U) 1533 #define SIUL2_GPDO13_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO13_PDO_n_SHIFT)) & SIUL2_GPDO13_PDO_n_MASK) 1534 /*! @} */ 1535 1536 /*! @name GPDO12 - SIUL2 GPIO Pad Data Output Register */ 1537 /*! @{ */ 1538 1539 #define SIUL2_GPDO12_PDO_n_MASK (0x1U) 1540 #define SIUL2_GPDO12_PDO_n_SHIFT (0U) 1541 #define SIUL2_GPDO12_PDO_n_WIDTH (1U) 1542 #define SIUL2_GPDO12_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO12_PDO_n_SHIFT)) & SIUL2_GPDO12_PDO_n_MASK) 1543 /*! @} */ 1544 1545 /*! @name GPDO19 - SIUL2 GPIO Pad Data Output Register */ 1546 /*! @{ */ 1547 1548 #define SIUL2_GPDO19_PDO_n_MASK (0x1U) 1549 #define SIUL2_GPDO19_PDO_n_SHIFT (0U) 1550 #define SIUL2_GPDO19_PDO_n_WIDTH (1U) 1551 #define SIUL2_GPDO19_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO19_PDO_n_SHIFT)) & SIUL2_GPDO19_PDO_n_MASK) 1552 /*! @} */ 1553 1554 /*! @name GPDO18 - SIUL2 GPIO Pad Data Output Register */ 1555 /*! @{ */ 1556 1557 #define SIUL2_GPDO18_PDO_n_MASK (0x1U) 1558 #define SIUL2_GPDO18_PDO_n_SHIFT (0U) 1559 #define SIUL2_GPDO18_PDO_n_WIDTH (1U) 1560 #define SIUL2_GPDO18_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO18_PDO_n_SHIFT)) & SIUL2_GPDO18_PDO_n_MASK) 1561 /*! @} */ 1562 1563 /*! @name GPDO17 - SIUL2 GPIO Pad Data Output Register */ 1564 /*! @{ */ 1565 1566 #define SIUL2_GPDO17_PDO_n_MASK (0x1U) 1567 #define SIUL2_GPDO17_PDO_n_SHIFT (0U) 1568 #define SIUL2_GPDO17_PDO_n_WIDTH (1U) 1569 #define SIUL2_GPDO17_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO17_PDO_n_SHIFT)) & SIUL2_GPDO17_PDO_n_MASK) 1570 /*! @} */ 1571 1572 /*! @name GPDO16 - SIUL2 GPIO Pad Data Output Register */ 1573 /*! @{ */ 1574 1575 #define SIUL2_GPDO16_PDO_n_MASK (0x1U) 1576 #define SIUL2_GPDO16_PDO_n_SHIFT (0U) 1577 #define SIUL2_GPDO16_PDO_n_WIDTH (1U) 1578 #define SIUL2_GPDO16_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO16_PDO_n_SHIFT)) & SIUL2_GPDO16_PDO_n_MASK) 1579 /*! @} */ 1580 1581 /*! @name GPDO23 - SIUL2 GPIO Pad Data Output Register */ 1582 /*! @{ */ 1583 1584 #define SIUL2_GPDO23_PDO_n_MASK (0x1U) 1585 #define SIUL2_GPDO23_PDO_n_SHIFT (0U) 1586 #define SIUL2_GPDO23_PDO_n_WIDTH (1U) 1587 #define SIUL2_GPDO23_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO23_PDO_n_SHIFT)) & SIUL2_GPDO23_PDO_n_MASK) 1588 /*! @} */ 1589 1590 /*! @name GPDO22 - SIUL2 GPIO Pad Data Output Register */ 1591 /*! @{ */ 1592 1593 #define SIUL2_GPDO22_PDO_n_MASK (0x1U) 1594 #define SIUL2_GPDO22_PDO_n_SHIFT (0U) 1595 #define SIUL2_GPDO22_PDO_n_WIDTH (1U) 1596 #define SIUL2_GPDO22_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO22_PDO_n_SHIFT)) & SIUL2_GPDO22_PDO_n_MASK) 1597 /*! @} */ 1598 1599 /*! @name GPDO21 - SIUL2 GPIO Pad Data Output Register */ 1600 /*! @{ */ 1601 1602 #define SIUL2_GPDO21_PDO_n_MASK (0x1U) 1603 #define SIUL2_GPDO21_PDO_n_SHIFT (0U) 1604 #define SIUL2_GPDO21_PDO_n_WIDTH (1U) 1605 #define SIUL2_GPDO21_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO21_PDO_n_SHIFT)) & SIUL2_GPDO21_PDO_n_MASK) 1606 /*! @} */ 1607 1608 /*! @name GPDO20 - SIUL2 GPIO Pad Data Output Register */ 1609 /*! @{ */ 1610 1611 #define SIUL2_GPDO20_PDO_n_MASK (0x1U) 1612 #define SIUL2_GPDO20_PDO_n_SHIFT (0U) 1613 #define SIUL2_GPDO20_PDO_n_WIDTH (1U) 1614 #define SIUL2_GPDO20_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO20_PDO_n_SHIFT)) & SIUL2_GPDO20_PDO_n_MASK) 1615 /*! @} */ 1616 1617 /*! @name GPDO27 - SIUL2 GPIO Pad Data Output Register */ 1618 /*! @{ */ 1619 1620 #define SIUL2_GPDO27_PDO_n_MASK (0x1U) 1621 #define SIUL2_GPDO27_PDO_n_SHIFT (0U) 1622 #define SIUL2_GPDO27_PDO_n_WIDTH (1U) 1623 #define SIUL2_GPDO27_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO27_PDO_n_SHIFT)) & SIUL2_GPDO27_PDO_n_MASK) 1624 /*! @} */ 1625 1626 /*! @name GPDO26 - SIUL2 GPIO Pad Data Output Register */ 1627 /*! @{ */ 1628 1629 #define SIUL2_GPDO26_PDO_n_MASK (0x1U) 1630 #define SIUL2_GPDO26_PDO_n_SHIFT (0U) 1631 #define SIUL2_GPDO26_PDO_n_WIDTH (1U) 1632 #define SIUL2_GPDO26_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO26_PDO_n_SHIFT)) & SIUL2_GPDO26_PDO_n_MASK) 1633 /*! @} */ 1634 1635 /*! @name GPDO25 - SIUL2 GPIO Pad Data Output Register */ 1636 /*! @{ */ 1637 1638 #define SIUL2_GPDO25_PDO_n_MASK (0x1U) 1639 #define SIUL2_GPDO25_PDO_n_SHIFT (0U) 1640 #define SIUL2_GPDO25_PDO_n_WIDTH (1U) 1641 #define SIUL2_GPDO25_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO25_PDO_n_SHIFT)) & SIUL2_GPDO25_PDO_n_MASK) 1642 /*! @} */ 1643 1644 /*! @name GPDO24 - SIUL2 GPIO Pad Data Output Register */ 1645 /*! @{ */ 1646 1647 #define SIUL2_GPDO24_PDO_n_MASK (0x1U) 1648 #define SIUL2_GPDO24_PDO_n_SHIFT (0U) 1649 #define SIUL2_GPDO24_PDO_n_WIDTH (1U) 1650 #define SIUL2_GPDO24_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO24_PDO_n_SHIFT)) & SIUL2_GPDO24_PDO_n_MASK) 1651 /*! @} */ 1652 1653 /*! @name GPDO31 - SIUL2 GPIO Pad Data Output Register */ 1654 /*! @{ */ 1655 1656 #define SIUL2_GPDO31_PDO_n_MASK (0x1U) 1657 #define SIUL2_GPDO31_PDO_n_SHIFT (0U) 1658 #define SIUL2_GPDO31_PDO_n_WIDTH (1U) 1659 #define SIUL2_GPDO31_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO31_PDO_n_SHIFT)) & SIUL2_GPDO31_PDO_n_MASK) 1660 /*! @} */ 1661 1662 /*! @name GPDO30 - SIUL2 GPIO Pad Data Output Register */ 1663 /*! @{ */ 1664 1665 #define SIUL2_GPDO30_PDO_n_MASK (0x1U) 1666 #define SIUL2_GPDO30_PDO_n_SHIFT (0U) 1667 #define SIUL2_GPDO30_PDO_n_WIDTH (1U) 1668 #define SIUL2_GPDO30_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO30_PDO_n_SHIFT)) & SIUL2_GPDO30_PDO_n_MASK) 1669 /*! @} */ 1670 1671 /*! @name GPDO29 - SIUL2 GPIO Pad Data Output Register */ 1672 /*! @{ */ 1673 1674 #define SIUL2_GPDO29_PDO_n_MASK (0x1U) 1675 #define SIUL2_GPDO29_PDO_n_SHIFT (0U) 1676 #define SIUL2_GPDO29_PDO_n_WIDTH (1U) 1677 #define SIUL2_GPDO29_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO29_PDO_n_SHIFT)) & SIUL2_GPDO29_PDO_n_MASK) 1678 /*! @} */ 1679 1680 /*! @name GPDO28 - SIUL2 GPIO Pad Data Output Register */ 1681 /*! @{ */ 1682 1683 #define SIUL2_GPDO28_PDO_n_MASK (0x1U) 1684 #define SIUL2_GPDO28_PDO_n_SHIFT (0U) 1685 #define SIUL2_GPDO28_PDO_n_WIDTH (1U) 1686 #define SIUL2_GPDO28_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO28_PDO_n_SHIFT)) & SIUL2_GPDO28_PDO_n_MASK) 1687 /*! @} */ 1688 1689 /*! @name GPDO35 - SIUL2 GPIO Pad Data Output Register */ 1690 /*! @{ */ 1691 1692 #define SIUL2_GPDO35_PDO_n_MASK (0x1U) 1693 #define SIUL2_GPDO35_PDO_n_SHIFT (0U) 1694 #define SIUL2_GPDO35_PDO_n_WIDTH (1U) 1695 #define SIUL2_GPDO35_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO35_PDO_n_SHIFT)) & SIUL2_GPDO35_PDO_n_MASK) 1696 /*! @} */ 1697 1698 /*! @name GPDO34 - SIUL2 GPIO Pad Data Output Register */ 1699 /*! @{ */ 1700 1701 #define SIUL2_GPDO34_PDO_n_MASK (0x1U) 1702 #define SIUL2_GPDO34_PDO_n_SHIFT (0U) 1703 #define SIUL2_GPDO34_PDO_n_WIDTH (1U) 1704 #define SIUL2_GPDO34_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO34_PDO_n_SHIFT)) & SIUL2_GPDO34_PDO_n_MASK) 1705 /*! @} */ 1706 1707 /*! @name GPDO33 - SIUL2 GPIO Pad Data Output Register */ 1708 /*! @{ */ 1709 1710 #define SIUL2_GPDO33_PDO_n_MASK (0x1U) 1711 #define SIUL2_GPDO33_PDO_n_SHIFT (0U) 1712 #define SIUL2_GPDO33_PDO_n_WIDTH (1U) 1713 #define SIUL2_GPDO33_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO33_PDO_n_SHIFT)) & SIUL2_GPDO33_PDO_n_MASK) 1714 /*! @} */ 1715 1716 /*! @name GPDO32 - SIUL2 GPIO Pad Data Output Register */ 1717 /*! @{ */ 1718 1719 #define SIUL2_GPDO32_PDO_n_MASK (0x1U) 1720 #define SIUL2_GPDO32_PDO_n_SHIFT (0U) 1721 #define SIUL2_GPDO32_PDO_n_WIDTH (1U) 1722 #define SIUL2_GPDO32_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO32_PDO_n_SHIFT)) & SIUL2_GPDO32_PDO_n_MASK) 1723 /*! @} */ 1724 1725 /*! @name GPDO39 - SIUL2 GPIO Pad Data Output Register */ 1726 /*! @{ */ 1727 1728 #define SIUL2_GPDO39_PDO_n_MASK (0x1U) 1729 #define SIUL2_GPDO39_PDO_n_SHIFT (0U) 1730 #define SIUL2_GPDO39_PDO_n_WIDTH (1U) 1731 #define SIUL2_GPDO39_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO39_PDO_n_SHIFT)) & SIUL2_GPDO39_PDO_n_MASK) 1732 /*! @} */ 1733 1734 /*! @name GPDO38 - SIUL2 GPIO Pad Data Output Register */ 1735 /*! @{ */ 1736 1737 #define SIUL2_GPDO38_PDO_n_MASK (0x1U) 1738 #define SIUL2_GPDO38_PDO_n_SHIFT (0U) 1739 #define SIUL2_GPDO38_PDO_n_WIDTH (1U) 1740 #define SIUL2_GPDO38_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO38_PDO_n_SHIFT)) & SIUL2_GPDO38_PDO_n_MASK) 1741 /*! @} */ 1742 1743 /*! @name GPDO37 - SIUL2 GPIO Pad Data Output Register */ 1744 /*! @{ */ 1745 1746 #define SIUL2_GPDO37_PDO_n_MASK (0x1U) 1747 #define SIUL2_GPDO37_PDO_n_SHIFT (0U) 1748 #define SIUL2_GPDO37_PDO_n_WIDTH (1U) 1749 #define SIUL2_GPDO37_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO37_PDO_n_SHIFT)) & SIUL2_GPDO37_PDO_n_MASK) 1750 /*! @} */ 1751 1752 /*! @name GPDO36 - SIUL2 GPIO Pad Data Output Register */ 1753 /*! @{ */ 1754 1755 #define SIUL2_GPDO36_PDO_n_MASK (0x1U) 1756 #define SIUL2_GPDO36_PDO_n_SHIFT (0U) 1757 #define SIUL2_GPDO36_PDO_n_WIDTH (1U) 1758 #define SIUL2_GPDO36_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO36_PDO_n_SHIFT)) & SIUL2_GPDO36_PDO_n_MASK) 1759 /*! @} */ 1760 1761 /*! @name GPDO43 - SIUL2 GPIO Pad Data Output Register */ 1762 /*! @{ */ 1763 1764 #define SIUL2_GPDO43_PDO_n_MASK (0x1U) 1765 #define SIUL2_GPDO43_PDO_n_SHIFT (0U) 1766 #define SIUL2_GPDO43_PDO_n_WIDTH (1U) 1767 #define SIUL2_GPDO43_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO43_PDO_n_SHIFT)) & SIUL2_GPDO43_PDO_n_MASK) 1768 /*! @} */ 1769 1770 /*! @name GPDO42 - SIUL2 GPIO Pad Data Output Register */ 1771 /*! @{ */ 1772 1773 #define SIUL2_GPDO42_PDO_n_MASK (0x1U) 1774 #define SIUL2_GPDO42_PDO_n_SHIFT (0U) 1775 #define SIUL2_GPDO42_PDO_n_WIDTH (1U) 1776 #define SIUL2_GPDO42_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO42_PDO_n_SHIFT)) & SIUL2_GPDO42_PDO_n_MASK) 1777 /*! @} */ 1778 1779 /*! @name GPDO41 - SIUL2 GPIO Pad Data Output Register */ 1780 /*! @{ */ 1781 1782 #define SIUL2_GPDO41_PDO_n_MASK (0x1U) 1783 #define SIUL2_GPDO41_PDO_n_SHIFT (0U) 1784 #define SIUL2_GPDO41_PDO_n_WIDTH (1U) 1785 #define SIUL2_GPDO41_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO41_PDO_n_SHIFT)) & SIUL2_GPDO41_PDO_n_MASK) 1786 /*! @} */ 1787 1788 /*! @name GPDO40 - SIUL2 GPIO Pad Data Output Register */ 1789 /*! @{ */ 1790 1791 #define SIUL2_GPDO40_PDO_n_MASK (0x1U) 1792 #define SIUL2_GPDO40_PDO_n_SHIFT (0U) 1793 #define SIUL2_GPDO40_PDO_n_WIDTH (1U) 1794 #define SIUL2_GPDO40_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO40_PDO_n_SHIFT)) & SIUL2_GPDO40_PDO_n_MASK) 1795 /*! @} */ 1796 1797 /*! @name GPDO47 - SIUL2 GPIO Pad Data Output Register */ 1798 /*! @{ */ 1799 1800 #define SIUL2_GPDO47_PDO_n_MASK (0x1U) 1801 #define SIUL2_GPDO47_PDO_n_SHIFT (0U) 1802 #define SIUL2_GPDO47_PDO_n_WIDTH (1U) 1803 #define SIUL2_GPDO47_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO47_PDO_n_SHIFT)) & SIUL2_GPDO47_PDO_n_MASK) 1804 /*! @} */ 1805 1806 /*! @name GPDO46 - SIUL2 GPIO Pad Data Output Register */ 1807 /*! @{ */ 1808 1809 #define SIUL2_GPDO46_PDO_n_MASK (0x1U) 1810 #define SIUL2_GPDO46_PDO_n_SHIFT (0U) 1811 #define SIUL2_GPDO46_PDO_n_WIDTH (1U) 1812 #define SIUL2_GPDO46_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO46_PDO_n_SHIFT)) & SIUL2_GPDO46_PDO_n_MASK) 1813 /*! @} */ 1814 1815 /*! @name GPDO45 - SIUL2 GPIO Pad Data Output Register */ 1816 /*! @{ */ 1817 1818 #define SIUL2_GPDO45_PDO_n_MASK (0x1U) 1819 #define SIUL2_GPDO45_PDO_n_SHIFT (0U) 1820 #define SIUL2_GPDO45_PDO_n_WIDTH (1U) 1821 #define SIUL2_GPDO45_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO45_PDO_n_SHIFT)) & SIUL2_GPDO45_PDO_n_MASK) 1822 /*! @} */ 1823 1824 /*! @name GPDO44 - SIUL2 GPIO Pad Data Output Register */ 1825 /*! @{ */ 1826 1827 #define SIUL2_GPDO44_PDO_n_MASK (0x1U) 1828 #define SIUL2_GPDO44_PDO_n_SHIFT (0U) 1829 #define SIUL2_GPDO44_PDO_n_WIDTH (1U) 1830 #define SIUL2_GPDO44_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO44_PDO_n_SHIFT)) & SIUL2_GPDO44_PDO_n_MASK) 1831 /*! @} */ 1832 1833 /*! @name GPDO51 - SIUL2 GPIO Pad Data Output Register */ 1834 /*! @{ */ 1835 1836 #define SIUL2_GPDO51_PDO_n_MASK (0x1U) 1837 #define SIUL2_GPDO51_PDO_n_SHIFT (0U) 1838 #define SIUL2_GPDO51_PDO_n_WIDTH (1U) 1839 #define SIUL2_GPDO51_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO51_PDO_n_SHIFT)) & SIUL2_GPDO51_PDO_n_MASK) 1840 /*! @} */ 1841 1842 /*! @name GPDO50 - SIUL2 GPIO Pad Data Output Register */ 1843 /*! @{ */ 1844 1845 #define SIUL2_GPDO50_PDO_n_MASK (0x1U) 1846 #define SIUL2_GPDO50_PDO_n_SHIFT (0U) 1847 #define SIUL2_GPDO50_PDO_n_WIDTH (1U) 1848 #define SIUL2_GPDO50_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO50_PDO_n_SHIFT)) & SIUL2_GPDO50_PDO_n_MASK) 1849 /*! @} */ 1850 1851 /*! @name GPDO49 - SIUL2 GPIO Pad Data Output Register */ 1852 /*! @{ */ 1853 1854 #define SIUL2_GPDO49_PDO_n_MASK (0x1U) 1855 #define SIUL2_GPDO49_PDO_n_SHIFT (0U) 1856 #define SIUL2_GPDO49_PDO_n_WIDTH (1U) 1857 #define SIUL2_GPDO49_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO49_PDO_n_SHIFT)) & SIUL2_GPDO49_PDO_n_MASK) 1858 /*! @} */ 1859 1860 /*! @name GPDO48 - SIUL2 GPIO Pad Data Output Register */ 1861 /*! @{ */ 1862 1863 #define SIUL2_GPDO48_PDO_n_MASK (0x1U) 1864 #define SIUL2_GPDO48_PDO_n_SHIFT (0U) 1865 #define SIUL2_GPDO48_PDO_n_WIDTH (1U) 1866 #define SIUL2_GPDO48_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO48_PDO_n_SHIFT)) & SIUL2_GPDO48_PDO_n_MASK) 1867 /*! @} */ 1868 1869 /*! @name GPDO55 - SIUL2 GPIO Pad Data Output Register */ 1870 /*! @{ */ 1871 1872 #define SIUL2_GPDO55_PDO_n_MASK (0x1U) 1873 #define SIUL2_GPDO55_PDO_n_SHIFT (0U) 1874 #define SIUL2_GPDO55_PDO_n_WIDTH (1U) 1875 #define SIUL2_GPDO55_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO55_PDO_n_SHIFT)) & SIUL2_GPDO55_PDO_n_MASK) 1876 /*! @} */ 1877 1878 /*! @name GPDO54 - SIUL2 GPIO Pad Data Output Register */ 1879 /*! @{ */ 1880 1881 #define SIUL2_GPDO54_PDO_n_MASK (0x1U) 1882 #define SIUL2_GPDO54_PDO_n_SHIFT (0U) 1883 #define SIUL2_GPDO54_PDO_n_WIDTH (1U) 1884 #define SIUL2_GPDO54_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO54_PDO_n_SHIFT)) & SIUL2_GPDO54_PDO_n_MASK) 1885 /*! @} */ 1886 1887 /*! @name GPDO53 - SIUL2 GPIO Pad Data Output Register */ 1888 /*! @{ */ 1889 1890 #define SIUL2_GPDO53_PDO_n_MASK (0x1U) 1891 #define SIUL2_GPDO53_PDO_n_SHIFT (0U) 1892 #define SIUL2_GPDO53_PDO_n_WIDTH (1U) 1893 #define SIUL2_GPDO53_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO53_PDO_n_SHIFT)) & SIUL2_GPDO53_PDO_n_MASK) 1894 /*! @} */ 1895 1896 /*! @name GPDO52 - SIUL2 GPIO Pad Data Output Register */ 1897 /*! @{ */ 1898 1899 #define SIUL2_GPDO52_PDO_n_MASK (0x1U) 1900 #define SIUL2_GPDO52_PDO_n_SHIFT (0U) 1901 #define SIUL2_GPDO52_PDO_n_WIDTH (1U) 1902 #define SIUL2_GPDO52_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO52_PDO_n_SHIFT)) & SIUL2_GPDO52_PDO_n_MASK) 1903 /*! @} */ 1904 1905 /*! @name GPDO59 - SIUL2 GPIO Pad Data Output Register */ 1906 /*! @{ */ 1907 1908 #define SIUL2_GPDO59_PDO_n_MASK (0x1U) 1909 #define SIUL2_GPDO59_PDO_n_SHIFT (0U) 1910 #define SIUL2_GPDO59_PDO_n_WIDTH (1U) 1911 #define SIUL2_GPDO59_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO59_PDO_n_SHIFT)) & SIUL2_GPDO59_PDO_n_MASK) 1912 /*! @} */ 1913 1914 /*! @name GPDO58 - SIUL2 GPIO Pad Data Output Register */ 1915 /*! @{ */ 1916 1917 #define SIUL2_GPDO58_PDO_n_MASK (0x1U) 1918 #define SIUL2_GPDO58_PDO_n_SHIFT (0U) 1919 #define SIUL2_GPDO58_PDO_n_WIDTH (1U) 1920 #define SIUL2_GPDO58_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO58_PDO_n_SHIFT)) & SIUL2_GPDO58_PDO_n_MASK) 1921 /*! @} */ 1922 1923 /*! @name GPDO57 - SIUL2 GPIO Pad Data Output Register */ 1924 /*! @{ */ 1925 1926 #define SIUL2_GPDO57_PDO_n_MASK (0x1U) 1927 #define SIUL2_GPDO57_PDO_n_SHIFT (0U) 1928 #define SIUL2_GPDO57_PDO_n_WIDTH (1U) 1929 #define SIUL2_GPDO57_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO57_PDO_n_SHIFT)) & SIUL2_GPDO57_PDO_n_MASK) 1930 /*! @} */ 1931 1932 /*! @name GPDO56 - SIUL2 GPIO Pad Data Output Register */ 1933 /*! @{ */ 1934 1935 #define SIUL2_GPDO56_PDO_n_MASK (0x1U) 1936 #define SIUL2_GPDO56_PDO_n_SHIFT (0U) 1937 #define SIUL2_GPDO56_PDO_n_WIDTH (1U) 1938 #define SIUL2_GPDO56_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO56_PDO_n_SHIFT)) & SIUL2_GPDO56_PDO_n_MASK) 1939 /*! @} */ 1940 1941 /*! @name GPDO63 - SIUL2 GPIO Pad Data Output Register */ 1942 /*! @{ */ 1943 1944 #define SIUL2_GPDO63_PDO_n_MASK (0x1U) 1945 #define SIUL2_GPDO63_PDO_n_SHIFT (0U) 1946 #define SIUL2_GPDO63_PDO_n_WIDTH (1U) 1947 #define SIUL2_GPDO63_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO63_PDO_n_SHIFT)) & SIUL2_GPDO63_PDO_n_MASK) 1948 /*! @} */ 1949 1950 /*! @name GPDO62 - SIUL2 GPIO Pad Data Output Register */ 1951 /*! @{ */ 1952 1953 #define SIUL2_GPDO62_PDO_n_MASK (0x1U) 1954 #define SIUL2_GPDO62_PDO_n_SHIFT (0U) 1955 #define SIUL2_GPDO62_PDO_n_WIDTH (1U) 1956 #define SIUL2_GPDO62_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO62_PDO_n_SHIFT)) & SIUL2_GPDO62_PDO_n_MASK) 1957 /*! @} */ 1958 1959 /*! @name GPDO61 - SIUL2 GPIO Pad Data Output Register */ 1960 /*! @{ */ 1961 1962 #define SIUL2_GPDO61_PDO_n_MASK (0x1U) 1963 #define SIUL2_GPDO61_PDO_n_SHIFT (0U) 1964 #define SIUL2_GPDO61_PDO_n_WIDTH (1U) 1965 #define SIUL2_GPDO61_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO61_PDO_n_SHIFT)) & SIUL2_GPDO61_PDO_n_MASK) 1966 /*! @} */ 1967 1968 /*! @name GPDO60 - SIUL2 GPIO Pad Data Output Register */ 1969 /*! @{ */ 1970 1971 #define SIUL2_GPDO60_PDO_n_MASK (0x1U) 1972 #define SIUL2_GPDO60_PDO_n_SHIFT (0U) 1973 #define SIUL2_GPDO60_PDO_n_WIDTH (1U) 1974 #define SIUL2_GPDO60_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO60_PDO_n_SHIFT)) & SIUL2_GPDO60_PDO_n_MASK) 1975 /*! @} */ 1976 1977 /*! @name GPDO67 - SIUL2 GPIO Pad Data Output Register */ 1978 /*! @{ */ 1979 1980 #define SIUL2_GPDO67_PDO_n_MASK (0x1U) 1981 #define SIUL2_GPDO67_PDO_n_SHIFT (0U) 1982 #define SIUL2_GPDO67_PDO_n_WIDTH (1U) 1983 #define SIUL2_GPDO67_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO67_PDO_n_SHIFT)) & SIUL2_GPDO67_PDO_n_MASK) 1984 /*! @} */ 1985 1986 /*! @name GPDO66 - SIUL2 GPIO Pad Data Output Register */ 1987 /*! @{ */ 1988 1989 #define SIUL2_GPDO66_PDO_n_MASK (0x1U) 1990 #define SIUL2_GPDO66_PDO_n_SHIFT (0U) 1991 #define SIUL2_GPDO66_PDO_n_WIDTH (1U) 1992 #define SIUL2_GPDO66_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO66_PDO_n_SHIFT)) & SIUL2_GPDO66_PDO_n_MASK) 1993 /*! @} */ 1994 1995 /*! @name GPDO65 - SIUL2 GPIO Pad Data Output Register */ 1996 /*! @{ */ 1997 1998 #define SIUL2_GPDO65_PDO_n_MASK (0x1U) 1999 #define SIUL2_GPDO65_PDO_n_SHIFT (0U) 2000 #define SIUL2_GPDO65_PDO_n_WIDTH (1U) 2001 #define SIUL2_GPDO65_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO65_PDO_n_SHIFT)) & SIUL2_GPDO65_PDO_n_MASK) 2002 /*! @} */ 2003 2004 /*! @name GPDO64 - SIUL2 GPIO Pad Data Output Register */ 2005 /*! @{ */ 2006 2007 #define SIUL2_GPDO64_PDO_n_MASK (0x1U) 2008 #define SIUL2_GPDO64_PDO_n_SHIFT (0U) 2009 #define SIUL2_GPDO64_PDO_n_WIDTH (1U) 2010 #define SIUL2_GPDO64_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO64_PDO_n_SHIFT)) & SIUL2_GPDO64_PDO_n_MASK) 2011 /*! @} */ 2012 2013 /*! @name GPDO71 - SIUL2 GPIO Pad Data Output Register */ 2014 /*! @{ */ 2015 2016 #define SIUL2_GPDO71_PDO_n_MASK (0x1U) 2017 #define SIUL2_GPDO71_PDO_n_SHIFT (0U) 2018 #define SIUL2_GPDO71_PDO_n_WIDTH (1U) 2019 #define SIUL2_GPDO71_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO71_PDO_n_SHIFT)) & SIUL2_GPDO71_PDO_n_MASK) 2020 /*! @} */ 2021 2022 /*! @name GPDO70 - SIUL2 GPIO Pad Data Output Register */ 2023 /*! @{ */ 2024 2025 #define SIUL2_GPDO70_PDO_n_MASK (0x1U) 2026 #define SIUL2_GPDO70_PDO_n_SHIFT (0U) 2027 #define SIUL2_GPDO70_PDO_n_WIDTH (1U) 2028 #define SIUL2_GPDO70_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO70_PDO_n_SHIFT)) & SIUL2_GPDO70_PDO_n_MASK) 2029 /*! @} */ 2030 2031 /*! @name GPDO69 - SIUL2 GPIO Pad Data Output Register */ 2032 /*! @{ */ 2033 2034 #define SIUL2_GPDO69_PDO_n_MASK (0x1U) 2035 #define SIUL2_GPDO69_PDO_n_SHIFT (0U) 2036 #define SIUL2_GPDO69_PDO_n_WIDTH (1U) 2037 #define SIUL2_GPDO69_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO69_PDO_n_SHIFT)) & SIUL2_GPDO69_PDO_n_MASK) 2038 /*! @} */ 2039 2040 /*! @name GPDO68 - SIUL2 GPIO Pad Data Output Register */ 2041 /*! @{ */ 2042 2043 #define SIUL2_GPDO68_PDO_n_MASK (0x1U) 2044 #define SIUL2_GPDO68_PDO_n_SHIFT (0U) 2045 #define SIUL2_GPDO68_PDO_n_WIDTH (1U) 2046 #define SIUL2_GPDO68_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO68_PDO_n_SHIFT)) & SIUL2_GPDO68_PDO_n_MASK) 2047 /*! @} */ 2048 2049 /*! @name GPDO75 - SIUL2 GPIO Pad Data Output Register */ 2050 /*! @{ */ 2051 2052 #define SIUL2_GPDO75_PDO_n_MASK (0x1U) 2053 #define SIUL2_GPDO75_PDO_n_SHIFT (0U) 2054 #define SIUL2_GPDO75_PDO_n_WIDTH (1U) 2055 #define SIUL2_GPDO75_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO75_PDO_n_SHIFT)) & SIUL2_GPDO75_PDO_n_MASK) 2056 /*! @} */ 2057 2058 /*! @name GPDO74 - SIUL2 GPIO Pad Data Output Register */ 2059 /*! @{ */ 2060 2061 #define SIUL2_GPDO74_PDO_n_MASK (0x1U) 2062 #define SIUL2_GPDO74_PDO_n_SHIFT (0U) 2063 #define SIUL2_GPDO74_PDO_n_WIDTH (1U) 2064 #define SIUL2_GPDO74_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO74_PDO_n_SHIFT)) & SIUL2_GPDO74_PDO_n_MASK) 2065 /*! @} */ 2066 2067 /*! @name GPDO73 - SIUL2 GPIO Pad Data Output Register */ 2068 /*! @{ */ 2069 2070 #define SIUL2_GPDO73_PDO_n_MASK (0x1U) 2071 #define SIUL2_GPDO73_PDO_n_SHIFT (0U) 2072 #define SIUL2_GPDO73_PDO_n_WIDTH (1U) 2073 #define SIUL2_GPDO73_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO73_PDO_n_SHIFT)) & SIUL2_GPDO73_PDO_n_MASK) 2074 /*! @} */ 2075 2076 /*! @name GPDO72 - SIUL2 GPIO Pad Data Output Register */ 2077 /*! @{ */ 2078 2079 #define SIUL2_GPDO72_PDO_n_MASK (0x1U) 2080 #define SIUL2_GPDO72_PDO_n_SHIFT (0U) 2081 #define SIUL2_GPDO72_PDO_n_WIDTH (1U) 2082 #define SIUL2_GPDO72_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO72_PDO_n_SHIFT)) & SIUL2_GPDO72_PDO_n_MASK) 2083 /*! @} */ 2084 2085 /*! @name GPDO79 - SIUL2 GPIO Pad Data Output Register */ 2086 /*! @{ */ 2087 2088 #define SIUL2_GPDO79_PDO_n_MASK (0x1U) 2089 #define SIUL2_GPDO79_PDO_n_SHIFT (0U) 2090 #define SIUL2_GPDO79_PDO_n_WIDTH (1U) 2091 #define SIUL2_GPDO79_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO79_PDO_n_SHIFT)) & SIUL2_GPDO79_PDO_n_MASK) 2092 /*! @} */ 2093 2094 /*! @name GPDO78 - SIUL2 GPIO Pad Data Output Register */ 2095 /*! @{ */ 2096 2097 #define SIUL2_GPDO78_PDO_n_MASK (0x1U) 2098 #define SIUL2_GPDO78_PDO_n_SHIFT (0U) 2099 #define SIUL2_GPDO78_PDO_n_WIDTH (1U) 2100 #define SIUL2_GPDO78_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO78_PDO_n_SHIFT)) & SIUL2_GPDO78_PDO_n_MASK) 2101 /*! @} */ 2102 2103 /*! @name GPDO77 - SIUL2 GPIO Pad Data Output Register */ 2104 /*! @{ */ 2105 2106 #define SIUL2_GPDO77_PDO_n_MASK (0x1U) 2107 #define SIUL2_GPDO77_PDO_n_SHIFT (0U) 2108 #define SIUL2_GPDO77_PDO_n_WIDTH (1U) 2109 #define SIUL2_GPDO77_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO77_PDO_n_SHIFT)) & SIUL2_GPDO77_PDO_n_MASK) 2110 /*! @} */ 2111 2112 /*! @name GPDO76 - SIUL2 GPIO Pad Data Output Register */ 2113 /*! @{ */ 2114 2115 #define SIUL2_GPDO76_PDO_n_MASK (0x1U) 2116 #define SIUL2_GPDO76_PDO_n_SHIFT (0U) 2117 #define SIUL2_GPDO76_PDO_n_WIDTH (1U) 2118 #define SIUL2_GPDO76_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO76_PDO_n_SHIFT)) & SIUL2_GPDO76_PDO_n_MASK) 2119 /*! @} */ 2120 2121 /*! @name GPDO83 - SIUL2 GPIO Pad Data Output Register */ 2122 /*! @{ */ 2123 2124 #define SIUL2_GPDO83_PDO_n_MASK (0x1U) 2125 #define SIUL2_GPDO83_PDO_n_SHIFT (0U) 2126 #define SIUL2_GPDO83_PDO_n_WIDTH (1U) 2127 #define SIUL2_GPDO83_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO83_PDO_n_SHIFT)) & SIUL2_GPDO83_PDO_n_MASK) 2128 /*! @} */ 2129 2130 /*! @name GPDO82 - SIUL2 GPIO Pad Data Output Register */ 2131 /*! @{ */ 2132 2133 #define SIUL2_GPDO82_PDO_n_MASK (0x1U) 2134 #define SIUL2_GPDO82_PDO_n_SHIFT (0U) 2135 #define SIUL2_GPDO82_PDO_n_WIDTH (1U) 2136 #define SIUL2_GPDO82_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO82_PDO_n_SHIFT)) & SIUL2_GPDO82_PDO_n_MASK) 2137 /*! @} */ 2138 2139 /*! @name GPDO81 - SIUL2 GPIO Pad Data Output Register */ 2140 /*! @{ */ 2141 2142 #define SIUL2_GPDO81_PDO_n_MASK (0x1U) 2143 #define SIUL2_GPDO81_PDO_n_SHIFT (0U) 2144 #define SIUL2_GPDO81_PDO_n_WIDTH (1U) 2145 #define SIUL2_GPDO81_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO81_PDO_n_SHIFT)) & SIUL2_GPDO81_PDO_n_MASK) 2146 /*! @} */ 2147 2148 /*! @name GPDO80 - SIUL2 GPIO Pad Data Output Register */ 2149 /*! @{ */ 2150 2151 #define SIUL2_GPDO80_PDO_n_MASK (0x1U) 2152 #define SIUL2_GPDO80_PDO_n_SHIFT (0U) 2153 #define SIUL2_GPDO80_PDO_n_WIDTH (1U) 2154 #define SIUL2_GPDO80_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO80_PDO_n_SHIFT)) & SIUL2_GPDO80_PDO_n_MASK) 2155 /*! @} */ 2156 2157 /*! @name GPDO87 - SIUL2 GPIO Pad Data Output Register */ 2158 /*! @{ */ 2159 2160 #define SIUL2_GPDO87_PDO_n_MASK (0x1U) 2161 #define SIUL2_GPDO87_PDO_n_SHIFT (0U) 2162 #define SIUL2_GPDO87_PDO_n_WIDTH (1U) 2163 #define SIUL2_GPDO87_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO87_PDO_n_SHIFT)) & SIUL2_GPDO87_PDO_n_MASK) 2164 /*! @} */ 2165 2166 /*! @name GPDO86 - SIUL2 GPIO Pad Data Output Register */ 2167 /*! @{ */ 2168 2169 #define SIUL2_GPDO86_PDO_n_MASK (0x1U) 2170 #define SIUL2_GPDO86_PDO_n_SHIFT (0U) 2171 #define SIUL2_GPDO86_PDO_n_WIDTH (1U) 2172 #define SIUL2_GPDO86_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO86_PDO_n_SHIFT)) & SIUL2_GPDO86_PDO_n_MASK) 2173 /*! @} */ 2174 2175 /*! @name GPDO85 - SIUL2 GPIO Pad Data Output Register */ 2176 /*! @{ */ 2177 2178 #define SIUL2_GPDO85_PDO_n_MASK (0x1U) 2179 #define SIUL2_GPDO85_PDO_n_SHIFT (0U) 2180 #define SIUL2_GPDO85_PDO_n_WIDTH (1U) 2181 #define SIUL2_GPDO85_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO85_PDO_n_SHIFT)) & SIUL2_GPDO85_PDO_n_MASK) 2182 /*! @} */ 2183 2184 /*! @name GPDO84 - SIUL2 GPIO Pad Data Output Register */ 2185 /*! @{ */ 2186 2187 #define SIUL2_GPDO84_PDO_n_MASK (0x1U) 2188 #define SIUL2_GPDO84_PDO_n_SHIFT (0U) 2189 #define SIUL2_GPDO84_PDO_n_WIDTH (1U) 2190 #define SIUL2_GPDO84_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO84_PDO_n_SHIFT)) & SIUL2_GPDO84_PDO_n_MASK) 2191 /*! @} */ 2192 2193 /*! @name GPDO91 - SIUL2 GPIO Pad Data Output Register */ 2194 /*! @{ */ 2195 2196 #define SIUL2_GPDO91_PDO_n_MASK (0x1U) 2197 #define SIUL2_GPDO91_PDO_n_SHIFT (0U) 2198 #define SIUL2_GPDO91_PDO_n_WIDTH (1U) 2199 #define SIUL2_GPDO91_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO91_PDO_n_SHIFT)) & SIUL2_GPDO91_PDO_n_MASK) 2200 /*! @} */ 2201 2202 /*! @name GPDO90 - SIUL2 GPIO Pad Data Output Register */ 2203 /*! @{ */ 2204 2205 #define SIUL2_GPDO90_PDO_n_MASK (0x1U) 2206 #define SIUL2_GPDO90_PDO_n_SHIFT (0U) 2207 #define SIUL2_GPDO90_PDO_n_WIDTH (1U) 2208 #define SIUL2_GPDO90_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO90_PDO_n_SHIFT)) & SIUL2_GPDO90_PDO_n_MASK) 2209 /*! @} */ 2210 2211 /*! @name GPDO89 - SIUL2 GPIO Pad Data Output Register */ 2212 /*! @{ */ 2213 2214 #define SIUL2_GPDO89_PDO_n_MASK (0x1U) 2215 #define SIUL2_GPDO89_PDO_n_SHIFT (0U) 2216 #define SIUL2_GPDO89_PDO_n_WIDTH (1U) 2217 #define SIUL2_GPDO89_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO89_PDO_n_SHIFT)) & SIUL2_GPDO89_PDO_n_MASK) 2218 /*! @} */ 2219 2220 /*! @name GPDO88 - SIUL2 GPIO Pad Data Output Register */ 2221 /*! @{ */ 2222 2223 #define SIUL2_GPDO88_PDO_n_MASK (0x1U) 2224 #define SIUL2_GPDO88_PDO_n_SHIFT (0U) 2225 #define SIUL2_GPDO88_PDO_n_WIDTH (1U) 2226 #define SIUL2_GPDO88_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO88_PDO_n_SHIFT)) & SIUL2_GPDO88_PDO_n_MASK) 2227 /*! @} */ 2228 2229 /*! @name GPDO95 - SIUL2 GPIO Pad Data Output Register */ 2230 /*! @{ */ 2231 2232 #define SIUL2_GPDO95_PDO_n_MASK (0x1U) 2233 #define SIUL2_GPDO95_PDO_n_SHIFT (0U) 2234 #define SIUL2_GPDO95_PDO_n_WIDTH (1U) 2235 #define SIUL2_GPDO95_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO95_PDO_n_SHIFT)) & SIUL2_GPDO95_PDO_n_MASK) 2236 /*! @} */ 2237 2238 /*! @name GPDO94 - SIUL2 GPIO Pad Data Output Register */ 2239 /*! @{ */ 2240 2241 #define SIUL2_GPDO94_PDO_n_MASK (0x1U) 2242 #define SIUL2_GPDO94_PDO_n_SHIFT (0U) 2243 #define SIUL2_GPDO94_PDO_n_WIDTH (1U) 2244 #define SIUL2_GPDO94_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO94_PDO_n_SHIFT)) & SIUL2_GPDO94_PDO_n_MASK) 2245 /*! @} */ 2246 2247 /*! @name GPDO93 - SIUL2 GPIO Pad Data Output Register */ 2248 /*! @{ */ 2249 2250 #define SIUL2_GPDO93_PDO_n_MASK (0x1U) 2251 #define SIUL2_GPDO93_PDO_n_SHIFT (0U) 2252 #define SIUL2_GPDO93_PDO_n_WIDTH (1U) 2253 #define SIUL2_GPDO93_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO93_PDO_n_SHIFT)) & SIUL2_GPDO93_PDO_n_MASK) 2254 /*! @} */ 2255 2256 /*! @name GPDO92 - SIUL2 GPIO Pad Data Output Register */ 2257 /*! @{ */ 2258 2259 #define SIUL2_GPDO92_PDO_n_MASK (0x1U) 2260 #define SIUL2_GPDO92_PDO_n_SHIFT (0U) 2261 #define SIUL2_GPDO92_PDO_n_WIDTH (1U) 2262 #define SIUL2_GPDO92_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO92_PDO_n_SHIFT)) & SIUL2_GPDO92_PDO_n_MASK) 2263 /*! @} */ 2264 2265 /*! @name GPDO99 - SIUL2 GPIO Pad Data Output Register */ 2266 /*! @{ */ 2267 2268 #define SIUL2_GPDO99_PDO_n_MASK (0x1U) 2269 #define SIUL2_GPDO99_PDO_n_SHIFT (0U) 2270 #define SIUL2_GPDO99_PDO_n_WIDTH (1U) 2271 #define SIUL2_GPDO99_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO99_PDO_n_SHIFT)) & SIUL2_GPDO99_PDO_n_MASK) 2272 /*! @} */ 2273 2274 /*! @name GPDO98 - SIUL2 GPIO Pad Data Output Register */ 2275 /*! @{ */ 2276 2277 #define SIUL2_GPDO98_PDO_n_MASK (0x1U) 2278 #define SIUL2_GPDO98_PDO_n_SHIFT (0U) 2279 #define SIUL2_GPDO98_PDO_n_WIDTH (1U) 2280 #define SIUL2_GPDO98_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO98_PDO_n_SHIFT)) & SIUL2_GPDO98_PDO_n_MASK) 2281 /*! @} */ 2282 2283 /*! @name GPDO97 - SIUL2 GPIO Pad Data Output Register */ 2284 /*! @{ */ 2285 2286 #define SIUL2_GPDO97_PDO_n_MASK (0x1U) 2287 #define SIUL2_GPDO97_PDO_n_SHIFT (0U) 2288 #define SIUL2_GPDO97_PDO_n_WIDTH (1U) 2289 #define SIUL2_GPDO97_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO97_PDO_n_SHIFT)) & SIUL2_GPDO97_PDO_n_MASK) 2290 /*! @} */ 2291 2292 /*! @name GPDO96 - SIUL2 GPIO Pad Data Output Register */ 2293 /*! @{ */ 2294 2295 #define SIUL2_GPDO96_PDO_n_MASK (0x1U) 2296 #define SIUL2_GPDO96_PDO_n_SHIFT (0U) 2297 #define SIUL2_GPDO96_PDO_n_WIDTH (1U) 2298 #define SIUL2_GPDO96_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO96_PDO_n_SHIFT)) & SIUL2_GPDO96_PDO_n_MASK) 2299 /*! @} */ 2300 2301 /*! @name GPDO103 - SIUL2 GPIO Pad Data Output Register */ 2302 /*! @{ */ 2303 2304 #define SIUL2_GPDO103_PDO_n_MASK (0x1U) 2305 #define SIUL2_GPDO103_PDO_n_SHIFT (0U) 2306 #define SIUL2_GPDO103_PDO_n_WIDTH (1U) 2307 #define SIUL2_GPDO103_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO103_PDO_n_SHIFT)) & SIUL2_GPDO103_PDO_n_MASK) 2308 /*! @} */ 2309 2310 /*! @name GPDO102 - SIUL2 GPIO Pad Data Output Register */ 2311 /*! @{ */ 2312 2313 #define SIUL2_GPDO102_PDO_n_MASK (0x1U) 2314 #define SIUL2_GPDO102_PDO_n_SHIFT (0U) 2315 #define SIUL2_GPDO102_PDO_n_WIDTH (1U) 2316 #define SIUL2_GPDO102_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO102_PDO_n_SHIFT)) & SIUL2_GPDO102_PDO_n_MASK) 2317 /*! @} */ 2318 2319 /*! @name GPDO101 - SIUL2 GPIO Pad Data Output Register */ 2320 /*! @{ */ 2321 2322 #define SIUL2_GPDO101_PDO_n_MASK (0x1U) 2323 #define SIUL2_GPDO101_PDO_n_SHIFT (0U) 2324 #define SIUL2_GPDO101_PDO_n_WIDTH (1U) 2325 #define SIUL2_GPDO101_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO101_PDO_n_SHIFT)) & SIUL2_GPDO101_PDO_n_MASK) 2326 /*! @} */ 2327 2328 /*! @name GPDO100 - SIUL2 GPIO Pad Data Output Register */ 2329 /*! @{ */ 2330 2331 #define SIUL2_GPDO100_PDO_n_MASK (0x1U) 2332 #define SIUL2_GPDO100_PDO_n_SHIFT (0U) 2333 #define SIUL2_GPDO100_PDO_n_WIDTH (1U) 2334 #define SIUL2_GPDO100_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO100_PDO_n_SHIFT)) & SIUL2_GPDO100_PDO_n_MASK) 2335 /*! @} */ 2336 2337 /*! @name GPDO107 - SIUL2 GPIO Pad Data Output Register */ 2338 /*! @{ */ 2339 2340 #define SIUL2_GPDO107_PDO_n_MASK (0x1U) 2341 #define SIUL2_GPDO107_PDO_n_SHIFT (0U) 2342 #define SIUL2_GPDO107_PDO_n_WIDTH (1U) 2343 #define SIUL2_GPDO107_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO107_PDO_n_SHIFT)) & SIUL2_GPDO107_PDO_n_MASK) 2344 /*! @} */ 2345 2346 /*! @name GPDO106 - SIUL2 GPIO Pad Data Output Register */ 2347 /*! @{ */ 2348 2349 #define SIUL2_GPDO106_PDO_n_MASK (0x1U) 2350 #define SIUL2_GPDO106_PDO_n_SHIFT (0U) 2351 #define SIUL2_GPDO106_PDO_n_WIDTH (1U) 2352 #define SIUL2_GPDO106_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO106_PDO_n_SHIFT)) & SIUL2_GPDO106_PDO_n_MASK) 2353 /*! @} */ 2354 2355 /*! @name GPDO105 - SIUL2 GPIO Pad Data Output Register */ 2356 /*! @{ */ 2357 2358 #define SIUL2_GPDO105_PDO_n_MASK (0x1U) 2359 #define SIUL2_GPDO105_PDO_n_SHIFT (0U) 2360 #define SIUL2_GPDO105_PDO_n_WIDTH (1U) 2361 #define SIUL2_GPDO105_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO105_PDO_n_SHIFT)) & SIUL2_GPDO105_PDO_n_MASK) 2362 /*! @} */ 2363 2364 /*! @name GPDO104 - SIUL2 GPIO Pad Data Output Register */ 2365 /*! @{ */ 2366 2367 #define SIUL2_GPDO104_PDO_n_MASK (0x1U) 2368 #define SIUL2_GPDO104_PDO_n_SHIFT (0U) 2369 #define SIUL2_GPDO104_PDO_n_WIDTH (1U) 2370 #define SIUL2_GPDO104_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO104_PDO_n_SHIFT)) & SIUL2_GPDO104_PDO_n_MASK) 2371 /*! @} */ 2372 2373 /*! @name GPDO111 - SIUL2 GPIO Pad Data Output Register */ 2374 /*! @{ */ 2375 2376 #define SIUL2_GPDO111_PDO_n_MASK (0x1U) 2377 #define SIUL2_GPDO111_PDO_n_SHIFT (0U) 2378 #define SIUL2_GPDO111_PDO_n_WIDTH (1U) 2379 #define SIUL2_GPDO111_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO111_PDO_n_SHIFT)) & SIUL2_GPDO111_PDO_n_MASK) 2380 /*! @} */ 2381 2382 /*! @name GPDO110 - SIUL2 GPIO Pad Data Output Register */ 2383 /*! @{ */ 2384 2385 #define SIUL2_GPDO110_PDO_n_MASK (0x1U) 2386 #define SIUL2_GPDO110_PDO_n_SHIFT (0U) 2387 #define SIUL2_GPDO110_PDO_n_WIDTH (1U) 2388 #define SIUL2_GPDO110_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO110_PDO_n_SHIFT)) & SIUL2_GPDO110_PDO_n_MASK) 2389 /*! @} */ 2390 2391 /*! @name GPDO109 - SIUL2 GPIO Pad Data Output Register */ 2392 /*! @{ */ 2393 2394 #define SIUL2_GPDO109_PDO_n_MASK (0x1U) 2395 #define SIUL2_GPDO109_PDO_n_SHIFT (0U) 2396 #define SIUL2_GPDO109_PDO_n_WIDTH (1U) 2397 #define SIUL2_GPDO109_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO109_PDO_n_SHIFT)) & SIUL2_GPDO109_PDO_n_MASK) 2398 /*! @} */ 2399 2400 /*! @name GPDO108 - SIUL2 GPIO Pad Data Output Register */ 2401 /*! @{ */ 2402 2403 #define SIUL2_GPDO108_PDO_n_MASK (0x1U) 2404 #define SIUL2_GPDO108_PDO_n_SHIFT (0U) 2405 #define SIUL2_GPDO108_PDO_n_WIDTH (1U) 2406 #define SIUL2_GPDO108_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO108_PDO_n_SHIFT)) & SIUL2_GPDO108_PDO_n_MASK) 2407 /*! @} */ 2408 2409 /*! @name GPDO115 - SIUL2 GPIO Pad Data Output Register */ 2410 /*! @{ */ 2411 2412 #define SIUL2_GPDO115_PDO_n_MASK (0x1U) 2413 #define SIUL2_GPDO115_PDO_n_SHIFT (0U) 2414 #define SIUL2_GPDO115_PDO_n_WIDTH (1U) 2415 #define SIUL2_GPDO115_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO115_PDO_n_SHIFT)) & SIUL2_GPDO115_PDO_n_MASK) 2416 /*! @} */ 2417 2418 /*! @name GPDO114 - SIUL2 GPIO Pad Data Output Register */ 2419 /*! @{ */ 2420 2421 #define SIUL2_GPDO114_PDO_n_MASK (0x1U) 2422 #define SIUL2_GPDO114_PDO_n_SHIFT (0U) 2423 #define SIUL2_GPDO114_PDO_n_WIDTH (1U) 2424 #define SIUL2_GPDO114_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO114_PDO_n_SHIFT)) & SIUL2_GPDO114_PDO_n_MASK) 2425 /*! @} */ 2426 2427 /*! @name GPDO113 - SIUL2 GPIO Pad Data Output Register */ 2428 /*! @{ */ 2429 2430 #define SIUL2_GPDO113_PDO_n_MASK (0x1U) 2431 #define SIUL2_GPDO113_PDO_n_SHIFT (0U) 2432 #define SIUL2_GPDO113_PDO_n_WIDTH (1U) 2433 #define SIUL2_GPDO113_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO113_PDO_n_SHIFT)) & SIUL2_GPDO113_PDO_n_MASK) 2434 /*! @} */ 2435 2436 /*! @name GPDO112 - SIUL2 GPIO Pad Data Output Register */ 2437 /*! @{ */ 2438 2439 #define SIUL2_GPDO112_PDO_n_MASK (0x1U) 2440 #define SIUL2_GPDO112_PDO_n_SHIFT (0U) 2441 #define SIUL2_GPDO112_PDO_n_WIDTH (1U) 2442 #define SIUL2_GPDO112_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO112_PDO_n_SHIFT)) & SIUL2_GPDO112_PDO_n_MASK) 2443 /*! @} */ 2444 2445 /*! @name GPDO119 - SIUL2 GPIO Pad Data Output Register */ 2446 /*! @{ */ 2447 2448 #define SIUL2_GPDO119_PDO_n_MASK (0x1U) 2449 #define SIUL2_GPDO119_PDO_n_SHIFT (0U) 2450 #define SIUL2_GPDO119_PDO_n_WIDTH (1U) 2451 #define SIUL2_GPDO119_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO119_PDO_n_SHIFT)) & SIUL2_GPDO119_PDO_n_MASK) 2452 /*! @} */ 2453 2454 /*! @name GPDO118 - SIUL2 GPIO Pad Data Output Register */ 2455 /*! @{ */ 2456 2457 #define SIUL2_GPDO118_PDO_n_MASK (0x1U) 2458 #define SIUL2_GPDO118_PDO_n_SHIFT (0U) 2459 #define SIUL2_GPDO118_PDO_n_WIDTH (1U) 2460 #define SIUL2_GPDO118_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO118_PDO_n_SHIFT)) & SIUL2_GPDO118_PDO_n_MASK) 2461 /*! @} */ 2462 2463 /*! @name GPDO117 - SIUL2 GPIO Pad Data Output Register */ 2464 /*! @{ */ 2465 2466 #define SIUL2_GPDO117_PDO_n_MASK (0x1U) 2467 #define SIUL2_GPDO117_PDO_n_SHIFT (0U) 2468 #define SIUL2_GPDO117_PDO_n_WIDTH (1U) 2469 #define SIUL2_GPDO117_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO117_PDO_n_SHIFT)) & SIUL2_GPDO117_PDO_n_MASK) 2470 /*! @} */ 2471 2472 /*! @name GPDO116 - SIUL2 GPIO Pad Data Output Register */ 2473 /*! @{ */ 2474 2475 #define SIUL2_GPDO116_PDO_n_MASK (0x1U) 2476 #define SIUL2_GPDO116_PDO_n_SHIFT (0U) 2477 #define SIUL2_GPDO116_PDO_n_WIDTH (1U) 2478 #define SIUL2_GPDO116_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO116_PDO_n_SHIFT)) & SIUL2_GPDO116_PDO_n_MASK) 2479 /*! @} */ 2480 2481 /*! @name GPDO123 - SIUL2 GPIO Pad Data Output Register */ 2482 /*! @{ */ 2483 2484 #define SIUL2_GPDO123_PDO_n_MASK (0x1U) 2485 #define SIUL2_GPDO123_PDO_n_SHIFT (0U) 2486 #define SIUL2_GPDO123_PDO_n_WIDTH (1U) 2487 #define SIUL2_GPDO123_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO123_PDO_n_SHIFT)) & SIUL2_GPDO123_PDO_n_MASK) 2488 /*! @} */ 2489 2490 /*! @name GPDO122 - SIUL2 GPIO Pad Data Output Register */ 2491 /*! @{ */ 2492 2493 #define SIUL2_GPDO122_PDO_n_MASK (0x1U) 2494 #define SIUL2_GPDO122_PDO_n_SHIFT (0U) 2495 #define SIUL2_GPDO122_PDO_n_WIDTH (1U) 2496 #define SIUL2_GPDO122_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO122_PDO_n_SHIFT)) & SIUL2_GPDO122_PDO_n_MASK) 2497 /*! @} */ 2498 2499 /*! @name GPDO121 - SIUL2 GPIO Pad Data Output Register */ 2500 /*! @{ */ 2501 2502 #define SIUL2_GPDO121_PDO_n_MASK (0x1U) 2503 #define SIUL2_GPDO121_PDO_n_SHIFT (0U) 2504 #define SIUL2_GPDO121_PDO_n_WIDTH (1U) 2505 #define SIUL2_GPDO121_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO121_PDO_n_SHIFT)) & SIUL2_GPDO121_PDO_n_MASK) 2506 /*! @} */ 2507 2508 /*! @name GPDO120 - SIUL2 GPIO Pad Data Output Register */ 2509 /*! @{ */ 2510 2511 #define SIUL2_GPDO120_PDO_n_MASK (0x1U) 2512 #define SIUL2_GPDO120_PDO_n_SHIFT (0U) 2513 #define SIUL2_GPDO120_PDO_n_WIDTH (1U) 2514 #define SIUL2_GPDO120_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO120_PDO_n_SHIFT)) & SIUL2_GPDO120_PDO_n_MASK) 2515 /*! @} */ 2516 2517 /*! @name GPDO127 - SIUL2 GPIO Pad Data Output Register */ 2518 /*! @{ */ 2519 2520 #define SIUL2_GPDO127_PDO_n_MASK (0x1U) 2521 #define SIUL2_GPDO127_PDO_n_SHIFT (0U) 2522 #define SIUL2_GPDO127_PDO_n_WIDTH (1U) 2523 #define SIUL2_GPDO127_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO127_PDO_n_SHIFT)) & SIUL2_GPDO127_PDO_n_MASK) 2524 /*! @} */ 2525 2526 /*! @name GPDO126 - SIUL2 GPIO Pad Data Output Register */ 2527 /*! @{ */ 2528 2529 #define SIUL2_GPDO126_PDO_n_MASK (0x1U) 2530 #define SIUL2_GPDO126_PDO_n_SHIFT (0U) 2531 #define SIUL2_GPDO126_PDO_n_WIDTH (1U) 2532 #define SIUL2_GPDO126_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO126_PDO_n_SHIFT)) & SIUL2_GPDO126_PDO_n_MASK) 2533 /*! @} */ 2534 2535 /*! @name GPDO125 - SIUL2 GPIO Pad Data Output Register */ 2536 /*! @{ */ 2537 2538 #define SIUL2_GPDO125_PDO_n_MASK (0x1U) 2539 #define SIUL2_GPDO125_PDO_n_SHIFT (0U) 2540 #define SIUL2_GPDO125_PDO_n_WIDTH (1U) 2541 #define SIUL2_GPDO125_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO125_PDO_n_SHIFT)) & SIUL2_GPDO125_PDO_n_MASK) 2542 /*! @} */ 2543 2544 /*! @name GPDO124 - SIUL2 GPIO Pad Data Output Register */ 2545 /*! @{ */ 2546 2547 #define SIUL2_GPDO124_PDO_n_MASK (0x1U) 2548 #define SIUL2_GPDO124_PDO_n_SHIFT (0U) 2549 #define SIUL2_GPDO124_PDO_n_WIDTH (1U) 2550 #define SIUL2_GPDO124_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO124_PDO_n_SHIFT)) & SIUL2_GPDO124_PDO_n_MASK) 2551 /*! @} */ 2552 2553 /*! @name GPDO131 - SIUL2 GPIO Pad Data Output Register */ 2554 /*! @{ */ 2555 2556 #define SIUL2_GPDO131_PDO_n_MASK (0x1U) 2557 #define SIUL2_GPDO131_PDO_n_SHIFT (0U) 2558 #define SIUL2_GPDO131_PDO_n_WIDTH (1U) 2559 #define SIUL2_GPDO131_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO131_PDO_n_SHIFT)) & SIUL2_GPDO131_PDO_n_MASK) 2560 /*! @} */ 2561 2562 /*! @name GPDO130 - SIUL2 GPIO Pad Data Output Register */ 2563 /*! @{ */ 2564 2565 #define SIUL2_GPDO130_PDO_n_MASK (0x1U) 2566 #define SIUL2_GPDO130_PDO_n_SHIFT (0U) 2567 #define SIUL2_GPDO130_PDO_n_WIDTH (1U) 2568 #define SIUL2_GPDO130_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO130_PDO_n_SHIFT)) & SIUL2_GPDO130_PDO_n_MASK) 2569 /*! @} */ 2570 2571 /*! @name GPDO129 - SIUL2 GPIO Pad Data Output Register */ 2572 /*! @{ */ 2573 2574 #define SIUL2_GPDO129_PDO_n_MASK (0x1U) 2575 #define SIUL2_GPDO129_PDO_n_SHIFT (0U) 2576 #define SIUL2_GPDO129_PDO_n_WIDTH (1U) 2577 #define SIUL2_GPDO129_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO129_PDO_n_SHIFT)) & SIUL2_GPDO129_PDO_n_MASK) 2578 /*! @} */ 2579 2580 /*! @name GPDO128 - SIUL2 GPIO Pad Data Output Register */ 2581 /*! @{ */ 2582 2583 #define SIUL2_GPDO128_PDO_n_MASK (0x1U) 2584 #define SIUL2_GPDO128_PDO_n_SHIFT (0U) 2585 #define SIUL2_GPDO128_PDO_n_WIDTH (1U) 2586 #define SIUL2_GPDO128_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO128_PDO_n_SHIFT)) & SIUL2_GPDO128_PDO_n_MASK) 2587 /*! @} */ 2588 2589 /*! @name GPDO135 - SIUL2 GPIO Pad Data Output Register */ 2590 /*! @{ */ 2591 2592 #define SIUL2_GPDO135_PDO_n_MASK (0x1U) 2593 #define SIUL2_GPDO135_PDO_n_SHIFT (0U) 2594 #define SIUL2_GPDO135_PDO_n_WIDTH (1U) 2595 #define SIUL2_GPDO135_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO135_PDO_n_SHIFT)) & SIUL2_GPDO135_PDO_n_MASK) 2596 /*! @} */ 2597 2598 /*! @name GPDO134 - SIUL2 GPIO Pad Data Output Register */ 2599 /*! @{ */ 2600 2601 #define SIUL2_GPDO134_PDO_n_MASK (0x1U) 2602 #define SIUL2_GPDO134_PDO_n_SHIFT (0U) 2603 #define SIUL2_GPDO134_PDO_n_WIDTH (1U) 2604 #define SIUL2_GPDO134_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO134_PDO_n_SHIFT)) & SIUL2_GPDO134_PDO_n_MASK) 2605 /*! @} */ 2606 2607 /*! @name GPDO133 - SIUL2 GPIO Pad Data Output Register */ 2608 /*! @{ */ 2609 2610 #define SIUL2_GPDO133_PDO_n_MASK (0x1U) 2611 #define SIUL2_GPDO133_PDO_n_SHIFT (0U) 2612 #define SIUL2_GPDO133_PDO_n_WIDTH (1U) 2613 #define SIUL2_GPDO133_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO133_PDO_n_SHIFT)) & SIUL2_GPDO133_PDO_n_MASK) 2614 /*! @} */ 2615 2616 /*! @name GPDO132 - SIUL2 GPIO Pad Data Output Register */ 2617 /*! @{ */ 2618 2619 #define SIUL2_GPDO132_PDO_n_MASK (0x1U) 2620 #define SIUL2_GPDO132_PDO_n_SHIFT (0U) 2621 #define SIUL2_GPDO132_PDO_n_WIDTH (1U) 2622 #define SIUL2_GPDO132_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO132_PDO_n_SHIFT)) & SIUL2_GPDO132_PDO_n_MASK) 2623 /*! @} */ 2624 2625 /*! @name GPDO139 - SIUL2 GPIO Pad Data Output Register */ 2626 /*! @{ */ 2627 2628 #define SIUL2_GPDO139_PDO_n_MASK (0x1U) 2629 #define SIUL2_GPDO139_PDO_n_SHIFT (0U) 2630 #define SIUL2_GPDO139_PDO_n_WIDTH (1U) 2631 #define SIUL2_GPDO139_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO139_PDO_n_SHIFT)) & SIUL2_GPDO139_PDO_n_MASK) 2632 /*! @} */ 2633 2634 /*! @name GPDO138 - SIUL2 GPIO Pad Data Output Register */ 2635 /*! @{ */ 2636 2637 #define SIUL2_GPDO138_PDO_n_MASK (0x1U) 2638 #define SIUL2_GPDO138_PDO_n_SHIFT (0U) 2639 #define SIUL2_GPDO138_PDO_n_WIDTH (1U) 2640 #define SIUL2_GPDO138_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO138_PDO_n_SHIFT)) & SIUL2_GPDO138_PDO_n_MASK) 2641 /*! @} */ 2642 2643 /*! @name GPDO137 - SIUL2 GPIO Pad Data Output Register */ 2644 /*! @{ */ 2645 2646 #define SIUL2_GPDO137_PDO_n_MASK (0x1U) 2647 #define SIUL2_GPDO137_PDO_n_SHIFT (0U) 2648 #define SIUL2_GPDO137_PDO_n_WIDTH (1U) 2649 #define SIUL2_GPDO137_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO137_PDO_n_SHIFT)) & SIUL2_GPDO137_PDO_n_MASK) 2650 /*! @} */ 2651 2652 /*! @name GPDO136 - SIUL2 GPIO Pad Data Output Register */ 2653 /*! @{ */ 2654 2655 #define SIUL2_GPDO136_PDO_n_MASK (0x1U) 2656 #define SIUL2_GPDO136_PDO_n_SHIFT (0U) 2657 #define SIUL2_GPDO136_PDO_n_WIDTH (1U) 2658 #define SIUL2_GPDO136_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO136_PDO_n_SHIFT)) & SIUL2_GPDO136_PDO_n_MASK) 2659 /*! @} */ 2660 2661 /*! @name GPDO143 - SIUL2 GPIO Pad Data Output Register */ 2662 /*! @{ */ 2663 2664 #define SIUL2_GPDO143_PDO_n_MASK (0x1U) 2665 #define SIUL2_GPDO143_PDO_n_SHIFT (0U) 2666 #define SIUL2_GPDO143_PDO_n_WIDTH (1U) 2667 #define SIUL2_GPDO143_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO143_PDO_n_SHIFT)) & SIUL2_GPDO143_PDO_n_MASK) 2668 /*! @} */ 2669 2670 /*! @name GPDO142 - SIUL2 GPIO Pad Data Output Register */ 2671 /*! @{ */ 2672 2673 #define SIUL2_GPDO142_PDO_n_MASK (0x1U) 2674 #define SIUL2_GPDO142_PDO_n_SHIFT (0U) 2675 #define SIUL2_GPDO142_PDO_n_WIDTH (1U) 2676 #define SIUL2_GPDO142_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO142_PDO_n_SHIFT)) & SIUL2_GPDO142_PDO_n_MASK) 2677 /*! @} */ 2678 2679 /*! @name GPDO141 - SIUL2 GPIO Pad Data Output Register */ 2680 /*! @{ */ 2681 2682 #define SIUL2_GPDO141_PDO_n_MASK (0x1U) 2683 #define SIUL2_GPDO141_PDO_n_SHIFT (0U) 2684 #define SIUL2_GPDO141_PDO_n_WIDTH (1U) 2685 #define SIUL2_GPDO141_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO141_PDO_n_SHIFT)) & SIUL2_GPDO141_PDO_n_MASK) 2686 /*! @} */ 2687 2688 /*! @name GPDO140 - SIUL2 GPIO Pad Data Output Register */ 2689 /*! @{ */ 2690 2691 #define SIUL2_GPDO140_PDO_n_MASK (0x1U) 2692 #define SIUL2_GPDO140_PDO_n_SHIFT (0U) 2693 #define SIUL2_GPDO140_PDO_n_WIDTH (1U) 2694 #define SIUL2_GPDO140_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO140_PDO_n_SHIFT)) & SIUL2_GPDO140_PDO_n_MASK) 2695 /*! @} */ 2696 2697 /*! @name GPDO147 - SIUL2 GPIO Pad Data Output Register */ 2698 /*! @{ */ 2699 2700 #define SIUL2_GPDO147_PDO_n_MASK (0x1U) 2701 #define SIUL2_GPDO147_PDO_n_SHIFT (0U) 2702 #define SIUL2_GPDO147_PDO_n_WIDTH (1U) 2703 #define SIUL2_GPDO147_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO147_PDO_n_SHIFT)) & SIUL2_GPDO147_PDO_n_MASK) 2704 /*! @} */ 2705 2706 /*! @name GPDO146 - SIUL2 GPIO Pad Data Output Register */ 2707 /*! @{ */ 2708 2709 #define SIUL2_GPDO146_PDO_n_MASK (0x1U) 2710 #define SIUL2_GPDO146_PDO_n_SHIFT (0U) 2711 #define SIUL2_GPDO146_PDO_n_WIDTH (1U) 2712 #define SIUL2_GPDO146_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO146_PDO_n_SHIFT)) & SIUL2_GPDO146_PDO_n_MASK) 2713 /*! @} */ 2714 2715 /*! @name GPDO145 - SIUL2 GPIO Pad Data Output Register */ 2716 /*! @{ */ 2717 2718 #define SIUL2_GPDO145_PDO_n_MASK (0x1U) 2719 #define SIUL2_GPDO145_PDO_n_SHIFT (0U) 2720 #define SIUL2_GPDO145_PDO_n_WIDTH (1U) 2721 #define SIUL2_GPDO145_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO145_PDO_n_SHIFT)) & SIUL2_GPDO145_PDO_n_MASK) 2722 /*! @} */ 2723 2724 /*! @name GPDO144 - SIUL2 GPIO Pad Data Output Register */ 2725 /*! @{ */ 2726 2727 #define SIUL2_GPDO144_PDO_n_MASK (0x1U) 2728 #define SIUL2_GPDO144_PDO_n_SHIFT (0U) 2729 #define SIUL2_GPDO144_PDO_n_WIDTH (1U) 2730 #define SIUL2_GPDO144_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO144_PDO_n_SHIFT)) & SIUL2_GPDO144_PDO_n_MASK) 2731 /*! @} */ 2732 2733 /*! @name GPDO151 - SIUL2 GPIO Pad Data Output Register */ 2734 /*! @{ */ 2735 2736 #define SIUL2_GPDO151_PDO_n_MASK (0x1U) 2737 #define SIUL2_GPDO151_PDO_n_SHIFT (0U) 2738 #define SIUL2_GPDO151_PDO_n_WIDTH (1U) 2739 #define SIUL2_GPDO151_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO151_PDO_n_SHIFT)) & SIUL2_GPDO151_PDO_n_MASK) 2740 /*! @} */ 2741 2742 /*! @name GPDO150 - SIUL2 GPIO Pad Data Output Register */ 2743 /*! @{ */ 2744 2745 #define SIUL2_GPDO150_PDO_n_MASK (0x1U) 2746 #define SIUL2_GPDO150_PDO_n_SHIFT (0U) 2747 #define SIUL2_GPDO150_PDO_n_WIDTH (1U) 2748 #define SIUL2_GPDO150_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO150_PDO_n_SHIFT)) & SIUL2_GPDO150_PDO_n_MASK) 2749 /*! @} */ 2750 2751 /*! @name GPDO149 - SIUL2 GPIO Pad Data Output Register */ 2752 /*! @{ */ 2753 2754 #define SIUL2_GPDO149_PDO_n_MASK (0x1U) 2755 #define SIUL2_GPDO149_PDO_n_SHIFT (0U) 2756 #define SIUL2_GPDO149_PDO_n_WIDTH (1U) 2757 #define SIUL2_GPDO149_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO149_PDO_n_SHIFT)) & SIUL2_GPDO149_PDO_n_MASK) 2758 /*! @} */ 2759 2760 /*! @name GPDO148 - SIUL2 GPIO Pad Data Output Register */ 2761 /*! @{ */ 2762 2763 #define SIUL2_GPDO148_PDO_n_MASK (0x1U) 2764 #define SIUL2_GPDO148_PDO_n_SHIFT (0U) 2765 #define SIUL2_GPDO148_PDO_n_WIDTH (1U) 2766 #define SIUL2_GPDO148_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO148_PDO_n_SHIFT)) & SIUL2_GPDO148_PDO_n_MASK) 2767 /*! @} */ 2768 2769 /*! @name GPDO155 - SIUL2 GPIO Pad Data Output Register */ 2770 /*! @{ */ 2771 2772 #define SIUL2_GPDO155_PDO_n_MASK (0x1U) 2773 #define SIUL2_GPDO155_PDO_n_SHIFT (0U) 2774 #define SIUL2_GPDO155_PDO_n_WIDTH (1U) 2775 #define SIUL2_GPDO155_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO155_PDO_n_SHIFT)) & SIUL2_GPDO155_PDO_n_MASK) 2776 /*! @} */ 2777 2778 /*! @name GPDO154 - SIUL2 GPIO Pad Data Output Register */ 2779 /*! @{ */ 2780 2781 #define SIUL2_GPDO154_PDO_n_MASK (0x1U) 2782 #define SIUL2_GPDO154_PDO_n_SHIFT (0U) 2783 #define SIUL2_GPDO154_PDO_n_WIDTH (1U) 2784 #define SIUL2_GPDO154_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO154_PDO_n_SHIFT)) & SIUL2_GPDO154_PDO_n_MASK) 2785 /*! @} */ 2786 2787 /*! @name GPDO153 - SIUL2 GPIO Pad Data Output Register */ 2788 /*! @{ */ 2789 2790 #define SIUL2_GPDO153_PDO_n_MASK (0x1U) 2791 #define SIUL2_GPDO153_PDO_n_SHIFT (0U) 2792 #define SIUL2_GPDO153_PDO_n_WIDTH (1U) 2793 #define SIUL2_GPDO153_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO153_PDO_n_SHIFT)) & SIUL2_GPDO153_PDO_n_MASK) 2794 /*! @} */ 2795 2796 /*! @name GPDO152 - SIUL2 GPIO Pad Data Output Register */ 2797 /*! @{ */ 2798 2799 #define SIUL2_GPDO152_PDO_n_MASK (0x1U) 2800 #define SIUL2_GPDO152_PDO_n_SHIFT (0U) 2801 #define SIUL2_GPDO152_PDO_n_WIDTH (1U) 2802 #define SIUL2_GPDO152_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO152_PDO_n_SHIFT)) & SIUL2_GPDO152_PDO_n_MASK) 2803 /*! @} */ 2804 2805 /*! @name GPDO159 - SIUL2 GPIO Pad Data Output Register */ 2806 /*! @{ */ 2807 2808 #define SIUL2_GPDO159_PDO_n_MASK (0x1U) 2809 #define SIUL2_GPDO159_PDO_n_SHIFT (0U) 2810 #define SIUL2_GPDO159_PDO_n_WIDTH (1U) 2811 #define SIUL2_GPDO159_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO159_PDO_n_SHIFT)) & SIUL2_GPDO159_PDO_n_MASK) 2812 /*! @} */ 2813 2814 /*! @name GPDO158 - SIUL2 GPIO Pad Data Output Register */ 2815 /*! @{ */ 2816 2817 #define SIUL2_GPDO158_PDO_n_MASK (0x1U) 2818 #define SIUL2_GPDO158_PDO_n_SHIFT (0U) 2819 #define SIUL2_GPDO158_PDO_n_WIDTH (1U) 2820 #define SIUL2_GPDO158_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO158_PDO_n_SHIFT)) & SIUL2_GPDO158_PDO_n_MASK) 2821 /*! @} */ 2822 2823 /*! @name GPDO157 - SIUL2 GPIO Pad Data Output Register */ 2824 /*! @{ */ 2825 2826 #define SIUL2_GPDO157_PDO_n_MASK (0x1U) 2827 #define SIUL2_GPDO157_PDO_n_SHIFT (0U) 2828 #define SIUL2_GPDO157_PDO_n_WIDTH (1U) 2829 #define SIUL2_GPDO157_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO157_PDO_n_SHIFT)) & SIUL2_GPDO157_PDO_n_MASK) 2830 /*! @} */ 2831 2832 /*! @name GPDO156 - SIUL2 GPIO Pad Data Output Register */ 2833 /*! @{ */ 2834 2835 #define SIUL2_GPDO156_PDO_n_MASK (0x1U) 2836 #define SIUL2_GPDO156_PDO_n_SHIFT (0U) 2837 #define SIUL2_GPDO156_PDO_n_WIDTH (1U) 2838 #define SIUL2_GPDO156_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO156_PDO_n_SHIFT)) & SIUL2_GPDO156_PDO_n_MASK) 2839 /*! @} */ 2840 2841 /*! @name GPDO163 - SIUL2 GPIO Pad Data Output Register */ 2842 /*! @{ */ 2843 2844 #define SIUL2_GPDO163_PDO_n_MASK (0x1U) 2845 #define SIUL2_GPDO163_PDO_n_SHIFT (0U) 2846 #define SIUL2_GPDO163_PDO_n_WIDTH (1U) 2847 #define SIUL2_GPDO163_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO163_PDO_n_SHIFT)) & SIUL2_GPDO163_PDO_n_MASK) 2848 /*! @} */ 2849 2850 /*! @name GPDO162 - SIUL2 GPIO Pad Data Output Register */ 2851 /*! @{ */ 2852 2853 #define SIUL2_GPDO162_PDO_n_MASK (0x1U) 2854 #define SIUL2_GPDO162_PDO_n_SHIFT (0U) 2855 #define SIUL2_GPDO162_PDO_n_WIDTH (1U) 2856 #define SIUL2_GPDO162_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO162_PDO_n_SHIFT)) & SIUL2_GPDO162_PDO_n_MASK) 2857 /*! @} */ 2858 2859 /*! @name GPDO161 - SIUL2 GPIO Pad Data Output Register */ 2860 /*! @{ */ 2861 2862 #define SIUL2_GPDO161_PDO_n_MASK (0x1U) 2863 #define SIUL2_GPDO161_PDO_n_SHIFT (0U) 2864 #define SIUL2_GPDO161_PDO_n_WIDTH (1U) 2865 #define SIUL2_GPDO161_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO161_PDO_n_SHIFT)) & SIUL2_GPDO161_PDO_n_MASK) 2866 /*! @} */ 2867 2868 /*! @name GPDO160 - SIUL2 GPIO Pad Data Output Register */ 2869 /*! @{ */ 2870 2871 #define SIUL2_GPDO160_PDO_n_MASK (0x1U) 2872 #define SIUL2_GPDO160_PDO_n_SHIFT (0U) 2873 #define SIUL2_GPDO160_PDO_n_WIDTH (1U) 2874 #define SIUL2_GPDO160_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO160_PDO_n_SHIFT)) & SIUL2_GPDO160_PDO_n_MASK) 2875 /*! @} */ 2876 2877 /*! @name GPDO167 - SIUL2 GPIO Pad Data Output Register */ 2878 /*! @{ */ 2879 2880 #define SIUL2_GPDO167_PDO_n_MASK (0x1U) 2881 #define SIUL2_GPDO167_PDO_n_SHIFT (0U) 2882 #define SIUL2_GPDO167_PDO_n_WIDTH (1U) 2883 #define SIUL2_GPDO167_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO167_PDO_n_SHIFT)) & SIUL2_GPDO167_PDO_n_MASK) 2884 /*! @} */ 2885 2886 /*! @name GPDO166 - SIUL2 GPIO Pad Data Output Register */ 2887 /*! @{ */ 2888 2889 #define SIUL2_GPDO166_PDO_n_MASK (0x1U) 2890 #define SIUL2_GPDO166_PDO_n_SHIFT (0U) 2891 #define SIUL2_GPDO166_PDO_n_WIDTH (1U) 2892 #define SIUL2_GPDO166_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO166_PDO_n_SHIFT)) & SIUL2_GPDO166_PDO_n_MASK) 2893 /*! @} */ 2894 2895 /*! @name GPDO165 - SIUL2 GPIO Pad Data Output Register */ 2896 /*! @{ */ 2897 2898 #define SIUL2_GPDO165_PDO_n_MASK (0x1U) 2899 #define SIUL2_GPDO165_PDO_n_SHIFT (0U) 2900 #define SIUL2_GPDO165_PDO_n_WIDTH (1U) 2901 #define SIUL2_GPDO165_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO165_PDO_n_SHIFT)) & SIUL2_GPDO165_PDO_n_MASK) 2902 /*! @} */ 2903 2904 /*! @name GPDO164 - SIUL2 GPIO Pad Data Output Register */ 2905 /*! @{ */ 2906 2907 #define SIUL2_GPDO164_PDO_n_MASK (0x1U) 2908 #define SIUL2_GPDO164_PDO_n_SHIFT (0U) 2909 #define SIUL2_GPDO164_PDO_n_WIDTH (1U) 2910 #define SIUL2_GPDO164_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO164_PDO_n_SHIFT)) & SIUL2_GPDO164_PDO_n_MASK) 2911 /*! @} */ 2912 2913 /*! @name GPDO171 - SIUL2 GPIO Pad Data Output Register */ 2914 /*! @{ */ 2915 2916 #define SIUL2_GPDO171_PDO_n_MASK (0x1U) 2917 #define SIUL2_GPDO171_PDO_n_SHIFT (0U) 2918 #define SIUL2_GPDO171_PDO_n_WIDTH (1U) 2919 #define SIUL2_GPDO171_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO171_PDO_n_SHIFT)) & SIUL2_GPDO171_PDO_n_MASK) 2920 /*! @} */ 2921 2922 /*! @name GPDO170 - SIUL2 GPIO Pad Data Output Register */ 2923 /*! @{ */ 2924 2925 #define SIUL2_GPDO170_PDO_n_MASK (0x1U) 2926 #define SIUL2_GPDO170_PDO_n_SHIFT (0U) 2927 #define SIUL2_GPDO170_PDO_n_WIDTH (1U) 2928 #define SIUL2_GPDO170_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO170_PDO_n_SHIFT)) & SIUL2_GPDO170_PDO_n_MASK) 2929 /*! @} */ 2930 2931 /*! @name GPDO169 - SIUL2 GPIO Pad Data Output Register */ 2932 /*! @{ */ 2933 2934 #define SIUL2_GPDO169_PDO_n_MASK (0x1U) 2935 #define SIUL2_GPDO169_PDO_n_SHIFT (0U) 2936 #define SIUL2_GPDO169_PDO_n_WIDTH (1U) 2937 #define SIUL2_GPDO169_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO169_PDO_n_SHIFT)) & SIUL2_GPDO169_PDO_n_MASK) 2938 /*! @} */ 2939 2940 /*! @name GPDO168 - SIUL2 GPIO Pad Data Output Register */ 2941 /*! @{ */ 2942 2943 #define SIUL2_GPDO168_PDO_n_MASK (0x1U) 2944 #define SIUL2_GPDO168_PDO_n_SHIFT (0U) 2945 #define SIUL2_GPDO168_PDO_n_WIDTH (1U) 2946 #define SIUL2_GPDO168_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO168_PDO_n_SHIFT)) & SIUL2_GPDO168_PDO_n_MASK) 2947 /*! @} */ 2948 2949 /*! @name GPDO173 - SIUL2 GPIO Pad Data Output Register */ 2950 /*! @{ */ 2951 2952 #define SIUL2_GPDO173_PDO_n_MASK (0x1U) 2953 #define SIUL2_GPDO173_PDO_n_SHIFT (0U) 2954 #define SIUL2_GPDO173_PDO_n_WIDTH (1U) 2955 #define SIUL2_GPDO173_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO173_PDO_n_SHIFT)) & SIUL2_GPDO173_PDO_n_MASK) 2956 /*! @} */ 2957 2958 /*! @name GPDO172 - SIUL2 GPIO Pad Data Output Register */ 2959 /*! @{ */ 2960 2961 #define SIUL2_GPDO172_PDO_n_MASK (0x1U) 2962 #define SIUL2_GPDO172_PDO_n_SHIFT (0U) 2963 #define SIUL2_GPDO172_PDO_n_WIDTH (1U) 2964 #define SIUL2_GPDO172_PDO_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDO172_PDO_n_SHIFT)) & SIUL2_GPDO172_PDO_n_MASK) 2965 /*! @} */ 2966 2967 /*! @name GPDI3 - SIUL2 GPIO Pad Data Input Register */ 2968 /*! @{ */ 2969 2970 #define SIUL2_GPDI3_PDI_n_MASK (0x1U) 2971 #define SIUL2_GPDI3_PDI_n_SHIFT (0U) 2972 #define SIUL2_GPDI3_PDI_n_WIDTH (1U) 2973 #define SIUL2_GPDI3_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI3_PDI_n_SHIFT)) & SIUL2_GPDI3_PDI_n_MASK) 2974 /*! @} */ 2975 2976 /*! @name GPDI2 - SIUL2 GPIO Pad Data Input Register */ 2977 /*! @{ */ 2978 2979 #define SIUL2_GPDI2_PDI_n_MASK (0x1U) 2980 #define SIUL2_GPDI2_PDI_n_SHIFT (0U) 2981 #define SIUL2_GPDI2_PDI_n_WIDTH (1U) 2982 #define SIUL2_GPDI2_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI2_PDI_n_SHIFT)) & SIUL2_GPDI2_PDI_n_MASK) 2983 /*! @} */ 2984 2985 /*! @name GPDI1 - SIUL2 GPIO Pad Data Input Register */ 2986 /*! @{ */ 2987 2988 #define SIUL2_GPDI1_PDI_n_MASK (0x1U) 2989 #define SIUL2_GPDI1_PDI_n_SHIFT (0U) 2990 #define SIUL2_GPDI1_PDI_n_WIDTH (1U) 2991 #define SIUL2_GPDI1_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI1_PDI_n_SHIFT)) & SIUL2_GPDI1_PDI_n_MASK) 2992 /*! @} */ 2993 2994 /*! @name GPDI0 - SIUL2 GPIO Pad Data Input Register */ 2995 /*! @{ */ 2996 2997 #define SIUL2_GPDI0_PDI_n_MASK (0x1U) 2998 #define SIUL2_GPDI0_PDI_n_SHIFT (0U) 2999 #define SIUL2_GPDI0_PDI_n_WIDTH (1U) 3000 #define SIUL2_GPDI0_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI0_PDI_n_SHIFT)) & SIUL2_GPDI0_PDI_n_MASK) 3001 /*! @} */ 3002 3003 /*! @name GPDI7 - SIUL2 GPIO Pad Data Input Register */ 3004 /*! @{ */ 3005 3006 #define SIUL2_GPDI7_PDI_n_MASK (0x1U) 3007 #define SIUL2_GPDI7_PDI_n_SHIFT (0U) 3008 #define SIUL2_GPDI7_PDI_n_WIDTH (1U) 3009 #define SIUL2_GPDI7_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI7_PDI_n_SHIFT)) & SIUL2_GPDI7_PDI_n_MASK) 3010 /*! @} */ 3011 3012 /*! @name GPDI6 - SIUL2 GPIO Pad Data Input Register */ 3013 /*! @{ */ 3014 3015 #define SIUL2_GPDI6_PDI_n_MASK (0x1U) 3016 #define SIUL2_GPDI6_PDI_n_SHIFT (0U) 3017 #define SIUL2_GPDI6_PDI_n_WIDTH (1U) 3018 #define SIUL2_GPDI6_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI6_PDI_n_SHIFT)) & SIUL2_GPDI6_PDI_n_MASK) 3019 /*! @} */ 3020 3021 /*! @name GPDI5 - SIUL2 GPIO Pad Data Input Register */ 3022 /*! @{ */ 3023 3024 #define SIUL2_GPDI5_PDI_n_MASK (0x1U) 3025 #define SIUL2_GPDI5_PDI_n_SHIFT (0U) 3026 #define SIUL2_GPDI5_PDI_n_WIDTH (1U) 3027 #define SIUL2_GPDI5_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI5_PDI_n_SHIFT)) & SIUL2_GPDI5_PDI_n_MASK) 3028 /*! @} */ 3029 3030 /*! @name GPDI4 - SIUL2 GPIO Pad Data Input Register */ 3031 /*! @{ */ 3032 3033 #define SIUL2_GPDI4_PDI_n_MASK (0x1U) 3034 #define SIUL2_GPDI4_PDI_n_SHIFT (0U) 3035 #define SIUL2_GPDI4_PDI_n_WIDTH (1U) 3036 #define SIUL2_GPDI4_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI4_PDI_n_SHIFT)) & SIUL2_GPDI4_PDI_n_MASK) 3037 /*! @} */ 3038 3039 /*! @name GPDI11 - SIUL2 GPIO Pad Data Input Register */ 3040 /*! @{ */ 3041 3042 #define SIUL2_GPDI11_PDI_n_MASK (0x1U) 3043 #define SIUL2_GPDI11_PDI_n_SHIFT (0U) 3044 #define SIUL2_GPDI11_PDI_n_WIDTH (1U) 3045 #define SIUL2_GPDI11_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI11_PDI_n_SHIFT)) & SIUL2_GPDI11_PDI_n_MASK) 3046 /*! @} */ 3047 3048 /*! @name GPDI10 - SIUL2 GPIO Pad Data Input Register */ 3049 /*! @{ */ 3050 3051 #define SIUL2_GPDI10_PDI_n_MASK (0x1U) 3052 #define SIUL2_GPDI10_PDI_n_SHIFT (0U) 3053 #define SIUL2_GPDI10_PDI_n_WIDTH (1U) 3054 #define SIUL2_GPDI10_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI10_PDI_n_SHIFT)) & SIUL2_GPDI10_PDI_n_MASK) 3055 /*! @} */ 3056 3057 /*! @name GPDI9 - SIUL2 GPIO Pad Data Input Register */ 3058 /*! @{ */ 3059 3060 #define SIUL2_GPDI9_PDI_n_MASK (0x1U) 3061 #define SIUL2_GPDI9_PDI_n_SHIFT (0U) 3062 #define SIUL2_GPDI9_PDI_n_WIDTH (1U) 3063 #define SIUL2_GPDI9_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI9_PDI_n_SHIFT)) & SIUL2_GPDI9_PDI_n_MASK) 3064 /*! @} */ 3065 3066 /*! @name GPDI8 - SIUL2 GPIO Pad Data Input Register */ 3067 /*! @{ */ 3068 3069 #define SIUL2_GPDI8_PDI_n_MASK (0x1U) 3070 #define SIUL2_GPDI8_PDI_n_SHIFT (0U) 3071 #define SIUL2_GPDI8_PDI_n_WIDTH (1U) 3072 #define SIUL2_GPDI8_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI8_PDI_n_SHIFT)) & SIUL2_GPDI8_PDI_n_MASK) 3073 /*! @} */ 3074 3075 /*! @name GPDI15 - SIUL2 GPIO Pad Data Input Register */ 3076 /*! @{ */ 3077 3078 #define SIUL2_GPDI15_PDI_n_MASK (0x1U) 3079 #define SIUL2_GPDI15_PDI_n_SHIFT (0U) 3080 #define SIUL2_GPDI15_PDI_n_WIDTH (1U) 3081 #define SIUL2_GPDI15_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI15_PDI_n_SHIFT)) & SIUL2_GPDI15_PDI_n_MASK) 3082 /*! @} */ 3083 3084 /*! @name GPDI14 - SIUL2 GPIO Pad Data Input Register */ 3085 /*! @{ */ 3086 3087 #define SIUL2_GPDI14_PDI_n_MASK (0x1U) 3088 #define SIUL2_GPDI14_PDI_n_SHIFT (0U) 3089 #define SIUL2_GPDI14_PDI_n_WIDTH (1U) 3090 #define SIUL2_GPDI14_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI14_PDI_n_SHIFT)) & SIUL2_GPDI14_PDI_n_MASK) 3091 /*! @} */ 3092 3093 /*! @name GPDI13 - SIUL2 GPIO Pad Data Input Register */ 3094 /*! @{ */ 3095 3096 #define SIUL2_GPDI13_PDI_n_MASK (0x1U) 3097 #define SIUL2_GPDI13_PDI_n_SHIFT (0U) 3098 #define SIUL2_GPDI13_PDI_n_WIDTH (1U) 3099 #define SIUL2_GPDI13_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI13_PDI_n_SHIFT)) & SIUL2_GPDI13_PDI_n_MASK) 3100 /*! @} */ 3101 3102 /*! @name GPDI12 - SIUL2 GPIO Pad Data Input Register */ 3103 /*! @{ */ 3104 3105 #define SIUL2_GPDI12_PDI_n_MASK (0x1U) 3106 #define SIUL2_GPDI12_PDI_n_SHIFT (0U) 3107 #define SIUL2_GPDI12_PDI_n_WIDTH (1U) 3108 #define SIUL2_GPDI12_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI12_PDI_n_SHIFT)) & SIUL2_GPDI12_PDI_n_MASK) 3109 /*! @} */ 3110 3111 /*! @name GPDI19 - SIUL2 GPIO Pad Data Input Register */ 3112 /*! @{ */ 3113 3114 #define SIUL2_GPDI19_PDI_n_MASK (0x1U) 3115 #define SIUL2_GPDI19_PDI_n_SHIFT (0U) 3116 #define SIUL2_GPDI19_PDI_n_WIDTH (1U) 3117 #define SIUL2_GPDI19_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI19_PDI_n_SHIFT)) & SIUL2_GPDI19_PDI_n_MASK) 3118 /*! @} */ 3119 3120 /*! @name GPDI18 - SIUL2 GPIO Pad Data Input Register */ 3121 /*! @{ */ 3122 3123 #define SIUL2_GPDI18_PDI_n_MASK (0x1U) 3124 #define SIUL2_GPDI18_PDI_n_SHIFT (0U) 3125 #define SIUL2_GPDI18_PDI_n_WIDTH (1U) 3126 #define SIUL2_GPDI18_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI18_PDI_n_SHIFT)) & SIUL2_GPDI18_PDI_n_MASK) 3127 /*! @} */ 3128 3129 /*! @name GPDI17 - SIUL2 GPIO Pad Data Input Register */ 3130 /*! @{ */ 3131 3132 #define SIUL2_GPDI17_PDI_n_MASK (0x1U) 3133 #define SIUL2_GPDI17_PDI_n_SHIFT (0U) 3134 #define SIUL2_GPDI17_PDI_n_WIDTH (1U) 3135 #define SIUL2_GPDI17_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI17_PDI_n_SHIFT)) & SIUL2_GPDI17_PDI_n_MASK) 3136 /*! @} */ 3137 3138 /*! @name GPDI16 - SIUL2 GPIO Pad Data Input Register */ 3139 /*! @{ */ 3140 3141 #define SIUL2_GPDI16_PDI_n_MASK (0x1U) 3142 #define SIUL2_GPDI16_PDI_n_SHIFT (0U) 3143 #define SIUL2_GPDI16_PDI_n_WIDTH (1U) 3144 #define SIUL2_GPDI16_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI16_PDI_n_SHIFT)) & SIUL2_GPDI16_PDI_n_MASK) 3145 /*! @} */ 3146 3147 /*! @name GPDI23 - SIUL2 GPIO Pad Data Input Register */ 3148 /*! @{ */ 3149 3150 #define SIUL2_GPDI23_PDI_n_MASK (0x1U) 3151 #define SIUL2_GPDI23_PDI_n_SHIFT (0U) 3152 #define SIUL2_GPDI23_PDI_n_WIDTH (1U) 3153 #define SIUL2_GPDI23_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI23_PDI_n_SHIFT)) & SIUL2_GPDI23_PDI_n_MASK) 3154 /*! @} */ 3155 3156 /*! @name GPDI22 - SIUL2 GPIO Pad Data Input Register */ 3157 /*! @{ */ 3158 3159 #define SIUL2_GPDI22_PDI_n_MASK (0x1U) 3160 #define SIUL2_GPDI22_PDI_n_SHIFT (0U) 3161 #define SIUL2_GPDI22_PDI_n_WIDTH (1U) 3162 #define SIUL2_GPDI22_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI22_PDI_n_SHIFT)) & SIUL2_GPDI22_PDI_n_MASK) 3163 /*! @} */ 3164 3165 /*! @name GPDI21 - SIUL2 GPIO Pad Data Input Register */ 3166 /*! @{ */ 3167 3168 #define SIUL2_GPDI21_PDI_n_MASK (0x1U) 3169 #define SIUL2_GPDI21_PDI_n_SHIFT (0U) 3170 #define SIUL2_GPDI21_PDI_n_WIDTH (1U) 3171 #define SIUL2_GPDI21_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI21_PDI_n_SHIFT)) & SIUL2_GPDI21_PDI_n_MASK) 3172 /*! @} */ 3173 3174 /*! @name GPDI20 - SIUL2 GPIO Pad Data Input Register */ 3175 /*! @{ */ 3176 3177 #define SIUL2_GPDI20_PDI_n_MASK (0x1U) 3178 #define SIUL2_GPDI20_PDI_n_SHIFT (0U) 3179 #define SIUL2_GPDI20_PDI_n_WIDTH (1U) 3180 #define SIUL2_GPDI20_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI20_PDI_n_SHIFT)) & SIUL2_GPDI20_PDI_n_MASK) 3181 /*! @} */ 3182 3183 /*! @name GPDI27 - SIUL2 GPIO Pad Data Input Register */ 3184 /*! @{ */ 3185 3186 #define SIUL2_GPDI27_PDI_n_MASK (0x1U) 3187 #define SIUL2_GPDI27_PDI_n_SHIFT (0U) 3188 #define SIUL2_GPDI27_PDI_n_WIDTH (1U) 3189 #define SIUL2_GPDI27_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI27_PDI_n_SHIFT)) & SIUL2_GPDI27_PDI_n_MASK) 3190 /*! @} */ 3191 3192 /*! @name GPDI26 - SIUL2 GPIO Pad Data Input Register */ 3193 /*! @{ */ 3194 3195 #define SIUL2_GPDI26_PDI_n_MASK (0x1U) 3196 #define SIUL2_GPDI26_PDI_n_SHIFT (0U) 3197 #define SIUL2_GPDI26_PDI_n_WIDTH (1U) 3198 #define SIUL2_GPDI26_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI26_PDI_n_SHIFT)) & SIUL2_GPDI26_PDI_n_MASK) 3199 /*! @} */ 3200 3201 /*! @name GPDI25 - SIUL2 GPIO Pad Data Input Register */ 3202 /*! @{ */ 3203 3204 #define SIUL2_GPDI25_PDI_n_MASK (0x1U) 3205 #define SIUL2_GPDI25_PDI_n_SHIFT (0U) 3206 #define SIUL2_GPDI25_PDI_n_WIDTH (1U) 3207 #define SIUL2_GPDI25_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI25_PDI_n_SHIFT)) & SIUL2_GPDI25_PDI_n_MASK) 3208 /*! @} */ 3209 3210 /*! @name GPDI24 - SIUL2 GPIO Pad Data Input Register */ 3211 /*! @{ */ 3212 3213 #define SIUL2_GPDI24_PDI_n_MASK (0x1U) 3214 #define SIUL2_GPDI24_PDI_n_SHIFT (0U) 3215 #define SIUL2_GPDI24_PDI_n_WIDTH (1U) 3216 #define SIUL2_GPDI24_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI24_PDI_n_SHIFT)) & SIUL2_GPDI24_PDI_n_MASK) 3217 /*! @} */ 3218 3219 /*! @name GPDI31 - SIUL2 GPIO Pad Data Input Register */ 3220 /*! @{ */ 3221 3222 #define SIUL2_GPDI31_PDI_n_MASK (0x1U) 3223 #define SIUL2_GPDI31_PDI_n_SHIFT (0U) 3224 #define SIUL2_GPDI31_PDI_n_WIDTH (1U) 3225 #define SIUL2_GPDI31_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI31_PDI_n_SHIFT)) & SIUL2_GPDI31_PDI_n_MASK) 3226 /*! @} */ 3227 3228 /*! @name GPDI30 - SIUL2 GPIO Pad Data Input Register */ 3229 /*! @{ */ 3230 3231 #define SIUL2_GPDI30_PDI_n_MASK (0x1U) 3232 #define SIUL2_GPDI30_PDI_n_SHIFT (0U) 3233 #define SIUL2_GPDI30_PDI_n_WIDTH (1U) 3234 #define SIUL2_GPDI30_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI30_PDI_n_SHIFT)) & SIUL2_GPDI30_PDI_n_MASK) 3235 /*! @} */ 3236 3237 /*! @name GPDI29 - SIUL2 GPIO Pad Data Input Register */ 3238 /*! @{ */ 3239 3240 #define SIUL2_GPDI29_PDI_n_MASK (0x1U) 3241 #define SIUL2_GPDI29_PDI_n_SHIFT (0U) 3242 #define SIUL2_GPDI29_PDI_n_WIDTH (1U) 3243 #define SIUL2_GPDI29_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI29_PDI_n_SHIFT)) & SIUL2_GPDI29_PDI_n_MASK) 3244 /*! @} */ 3245 3246 /*! @name GPDI28 - SIUL2 GPIO Pad Data Input Register */ 3247 /*! @{ */ 3248 3249 #define SIUL2_GPDI28_PDI_n_MASK (0x1U) 3250 #define SIUL2_GPDI28_PDI_n_SHIFT (0U) 3251 #define SIUL2_GPDI28_PDI_n_WIDTH (1U) 3252 #define SIUL2_GPDI28_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI28_PDI_n_SHIFT)) & SIUL2_GPDI28_PDI_n_MASK) 3253 /*! @} */ 3254 3255 /*! @name GPDI35 - SIUL2 GPIO Pad Data Input Register */ 3256 /*! @{ */ 3257 3258 #define SIUL2_GPDI35_PDI_n_MASK (0x1U) 3259 #define SIUL2_GPDI35_PDI_n_SHIFT (0U) 3260 #define SIUL2_GPDI35_PDI_n_WIDTH (1U) 3261 #define SIUL2_GPDI35_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI35_PDI_n_SHIFT)) & SIUL2_GPDI35_PDI_n_MASK) 3262 /*! @} */ 3263 3264 /*! @name GPDI34 - SIUL2 GPIO Pad Data Input Register */ 3265 /*! @{ */ 3266 3267 #define SIUL2_GPDI34_PDI_n_MASK (0x1U) 3268 #define SIUL2_GPDI34_PDI_n_SHIFT (0U) 3269 #define SIUL2_GPDI34_PDI_n_WIDTH (1U) 3270 #define SIUL2_GPDI34_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI34_PDI_n_SHIFT)) & SIUL2_GPDI34_PDI_n_MASK) 3271 /*! @} */ 3272 3273 /*! @name GPDI33 - SIUL2 GPIO Pad Data Input Register */ 3274 /*! @{ */ 3275 3276 #define SIUL2_GPDI33_PDI_n_MASK (0x1U) 3277 #define SIUL2_GPDI33_PDI_n_SHIFT (0U) 3278 #define SIUL2_GPDI33_PDI_n_WIDTH (1U) 3279 #define SIUL2_GPDI33_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI33_PDI_n_SHIFT)) & SIUL2_GPDI33_PDI_n_MASK) 3280 /*! @} */ 3281 3282 /*! @name GPDI32 - SIUL2 GPIO Pad Data Input Register */ 3283 /*! @{ */ 3284 3285 #define SIUL2_GPDI32_PDI_n_MASK (0x1U) 3286 #define SIUL2_GPDI32_PDI_n_SHIFT (0U) 3287 #define SIUL2_GPDI32_PDI_n_WIDTH (1U) 3288 #define SIUL2_GPDI32_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI32_PDI_n_SHIFT)) & SIUL2_GPDI32_PDI_n_MASK) 3289 /*! @} */ 3290 3291 /*! @name GPDI39 - SIUL2 GPIO Pad Data Input Register */ 3292 /*! @{ */ 3293 3294 #define SIUL2_GPDI39_PDI_n_MASK (0x1U) 3295 #define SIUL2_GPDI39_PDI_n_SHIFT (0U) 3296 #define SIUL2_GPDI39_PDI_n_WIDTH (1U) 3297 #define SIUL2_GPDI39_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI39_PDI_n_SHIFT)) & SIUL2_GPDI39_PDI_n_MASK) 3298 /*! @} */ 3299 3300 /*! @name GPDI38 - SIUL2 GPIO Pad Data Input Register */ 3301 /*! @{ */ 3302 3303 #define SIUL2_GPDI38_PDI_n_MASK (0x1U) 3304 #define SIUL2_GPDI38_PDI_n_SHIFT (0U) 3305 #define SIUL2_GPDI38_PDI_n_WIDTH (1U) 3306 #define SIUL2_GPDI38_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI38_PDI_n_SHIFT)) & SIUL2_GPDI38_PDI_n_MASK) 3307 /*! @} */ 3308 3309 /*! @name GPDI37 - SIUL2 GPIO Pad Data Input Register */ 3310 /*! @{ */ 3311 3312 #define SIUL2_GPDI37_PDI_n_MASK (0x1U) 3313 #define SIUL2_GPDI37_PDI_n_SHIFT (0U) 3314 #define SIUL2_GPDI37_PDI_n_WIDTH (1U) 3315 #define SIUL2_GPDI37_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI37_PDI_n_SHIFT)) & SIUL2_GPDI37_PDI_n_MASK) 3316 /*! @} */ 3317 3318 /*! @name GPDI36 - SIUL2 GPIO Pad Data Input Register */ 3319 /*! @{ */ 3320 3321 #define SIUL2_GPDI36_PDI_n_MASK (0x1U) 3322 #define SIUL2_GPDI36_PDI_n_SHIFT (0U) 3323 #define SIUL2_GPDI36_PDI_n_WIDTH (1U) 3324 #define SIUL2_GPDI36_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI36_PDI_n_SHIFT)) & SIUL2_GPDI36_PDI_n_MASK) 3325 /*! @} */ 3326 3327 /*! @name GPDI43 - SIUL2 GPIO Pad Data Input Register */ 3328 /*! @{ */ 3329 3330 #define SIUL2_GPDI43_PDI_n_MASK (0x1U) 3331 #define SIUL2_GPDI43_PDI_n_SHIFT (0U) 3332 #define SIUL2_GPDI43_PDI_n_WIDTH (1U) 3333 #define SIUL2_GPDI43_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI43_PDI_n_SHIFT)) & SIUL2_GPDI43_PDI_n_MASK) 3334 /*! @} */ 3335 3336 /*! @name GPDI42 - SIUL2 GPIO Pad Data Input Register */ 3337 /*! @{ */ 3338 3339 #define SIUL2_GPDI42_PDI_n_MASK (0x1U) 3340 #define SIUL2_GPDI42_PDI_n_SHIFT (0U) 3341 #define SIUL2_GPDI42_PDI_n_WIDTH (1U) 3342 #define SIUL2_GPDI42_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI42_PDI_n_SHIFT)) & SIUL2_GPDI42_PDI_n_MASK) 3343 /*! @} */ 3344 3345 /*! @name GPDI41 - SIUL2 GPIO Pad Data Input Register */ 3346 /*! @{ */ 3347 3348 #define SIUL2_GPDI41_PDI_n_MASK (0x1U) 3349 #define SIUL2_GPDI41_PDI_n_SHIFT (0U) 3350 #define SIUL2_GPDI41_PDI_n_WIDTH (1U) 3351 #define SIUL2_GPDI41_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI41_PDI_n_SHIFT)) & SIUL2_GPDI41_PDI_n_MASK) 3352 /*! @} */ 3353 3354 /*! @name GPDI40 - SIUL2 GPIO Pad Data Input Register */ 3355 /*! @{ */ 3356 3357 #define SIUL2_GPDI40_PDI_n_MASK (0x1U) 3358 #define SIUL2_GPDI40_PDI_n_SHIFT (0U) 3359 #define SIUL2_GPDI40_PDI_n_WIDTH (1U) 3360 #define SIUL2_GPDI40_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI40_PDI_n_SHIFT)) & SIUL2_GPDI40_PDI_n_MASK) 3361 /*! @} */ 3362 3363 /*! @name GPDI47 - SIUL2 GPIO Pad Data Input Register */ 3364 /*! @{ */ 3365 3366 #define SIUL2_GPDI47_PDI_n_MASK (0x1U) 3367 #define SIUL2_GPDI47_PDI_n_SHIFT (0U) 3368 #define SIUL2_GPDI47_PDI_n_WIDTH (1U) 3369 #define SIUL2_GPDI47_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI47_PDI_n_SHIFT)) & SIUL2_GPDI47_PDI_n_MASK) 3370 /*! @} */ 3371 3372 /*! @name GPDI46 - SIUL2 GPIO Pad Data Input Register */ 3373 /*! @{ */ 3374 3375 #define SIUL2_GPDI46_PDI_n_MASK (0x1U) 3376 #define SIUL2_GPDI46_PDI_n_SHIFT (0U) 3377 #define SIUL2_GPDI46_PDI_n_WIDTH (1U) 3378 #define SIUL2_GPDI46_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI46_PDI_n_SHIFT)) & SIUL2_GPDI46_PDI_n_MASK) 3379 /*! @} */ 3380 3381 /*! @name GPDI45 - SIUL2 GPIO Pad Data Input Register */ 3382 /*! @{ */ 3383 3384 #define SIUL2_GPDI45_PDI_n_MASK (0x1U) 3385 #define SIUL2_GPDI45_PDI_n_SHIFT (0U) 3386 #define SIUL2_GPDI45_PDI_n_WIDTH (1U) 3387 #define SIUL2_GPDI45_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI45_PDI_n_SHIFT)) & SIUL2_GPDI45_PDI_n_MASK) 3388 /*! @} */ 3389 3390 /*! @name GPDI44 - SIUL2 GPIO Pad Data Input Register */ 3391 /*! @{ */ 3392 3393 #define SIUL2_GPDI44_PDI_n_MASK (0x1U) 3394 #define SIUL2_GPDI44_PDI_n_SHIFT (0U) 3395 #define SIUL2_GPDI44_PDI_n_WIDTH (1U) 3396 #define SIUL2_GPDI44_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI44_PDI_n_SHIFT)) & SIUL2_GPDI44_PDI_n_MASK) 3397 /*! @} */ 3398 3399 /*! @name GPDI51 - SIUL2 GPIO Pad Data Input Register */ 3400 /*! @{ */ 3401 3402 #define SIUL2_GPDI51_PDI_n_MASK (0x1U) 3403 #define SIUL2_GPDI51_PDI_n_SHIFT (0U) 3404 #define SIUL2_GPDI51_PDI_n_WIDTH (1U) 3405 #define SIUL2_GPDI51_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI51_PDI_n_SHIFT)) & SIUL2_GPDI51_PDI_n_MASK) 3406 /*! @} */ 3407 3408 /*! @name GPDI50 - SIUL2 GPIO Pad Data Input Register */ 3409 /*! @{ */ 3410 3411 #define SIUL2_GPDI50_PDI_n_MASK (0x1U) 3412 #define SIUL2_GPDI50_PDI_n_SHIFT (0U) 3413 #define SIUL2_GPDI50_PDI_n_WIDTH (1U) 3414 #define SIUL2_GPDI50_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI50_PDI_n_SHIFT)) & SIUL2_GPDI50_PDI_n_MASK) 3415 /*! @} */ 3416 3417 /*! @name GPDI49 - SIUL2 GPIO Pad Data Input Register */ 3418 /*! @{ */ 3419 3420 #define SIUL2_GPDI49_PDI_n_MASK (0x1U) 3421 #define SIUL2_GPDI49_PDI_n_SHIFT (0U) 3422 #define SIUL2_GPDI49_PDI_n_WIDTH (1U) 3423 #define SIUL2_GPDI49_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI49_PDI_n_SHIFT)) & SIUL2_GPDI49_PDI_n_MASK) 3424 /*! @} */ 3425 3426 /*! @name GPDI48 - SIUL2 GPIO Pad Data Input Register */ 3427 /*! @{ */ 3428 3429 #define SIUL2_GPDI48_PDI_n_MASK (0x1U) 3430 #define SIUL2_GPDI48_PDI_n_SHIFT (0U) 3431 #define SIUL2_GPDI48_PDI_n_WIDTH (1U) 3432 #define SIUL2_GPDI48_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI48_PDI_n_SHIFT)) & SIUL2_GPDI48_PDI_n_MASK) 3433 /*! @} */ 3434 3435 /*! @name GPDI55 - SIUL2 GPIO Pad Data Input Register */ 3436 /*! @{ */ 3437 3438 #define SIUL2_GPDI55_PDI_n_MASK (0x1U) 3439 #define SIUL2_GPDI55_PDI_n_SHIFT (0U) 3440 #define SIUL2_GPDI55_PDI_n_WIDTH (1U) 3441 #define SIUL2_GPDI55_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI55_PDI_n_SHIFT)) & SIUL2_GPDI55_PDI_n_MASK) 3442 /*! @} */ 3443 3444 /*! @name GPDI54 - SIUL2 GPIO Pad Data Input Register */ 3445 /*! @{ */ 3446 3447 #define SIUL2_GPDI54_PDI_n_MASK (0x1U) 3448 #define SIUL2_GPDI54_PDI_n_SHIFT (0U) 3449 #define SIUL2_GPDI54_PDI_n_WIDTH (1U) 3450 #define SIUL2_GPDI54_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI54_PDI_n_SHIFT)) & SIUL2_GPDI54_PDI_n_MASK) 3451 /*! @} */ 3452 3453 /*! @name GPDI53 - SIUL2 GPIO Pad Data Input Register */ 3454 /*! @{ */ 3455 3456 #define SIUL2_GPDI53_PDI_n_MASK (0x1U) 3457 #define SIUL2_GPDI53_PDI_n_SHIFT (0U) 3458 #define SIUL2_GPDI53_PDI_n_WIDTH (1U) 3459 #define SIUL2_GPDI53_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI53_PDI_n_SHIFT)) & SIUL2_GPDI53_PDI_n_MASK) 3460 /*! @} */ 3461 3462 /*! @name GPDI52 - SIUL2 GPIO Pad Data Input Register */ 3463 /*! @{ */ 3464 3465 #define SIUL2_GPDI52_PDI_n_MASK (0x1U) 3466 #define SIUL2_GPDI52_PDI_n_SHIFT (0U) 3467 #define SIUL2_GPDI52_PDI_n_WIDTH (1U) 3468 #define SIUL2_GPDI52_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI52_PDI_n_SHIFT)) & SIUL2_GPDI52_PDI_n_MASK) 3469 /*! @} */ 3470 3471 /*! @name GPDI59 - SIUL2 GPIO Pad Data Input Register */ 3472 /*! @{ */ 3473 3474 #define SIUL2_GPDI59_PDI_n_MASK (0x1U) 3475 #define SIUL2_GPDI59_PDI_n_SHIFT (0U) 3476 #define SIUL2_GPDI59_PDI_n_WIDTH (1U) 3477 #define SIUL2_GPDI59_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI59_PDI_n_SHIFT)) & SIUL2_GPDI59_PDI_n_MASK) 3478 /*! @} */ 3479 3480 /*! @name GPDI58 - SIUL2 GPIO Pad Data Input Register */ 3481 /*! @{ */ 3482 3483 #define SIUL2_GPDI58_PDI_n_MASK (0x1U) 3484 #define SIUL2_GPDI58_PDI_n_SHIFT (0U) 3485 #define SIUL2_GPDI58_PDI_n_WIDTH (1U) 3486 #define SIUL2_GPDI58_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI58_PDI_n_SHIFT)) & SIUL2_GPDI58_PDI_n_MASK) 3487 /*! @} */ 3488 3489 /*! @name GPDI57 - SIUL2 GPIO Pad Data Input Register */ 3490 /*! @{ */ 3491 3492 #define SIUL2_GPDI57_PDI_n_MASK (0x1U) 3493 #define SIUL2_GPDI57_PDI_n_SHIFT (0U) 3494 #define SIUL2_GPDI57_PDI_n_WIDTH (1U) 3495 #define SIUL2_GPDI57_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI57_PDI_n_SHIFT)) & SIUL2_GPDI57_PDI_n_MASK) 3496 /*! @} */ 3497 3498 /*! @name GPDI56 - SIUL2 GPIO Pad Data Input Register */ 3499 /*! @{ */ 3500 3501 #define SIUL2_GPDI56_PDI_n_MASK (0x1U) 3502 #define SIUL2_GPDI56_PDI_n_SHIFT (0U) 3503 #define SIUL2_GPDI56_PDI_n_WIDTH (1U) 3504 #define SIUL2_GPDI56_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI56_PDI_n_SHIFT)) & SIUL2_GPDI56_PDI_n_MASK) 3505 /*! @} */ 3506 3507 /*! @name GPDI63 - SIUL2 GPIO Pad Data Input Register */ 3508 /*! @{ */ 3509 3510 #define SIUL2_GPDI63_PDI_n_MASK (0x1U) 3511 #define SIUL2_GPDI63_PDI_n_SHIFT (0U) 3512 #define SIUL2_GPDI63_PDI_n_WIDTH (1U) 3513 #define SIUL2_GPDI63_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI63_PDI_n_SHIFT)) & SIUL2_GPDI63_PDI_n_MASK) 3514 /*! @} */ 3515 3516 /*! @name GPDI62 - SIUL2 GPIO Pad Data Input Register */ 3517 /*! @{ */ 3518 3519 #define SIUL2_GPDI62_PDI_n_MASK (0x1U) 3520 #define SIUL2_GPDI62_PDI_n_SHIFT (0U) 3521 #define SIUL2_GPDI62_PDI_n_WIDTH (1U) 3522 #define SIUL2_GPDI62_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI62_PDI_n_SHIFT)) & SIUL2_GPDI62_PDI_n_MASK) 3523 /*! @} */ 3524 3525 /*! @name GPDI61 - SIUL2 GPIO Pad Data Input Register */ 3526 /*! @{ */ 3527 3528 #define SIUL2_GPDI61_PDI_n_MASK (0x1U) 3529 #define SIUL2_GPDI61_PDI_n_SHIFT (0U) 3530 #define SIUL2_GPDI61_PDI_n_WIDTH (1U) 3531 #define SIUL2_GPDI61_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI61_PDI_n_SHIFT)) & SIUL2_GPDI61_PDI_n_MASK) 3532 /*! @} */ 3533 3534 /*! @name GPDI60 - SIUL2 GPIO Pad Data Input Register */ 3535 /*! @{ */ 3536 3537 #define SIUL2_GPDI60_PDI_n_MASK (0x1U) 3538 #define SIUL2_GPDI60_PDI_n_SHIFT (0U) 3539 #define SIUL2_GPDI60_PDI_n_WIDTH (1U) 3540 #define SIUL2_GPDI60_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI60_PDI_n_SHIFT)) & SIUL2_GPDI60_PDI_n_MASK) 3541 /*! @} */ 3542 3543 /*! @name GPDI67 - SIUL2 GPIO Pad Data Input Register */ 3544 /*! @{ */ 3545 3546 #define SIUL2_GPDI67_PDI_n_MASK (0x1U) 3547 #define SIUL2_GPDI67_PDI_n_SHIFT (0U) 3548 #define SIUL2_GPDI67_PDI_n_WIDTH (1U) 3549 #define SIUL2_GPDI67_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI67_PDI_n_SHIFT)) & SIUL2_GPDI67_PDI_n_MASK) 3550 /*! @} */ 3551 3552 /*! @name GPDI66 - SIUL2 GPIO Pad Data Input Register */ 3553 /*! @{ */ 3554 3555 #define SIUL2_GPDI66_PDI_n_MASK (0x1U) 3556 #define SIUL2_GPDI66_PDI_n_SHIFT (0U) 3557 #define SIUL2_GPDI66_PDI_n_WIDTH (1U) 3558 #define SIUL2_GPDI66_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI66_PDI_n_SHIFT)) & SIUL2_GPDI66_PDI_n_MASK) 3559 /*! @} */ 3560 3561 /*! @name GPDI65 - SIUL2 GPIO Pad Data Input Register */ 3562 /*! @{ */ 3563 3564 #define SIUL2_GPDI65_PDI_n_MASK (0x1U) 3565 #define SIUL2_GPDI65_PDI_n_SHIFT (0U) 3566 #define SIUL2_GPDI65_PDI_n_WIDTH (1U) 3567 #define SIUL2_GPDI65_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI65_PDI_n_SHIFT)) & SIUL2_GPDI65_PDI_n_MASK) 3568 /*! @} */ 3569 3570 /*! @name GPDI64 - SIUL2 GPIO Pad Data Input Register */ 3571 /*! @{ */ 3572 3573 #define SIUL2_GPDI64_PDI_n_MASK (0x1U) 3574 #define SIUL2_GPDI64_PDI_n_SHIFT (0U) 3575 #define SIUL2_GPDI64_PDI_n_WIDTH (1U) 3576 #define SIUL2_GPDI64_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI64_PDI_n_SHIFT)) & SIUL2_GPDI64_PDI_n_MASK) 3577 /*! @} */ 3578 3579 /*! @name GPDI71 - SIUL2 GPIO Pad Data Input Register */ 3580 /*! @{ */ 3581 3582 #define SIUL2_GPDI71_PDI_n_MASK (0x1U) 3583 #define SIUL2_GPDI71_PDI_n_SHIFT (0U) 3584 #define SIUL2_GPDI71_PDI_n_WIDTH (1U) 3585 #define SIUL2_GPDI71_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI71_PDI_n_SHIFT)) & SIUL2_GPDI71_PDI_n_MASK) 3586 /*! @} */ 3587 3588 /*! @name GPDI70 - SIUL2 GPIO Pad Data Input Register */ 3589 /*! @{ */ 3590 3591 #define SIUL2_GPDI70_PDI_n_MASK (0x1U) 3592 #define SIUL2_GPDI70_PDI_n_SHIFT (0U) 3593 #define SIUL2_GPDI70_PDI_n_WIDTH (1U) 3594 #define SIUL2_GPDI70_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI70_PDI_n_SHIFT)) & SIUL2_GPDI70_PDI_n_MASK) 3595 /*! @} */ 3596 3597 /*! @name GPDI69 - SIUL2 GPIO Pad Data Input Register */ 3598 /*! @{ */ 3599 3600 #define SIUL2_GPDI69_PDI_n_MASK (0x1U) 3601 #define SIUL2_GPDI69_PDI_n_SHIFT (0U) 3602 #define SIUL2_GPDI69_PDI_n_WIDTH (1U) 3603 #define SIUL2_GPDI69_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI69_PDI_n_SHIFT)) & SIUL2_GPDI69_PDI_n_MASK) 3604 /*! @} */ 3605 3606 /*! @name GPDI68 - SIUL2 GPIO Pad Data Input Register */ 3607 /*! @{ */ 3608 3609 #define SIUL2_GPDI68_PDI_n_MASK (0x1U) 3610 #define SIUL2_GPDI68_PDI_n_SHIFT (0U) 3611 #define SIUL2_GPDI68_PDI_n_WIDTH (1U) 3612 #define SIUL2_GPDI68_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI68_PDI_n_SHIFT)) & SIUL2_GPDI68_PDI_n_MASK) 3613 /*! @} */ 3614 3615 /*! @name GPDI75 - SIUL2 GPIO Pad Data Input Register */ 3616 /*! @{ */ 3617 3618 #define SIUL2_GPDI75_PDI_n_MASK (0x1U) 3619 #define SIUL2_GPDI75_PDI_n_SHIFT (0U) 3620 #define SIUL2_GPDI75_PDI_n_WIDTH (1U) 3621 #define SIUL2_GPDI75_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI75_PDI_n_SHIFT)) & SIUL2_GPDI75_PDI_n_MASK) 3622 /*! @} */ 3623 3624 /*! @name GPDI74 - SIUL2 GPIO Pad Data Input Register */ 3625 /*! @{ */ 3626 3627 #define SIUL2_GPDI74_PDI_n_MASK (0x1U) 3628 #define SIUL2_GPDI74_PDI_n_SHIFT (0U) 3629 #define SIUL2_GPDI74_PDI_n_WIDTH (1U) 3630 #define SIUL2_GPDI74_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI74_PDI_n_SHIFT)) & SIUL2_GPDI74_PDI_n_MASK) 3631 /*! @} */ 3632 3633 /*! @name GPDI73 - SIUL2 GPIO Pad Data Input Register */ 3634 /*! @{ */ 3635 3636 #define SIUL2_GPDI73_PDI_n_MASK (0x1U) 3637 #define SIUL2_GPDI73_PDI_n_SHIFT (0U) 3638 #define SIUL2_GPDI73_PDI_n_WIDTH (1U) 3639 #define SIUL2_GPDI73_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI73_PDI_n_SHIFT)) & SIUL2_GPDI73_PDI_n_MASK) 3640 /*! @} */ 3641 3642 /*! @name GPDI72 - SIUL2 GPIO Pad Data Input Register */ 3643 /*! @{ */ 3644 3645 #define SIUL2_GPDI72_PDI_n_MASK (0x1U) 3646 #define SIUL2_GPDI72_PDI_n_SHIFT (0U) 3647 #define SIUL2_GPDI72_PDI_n_WIDTH (1U) 3648 #define SIUL2_GPDI72_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI72_PDI_n_SHIFT)) & SIUL2_GPDI72_PDI_n_MASK) 3649 /*! @} */ 3650 3651 /*! @name GPDI79 - SIUL2 GPIO Pad Data Input Register */ 3652 /*! @{ */ 3653 3654 #define SIUL2_GPDI79_PDI_n_MASK (0x1U) 3655 #define SIUL2_GPDI79_PDI_n_SHIFT (0U) 3656 #define SIUL2_GPDI79_PDI_n_WIDTH (1U) 3657 #define SIUL2_GPDI79_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI79_PDI_n_SHIFT)) & SIUL2_GPDI79_PDI_n_MASK) 3658 /*! @} */ 3659 3660 /*! @name GPDI78 - SIUL2 GPIO Pad Data Input Register */ 3661 /*! @{ */ 3662 3663 #define SIUL2_GPDI78_PDI_n_MASK (0x1U) 3664 #define SIUL2_GPDI78_PDI_n_SHIFT (0U) 3665 #define SIUL2_GPDI78_PDI_n_WIDTH (1U) 3666 #define SIUL2_GPDI78_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI78_PDI_n_SHIFT)) & SIUL2_GPDI78_PDI_n_MASK) 3667 /*! @} */ 3668 3669 /*! @name GPDI77 - SIUL2 GPIO Pad Data Input Register */ 3670 /*! @{ */ 3671 3672 #define SIUL2_GPDI77_PDI_n_MASK (0x1U) 3673 #define SIUL2_GPDI77_PDI_n_SHIFT (0U) 3674 #define SIUL2_GPDI77_PDI_n_WIDTH (1U) 3675 #define SIUL2_GPDI77_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI77_PDI_n_SHIFT)) & SIUL2_GPDI77_PDI_n_MASK) 3676 /*! @} */ 3677 3678 /*! @name GPDI76 - SIUL2 GPIO Pad Data Input Register */ 3679 /*! @{ */ 3680 3681 #define SIUL2_GPDI76_PDI_n_MASK (0x1U) 3682 #define SIUL2_GPDI76_PDI_n_SHIFT (0U) 3683 #define SIUL2_GPDI76_PDI_n_WIDTH (1U) 3684 #define SIUL2_GPDI76_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI76_PDI_n_SHIFT)) & SIUL2_GPDI76_PDI_n_MASK) 3685 /*! @} */ 3686 3687 /*! @name GPDI83 - SIUL2 GPIO Pad Data Input Register */ 3688 /*! @{ */ 3689 3690 #define SIUL2_GPDI83_PDI_n_MASK (0x1U) 3691 #define SIUL2_GPDI83_PDI_n_SHIFT (0U) 3692 #define SIUL2_GPDI83_PDI_n_WIDTH (1U) 3693 #define SIUL2_GPDI83_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI83_PDI_n_SHIFT)) & SIUL2_GPDI83_PDI_n_MASK) 3694 /*! @} */ 3695 3696 /*! @name GPDI82 - SIUL2 GPIO Pad Data Input Register */ 3697 /*! @{ */ 3698 3699 #define SIUL2_GPDI82_PDI_n_MASK (0x1U) 3700 #define SIUL2_GPDI82_PDI_n_SHIFT (0U) 3701 #define SIUL2_GPDI82_PDI_n_WIDTH (1U) 3702 #define SIUL2_GPDI82_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI82_PDI_n_SHIFT)) & SIUL2_GPDI82_PDI_n_MASK) 3703 /*! @} */ 3704 3705 /*! @name GPDI81 - SIUL2 GPIO Pad Data Input Register */ 3706 /*! @{ */ 3707 3708 #define SIUL2_GPDI81_PDI_n_MASK (0x1U) 3709 #define SIUL2_GPDI81_PDI_n_SHIFT (0U) 3710 #define SIUL2_GPDI81_PDI_n_WIDTH (1U) 3711 #define SIUL2_GPDI81_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI81_PDI_n_SHIFT)) & SIUL2_GPDI81_PDI_n_MASK) 3712 /*! @} */ 3713 3714 /*! @name GPDI80 - SIUL2 GPIO Pad Data Input Register */ 3715 /*! @{ */ 3716 3717 #define SIUL2_GPDI80_PDI_n_MASK (0x1U) 3718 #define SIUL2_GPDI80_PDI_n_SHIFT (0U) 3719 #define SIUL2_GPDI80_PDI_n_WIDTH (1U) 3720 #define SIUL2_GPDI80_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI80_PDI_n_SHIFT)) & SIUL2_GPDI80_PDI_n_MASK) 3721 /*! @} */ 3722 3723 /*! @name GPDI87 - SIUL2 GPIO Pad Data Input Register */ 3724 /*! @{ */ 3725 3726 #define SIUL2_GPDI87_PDI_n_MASK (0x1U) 3727 #define SIUL2_GPDI87_PDI_n_SHIFT (0U) 3728 #define SIUL2_GPDI87_PDI_n_WIDTH (1U) 3729 #define SIUL2_GPDI87_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI87_PDI_n_SHIFT)) & SIUL2_GPDI87_PDI_n_MASK) 3730 /*! @} */ 3731 3732 /*! @name GPDI86 - SIUL2 GPIO Pad Data Input Register */ 3733 /*! @{ */ 3734 3735 #define SIUL2_GPDI86_PDI_n_MASK (0x1U) 3736 #define SIUL2_GPDI86_PDI_n_SHIFT (0U) 3737 #define SIUL2_GPDI86_PDI_n_WIDTH (1U) 3738 #define SIUL2_GPDI86_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI86_PDI_n_SHIFT)) & SIUL2_GPDI86_PDI_n_MASK) 3739 /*! @} */ 3740 3741 /*! @name GPDI85 - SIUL2 GPIO Pad Data Input Register */ 3742 /*! @{ */ 3743 3744 #define SIUL2_GPDI85_PDI_n_MASK (0x1U) 3745 #define SIUL2_GPDI85_PDI_n_SHIFT (0U) 3746 #define SIUL2_GPDI85_PDI_n_WIDTH (1U) 3747 #define SIUL2_GPDI85_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI85_PDI_n_SHIFT)) & SIUL2_GPDI85_PDI_n_MASK) 3748 /*! @} */ 3749 3750 /*! @name GPDI84 - SIUL2 GPIO Pad Data Input Register */ 3751 /*! @{ */ 3752 3753 #define SIUL2_GPDI84_PDI_n_MASK (0x1U) 3754 #define SIUL2_GPDI84_PDI_n_SHIFT (0U) 3755 #define SIUL2_GPDI84_PDI_n_WIDTH (1U) 3756 #define SIUL2_GPDI84_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI84_PDI_n_SHIFT)) & SIUL2_GPDI84_PDI_n_MASK) 3757 /*! @} */ 3758 3759 /*! @name GPDI91 - SIUL2 GPIO Pad Data Input Register */ 3760 /*! @{ */ 3761 3762 #define SIUL2_GPDI91_PDI_n_MASK (0x1U) 3763 #define SIUL2_GPDI91_PDI_n_SHIFT (0U) 3764 #define SIUL2_GPDI91_PDI_n_WIDTH (1U) 3765 #define SIUL2_GPDI91_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI91_PDI_n_SHIFT)) & SIUL2_GPDI91_PDI_n_MASK) 3766 /*! @} */ 3767 3768 /*! @name GPDI90 - SIUL2 GPIO Pad Data Input Register */ 3769 /*! @{ */ 3770 3771 #define SIUL2_GPDI90_PDI_n_MASK (0x1U) 3772 #define SIUL2_GPDI90_PDI_n_SHIFT (0U) 3773 #define SIUL2_GPDI90_PDI_n_WIDTH (1U) 3774 #define SIUL2_GPDI90_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI90_PDI_n_SHIFT)) & SIUL2_GPDI90_PDI_n_MASK) 3775 /*! @} */ 3776 3777 /*! @name GPDI89 - SIUL2 GPIO Pad Data Input Register */ 3778 /*! @{ */ 3779 3780 #define SIUL2_GPDI89_PDI_n_MASK (0x1U) 3781 #define SIUL2_GPDI89_PDI_n_SHIFT (0U) 3782 #define SIUL2_GPDI89_PDI_n_WIDTH (1U) 3783 #define SIUL2_GPDI89_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI89_PDI_n_SHIFT)) & SIUL2_GPDI89_PDI_n_MASK) 3784 /*! @} */ 3785 3786 /*! @name GPDI88 - SIUL2 GPIO Pad Data Input Register */ 3787 /*! @{ */ 3788 3789 #define SIUL2_GPDI88_PDI_n_MASK (0x1U) 3790 #define SIUL2_GPDI88_PDI_n_SHIFT (0U) 3791 #define SIUL2_GPDI88_PDI_n_WIDTH (1U) 3792 #define SIUL2_GPDI88_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI88_PDI_n_SHIFT)) & SIUL2_GPDI88_PDI_n_MASK) 3793 /*! @} */ 3794 3795 /*! @name GPDI95 - SIUL2 GPIO Pad Data Input Register */ 3796 /*! @{ */ 3797 3798 #define SIUL2_GPDI95_PDI_n_MASK (0x1U) 3799 #define SIUL2_GPDI95_PDI_n_SHIFT (0U) 3800 #define SIUL2_GPDI95_PDI_n_WIDTH (1U) 3801 #define SIUL2_GPDI95_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI95_PDI_n_SHIFT)) & SIUL2_GPDI95_PDI_n_MASK) 3802 /*! @} */ 3803 3804 /*! @name GPDI94 - SIUL2 GPIO Pad Data Input Register */ 3805 /*! @{ */ 3806 3807 #define SIUL2_GPDI94_PDI_n_MASK (0x1U) 3808 #define SIUL2_GPDI94_PDI_n_SHIFT (0U) 3809 #define SIUL2_GPDI94_PDI_n_WIDTH (1U) 3810 #define SIUL2_GPDI94_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI94_PDI_n_SHIFT)) & SIUL2_GPDI94_PDI_n_MASK) 3811 /*! @} */ 3812 3813 /*! @name GPDI93 - SIUL2 GPIO Pad Data Input Register */ 3814 /*! @{ */ 3815 3816 #define SIUL2_GPDI93_PDI_n_MASK (0x1U) 3817 #define SIUL2_GPDI93_PDI_n_SHIFT (0U) 3818 #define SIUL2_GPDI93_PDI_n_WIDTH (1U) 3819 #define SIUL2_GPDI93_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI93_PDI_n_SHIFT)) & SIUL2_GPDI93_PDI_n_MASK) 3820 /*! @} */ 3821 3822 /*! @name GPDI92 - SIUL2 GPIO Pad Data Input Register */ 3823 /*! @{ */ 3824 3825 #define SIUL2_GPDI92_PDI_n_MASK (0x1U) 3826 #define SIUL2_GPDI92_PDI_n_SHIFT (0U) 3827 #define SIUL2_GPDI92_PDI_n_WIDTH (1U) 3828 #define SIUL2_GPDI92_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI92_PDI_n_SHIFT)) & SIUL2_GPDI92_PDI_n_MASK) 3829 /*! @} */ 3830 3831 /*! @name GPDI99 - SIUL2 GPIO Pad Data Input Register */ 3832 /*! @{ */ 3833 3834 #define SIUL2_GPDI99_PDI_n_MASK (0x1U) 3835 #define SIUL2_GPDI99_PDI_n_SHIFT (0U) 3836 #define SIUL2_GPDI99_PDI_n_WIDTH (1U) 3837 #define SIUL2_GPDI99_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI99_PDI_n_SHIFT)) & SIUL2_GPDI99_PDI_n_MASK) 3838 /*! @} */ 3839 3840 /*! @name GPDI98 - SIUL2 GPIO Pad Data Input Register */ 3841 /*! @{ */ 3842 3843 #define SIUL2_GPDI98_PDI_n_MASK (0x1U) 3844 #define SIUL2_GPDI98_PDI_n_SHIFT (0U) 3845 #define SIUL2_GPDI98_PDI_n_WIDTH (1U) 3846 #define SIUL2_GPDI98_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI98_PDI_n_SHIFT)) & SIUL2_GPDI98_PDI_n_MASK) 3847 /*! @} */ 3848 3849 /*! @name GPDI97 - SIUL2 GPIO Pad Data Input Register */ 3850 /*! @{ */ 3851 3852 #define SIUL2_GPDI97_PDI_n_MASK (0x1U) 3853 #define SIUL2_GPDI97_PDI_n_SHIFT (0U) 3854 #define SIUL2_GPDI97_PDI_n_WIDTH (1U) 3855 #define SIUL2_GPDI97_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI97_PDI_n_SHIFT)) & SIUL2_GPDI97_PDI_n_MASK) 3856 /*! @} */ 3857 3858 /*! @name GPDI96 - SIUL2 GPIO Pad Data Input Register */ 3859 /*! @{ */ 3860 3861 #define SIUL2_GPDI96_PDI_n_MASK (0x1U) 3862 #define SIUL2_GPDI96_PDI_n_SHIFT (0U) 3863 #define SIUL2_GPDI96_PDI_n_WIDTH (1U) 3864 #define SIUL2_GPDI96_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI96_PDI_n_SHIFT)) & SIUL2_GPDI96_PDI_n_MASK) 3865 /*! @} */ 3866 3867 /*! @name GPDI103 - SIUL2 GPIO Pad Data Input Register */ 3868 /*! @{ */ 3869 3870 #define SIUL2_GPDI103_PDI_n_MASK (0x1U) 3871 #define SIUL2_GPDI103_PDI_n_SHIFT (0U) 3872 #define SIUL2_GPDI103_PDI_n_WIDTH (1U) 3873 #define SIUL2_GPDI103_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI103_PDI_n_SHIFT)) & SIUL2_GPDI103_PDI_n_MASK) 3874 /*! @} */ 3875 3876 /*! @name GPDI102 - SIUL2 GPIO Pad Data Input Register */ 3877 /*! @{ */ 3878 3879 #define SIUL2_GPDI102_PDI_n_MASK (0x1U) 3880 #define SIUL2_GPDI102_PDI_n_SHIFT (0U) 3881 #define SIUL2_GPDI102_PDI_n_WIDTH (1U) 3882 #define SIUL2_GPDI102_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI102_PDI_n_SHIFT)) & SIUL2_GPDI102_PDI_n_MASK) 3883 /*! @} */ 3884 3885 /*! @name GPDI101 - SIUL2 GPIO Pad Data Input Register */ 3886 /*! @{ */ 3887 3888 #define SIUL2_GPDI101_PDI_n_MASK (0x1U) 3889 #define SIUL2_GPDI101_PDI_n_SHIFT (0U) 3890 #define SIUL2_GPDI101_PDI_n_WIDTH (1U) 3891 #define SIUL2_GPDI101_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI101_PDI_n_SHIFT)) & SIUL2_GPDI101_PDI_n_MASK) 3892 /*! @} */ 3893 3894 /*! @name GPDI100 - SIUL2 GPIO Pad Data Input Register */ 3895 /*! @{ */ 3896 3897 #define SIUL2_GPDI100_PDI_n_MASK (0x1U) 3898 #define SIUL2_GPDI100_PDI_n_SHIFT (0U) 3899 #define SIUL2_GPDI100_PDI_n_WIDTH (1U) 3900 #define SIUL2_GPDI100_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI100_PDI_n_SHIFT)) & SIUL2_GPDI100_PDI_n_MASK) 3901 /*! @} */ 3902 3903 /*! @name GPDI107 - SIUL2 GPIO Pad Data Input Register */ 3904 /*! @{ */ 3905 3906 #define SIUL2_GPDI107_PDI_n_MASK (0x1U) 3907 #define SIUL2_GPDI107_PDI_n_SHIFT (0U) 3908 #define SIUL2_GPDI107_PDI_n_WIDTH (1U) 3909 #define SIUL2_GPDI107_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI107_PDI_n_SHIFT)) & SIUL2_GPDI107_PDI_n_MASK) 3910 /*! @} */ 3911 3912 /*! @name GPDI106 - SIUL2 GPIO Pad Data Input Register */ 3913 /*! @{ */ 3914 3915 #define SIUL2_GPDI106_PDI_n_MASK (0x1U) 3916 #define SIUL2_GPDI106_PDI_n_SHIFT (0U) 3917 #define SIUL2_GPDI106_PDI_n_WIDTH (1U) 3918 #define SIUL2_GPDI106_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI106_PDI_n_SHIFT)) & SIUL2_GPDI106_PDI_n_MASK) 3919 /*! @} */ 3920 3921 /*! @name GPDI105 - SIUL2 GPIO Pad Data Input Register */ 3922 /*! @{ */ 3923 3924 #define SIUL2_GPDI105_PDI_n_MASK (0x1U) 3925 #define SIUL2_GPDI105_PDI_n_SHIFT (0U) 3926 #define SIUL2_GPDI105_PDI_n_WIDTH (1U) 3927 #define SIUL2_GPDI105_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI105_PDI_n_SHIFT)) & SIUL2_GPDI105_PDI_n_MASK) 3928 /*! @} */ 3929 3930 /*! @name GPDI104 - SIUL2 GPIO Pad Data Input Register */ 3931 /*! @{ */ 3932 3933 #define SIUL2_GPDI104_PDI_n_MASK (0x1U) 3934 #define SIUL2_GPDI104_PDI_n_SHIFT (0U) 3935 #define SIUL2_GPDI104_PDI_n_WIDTH (1U) 3936 #define SIUL2_GPDI104_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI104_PDI_n_SHIFT)) & SIUL2_GPDI104_PDI_n_MASK) 3937 /*! @} */ 3938 3939 /*! @name GPDI111 - SIUL2 GPIO Pad Data Input Register */ 3940 /*! @{ */ 3941 3942 #define SIUL2_GPDI111_PDI_n_MASK (0x1U) 3943 #define SIUL2_GPDI111_PDI_n_SHIFT (0U) 3944 #define SIUL2_GPDI111_PDI_n_WIDTH (1U) 3945 #define SIUL2_GPDI111_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI111_PDI_n_SHIFT)) & SIUL2_GPDI111_PDI_n_MASK) 3946 /*! @} */ 3947 3948 /*! @name GPDI110 - SIUL2 GPIO Pad Data Input Register */ 3949 /*! @{ */ 3950 3951 #define SIUL2_GPDI110_PDI_n_MASK (0x1U) 3952 #define SIUL2_GPDI110_PDI_n_SHIFT (0U) 3953 #define SIUL2_GPDI110_PDI_n_WIDTH (1U) 3954 #define SIUL2_GPDI110_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI110_PDI_n_SHIFT)) & SIUL2_GPDI110_PDI_n_MASK) 3955 /*! @} */ 3956 3957 /*! @name GPDI109 - SIUL2 GPIO Pad Data Input Register */ 3958 /*! @{ */ 3959 3960 #define SIUL2_GPDI109_PDI_n_MASK (0x1U) 3961 #define SIUL2_GPDI109_PDI_n_SHIFT (0U) 3962 #define SIUL2_GPDI109_PDI_n_WIDTH (1U) 3963 #define SIUL2_GPDI109_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI109_PDI_n_SHIFT)) & SIUL2_GPDI109_PDI_n_MASK) 3964 /*! @} */ 3965 3966 /*! @name GPDI108 - SIUL2 GPIO Pad Data Input Register */ 3967 /*! @{ */ 3968 3969 #define SIUL2_GPDI108_PDI_n_MASK (0x1U) 3970 #define SIUL2_GPDI108_PDI_n_SHIFT (0U) 3971 #define SIUL2_GPDI108_PDI_n_WIDTH (1U) 3972 #define SIUL2_GPDI108_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI108_PDI_n_SHIFT)) & SIUL2_GPDI108_PDI_n_MASK) 3973 /*! @} */ 3974 3975 /*! @name GPDI115 - SIUL2 GPIO Pad Data Input Register */ 3976 /*! @{ */ 3977 3978 #define SIUL2_GPDI115_PDI_n_MASK (0x1U) 3979 #define SIUL2_GPDI115_PDI_n_SHIFT (0U) 3980 #define SIUL2_GPDI115_PDI_n_WIDTH (1U) 3981 #define SIUL2_GPDI115_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI115_PDI_n_SHIFT)) & SIUL2_GPDI115_PDI_n_MASK) 3982 /*! @} */ 3983 3984 /*! @name GPDI114 - SIUL2 GPIO Pad Data Input Register */ 3985 /*! @{ */ 3986 3987 #define SIUL2_GPDI114_PDI_n_MASK (0x1U) 3988 #define SIUL2_GPDI114_PDI_n_SHIFT (0U) 3989 #define SIUL2_GPDI114_PDI_n_WIDTH (1U) 3990 #define SIUL2_GPDI114_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI114_PDI_n_SHIFT)) & SIUL2_GPDI114_PDI_n_MASK) 3991 /*! @} */ 3992 3993 /*! @name GPDI113 - SIUL2 GPIO Pad Data Input Register */ 3994 /*! @{ */ 3995 3996 #define SIUL2_GPDI113_PDI_n_MASK (0x1U) 3997 #define SIUL2_GPDI113_PDI_n_SHIFT (0U) 3998 #define SIUL2_GPDI113_PDI_n_WIDTH (1U) 3999 #define SIUL2_GPDI113_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI113_PDI_n_SHIFT)) & SIUL2_GPDI113_PDI_n_MASK) 4000 /*! @} */ 4001 4002 /*! @name GPDI112 - SIUL2 GPIO Pad Data Input Register */ 4003 /*! @{ */ 4004 4005 #define SIUL2_GPDI112_PDI_n_MASK (0x1U) 4006 #define SIUL2_GPDI112_PDI_n_SHIFT (0U) 4007 #define SIUL2_GPDI112_PDI_n_WIDTH (1U) 4008 #define SIUL2_GPDI112_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI112_PDI_n_SHIFT)) & SIUL2_GPDI112_PDI_n_MASK) 4009 /*! @} */ 4010 4011 /*! @name GPDI119 - SIUL2 GPIO Pad Data Input Register */ 4012 /*! @{ */ 4013 4014 #define SIUL2_GPDI119_PDI_n_MASK (0x1U) 4015 #define SIUL2_GPDI119_PDI_n_SHIFT (0U) 4016 #define SIUL2_GPDI119_PDI_n_WIDTH (1U) 4017 #define SIUL2_GPDI119_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI119_PDI_n_SHIFT)) & SIUL2_GPDI119_PDI_n_MASK) 4018 /*! @} */ 4019 4020 /*! @name GPDI118 - SIUL2 GPIO Pad Data Input Register */ 4021 /*! @{ */ 4022 4023 #define SIUL2_GPDI118_PDI_n_MASK (0x1U) 4024 #define SIUL2_GPDI118_PDI_n_SHIFT (0U) 4025 #define SIUL2_GPDI118_PDI_n_WIDTH (1U) 4026 #define SIUL2_GPDI118_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI118_PDI_n_SHIFT)) & SIUL2_GPDI118_PDI_n_MASK) 4027 /*! @} */ 4028 4029 /*! @name GPDI117 - SIUL2 GPIO Pad Data Input Register */ 4030 /*! @{ */ 4031 4032 #define SIUL2_GPDI117_PDI_n_MASK (0x1U) 4033 #define SIUL2_GPDI117_PDI_n_SHIFT (0U) 4034 #define SIUL2_GPDI117_PDI_n_WIDTH (1U) 4035 #define SIUL2_GPDI117_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI117_PDI_n_SHIFT)) & SIUL2_GPDI117_PDI_n_MASK) 4036 /*! @} */ 4037 4038 /*! @name GPDI116 - SIUL2 GPIO Pad Data Input Register */ 4039 /*! @{ */ 4040 4041 #define SIUL2_GPDI116_PDI_n_MASK (0x1U) 4042 #define SIUL2_GPDI116_PDI_n_SHIFT (0U) 4043 #define SIUL2_GPDI116_PDI_n_WIDTH (1U) 4044 #define SIUL2_GPDI116_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI116_PDI_n_SHIFT)) & SIUL2_GPDI116_PDI_n_MASK) 4045 /*! @} */ 4046 4047 /*! @name GPDI123 - SIUL2 GPIO Pad Data Input Register */ 4048 /*! @{ */ 4049 4050 #define SIUL2_GPDI123_PDI_n_MASK (0x1U) 4051 #define SIUL2_GPDI123_PDI_n_SHIFT (0U) 4052 #define SIUL2_GPDI123_PDI_n_WIDTH (1U) 4053 #define SIUL2_GPDI123_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI123_PDI_n_SHIFT)) & SIUL2_GPDI123_PDI_n_MASK) 4054 /*! @} */ 4055 4056 /*! @name GPDI122 - SIUL2 GPIO Pad Data Input Register */ 4057 /*! @{ */ 4058 4059 #define SIUL2_GPDI122_PDI_n_MASK (0x1U) 4060 #define SIUL2_GPDI122_PDI_n_SHIFT (0U) 4061 #define SIUL2_GPDI122_PDI_n_WIDTH (1U) 4062 #define SIUL2_GPDI122_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI122_PDI_n_SHIFT)) & SIUL2_GPDI122_PDI_n_MASK) 4063 /*! @} */ 4064 4065 /*! @name GPDI121 - SIUL2 GPIO Pad Data Input Register */ 4066 /*! @{ */ 4067 4068 #define SIUL2_GPDI121_PDI_n_MASK (0x1U) 4069 #define SIUL2_GPDI121_PDI_n_SHIFT (0U) 4070 #define SIUL2_GPDI121_PDI_n_WIDTH (1U) 4071 #define SIUL2_GPDI121_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI121_PDI_n_SHIFT)) & SIUL2_GPDI121_PDI_n_MASK) 4072 /*! @} */ 4073 4074 /*! @name GPDI120 - SIUL2 GPIO Pad Data Input Register */ 4075 /*! @{ */ 4076 4077 #define SIUL2_GPDI120_PDI_n_MASK (0x1U) 4078 #define SIUL2_GPDI120_PDI_n_SHIFT (0U) 4079 #define SIUL2_GPDI120_PDI_n_WIDTH (1U) 4080 #define SIUL2_GPDI120_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI120_PDI_n_SHIFT)) & SIUL2_GPDI120_PDI_n_MASK) 4081 /*! @} */ 4082 4083 /*! @name GPDI127 - SIUL2 GPIO Pad Data Input Register */ 4084 /*! @{ */ 4085 4086 #define SIUL2_GPDI127_PDI_n_MASK (0x1U) 4087 #define SIUL2_GPDI127_PDI_n_SHIFT (0U) 4088 #define SIUL2_GPDI127_PDI_n_WIDTH (1U) 4089 #define SIUL2_GPDI127_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI127_PDI_n_SHIFT)) & SIUL2_GPDI127_PDI_n_MASK) 4090 /*! @} */ 4091 4092 /*! @name GPDI126 - SIUL2 GPIO Pad Data Input Register */ 4093 /*! @{ */ 4094 4095 #define SIUL2_GPDI126_PDI_n_MASK (0x1U) 4096 #define SIUL2_GPDI126_PDI_n_SHIFT (0U) 4097 #define SIUL2_GPDI126_PDI_n_WIDTH (1U) 4098 #define SIUL2_GPDI126_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI126_PDI_n_SHIFT)) & SIUL2_GPDI126_PDI_n_MASK) 4099 /*! @} */ 4100 4101 /*! @name GPDI125 - SIUL2 GPIO Pad Data Input Register */ 4102 /*! @{ */ 4103 4104 #define SIUL2_GPDI125_PDI_n_MASK (0x1U) 4105 #define SIUL2_GPDI125_PDI_n_SHIFT (0U) 4106 #define SIUL2_GPDI125_PDI_n_WIDTH (1U) 4107 #define SIUL2_GPDI125_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI125_PDI_n_SHIFT)) & SIUL2_GPDI125_PDI_n_MASK) 4108 /*! @} */ 4109 4110 /*! @name GPDI124 - SIUL2 GPIO Pad Data Input Register */ 4111 /*! @{ */ 4112 4113 #define SIUL2_GPDI124_PDI_n_MASK (0x1U) 4114 #define SIUL2_GPDI124_PDI_n_SHIFT (0U) 4115 #define SIUL2_GPDI124_PDI_n_WIDTH (1U) 4116 #define SIUL2_GPDI124_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI124_PDI_n_SHIFT)) & SIUL2_GPDI124_PDI_n_MASK) 4117 /*! @} */ 4118 4119 /*! @name GPDI131 - SIUL2 GPIO Pad Data Input Register */ 4120 /*! @{ */ 4121 4122 #define SIUL2_GPDI131_PDI_n_MASK (0x1U) 4123 #define SIUL2_GPDI131_PDI_n_SHIFT (0U) 4124 #define SIUL2_GPDI131_PDI_n_WIDTH (1U) 4125 #define SIUL2_GPDI131_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI131_PDI_n_SHIFT)) & SIUL2_GPDI131_PDI_n_MASK) 4126 /*! @} */ 4127 4128 /*! @name GPDI130 - SIUL2 GPIO Pad Data Input Register */ 4129 /*! @{ */ 4130 4131 #define SIUL2_GPDI130_PDI_n_MASK (0x1U) 4132 #define SIUL2_GPDI130_PDI_n_SHIFT (0U) 4133 #define SIUL2_GPDI130_PDI_n_WIDTH (1U) 4134 #define SIUL2_GPDI130_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI130_PDI_n_SHIFT)) & SIUL2_GPDI130_PDI_n_MASK) 4135 /*! @} */ 4136 4137 /*! @name GPDI129 - SIUL2 GPIO Pad Data Input Register */ 4138 /*! @{ */ 4139 4140 #define SIUL2_GPDI129_PDI_n_MASK (0x1U) 4141 #define SIUL2_GPDI129_PDI_n_SHIFT (0U) 4142 #define SIUL2_GPDI129_PDI_n_WIDTH (1U) 4143 #define SIUL2_GPDI129_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI129_PDI_n_SHIFT)) & SIUL2_GPDI129_PDI_n_MASK) 4144 /*! @} */ 4145 4146 /*! @name GPDI128 - SIUL2 GPIO Pad Data Input Register */ 4147 /*! @{ */ 4148 4149 #define SIUL2_GPDI128_PDI_n_MASK (0x1U) 4150 #define SIUL2_GPDI128_PDI_n_SHIFT (0U) 4151 #define SIUL2_GPDI128_PDI_n_WIDTH (1U) 4152 #define SIUL2_GPDI128_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI128_PDI_n_SHIFT)) & SIUL2_GPDI128_PDI_n_MASK) 4153 /*! @} */ 4154 4155 /*! @name GPDI135 - SIUL2 GPIO Pad Data Input Register */ 4156 /*! @{ */ 4157 4158 #define SIUL2_GPDI135_PDI_n_MASK (0x1U) 4159 #define SIUL2_GPDI135_PDI_n_SHIFT (0U) 4160 #define SIUL2_GPDI135_PDI_n_WIDTH (1U) 4161 #define SIUL2_GPDI135_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI135_PDI_n_SHIFT)) & SIUL2_GPDI135_PDI_n_MASK) 4162 /*! @} */ 4163 4164 /*! @name GPDI134 - SIUL2 GPIO Pad Data Input Register */ 4165 /*! @{ */ 4166 4167 #define SIUL2_GPDI134_PDI_n_MASK (0x1U) 4168 #define SIUL2_GPDI134_PDI_n_SHIFT (0U) 4169 #define SIUL2_GPDI134_PDI_n_WIDTH (1U) 4170 #define SIUL2_GPDI134_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI134_PDI_n_SHIFT)) & SIUL2_GPDI134_PDI_n_MASK) 4171 /*! @} */ 4172 4173 /*! @name GPDI133 - SIUL2 GPIO Pad Data Input Register */ 4174 /*! @{ */ 4175 4176 #define SIUL2_GPDI133_PDI_n_MASK (0x1U) 4177 #define SIUL2_GPDI133_PDI_n_SHIFT (0U) 4178 #define SIUL2_GPDI133_PDI_n_WIDTH (1U) 4179 #define SIUL2_GPDI133_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI133_PDI_n_SHIFT)) & SIUL2_GPDI133_PDI_n_MASK) 4180 /*! @} */ 4181 4182 /*! @name GPDI132 - SIUL2 GPIO Pad Data Input Register */ 4183 /*! @{ */ 4184 4185 #define SIUL2_GPDI132_PDI_n_MASK (0x1U) 4186 #define SIUL2_GPDI132_PDI_n_SHIFT (0U) 4187 #define SIUL2_GPDI132_PDI_n_WIDTH (1U) 4188 #define SIUL2_GPDI132_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI132_PDI_n_SHIFT)) & SIUL2_GPDI132_PDI_n_MASK) 4189 /*! @} */ 4190 4191 /*! @name GPDI139 - SIUL2 GPIO Pad Data Input Register */ 4192 /*! @{ */ 4193 4194 #define SIUL2_GPDI139_PDI_n_MASK (0x1U) 4195 #define SIUL2_GPDI139_PDI_n_SHIFT (0U) 4196 #define SIUL2_GPDI139_PDI_n_WIDTH (1U) 4197 #define SIUL2_GPDI139_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI139_PDI_n_SHIFT)) & SIUL2_GPDI139_PDI_n_MASK) 4198 /*! @} */ 4199 4200 /*! @name GPDI138 - SIUL2 GPIO Pad Data Input Register */ 4201 /*! @{ */ 4202 4203 #define SIUL2_GPDI138_PDI_n_MASK (0x1U) 4204 #define SIUL2_GPDI138_PDI_n_SHIFT (0U) 4205 #define SIUL2_GPDI138_PDI_n_WIDTH (1U) 4206 #define SIUL2_GPDI138_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI138_PDI_n_SHIFT)) & SIUL2_GPDI138_PDI_n_MASK) 4207 /*! @} */ 4208 4209 /*! @name GPDI137 - SIUL2 GPIO Pad Data Input Register */ 4210 /*! @{ */ 4211 4212 #define SIUL2_GPDI137_PDI_n_MASK (0x1U) 4213 #define SIUL2_GPDI137_PDI_n_SHIFT (0U) 4214 #define SIUL2_GPDI137_PDI_n_WIDTH (1U) 4215 #define SIUL2_GPDI137_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI137_PDI_n_SHIFT)) & SIUL2_GPDI137_PDI_n_MASK) 4216 /*! @} */ 4217 4218 /*! @name GPDI136 - SIUL2 GPIO Pad Data Input Register */ 4219 /*! @{ */ 4220 4221 #define SIUL2_GPDI136_PDI_n_MASK (0x1U) 4222 #define SIUL2_GPDI136_PDI_n_SHIFT (0U) 4223 #define SIUL2_GPDI136_PDI_n_WIDTH (1U) 4224 #define SIUL2_GPDI136_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI136_PDI_n_SHIFT)) & SIUL2_GPDI136_PDI_n_MASK) 4225 /*! @} */ 4226 4227 /*! @name GPDI143 - SIUL2 GPIO Pad Data Input Register */ 4228 /*! @{ */ 4229 4230 #define SIUL2_GPDI143_PDI_n_MASK (0x1U) 4231 #define SIUL2_GPDI143_PDI_n_SHIFT (0U) 4232 #define SIUL2_GPDI143_PDI_n_WIDTH (1U) 4233 #define SIUL2_GPDI143_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI143_PDI_n_SHIFT)) & SIUL2_GPDI143_PDI_n_MASK) 4234 /*! @} */ 4235 4236 /*! @name GPDI142 - SIUL2 GPIO Pad Data Input Register */ 4237 /*! @{ */ 4238 4239 #define SIUL2_GPDI142_PDI_n_MASK (0x1U) 4240 #define SIUL2_GPDI142_PDI_n_SHIFT (0U) 4241 #define SIUL2_GPDI142_PDI_n_WIDTH (1U) 4242 #define SIUL2_GPDI142_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI142_PDI_n_SHIFT)) & SIUL2_GPDI142_PDI_n_MASK) 4243 /*! @} */ 4244 4245 /*! @name GPDI141 - SIUL2 GPIO Pad Data Input Register */ 4246 /*! @{ */ 4247 4248 #define SIUL2_GPDI141_PDI_n_MASK (0x1U) 4249 #define SIUL2_GPDI141_PDI_n_SHIFT (0U) 4250 #define SIUL2_GPDI141_PDI_n_WIDTH (1U) 4251 #define SIUL2_GPDI141_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI141_PDI_n_SHIFT)) & SIUL2_GPDI141_PDI_n_MASK) 4252 /*! @} */ 4253 4254 /*! @name GPDI140 - SIUL2 GPIO Pad Data Input Register */ 4255 /*! @{ */ 4256 4257 #define SIUL2_GPDI140_PDI_n_MASK (0x1U) 4258 #define SIUL2_GPDI140_PDI_n_SHIFT (0U) 4259 #define SIUL2_GPDI140_PDI_n_WIDTH (1U) 4260 #define SIUL2_GPDI140_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI140_PDI_n_SHIFT)) & SIUL2_GPDI140_PDI_n_MASK) 4261 /*! @} */ 4262 4263 /*! @name GPDI147 - SIUL2 GPIO Pad Data Input Register */ 4264 /*! @{ */ 4265 4266 #define SIUL2_GPDI147_PDI_n_MASK (0x1U) 4267 #define SIUL2_GPDI147_PDI_n_SHIFT (0U) 4268 #define SIUL2_GPDI147_PDI_n_WIDTH (1U) 4269 #define SIUL2_GPDI147_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI147_PDI_n_SHIFT)) & SIUL2_GPDI147_PDI_n_MASK) 4270 /*! @} */ 4271 4272 /*! @name GPDI146 - SIUL2 GPIO Pad Data Input Register */ 4273 /*! @{ */ 4274 4275 #define SIUL2_GPDI146_PDI_n_MASK (0x1U) 4276 #define SIUL2_GPDI146_PDI_n_SHIFT (0U) 4277 #define SIUL2_GPDI146_PDI_n_WIDTH (1U) 4278 #define SIUL2_GPDI146_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI146_PDI_n_SHIFT)) & SIUL2_GPDI146_PDI_n_MASK) 4279 /*! @} */ 4280 4281 /*! @name GPDI145 - SIUL2 GPIO Pad Data Input Register */ 4282 /*! @{ */ 4283 4284 #define SIUL2_GPDI145_PDI_n_MASK (0x1U) 4285 #define SIUL2_GPDI145_PDI_n_SHIFT (0U) 4286 #define SIUL2_GPDI145_PDI_n_WIDTH (1U) 4287 #define SIUL2_GPDI145_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI145_PDI_n_SHIFT)) & SIUL2_GPDI145_PDI_n_MASK) 4288 /*! @} */ 4289 4290 /*! @name GPDI144 - SIUL2 GPIO Pad Data Input Register */ 4291 /*! @{ */ 4292 4293 #define SIUL2_GPDI144_PDI_n_MASK (0x1U) 4294 #define SIUL2_GPDI144_PDI_n_SHIFT (0U) 4295 #define SIUL2_GPDI144_PDI_n_WIDTH (1U) 4296 #define SIUL2_GPDI144_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI144_PDI_n_SHIFT)) & SIUL2_GPDI144_PDI_n_MASK) 4297 /*! @} */ 4298 4299 /*! @name GPDI151 - SIUL2 GPIO Pad Data Input Register */ 4300 /*! @{ */ 4301 4302 #define SIUL2_GPDI151_PDI_n_MASK (0x1U) 4303 #define SIUL2_GPDI151_PDI_n_SHIFT (0U) 4304 #define SIUL2_GPDI151_PDI_n_WIDTH (1U) 4305 #define SIUL2_GPDI151_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI151_PDI_n_SHIFT)) & SIUL2_GPDI151_PDI_n_MASK) 4306 /*! @} */ 4307 4308 /*! @name GPDI150 - SIUL2 GPIO Pad Data Input Register */ 4309 /*! @{ */ 4310 4311 #define SIUL2_GPDI150_PDI_n_MASK (0x1U) 4312 #define SIUL2_GPDI150_PDI_n_SHIFT (0U) 4313 #define SIUL2_GPDI150_PDI_n_WIDTH (1U) 4314 #define SIUL2_GPDI150_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI150_PDI_n_SHIFT)) & SIUL2_GPDI150_PDI_n_MASK) 4315 /*! @} */ 4316 4317 /*! @name GPDI149 - SIUL2 GPIO Pad Data Input Register */ 4318 /*! @{ */ 4319 4320 #define SIUL2_GPDI149_PDI_n_MASK (0x1U) 4321 #define SIUL2_GPDI149_PDI_n_SHIFT (0U) 4322 #define SIUL2_GPDI149_PDI_n_WIDTH (1U) 4323 #define SIUL2_GPDI149_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI149_PDI_n_SHIFT)) & SIUL2_GPDI149_PDI_n_MASK) 4324 /*! @} */ 4325 4326 /*! @name GPDI148 - SIUL2 GPIO Pad Data Input Register */ 4327 /*! @{ */ 4328 4329 #define SIUL2_GPDI148_PDI_n_MASK (0x1U) 4330 #define SIUL2_GPDI148_PDI_n_SHIFT (0U) 4331 #define SIUL2_GPDI148_PDI_n_WIDTH (1U) 4332 #define SIUL2_GPDI148_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI148_PDI_n_SHIFT)) & SIUL2_GPDI148_PDI_n_MASK) 4333 /*! @} */ 4334 4335 /*! @name GPDI155 - SIUL2 GPIO Pad Data Input Register */ 4336 /*! @{ */ 4337 4338 #define SIUL2_GPDI155_PDI_n_MASK (0x1U) 4339 #define SIUL2_GPDI155_PDI_n_SHIFT (0U) 4340 #define SIUL2_GPDI155_PDI_n_WIDTH (1U) 4341 #define SIUL2_GPDI155_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI155_PDI_n_SHIFT)) & SIUL2_GPDI155_PDI_n_MASK) 4342 /*! @} */ 4343 4344 /*! @name GPDI154 - SIUL2 GPIO Pad Data Input Register */ 4345 /*! @{ */ 4346 4347 #define SIUL2_GPDI154_PDI_n_MASK (0x1U) 4348 #define SIUL2_GPDI154_PDI_n_SHIFT (0U) 4349 #define SIUL2_GPDI154_PDI_n_WIDTH (1U) 4350 #define SIUL2_GPDI154_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI154_PDI_n_SHIFT)) & SIUL2_GPDI154_PDI_n_MASK) 4351 /*! @} */ 4352 4353 /*! @name GPDI153 - SIUL2 GPIO Pad Data Input Register */ 4354 /*! @{ */ 4355 4356 #define SIUL2_GPDI153_PDI_n_MASK (0x1U) 4357 #define SIUL2_GPDI153_PDI_n_SHIFT (0U) 4358 #define SIUL2_GPDI153_PDI_n_WIDTH (1U) 4359 #define SIUL2_GPDI153_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI153_PDI_n_SHIFT)) & SIUL2_GPDI153_PDI_n_MASK) 4360 /*! @} */ 4361 4362 /*! @name GPDI152 - SIUL2 GPIO Pad Data Input Register */ 4363 /*! @{ */ 4364 4365 #define SIUL2_GPDI152_PDI_n_MASK (0x1U) 4366 #define SIUL2_GPDI152_PDI_n_SHIFT (0U) 4367 #define SIUL2_GPDI152_PDI_n_WIDTH (1U) 4368 #define SIUL2_GPDI152_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI152_PDI_n_SHIFT)) & SIUL2_GPDI152_PDI_n_MASK) 4369 /*! @} */ 4370 4371 /*! @name GPDI159 - SIUL2 GPIO Pad Data Input Register */ 4372 /*! @{ */ 4373 4374 #define SIUL2_GPDI159_PDI_n_MASK (0x1U) 4375 #define SIUL2_GPDI159_PDI_n_SHIFT (0U) 4376 #define SIUL2_GPDI159_PDI_n_WIDTH (1U) 4377 #define SIUL2_GPDI159_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI159_PDI_n_SHIFT)) & SIUL2_GPDI159_PDI_n_MASK) 4378 /*! @} */ 4379 4380 /*! @name GPDI158 - SIUL2 GPIO Pad Data Input Register */ 4381 /*! @{ */ 4382 4383 #define SIUL2_GPDI158_PDI_n_MASK (0x1U) 4384 #define SIUL2_GPDI158_PDI_n_SHIFT (0U) 4385 #define SIUL2_GPDI158_PDI_n_WIDTH (1U) 4386 #define SIUL2_GPDI158_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI158_PDI_n_SHIFT)) & SIUL2_GPDI158_PDI_n_MASK) 4387 /*! @} */ 4388 4389 /*! @name GPDI157 - SIUL2 GPIO Pad Data Input Register */ 4390 /*! @{ */ 4391 4392 #define SIUL2_GPDI157_PDI_n_MASK (0x1U) 4393 #define SIUL2_GPDI157_PDI_n_SHIFT (0U) 4394 #define SIUL2_GPDI157_PDI_n_WIDTH (1U) 4395 #define SIUL2_GPDI157_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI157_PDI_n_SHIFT)) & SIUL2_GPDI157_PDI_n_MASK) 4396 /*! @} */ 4397 4398 /*! @name GPDI156 - SIUL2 GPIO Pad Data Input Register */ 4399 /*! @{ */ 4400 4401 #define SIUL2_GPDI156_PDI_n_MASK (0x1U) 4402 #define SIUL2_GPDI156_PDI_n_SHIFT (0U) 4403 #define SIUL2_GPDI156_PDI_n_WIDTH (1U) 4404 #define SIUL2_GPDI156_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI156_PDI_n_SHIFT)) & SIUL2_GPDI156_PDI_n_MASK) 4405 /*! @} */ 4406 4407 /*! @name GPDI163 - SIUL2 GPIO Pad Data Input Register */ 4408 /*! @{ */ 4409 4410 #define SIUL2_GPDI163_PDI_n_MASK (0x1U) 4411 #define SIUL2_GPDI163_PDI_n_SHIFT (0U) 4412 #define SIUL2_GPDI163_PDI_n_WIDTH (1U) 4413 #define SIUL2_GPDI163_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI163_PDI_n_SHIFT)) & SIUL2_GPDI163_PDI_n_MASK) 4414 /*! @} */ 4415 4416 /*! @name GPDI162 - SIUL2 GPIO Pad Data Input Register */ 4417 /*! @{ */ 4418 4419 #define SIUL2_GPDI162_PDI_n_MASK (0x1U) 4420 #define SIUL2_GPDI162_PDI_n_SHIFT (0U) 4421 #define SIUL2_GPDI162_PDI_n_WIDTH (1U) 4422 #define SIUL2_GPDI162_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI162_PDI_n_SHIFT)) & SIUL2_GPDI162_PDI_n_MASK) 4423 /*! @} */ 4424 4425 /*! @name GPDI161 - SIUL2 GPIO Pad Data Input Register */ 4426 /*! @{ */ 4427 4428 #define SIUL2_GPDI161_PDI_n_MASK (0x1U) 4429 #define SIUL2_GPDI161_PDI_n_SHIFT (0U) 4430 #define SIUL2_GPDI161_PDI_n_WIDTH (1U) 4431 #define SIUL2_GPDI161_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI161_PDI_n_SHIFT)) & SIUL2_GPDI161_PDI_n_MASK) 4432 /*! @} */ 4433 4434 /*! @name GPDI160 - SIUL2 GPIO Pad Data Input Register */ 4435 /*! @{ */ 4436 4437 #define SIUL2_GPDI160_PDI_n_MASK (0x1U) 4438 #define SIUL2_GPDI160_PDI_n_SHIFT (0U) 4439 #define SIUL2_GPDI160_PDI_n_WIDTH (1U) 4440 #define SIUL2_GPDI160_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI160_PDI_n_SHIFT)) & SIUL2_GPDI160_PDI_n_MASK) 4441 /*! @} */ 4442 4443 /*! @name GPDI167 - SIUL2 GPIO Pad Data Input Register */ 4444 /*! @{ */ 4445 4446 #define SIUL2_GPDI167_PDI_n_MASK (0x1U) 4447 #define SIUL2_GPDI167_PDI_n_SHIFT (0U) 4448 #define SIUL2_GPDI167_PDI_n_WIDTH (1U) 4449 #define SIUL2_GPDI167_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI167_PDI_n_SHIFT)) & SIUL2_GPDI167_PDI_n_MASK) 4450 /*! @} */ 4451 4452 /*! @name GPDI166 - SIUL2 GPIO Pad Data Input Register */ 4453 /*! @{ */ 4454 4455 #define SIUL2_GPDI166_PDI_n_MASK (0x1U) 4456 #define SIUL2_GPDI166_PDI_n_SHIFT (0U) 4457 #define SIUL2_GPDI166_PDI_n_WIDTH (1U) 4458 #define SIUL2_GPDI166_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI166_PDI_n_SHIFT)) & SIUL2_GPDI166_PDI_n_MASK) 4459 /*! @} */ 4460 4461 /*! @name GPDI165 - SIUL2 GPIO Pad Data Input Register */ 4462 /*! @{ */ 4463 4464 #define SIUL2_GPDI165_PDI_n_MASK (0x1U) 4465 #define SIUL2_GPDI165_PDI_n_SHIFT (0U) 4466 #define SIUL2_GPDI165_PDI_n_WIDTH (1U) 4467 #define SIUL2_GPDI165_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI165_PDI_n_SHIFT)) & SIUL2_GPDI165_PDI_n_MASK) 4468 /*! @} */ 4469 4470 /*! @name GPDI164 - SIUL2 GPIO Pad Data Input Register */ 4471 /*! @{ */ 4472 4473 #define SIUL2_GPDI164_PDI_n_MASK (0x1U) 4474 #define SIUL2_GPDI164_PDI_n_SHIFT (0U) 4475 #define SIUL2_GPDI164_PDI_n_WIDTH (1U) 4476 #define SIUL2_GPDI164_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI164_PDI_n_SHIFT)) & SIUL2_GPDI164_PDI_n_MASK) 4477 /*! @} */ 4478 4479 /*! @name GPDI171 - SIUL2 GPIO Pad Data Input Register */ 4480 /*! @{ */ 4481 4482 #define SIUL2_GPDI171_PDI_n_MASK (0x1U) 4483 #define SIUL2_GPDI171_PDI_n_SHIFT (0U) 4484 #define SIUL2_GPDI171_PDI_n_WIDTH (1U) 4485 #define SIUL2_GPDI171_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI171_PDI_n_SHIFT)) & SIUL2_GPDI171_PDI_n_MASK) 4486 /*! @} */ 4487 4488 /*! @name GPDI170 - SIUL2 GPIO Pad Data Input Register */ 4489 /*! @{ */ 4490 4491 #define SIUL2_GPDI170_PDI_n_MASK (0x1U) 4492 #define SIUL2_GPDI170_PDI_n_SHIFT (0U) 4493 #define SIUL2_GPDI170_PDI_n_WIDTH (1U) 4494 #define SIUL2_GPDI170_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI170_PDI_n_SHIFT)) & SIUL2_GPDI170_PDI_n_MASK) 4495 /*! @} */ 4496 4497 /*! @name GPDI169 - SIUL2 GPIO Pad Data Input Register */ 4498 /*! @{ */ 4499 4500 #define SIUL2_GPDI169_PDI_n_MASK (0x1U) 4501 #define SIUL2_GPDI169_PDI_n_SHIFT (0U) 4502 #define SIUL2_GPDI169_PDI_n_WIDTH (1U) 4503 #define SIUL2_GPDI169_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI169_PDI_n_SHIFT)) & SIUL2_GPDI169_PDI_n_MASK) 4504 /*! @} */ 4505 4506 /*! @name GPDI168 - SIUL2 GPIO Pad Data Input Register */ 4507 /*! @{ */ 4508 4509 #define SIUL2_GPDI168_PDI_n_MASK (0x1U) 4510 #define SIUL2_GPDI168_PDI_n_SHIFT (0U) 4511 #define SIUL2_GPDI168_PDI_n_WIDTH (1U) 4512 #define SIUL2_GPDI168_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI168_PDI_n_SHIFT)) & SIUL2_GPDI168_PDI_n_MASK) 4513 /*! @} */ 4514 4515 /*! @name GPDI173 - SIUL2 GPIO Pad Data Input Register */ 4516 /*! @{ */ 4517 4518 #define SIUL2_GPDI173_PDI_n_MASK (0x1U) 4519 #define SIUL2_GPDI173_PDI_n_SHIFT (0U) 4520 #define SIUL2_GPDI173_PDI_n_WIDTH (1U) 4521 #define SIUL2_GPDI173_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI173_PDI_n_SHIFT)) & SIUL2_GPDI173_PDI_n_MASK) 4522 /*! @} */ 4523 4524 /*! @name GPDI172 - SIUL2 GPIO Pad Data Input Register */ 4525 /*! @{ */ 4526 4527 #define SIUL2_GPDI172_PDI_n_MASK (0x1U) 4528 #define SIUL2_GPDI172_PDI_n_SHIFT (0U) 4529 #define SIUL2_GPDI172_PDI_n_WIDTH (1U) 4530 #define SIUL2_GPDI172_PDI_n(x) (((uint8_t)(((uint8_t)(x)) << SIUL2_GPDI172_PDI_n_SHIFT)) & SIUL2_GPDI172_PDI_n_MASK) 4531 /*! @} */ 4532 4533 /*! @name PGPDO1 - SIUL2 Parallel GPIO Pad Data Out Register */ 4534 /*! @{ */ 4535 4536 #define SIUL2_PGPDO1_PPDO0_MASK (0x1U) 4537 #define SIUL2_PGPDO1_PPDO0_SHIFT (0U) 4538 #define SIUL2_PGPDO1_PPDO0_WIDTH (1U) 4539 #define SIUL2_PGPDO1_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO0_SHIFT)) & SIUL2_PGPDO1_PPDO0_MASK) 4540 4541 #define SIUL2_PGPDO1_PPDO1_MASK (0x2U) 4542 #define SIUL2_PGPDO1_PPDO1_SHIFT (1U) 4543 #define SIUL2_PGPDO1_PPDO1_WIDTH (1U) 4544 #define SIUL2_PGPDO1_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO1_SHIFT)) & SIUL2_PGPDO1_PPDO1_MASK) 4545 4546 #define SIUL2_PGPDO1_PPDO2_MASK (0x4U) 4547 #define SIUL2_PGPDO1_PPDO2_SHIFT (2U) 4548 #define SIUL2_PGPDO1_PPDO2_WIDTH (1U) 4549 #define SIUL2_PGPDO1_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO2_SHIFT)) & SIUL2_PGPDO1_PPDO2_MASK) 4550 4551 #define SIUL2_PGPDO1_PPDO3_MASK (0x8U) 4552 #define SIUL2_PGPDO1_PPDO3_SHIFT (3U) 4553 #define SIUL2_PGPDO1_PPDO3_WIDTH (1U) 4554 #define SIUL2_PGPDO1_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO3_SHIFT)) & SIUL2_PGPDO1_PPDO3_MASK) 4555 4556 #define SIUL2_PGPDO1_PPDO4_MASK (0x10U) 4557 #define SIUL2_PGPDO1_PPDO4_SHIFT (4U) 4558 #define SIUL2_PGPDO1_PPDO4_WIDTH (1U) 4559 #define SIUL2_PGPDO1_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO4_SHIFT)) & SIUL2_PGPDO1_PPDO4_MASK) 4560 4561 #define SIUL2_PGPDO1_PPDO5_MASK (0x20U) 4562 #define SIUL2_PGPDO1_PPDO5_SHIFT (5U) 4563 #define SIUL2_PGPDO1_PPDO5_WIDTH (1U) 4564 #define SIUL2_PGPDO1_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO5_SHIFT)) & SIUL2_PGPDO1_PPDO5_MASK) 4565 4566 #define SIUL2_PGPDO1_PPDO6_MASK (0x40U) 4567 #define SIUL2_PGPDO1_PPDO6_SHIFT (6U) 4568 #define SIUL2_PGPDO1_PPDO6_WIDTH (1U) 4569 #define SIUL2_PGPDO1_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO6_SHIFT)) & SIUL2_PGPDO1_PPDO6_MASK) 4570 4571 #define SIUL2_PGPDO1_PPDO7_MASK (0x80U) 4572 #define SIUL2_PGPDO1_PPDO7_SHIFT (7U) 4573 #define SIUL2_PGPDO1_PPDO7_WIDTH (1U) 4574 #define SIUL2_PGPDO1_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO7_SHIFT)) & SIUL2_PGPDO1_PPDO7_MASK) 4575 4576 #define SIUL2_PGPDO1_PPDO8_MASK (0x100U) 4577 #define SIUL2_PGPDO1_PPDO8_SHIFT (8U) 4578 #define SIUL2_PGPDO1_PPDO8_WIDTH (1U) 4579 #define SIUL2_PGPDO1_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO8_SHIFT)) & SIUL2_PGPDO1_PPDO8_MASK) 4580 4581 #define SIUL2_PGPDO1_PPDO9_MASK (0x200U) 4582 #define SIUL2_PGPDO1_PPDO9_SHIFT (9U) 4583 #define SIUL2_PGPDO1_PPDO9_WIDTH (1U) 4584 #define SIUL2_PGPDO1_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO9_SHIFT)) & SIUL2_PGPDO1_PPDO9_MASK) 4585 4586 #define SIUL2_PGPDO1_PPDO10_MASK (0x400U) 4587 #define SIUL2_PGPDO1_PPDO10_SHIFT (10U) 4588 #define SIUL2_PGPDO1_PPDO10_WIDTH (1U) 4589 #define SIUL2_PGPDO1_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO10_SHIFT)) & SIUL2_PGPDO1_PPDO10_MASK) 4590 4591 #define SIUL2_PGPDO1_PPDO11_MASK (0x800U) 4592 #define SIUL2_PGPDO1_PPDO11_SHIFT (11U) 4593 #define SIUL2_PGPDO1_PPDO11_WIDTH (1U) 4594 #define SIUL2_PGPDO1_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO11_SHIFT)) & SIUL2_PGPDO1_PPDO11_MASK) 4595 4596 #define SIUL2_PGPDO1_PPDO12_MASK (0x1000U) 4597 #define SIUL2_PGPDO1_PPDO12_SHIFT (12U) 4598 #define SIUL2_PGPDO1_PPDO12_WIDTH (1U) 4599 #define SIUL2_PGPDO1_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO12_SHIFT)) & SIUL2_PGPDO1_PPDO12_MASK) 4600 4601 #define SIUL2_PGPDO1_PPDO13_MASK (0x2000U) 4602 #define SIUL2_PGPDO1_PPDO13_SHIFT (13U) 4603 #define SIUL2_PGPDO1_PPDO13_WIDTH (1U) 4604 #define SIUL2_PGPDO1_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO13_SHIFT)) & SIUL2_PGPDO1_PPDO13_MASK) 4605 4606 #define SIUL2_PGPDO1_PPDO14_MASK (0x4000U) 4607 #define SIUL2_PGPDO1_PPDO14_SHIFT (14U) 4608 #define SIUL2_PGPDO1_PPDO14_WIDTH (1U) 4609 #define SIUL2_PGPDO1_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO14_SHIFT)) & SIUL2_PGPDO1_PPDO14_MASK) 4610 4611 #define SIUL2_PGPDO1_PPDO15_MASK (0x8000U) 4612 #define SIUL2_PGPDO1_PPDO15_SHIFT (15U) 4613 #define SIUL2_PGPDO1_PPDO15_WIDTH (1U) 4614 #define SIUL2_PGPDO1_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO1_PPDO15_SHIFT)) & SIUL2_PGPDO1_PPDO15_MASK) 4615 /*! @} */ 4616 4617 /*! @name PGPDO0 - SIUL2 Parallel GPIO Pad Data Out Register */ 4618 /*! @{ */ 4619 4620 #define SIUL2_PGPDO0_PPDO0_MASK (0x1U) 4621 #define SIUL2_PGPDO0_PPDO0_SHIFT (0U) 4622 #define SIUL2_PGPDO0_PPDO0_WIDTH (1U) 4623 #define SIUL2_PGPDO0_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO0_SHIFT)) & SIUL2_PGPDO0_PPDO0_MASK) 4624 4625 #define SIUL2_PGPDO0_PPDO1_MASK (0x2U) 4626 #define SIUL2_PGPDO0_PPDO1_SHIFT (1U) 4627 #define SIUL2_PGPDO0_PPDO1_WIDTH (1U) 4628 #define SIUL2_PGPDO0_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO1_SHIFT)) & SIUL2_PGPDO0_PPDO1_MASK) 4629 4630 #define SIUL2_PGPDO0_PPDO2_MASK (0x4U) 4631 #define SIUL2_PGPDO0_PPDO2_SHIFT (2U) 4632 #define SIUL2_PGPDO0_PPDO2_WIDTH (1U) 4633 #define SIUL2_PGPDO0_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO2_SHIFT)) & SIUL2_PGPDO0_PPDO2_MASK) 4634 4635 #define SIUL2_PGPDO0_PPDO3_MASK (0x8U) 4636 #define SIUL2_PGPDO0_PPDO3_SHIFT (3U) 4637 #define SIUL2_PGPDO0_PPDO3_WIDTH (1U) 4638 #define SIUL2_PGPDO0_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO3_SHIFT)) & SIUL2_PGPDO0_PPDO3_MASK) 4639 4640 #define SIUL2_PGPDO0_PPDO4_MASK (0x10U) 4641 #define SIUL2_PGPDO0_PPDO4_SHIFT (4U) 4642 #define SIUL2_PGPDO0_PPDO4_WIDTH (1U) 4643 #define SIUL2_PGPDO0_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO4_SHIFT)) & SIUL2_PGPDO0_PPDO4_MASK) 4644 4645 #define SIUL2_PGPDO0_PPDO5_MASK (0x20U) 4646 #define SIUL2_PGPDO0_PPDO5_SHIFT (5U) 4647 #define SIUL2_PGPDO0_PPDO5_WIDTH (1U) 4648 #define SIUL2_PGPDO0_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO5_SHIFT)) & SIUL2_PGPDO0_PPDO5_MASK) 4649 4650 #define SIUL2_PGPDO0_PPDO6_MASK (0x40U) 4651 #define SIUL2_PGPDO0_PPDO6_SHIFT (6U) 4652 #define SIUL2_PGPDO0_PPDO6_WIDTH (1U) 4653 #define SIUL2_PGPDO0_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO6_SHIFT)) & SIUL2_PGPDO0_PPDO6_MASK) 4654 4655 #define SIUL2_PGPDO0_PPDO7_MASK (0x80U) 4656 #define SIUL2_PGPDO0_PPDO7_SHIFT (7U) 4657 #define SIUL2_PGPDO0_PPDO7_WIDTH (1U) 4658 #define SIUL2_PGPDO0_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO7_SHIFT)) & SIUL2_PGPDO0_PPDO7_MASK) 4659 4660 #define SIUL2_PGPDO0_PPDO8_MASK (0x100U) 4661 #define SIUL2_PGPDO0_PPDO8_SHIFT (8U) 4662 #define SIUL2_PGPDO0_PPDO8_WIDTH (1U) 4663 #define SIUL2_PGPDO0_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO8_SHIFT)) & SIUL2_PGPDO0_PPDO8_MASK) 4664 4665 #define SIUL2_PGPDO0_PPDO9_MASK (0x200U) 4666 #define SIUL2_PGPDO0_PPDO9_SHIFT (9U) 4667 #define SIUL2_PGPDO0_PPDO9_WIDTH (1U) 4668 #define SIUL2_PGPDO0_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO9_SHIFT)) & SIUL2_PGPDO0_PPDO9_MASK) 4669 4670 #define SIUL2_PGPDO0_PPDO10_MASK (0x400U) 4671 #define SIUL2_PGPDO0_PPDO10_SHIFT (10U) 4672 #define SIUL2_PGPDO0_PPDO10_WIDTH (1U) 4673 #define SIUL2_PGPDO0_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO10_SHIFT)) & SIUL2_PGPDO0_PPDO10_MASK) 4674 4675 #define SIUL2_PGPDO0_PPDO11_MASK (0x800U) 4676 #define SIUL2_PGPDO0_PPDO11_SHIFT (11U) 4677 #define SIUL2_PGPDO0_PPDO11_WIDTH (1U) 4678 #define SIUL2_PGPDO0_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO11_SHIFT)) & SIUL2_PGPDO0_PPDO11_MASK) 4679 4680 #define SIUL2_PGPDO0_PPDO12_MASK (0x1000U) 4681 #define SIUL2_PGPDO0_PPDO12_SHIFT (12U) 4682 #define SIUL2_PGPDO0_PPDO12_WIDTH (1U) 4683 #define SIUL2_PGPDO0_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO12_SHIFT)) & SIUL2_PGPDO0_PPDO12_MASK) 4684 4685 #define SIUL2_PGPDO0_PPDO13_MASK (0x2000U) 4686 #define SIUL2_PGPDO0_PPDO13_SHIFT (13U) 4687 #define SIUL2_PGPDO0_PPDO13_WIDTH (1U) 4688 #define SIUL2_PGPDO0_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO13_SHIFT)) & SIUL2_PGPDO0_PPDO13_MASK) 4689 4690 #define SIUL2_PGPDO0_PPDO14_MASK (0x4000U) 4691 #define SIUL2_PGPDO0_PPDO14_SHIFT (14U) 4692 #define SIUL2_PGPDO0_PPDO14_WIDTH (1U) 4693 #define SIUL2_PGPDO0_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO14_SHIFT)) & SIUL2_PGPDO0_PPDO14_MASK) 4694 4695 #define SIUL2_PGPDO0_PPDO15_MASK (0x8000U) 4696 #define SIUL2_PGPDO0_PPDO15_SHIFT (15U) 4697 #define SIUL2_PGPDO0_PPDO15_WIDTH (1U) 4698 #define SIUL2_PGPDO0_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO0_PPDO15_SHIFT)) & SIUL2_PGPDO0_PPDO15_MASK) 4699 /*! @} */ 4700 4701 /*! @name PGPDO3 - SIUL2 Parallel GPIO Pad Data Out Register */ 4702 /*! @{ */ 4703 4704 #define SIUL2_PGPDO3_PPDO0_MASK (0x1U) 4705 #define SIUL2_PGPDO3_PPDO0_SHIFT (0U) 4706 #define SIUL2_PGPDO3_PPDO0_WIDTH (1U) 4707 #define SIUL2_PGPDO3_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO0_SHIFT)) & SIUL2_PGPDO3_PPDO0_MASK) 4708 4709 #define SIUL2_PGPDO3_PPDO1_MASK (0x2U) 4710 #define SIUL2_PGPDO3_PPDO1_SHIFT (1U) 4711 #define SIUL2_PGPDO3_PPDO1_WIDTH (1U) 4712 #define SIUL2_PGPDO3_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO1_SHIFT)) & SIUL2_PGPDO3_PPDO1_MASK) 4713 4714 #define SIUL2_PGPDO3_PPDO2_MASK (0x4U) 4715 #define SIUL2_PGPDO3_PPDO2_SHIFT (2U) 4716 #define SIUL2_PGPDO3_PPDO2_WIDTH (1U) 4717 #define SIUL2_PGPDO3_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO2_SHIFT)) & SIUL2_PGPDO3_PPDO2_MASK) 4718 4719 #define SIUL2_PGPDO3_PPDO3_MASK (0x8U) 4720 #define SIUL2_PGPDO3_PPDO3_SHIFT (3U) 4721 #define SIUL2_PGPDO3_PPDO3_WIDTH (1U) 4722 #define SIUL2_PGPDO3_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO3_SHIFT)) & SIUL2_PGPDO3_PPDO3_MASK) 4723 4724 #define SIUL2_PGPDO3_PPDO4_MASK (0x10U) 4725 #define SIUL2_PGPDO3_PPDO4_SHIFT (4U) 4726 #define SIUL2_PGPDO3_PPDO4_WIDTH (1U) 4727 #define SIUL2_PGPDO3_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO4_SHIFT)) & SIUL2_PGPDO3_PPDO4_MASK) 4728 4729 #define SIUL2_PGPDO3_PPDO5_MASK (0x20U) 4730 #define SIUL2_PGPDO3_PPDO5_SHIFT (5U) 4731 #define SIUL2_PGPDO3_PPDO5_WIDTH (1U) 4732 #define SIUL2_PGPDO3_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO5_SHIFT)) & SIUL2_PGPDO3_PPDO5_MASK) 4733 4734 #define SIUL2_PGPDO3_PPDO6_MASK (0x40U) 4735 #define SIUL2_PGPDO3_PPDO6_SHIFT (6U) 4736 #define SIUL2_PGPDO3_PPDO6_WIDTH (1U) 4737 #define SIUL2_PGPDO3_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO6_SHIFT)) & SIUL2_PGPDO3_PPDO6_MASK) 4738 4739 #define SIUL2_PGPDO3_PPDO7_MASK (0x80U) 4740 #define SIUL2_PGPDO3_PPDO7_SHIFT (7U) 4741 #define SIUL2_PGPDO3_PPDO7_WIDTH (1U) 4742 #define SIUL2_PGPDO3_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO7_SHIFT)) & SIUL2_PGPDO3_PPDO7_MASK) 4743 4744 #define SIUL2_PGPDO3_PPDO8_MASK (0x100U) 4745 #define SIUL2_PGPDO3_PPDO8_SHIFT (8U) 4746 #define SIUL2_PGPDO3_PPDO8_WIDTH (1U) 4747 #define SIUL2_PGPDO3_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO8_SHIFT)) & SIUL2_PGPDO3_PPDO8_MASK) 4748 4749 #define SIUL2_PGPDO3_PPDO9_MASK (0x200U) 4750 #define SIUL2_PGPDO3_PPDO9_SHIFT (9U) 4751 #define SIUL2_PGPDO3_PPDO9_WIDTH (1U) 4752 #define SIUL2_PGPDO3_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO9_SHIFT)) & SIUL2_PGPDO3_PPDO9_MASK) 4753 4754 #define SIUL2_PGPDO3_PPDO10_MASK (0x400U) 4755 #define SIUL2_PGPDO3_PPDO10_SHIFT (10U) 4756 #define SIUL2_PGPDO3_PPDO10_WIDTH (1U) 4757 #define SIUL2_PGPDO3_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO10_SHIFT)) & SIUL2_PGPDO3_PPDO10_MASK) 4758 4759 #define SIUL2_PGPDO3_PPDO11_MASK (0x800U) 4760 #define SIUL2_PGPDO3_PPDO11_SHIFT (11U) 4761 #define SIUL2_PGPDO3_PPDO11_WIDTH (1U) 4762 #define SIUL2_PGPDO3_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO11_SHIFT)) & SIUL2_PGPDO3_PPDO11_MASK) 4763 4764 #define SIUL2_PGPDO3_PPDO12_MASK (0x1000U) 4765 #define SIUL2_PGPDO3_PPDO12_SHIFT (12U) 4766 #define SIUL2_PGPDO3_PPDO12_WIDTH (1U) 4767 #define SIUL2_PGPDO3_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO12_SHIFT)) & SIUL2_PGPDO3_PPDO12_MASK) 4768 4769 #define SIUL2_PGPDO3_PPDO13_MASK (0x2000U) 4770 #define SIUL2_PGPDO3_PPDO13_SHIFT (13U) 4771 #define SIUL2_PGPDO3_PPDO13_WIDTH (1U) 4772 #define SIUL2_PGPDO3_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO13_SHIFT)) & SIUL2_PGPDO3_PPDO13_MASK) 4773 4774 #define SIUL2_PGPDO3_PPDO14_MASK (0x4000U) 4775 #define SIUL2_PGPDO3_PPDO14_SHIFT (14U) 4776 #define SIUL2_PGPDO3_PPDO14_WIDTH (1U) 4777 #define SIUL2_PGPDO3_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO14_SHIFT)) & SIUL2_PGPDO3_PPDO14_MASK) 4778 4779 #define SIUL2_PGPDO3_PPDO15_MASK (0x8000U) 4780 #define SIUL2_PGPDO3_PPDO15_SHIFT (15U) 4781 #define SIUL2_PGPDO3_PPDO15_WIDTH (1U) 4782 #define SIUL2_PGPDO3_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO3_PPDO15_SHIFT)) & SIUL2_PGPDO3_PPDO15_MASK) 4783 /*! @} */ 4784 4785 /*! @name PGPDO2 - SIUL2 Parallel GPIO Pad Data Out Register */ 4786 /*! @{ */ 4787 4788 #define SIUL2_PGPDO2_PPDO0_MASK (0x1U) 4789 #define SIUL2_PGPDO2_PPDO0_SHIFT (0U) 4790 #define SIUL2_PGPDO2_PPDO0_WIDTH (1U) 4791 #define SIUL2_PGPDO2_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO0_SHIFT)) & SIUL2_PGPDO2_PPDO0_MASK) 4792 4793 #define SIUL2_PGPDO2_PPDO1_MASK (0x2U) 4794 #define SIUL2_PGPDO2_PPDO1_SHIFT (1U) 4795 #define SIUL2_PGPDO2_PPDO1_WIDTH (1U) 4796 #define SIUL2_PGPDO2_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO1_SHIFT)) & SIUL2_PGPDO2_PPDO1_MASK) 4797 4798 #define SIUL2_PGPDO2_PPDO2_MASK (0x4U) 4799 #define SIUL2_PGPDO2_PPDO2_SHIFT (2U) 4800 #define SIUL2_PGPDO2_PPDO2_WIDTH (1U) 4801 #define SIUL2_PGPDO2_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO2_SHIFT)) & SIUL2_PGPDO2_PPDO2_MASK) 4802 4803 #define SIUL2_PGPDO2_PPDO3_MASK (0x8U) 4804 #define SIUL2_PGPDO2_PPDO3_SHIFT (3U) 4805 #define SIUL2_PGPDO2_PPDO3_WIDTH (1U) 4806 #define SIUL2_PGPDO2_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO3_SHIFT)) & SIUL2_PGPDO2_PPDO3_MASK) 4807 4808 #define SIUL2_PGPDO2_PPDO4_MASK (0x10U) 4809 #define SIUL2_PGPDO2_PPDO4_SHIFT (4U) 4810 #define SIUL2_PGPDO2_PPDO4_WIDTH (1U) 4811 #define SIUL2_PGPDO2_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO4_SHIFT)) & SIUL2_PGPDO2_PPDO4_MASK) 4812 4813 #define SIUL2_PGPDO2_PPDO5_MASK (0x20U) 4814 #define SIUL2_PGPDO2_PPDO5_SHIFT (5U) 4815 #define SIUL2_PGPDO2_PPDO5_WIDTH (1U) 4816 #define SIUL2_PGPDO2_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO5_SHIFT)) & SIUL2_PGPDO2_PPDO5_MASK) 4817 4818 #define SIUL2_PGPDO2_PPDO6_MASK (0x40U) 4819 #define SIUL2_PGPDO2_PPDO6_SHIFT (6U) 4820 #define SIUL2_PGPDO2_PPDO6_WIDTH (1U) 4821 #define SIUL2_PGPDO2_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO6_SHIFT)) & SIUL2_PGPDO2_PPDO6_MASK) 4822 4823 #define SIUL2_PGPDO2_PPDO7_MASK (0x80U) 4824 #define SIUL2_PGPDO2_PPDO7_SHIFT (7U) 4825 #define SIUL2_PGPDO2_PPDO7_WIDTH (1U) 4826 #define SIUL2_PGPDO2_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO7_SHIFT)) & SIUL2_PGPDO2_PPDO7_MASK) 4827 4828 #define SIUL2_PGPDO2_PPDO8_MASK (0x100U) 4829 #define SIUL2_PGPDO2_PPDO8_SHIFT (8U) 4830 #define SIUL2_PGPDO2_PPDO8_WIDTH (1U) 4831 #define SIUL2_PGPDO2_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO8_SHIFT)) & SIUL2_PGPDO2_PPDO8_MASK) 4832 4833 #define SIUL2_PGPDO2_PPDO9_MASK (0x200U) 4834 #define SIUL2_PGPDO2_PPDO9_SHIFT (9U) 4835 #define SIUL2_PGPDO2_PPDO9_WIDTH (1U) 4836 #define SIUL2_PGPDO2_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO9_SHIFT)) & SIUL2_PGPDO2_PPDO9_MASK) 4837 4838 #define SIUL2_PGPDO2_PPDO10_MASK (0x400U) 4839 #define SIUL2_PGPDO2_PPDO10_SHIFT (10U) 4840 #define SIUL2_PGPDO2_PPDO10_WIDTH (1U) 4841 #define SIUL2_PGPDO2_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO10_SHIFT)) & SIUL2_PGPDO2_PPDO10_MASK) 4842 4843 #define SIUL2_PGPDO2_PPDO11_MASK (0x800U) 4844 #define SIUL2_PGPDO2_PPDO11_SHIFT (11U) 4845 #define SIUL2_PGPDO2_PPDO11_WIDTH (1U) 4846 #define SIUL2_PGPDO2_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO11_SHIFT)) & SIUL2_PGPDO2_PPDO11_MASK) 4847 4848 #define SIUL2_PGPDO2_PPDO12_MASK (0x1000U) 4849 #define SIUL2_PGPDO2_PPDO12_SHIFT (12U) 4850 #define SIUL2_PGPDO2_PPDO12_WIDTH (1U) 4851 #define SIUL2_PGPDO2_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO12_SHIFT)) & SIUL2_PGPDO2_PPDO12_MASK) 4852 4853 #define SIUL2_PGPDO2_PPDO13_MASK (0x2000U) 4854 #define SIUL2_PGPDO2_PPDO13_SHIFT (13U) 4855 #define SIUL2_PGPDO2_PPDO13_WIDTH (1U) 4856 #define SIUL2_PGPDO2_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO13_SHIFT)) & SIUL2_PGPDO2_PPDO13_MASK) 4857 4858 #define SIUL2_PGPDO2_PPDO14_MASK (0x4000U) 4859 #define SIUL2_PGPDO2_PPDO14_SHIFT (14U) 4860 #define SIUL2_PGPDO2_PPDO14_WIDTH (1U) 4861 #define SIUL2_PGPDO2_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO14_SHIFT)) & SIUL2_PGPDO2_PPDO14_MASK) 4862 4863 #define SIUL2_PGPDO2_PPDO15_MASK (0x8000U) 4864 #define SIUL2_PGPDO2_PPDO15_SHIFT (15U) 4865 #define SIUL2_PGPDO2_PPDO15_WIDTH (1U) 4866 #define SIUL2_PGPDO2_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO2_PPDO15_SHIFT)) & SIUL2_PGPDO2_PPDO15_MASK) 4867 /*! @} */ 4868 4869 /*! @name PGPDO5 - SIUL2 Parallel GPIO Pad Data Out Register */ 4870 /*! @{ */ 4871 4872 #define SIUL2_PGPDO5_PPDO0_MASK (0x1U) 4873 #define SIUL2_PGPDO5_PPDO0_SHIFT (0U) 4874 #define SIUL2_PGPDO5_PPDO0_WIDTH (1U) 4875 #define SIUL2_PGPDO5_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO0_SHIFT)) & SIUL2_PGPDO5_PPDO0_MASK) 4876 4877 #define SIUL2_PGPDO5_PPDO1_MASK (0x2U) 4878 #define SIUL2_PGPDO5_PPDO1_SHIFT (1U) 4879 #define SIUL2_PGPDO5_PPDO1_WIDTH (1U) 4880 #define SIUL2_PGPDO5_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO1_SHIFT)) & SIUL2_PGPDO5_PPDO1_MASK) 4881 4882 #define SIUL2_PGPDO5_PPDO2_MASK (0x4U) 4883 #define SIUL2_PGPDO5_PPDO2_SHIFT (2U) 4884 #define SIUL2_PGPDO5_PPDO2_WIDTH (1U) 4885 #define SIUL2_PGPDO5_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO2_SHIFT)) & SIUL2_PGPDO5_PPDO2_MASK) 4886 4887 #define SIUL2_PGPDO5_PPDO3_MASK (0x8U) 4888 #define SIUL2_PGPDO5_PPDO3_SHIFT (3U) 4889 #define SIUL2_PGPDO5_PPDO3_WIDTH (1U) 4890 #define SIUL2_PGPDO5_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO3_SHIFT)) & SIUL2_PGPDO5_PPDO3_MASK) 4891 4892 #define SIUL2_PGPDO5_PPDO4_MASK (0x10U) 4893 #define SIUL2_PGPDO5_PPDO4_SHIFT (4U) 4894 #define SIUL2_PGPDO5_PPDO4_WIDTH (1U) 4895 #define SIUL2_PGPDO5_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO4_SHIFT)) & SIUL2_PGPDO5_PPDO4_MASK) 4896 4897 #define SIUL2_PGPDO5_PPDO5_MASK (0x20U) 4898 #define SIUL2_PGPDO5_PPDO5_SHIFT (5U) 4899 #define SIUL2_PGPDO5_PPDO5_WIDTH (1U) 4900 #define SIUL2_PGPDO5_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO5_SHIFT)) & SIUL2_PGPDO5_PPDO5_MASK) 4901 4902 #define SIUL2_PGPDO5_PPDO6_MASK (0x40U) 4903 #define SIUL2_PGPDO5_PPDO6_SHIFT (6U) 4904 #define SIUL2_PGPDO5_PPDO6_WIDTH (1U) 4905 #define SIUL2_PGPDO5_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO6_SHIFT)) & SIUL2_PGPDO5_PPDO6_MASK) 4906 4907 #define SIUL2_PGPDO5_PPDO7_MASK (0x80U) 4908 #define SIUL2_PGPDO5_PPDO7_SHIFT (7U) 4909 #define SIUL2_PGPDO5_PPDO7_WIDTH (1U) 4910 #define SIUL2_PGPDO5_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO7_SHIFT)) & SIUL2_PGPDO5_PPDO7_MASK) 4911 4912 #define SIUL2_PGPDO5_PPDO8_MASK (0x100U) 4913 #define SIUL2_PGPDO5_PPDO8_SHIFT (8U) 4914 #define SIUL2_PGPDO5_PPDO8_WIDTH (1U) 4915 #define SIUL2_PGPDO5_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO8_SHIFT)) & SIUL2_PGPDO5_PPDO8_MASK) 4916 4917 #define SIUL2_PGPDO5_PPDO9_MASK (0x200U) 4918 #define SIUL2_PGPDO5_PPDO9_SHIFT (9U) 4919 #define SIUL2_PGPDO5_PPDO9_WIDTH (1U) 4920 #define SIUL2_PGPDO5_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO9_SHIFT)) & SIUL2_PGPDO5_PPDO9_MASK) 4921 4922 #define SIUL2_PGPDO5_PPDO10_MASK (0x400U) 4923 #define SIUL2_PGPDO5_PPDO10_SHIFT (10U) 4924 #define SIUL2_PGPDO5_PPDO10_WIDTH (1U) 4925 #define SIUL2_PGPDO5_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO10_SHIFT)) & SIUL2_PGPDO5_PPDO10_MASK) 4926 4927 #define SIUL2_PGPDO5_PPDO11_MASK (0x800U) 4928 #define SIUL2_PGPDO5_PPDO11_SHIFT (11U) 4929 #define SIUL2_PGPDO5_PPDO11_WIDTH (1U) 4930 #define SIUL2_PGPDO5_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO11_SHIFT)) & SIUL2_PGPDO5_PPDO11_MASK) 4931 4932 #define SIUL2_PGPDO5_PPDO12_MASK (0x1000U) 4933 #define SIUL2_PGPDO5_PPDO12_SHIFT (12U) 4934 #define SIUL2_PGPDO5_PPDO12_WIDTH (1U) 4935 #define SIUL2_PGPDO5_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO12_SHIFT)) & SIUL2_PGPDO5_PPDO12_MASK) 4936 4937 #define SIUL2_PGPDO5_PPDO13_MASK (0x2000U) 4938 #define SIUL2_PGPDO5_PPDO13_SHIFT (13U) 4939 #define SIUL2_PGPDO5_PPDO13_WIDTH (1U) 4940 #define SIUL2_PGPDO5_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO13_SHIFT)) & SIUL2_PGPDO5_PPDO13_MASK) 4941 4942 #define SIUL2_PGPDO5_PPDO14_MASK (0x4000U) 4943 #define SIUL2_PGPDO5_PPDO14_SHIFT (14U) 4944 #define SIUL2_PGPDO5_PPDO14_WIDTH (1U) 4945 #define SIUL2_PGPDO5_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO14_SHIFT)) & SIUL2_PGPDO5_PPDO14_MASK) 4946 4947 #define SIUL2_PGPDO5_PPDO15_MASK (0x8000U) 4948 #define SIUL2_PGPDO5_PPDO15_SHIFT (15U) 4949 #define SIUL2_PGPDO5_PPDO15_WIDTH (1U) 4950 #define SIUL2_PGPDO5_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO5_PPDO15_SHIFT)) & SIUL2_PGPDO5_PPDO15_MASK) 4951 /*! @} */ 4952 4953 /*! @name PGPDO4 - SIUL2 Parallel GPIO Pad Data Out Register */ 4954 /*! @{ */ 4955 4956 #define SIUL2_PGPDO4_PPDO0_MASK (0x1U) 4957 #define SIUL2_PGPDO4_PPDO0_SHIFT (0U) 4958 #define SIUL2_PGPDO4_PPDO0_WIDTH (1U) 4959 #define SIUL2_PGPDO4_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO0_SHIFT)) & SIUL2_PGPDO4_PPDO0_MASK) 4960 4961 #define SIUL2_PGPDO4_PPDO1_MASK (0x2U) 4962 #define SIUL2_PGPDO4_PPDO1_SHIFT (1U) 4963 #define SIUL2_PGPDO4_PPDO1_WIDTH (1U) 4964 #define SIUL2_PGPDO4_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO1_SHIFT)) & SIUL2_PGPDO4_PPDO1_MASK) 4965 4966 #define SIUL2_PGPDO4_PPDO2_MASK (0x4U) 4967 #define SIUL2_PGPDO4_PPDO2_SHIFT (2U) 4968 #define SIUL2_PGPDO4_PPDO2_WIDTH (1U) 4969 #define SIUL2_PGPDO4_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO2_SHIFT)) & SIUL2_PGPDO4_PPDO2_MASK) 4970 4971 #define SIUL2_PGPDO4_PPDO3_MASK (0x8U) 4972 #define SIUL2_PGPDO4_PPDO3_SHIFT (3U) 4973 #define SIUL2_PGPDO4_PPDO3_WIDTH (1U) 4974 #define SIUL2_PGPDO4_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO3_SHIFT)) & SIUL2_PGPDO4_PPDO3_MASK) 4975 4976 #define SIUL2_PGPDO4_PPDO4_MASK (0x10U) 4977 #define SIUL2_PGPDO4_PPDO4_SHIFT (4U) 4978 #define SIUL2_PGPDO4_PPDO4_WIDTH (1U) 4979 #define SIUL2_PGPDO4_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO4_SHIFT)) & SIUL2_PGPDO4_PPDO4_MASK) 4980 4981 #define SIUL2_PGPDO4_PPDO5_MASK (0x20U) 4982 #define SIUL2_PGPDO4_PPDO5_SHIFT (5U) 4983 #define SIUL2_PGPDO4_PPDO5_WIDTH (1U) 4984 #define SIUL2_PGPDO4_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO5_SHIFT)) & SIUL2_PGPDO4_PPDO5_MASK) 4985 4986 #define SIUL2_PGPDO4_PPDO6_MASK (0x40U) 4987 #define SIUL2_PGPDO4_PPDO6_SHIFT (6U) 4988 #define SIUL2_PGPDO4_PPDO6_WIDTH (1U) 4989 #define SIUL2_PGPDO4_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO6_SHIFT)) & SIUL2_PGPDO4_PPDO6_MASK) 4990 4991 #define SIUL2_PGPDO4_PPDO7_MASK (0x80U) 4992 #define SIUL2_PGPDO4_PPDO7_SHIFT (7U) 4993 #define SIUL2_PGPDO4_PPDO7_WIDTH (1U) 4994 #define SIUL2_PGPDO4_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO7_SHIFT)) & SIUL2_PGPDO4_PPDO7_MASK) 4995 4996 #define SIUL2_PGPDO4_PPDO8_MASK (0x100U) 4997 #define SIUL2_PGPDO4_PPDO8_SHIFT (8U) 4998 #define SIUL2_PGPDO4_PPDO8_WIDTH (1U) 4999 #define SIUL2_PGPDO4_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO8_SHIFT)) & SIUL2_PGPDO4_PPDO8_MASK) 5000 5001 #define SIUL2_PGPDO4_PPDO9_MASK (0x200U) 5002 #define SIUL2_PGPDO4_PPDO9_SHIFT (9U) 5003 #define SIUL2_PGPDO4_PPDO9_WIDTH (1U) 5004 #define SIUL2_PGPDO4_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO9_SHIFT)) & SIUL2_PGPDO4_PPDO9_MASK) 5005 5006 #define SIUL2_PGPDO4_PPDO10_MASK (0x400U) 5007 #define SIUL2_PGPDO4_PPDO10_SHIFT (10U) 5008 #define SIUL2_PGPDO4_PPDO10_WIDTH (1U) 5009 #define SIUL2_PGPDO4_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO10_SHIFT)) & SIUL2_PGPDO4_PPDO10_MASK) 5010 5011 #define SIUL2_PGPDO4_PPDO11_MASK (0x800U) 5012 #define SIUL2_PGPDO4_PPDO11_SHIFT (11U) 5013 #define SIUL2_PGPDO4_PPDO11_WIDTH (1U) 5014 #define SIUL2_PGPDO4_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO11_SHIFT)) & SIUL2_PGPDO4_PPDO11_MASK) 5015 5016 #define SIUL2_PGPDO4_PPDO12_MASK (0x1000U) 5017 #define SIUL2_PGPDO4_PPDO12_SHIFT (12U) 5018 #define SIUL2_PGPDO4_PPDO12_WIDTH (1U) 5019 #define SIUL2_PGPDO4_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO12_SHIFT)) & SIUL2_PGPDO4_PPDO12_MASK) 5020 5021 #define SIUL2_PGPDO4_PPDO13_MASK (0x2000U) 5022 #define SIUL2_PGPDO4_PPDO13_SHIFT (13U) 5023 #define SIUL2_PGPDO4_PPDO13_WIDTH (1U) 5024 #define SIUL2_PGPDO4_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO13_SHIFT)) & SIUL2_PGPDO4_PPDO13_MASK) 5025 5026 #define SIUL2_PGPDO4_PPDO14_MASK (0x4000U) 5027 #define SIUL2_PGPDO4_PPDO14_SHIFT (14U) 5028 #define SIUL2_PGPDO4_PPDO14_WIDTH (1U) 5029 #define SIUL2_PGPDO4_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO14_SHIFT)) & SIUL2_PGPDO4_PPDO14_MASK) 5030 5031 #define SIUL2_PGPDO4_PPDO15_MASK (0x8000U) 5032 #define SIUL2_PGPDO4_PPDO15_SHIFT (15U) 5033 #define SIUL2_PGPDO4_PPDO15_WIDTH (1U) 5034 #define SIUL2_PGPDO4_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO4_PPDO15_SHIFT)) & SIUL2_PGPDO4_PPDO15_MASK) 5035 /*! @} */ 5036 5037 /*! @name PGPDO7 - SIUL2 Parallel GPIO Pad Data Out Register */ 5038 /*! @{ */ 5039 5040 #define SIUL2_PGPDO7_PPDO0_MASK (0x1U) 5041 #define SIUL2_PGPDO7_PPDO0_SHIFT (0U) 5042 #define SIUL2_PGPDO7_PPDO0_WIDTH (1U) 5043 #define SIUL2_PGPDO7_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO0_SHIFT)) & SIUL2_PGPDO7_PPDO0_MASK) 5044 5045 #define SIUL2_PGPDO7_PPDO1_MASK (0x2U) 5046 #define SIUL2_PGPDO7_PPDO1_SHIFT (1U) 5047 #define SIUL2_PGPDO7_PPDO1_WIDTH (1U) 5048 #define SIUL2_PGPDO7_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO1_SHIFT)) & SIUL2_PGPDO7_PPDO1_MASK) 5049 5050 #define SIUL2_PGPDO7_PPDO2_MASK (0x4U) 5051 #define SIUL2_PGPDO7_PPDO2_SHIFT (2U) 5052 #define SIUL2_PGPDO7_PPDO2_WIDTH (1U) 5053 #define SIUL2_PGPDO7_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO2_SHIFT)) & SIUL2_PGPDO7_PPDO2_MASK) 5054 5055 #define SIUL2_PGPDO7_PPDO3_MASK (0x8U) 5056 #define SIUL2_PGPDO7_PPDO3_SHIFT (3U) 5057 #define SIUL2_PGPDO7_PPDO3_WIDTH (1U) 5058 #define SIUL2_PGPDO7_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO3_SHIFT)) & SIUL2_PGPDO7_PPDO3_MASK) 5059 5060 #define SIUL2_PGPDO7_PPDO4_MASK (0x10U) 5061 #define SIUL2_PGPDO7_PPDO4_SHIFT (4U) 5062 #define SIUL2_PGPDO7_PPDO4_WIDTH (1U) 5063 #define SIUL2_PGPDO7_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO4_SHIFT)) & SIUL2_PGPDO7_PPDO4_MASK) 5064 5065 #define SIUL2_PGPDO7_PPDO5_MASK (0x20U) 5066 #define SIUL2_PGPDO7_PPDO5_SHIFT (5U) 5067 #define SIUL2_PGPDO7_PPDO5_WIDTH (1U) 5068 #define SIUL2_PGPDO7_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO5_SHIFT)) & SIUL2_PGPDO7_PPDO5_MASK) 5069 5070 #define SIUL2_PGPDO7_PPDO6_MASK (0x40U) 5071 #define SIUL2_PGPDO7_PPDO6_SHIFT (6U) 5072 #define SIUL2_PGPDO7_PPDO6_WIDTH (1U) 5073 #define SIUL2_PGPDO7_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO6_SHIFT)) & SIUL2_PGPDO7_PPDO6_MASK) 5074 5075 #define SIUL2_PGPDO7_PPDO7_MASK (0x80U) 5076 #define SIUL2_PGPDO7_PPDO7_SHIFT (7U) 5077 #define SIUL2_PGPDO7_PPDO7_WIDTH (1U) 5078 #define SIUL2_PGPDO7_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO7_SHIFT)) & SIUL2_PGPDO7_PPDO7_MASK) 5079 5080 #define SIUL2_PGPDO7_PPDO8_MASK (0x100U) 5081 #define SIUL2_PGPDO7_PPDO8_SHIFT (8U) 5082 #define SIUL2_PGPDO7_PPDO8_WIDTH (1U) 5083 #define SIUL2_PGPDO7_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO8_SHIFT)) & SIUL2_PGPDO7_PPDO8_MASK) 5084 5085 #define SIUL2_PGPDO7_PPDO9_MASK (0x200U) 5086 #define SIUL2_PGPDO7_PPDO9_SHIFT (9U) 5087 #define SIUL2_PGPDO7_PPDO9_WIDTH (1U) 5088 #define SIUL2_PGPDO7_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO9_SHIFT)) & SIUL2_PGPDO7_PPDO9_MASK) 5089 5090 #define SIUL2_PGPDO7_PPDO10_MASK (0x400U) 5091 #define SIUL2_PGPDO7_PPDO10_SHIFT (10U) 5092 #define SIUL2_PGPDO7_PPDO10_WIDTH (1U) 5093 #define SIUL2_PGPDO7_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO10_SHIFT)) & SIUL2_PGPDO7_PPDO10_MASK) 5094 5095 #define SIUL2_PGPDO7_PPDO11_MASK (0x800U) 5096 #define SIUL2_PGPDO7_PPDO11_SHIFT (11U) 5097 #define SIUL2_PGPDO7_PPDO11_WIDTH (1U) 5098 #define SIUL2_PGPDO7_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO11_SHIFT)) & SIUL2_PGPDO7_PPDO11_MASK) 5099 5100 #define SIUL2_PGPDO7_PPDO12_MASK (0x1000U) 5101 #define SIUL2_PGPDO7_PPDO12_SHIFT (12U) 5102 #define SIUL2_PGPDO7_PPDO12_WIDTH (1U) 5103 #define SIUL2_PGPDO7_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO12_SHIFT)) & SIUL2_PGPDO7_PPDO12_MASK) 5104 5105 #define SIUL2_PGPDO7_PPDO13_MASK (0x2000U) 5106 #define SIUL2_PGPDO7_PPDO13_SHIFT (13U) 5107 #define SIUL2_PGPDO7_PPDO13_WIDTH (1U) 5108 #define SIUL2_PGPDO7_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO13_SHIFT)) & SIUL2_PGPDO7_PPDO13_MASK) 5109 5110 #define SIUL2_PGPDO7_PPDO14_MASK (0x4000U) 5111 #define SIUL2_PGPDO7_PPDO14_SHIFT (14U) 5112 #define SIUL2_PGPDO7_PPDO14_WIDTH (1U) 5113 #define SIUL2_PGPDO7_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO14_SHIFT)) & SIUL2_PGPDO7_PPDO14_MASK) 5114 5115 #define SIUL2_PGPDO7_PPDO15_MASK (0x8000U) 5116 #define SIUL2_PGPDO7_PPDO15_SHIFT (15U) 5117 #define SIUL2_PGPDO7_PPDO15_WIDTH (1U) 5118 #define SIUL2_PGPDO7_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO7_PPDO15_SHIFT)) & SIUL2_PGPDO7_PPDO15_MASK) 5119 /*! @} */ 5120 5121 /*! @name PGPDO6 - SIUL2 Parallel GPIO Pad Data Out Register */ 5122 /*! @{ */ 5123 5124 #define SIUL2_PGPDO6_PPDO0_MASK (0x1U) 5125 #define SIUL2_PGPDO6_PPDO0_SHIFT (0U) 5126 #define SIUL2_PGPDO6_PPDO0_WIDTH (1U) 5127 #define SIUL2_PGPDO6_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO0_SHIFT)) & SIUL2_PGPDO6_PPDO0_MASK) 5128 5129 #define SIUL2_PGPDO6_PPDO1_MASK (0x2U) 5130 #define SIUL2_PGPDO6_PPDO1_SHIFT (1U) 5131 #define SIUL2_PGPDO6_PPDO1_WIDTH (1U) 5132 #define SIUL2_PGPDO6_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO1_SHIFT)) & SIUL2_PGPDO6_PPDO1_MASK) 5133 5134 #define SIUL2_PGPDO6_PPDO2_MASK (0x4U) 5135 #define SIUL2_PGPDO6_PPDO2_SHIFT (2U) 5136 #define SIUL2_PGPDO6_PPDO2_WIDTH (1U) 5137 #define SIUL2_PGPDO6_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO2_SHIFT)) & SIUL2_PGPDO6_PPDO2_MASK) 5138 5139 #define SIUL2_PGPDO6_PPDO3_MASK (0x8U) 5140 #define SIUL2_PGPDO6_PPDO3_SHIFT (3U) 5141 #define SIUL2_PGPDO6_PPDO3_WIDTH (1U) 5142 #define SIUL2_PGPDO6_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO3_SHIFT)) & SIUL2_PGPDO6_PPDO3_MASK) 5143 5144 #define SIUL2_PGPDO6_PPDO4_MASK (0x10U) 5145 #define SIUL2_PGPDO6_PPDO4_SHIFT (4U) 5146 #define SIUL2_PGPDO6_PPDO4_WIDTH (1U) 5147 #define SIUL2_PGPDO6_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO4_SHIFT)) & SIUL2_PGPDO6_PPDO4_MASK) 5148 5149 #define SIUL2_PGPDO6_PPDO5_MASK (0x20U) 5150 #define SIUL2_PGPDO6_PPDO5_SHIFT (5U) 5151 #define SIUL2_PGPDO6_PPDO5_WIDTH (1U) 5152 #define SIUL2_PGPDO6_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO5_SHIFT)) & SIUL2_PGPDO6_PPDO5_MASK) 5153 5154 #define SIUL2_PGPDO6_PPDO6_MASK (0x40U) 5155 #define SIUL2_PGPDO6_PPDO6_SHIFT (6U) 5156 #define SIUL2_PGPDO6_PPDO6_WIDTH (1U) 5157 #define SIUL2_PGPDO6_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO6_SHIFT)) & SIUL2_PGPDO6_PPDO6_MASK) 5158 5159 #define SIUL2_PGPDO6_PPDO7_MASK (0x80U) 5160 #define SIUL2_PGPDO6_PPDO7_SHIFT (7U) 5161 #define SIUL2_PGPDO6_PPDO7_WIDTH (1U) 5162 #define SIUL2_PGPDO6_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO7_SHIFT)) & SIUL2_PGPDO6_PPDO7_MASK) 5163 5164 #define SIUL2_PGPDO6_PPDO8_MASK (0x100U) 5165 #define SIUL2_PGPDO6_PPDO8_SHIFT (8U) 5166 #define SIUL2_PGPDO6_PPDO8_WIDTH (1U) 5167 #define SIUL2_PGPDO6_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO8_SHIFT)) & SIUL2_PGPDO6_PPDO8_MASK) 5168 5169 #define SIUL2_PGPDO6_PPDO9_MASK (0x200U) 5170 #define SIUL2_PGPDO6_PPDO9_SHIFT (9U) 5171 #define SIUL2_PGPDO6_PPDO9_WIDTH (1U) 5172 #define SIUL2_PGPDO6_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO9_SHIFT)) & SIUL2_PGPDO6_PPDO9_MASK) 5173 5174 #define SIUL2_PGPDO6_PPDO10_MASK (0x400U) 5175 #define SIUL2_PGPDO6_PPDO10_SHIFT (10U) 5176 #define SIUL2_PGPDO6_PPDO10_WIDTH (1U) 5177 #define SIUL2_PGPDO6_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO10_SHIFT)) & SIUL2_PGPDO6_PPDO10_MASK) 5178 5179 #define SIUL2_PGPDO6_PPDO11_MASK (0x800U) 5180 #define SIUL2_PGPDO6_PPDO11_SHIFT (11U) 5181 #define SIUL2_PGPDO6_PPDO11_WIDTH (1U) 5182 #define SIUL2_PGPDO6_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO11_SHIFT)) & SIUL2_PGPDO6_PPDO11_MASK) 5183 5184 #define SIUL2_PGPDO6_PPDO12_MASK (0x1000U) 5185 #define SIUL2_PGPDO6_PPDO12_SHIFT (12U) 5186 #define SIUL2_PGPDO6_PPDO12_WIDTH (1U) 5187 #define SIUL2_PGPDO6_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO12_SHIFT)) & SIUL2_PGPDO6_PPDO12_MASK) 5188 5189 #define SIUL2_PGPDO6_PPDO13_MASK (0x2000U) 5190 #define SIUL2_PGPDO6_PPDO13_SHIFT (13U) 5191 #define SIUL2_PGPDO6_PPDO13_WIDTH (1U) 5192 #define SIUL2_PGPDO6_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO13_SHIFT)) & SIUL2_PGPDO6_PPDO13_MASK) 5193 5194 #define SIUL2_PGPDO6_PPDO14_MASK (0x4000U) 5195 #define SIUL2_PGPDO6_PPDO14_SHIFT (14U) 5196 #define SIUL2_PGPDO6_PPDO14_WIDTH (1U) 5197 #define SIUL2_PGPDO6_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO14_SHIFT)) & SIUL2_PGPDO6_PPDO14_MASK) 5198 5199 #define SIUL2_PGPDO6_PPDO15_MASK (0x8000U) 5200 #define SIUL2_PGPDO6_PPDO15_SHIFT (15U) 5201 #define SIUL2_PGPDO6_PPDO15_WIDTH (1U) 5202 #define SIUL2_PGPDO6_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO6_PPDO15_SHIFT)) & SIUL2_PGPDO6_PPDO15_MASK) 5203 /*! @} */ 5204 5205 /*! @name PGPDO9 - SIUL2 Parallel GPIO Pad Data Out Register */ 5206 /*! @{ */ 5207 5208 #define SIUL2_PGPDO9_PPDO0_MASK (0x1U) 5209 #define SIUL2_PGPDO9_PPDO0_SHIFT (0U) 5210 #define SIUL2_PGPDO9_PPDO0_WIDTH (1U) 5211 #define SIUL2_PGPDO9_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO0_SHIFT)) & SIUL2_PGPDO9_PPDO0_MASK) 5212 5213 #define SIUL2_PGPDO9_PPDO1_MASK (0x2U) 5214 #define SIUL2_PGPDO9_PPDO1_SHIFT (1U) 5215 #define SIUL2_PGPDO9_PPDO1_WIDTH (1U) 5216 #define SIUL2_PGPDO9_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO1_SHIFT)) & SIUL2_PGPDO9_PPDO1_MASK) 5217 5218 #define SIUL2_PGPDO9_PPDO2_MASK (0x4U) 5219 #define SIUL2_PGPDO9_PPDO2_SHIFT (2U) 5220 #define SIUL2_PGPDO9_PPDO2_WIDTH (1U) 5221 #define SIUL2_PGPDO9_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO2_SHIFT)) & SIUL2_PGPDO9_PPDO2_MASK) 5222 5223 #define SIUL2_PGPDO9_PPDO3_MASK (0x8U) 5224 #define SIUL2_PGPDO9_PPDO3_SHIFT (3U) 5225 #define SIUL2_PGPDO9_PPDO3_WIDTH (1U) 5226 #define SIUL2_PGPDO9_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO3_SHIFT)) & SIUL2_PGPDO9_PPDO3_MASK) 5227 5228 #define SIUL2_PGPDO9_PPDO4_MASK (0x10U) 5229 #define SIUL2_PGPDO9_PPDO4_SHIFT (4U) 5230 #define SIUL2_PGPDO9_PPDO4_WIDTH (1U) 5231 #define SIUL2_PGPDO9_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO4_SHIFT)) & SIUL2_PGPDO9_PPDO4_MASK) 5232 5233 #define SIUL2_PGPDO9_PPDO5_MASK (0x20U) 5234 #define SIUL2_PGPDO9_PPDO5_SHIFT (5U) 5235 #define SIUL2_PGPDO9_PPDO5_WIDTH (1U) 5236 #define SIUL2_PGPDO9_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO5_SHIFT)) & SIUL2_PGPDO9_PPDO5_MASK) 5237 5238 #define SIUL2_PGPDO9_PPDO6_MASK (0x40U) 5239 #define SIUL2_PGPDO9_PPDO6_SHIFT (6U) 5240 #define SIUL2_PGPDO9_PPDO6_WIDTH (1U) 5241 #define SIUL2_PGPDO9_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO6_SHIFT)) & SIUL2_PGPDO9_PPDO6_MASK) 5242 5243 #define SIUL2_PGPDO9_PPDO7_MASK (0x80U) 5244 #define SIUL2_PGPDO9_PPDO7_SHIFT (7U) 5245 #define SIUL2_PGPDO9_PPDO7_WIDTH (1U) 5246 #define SIUL2_PGPDO9_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO7_SHIFT)) & SIUL2_PGPDO9_PPDO7_MASK) 5247 5248 #define SIUL2_PGPDO9_PPDO8_MASK (0x100U) 5249 #define SIUL2_PGPDO9_PPDO8_SHIFT (8U) 5250 #define SIUL2_PGPDO9_PPDO8_WIDTH (1U) 5251 #define SIUL2_PGPDO9_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO8_SHIFT)) & SIUL2_PGPDO9_PPDO8_MASK) 5252 5253 #define SIUL2_PGPDO9_PPDO9_MASK (0x200U) 5254 #define SIUL2_PGPDO9_PPDO9_SHIFT (9U) 5255 #define SIUL2_PGPDO9_PPDO9_WIDTH (1U) 5256 #define SIUL2_PGPDO9_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO9_SHIFT)) & SIUL2_PGPDO9_PPDO9_MASK) 5257 5258 #define SIUL2_PGPDO9_PPDO10_MASK (0x400U) 5259 #define SIUL2_PGPDO9_PPDO10_SHIFT (10U) 5260 #define SIUL2_PGPDO9_PPDO10_WIDTH (1U) 5261 #define SIUL2_PGPDO9_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO10_SHIFT)) & SIUL2_PGPDO9_PPDO10_MASK) 5262 5263 #define SIUL2_PGPDO9_PPDO11_MASK (0x800U) 5264 #define SIUL2_PGPDO9_PPDO11_SHIFT (11U) 5265 #define SIUL2_PGPDO9_PPDO11_WIDTH (1U) 5266 #define SIUL2_PGPDO9_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO11_SHIFT)) & SIUL2_PGPDO9_PPDO11_MASK) 5267 5268 #define SIUL2_PGPDO9_PPDO12_MASK (0x1000U) 5269 #define SIUL2_PGPDO9_PPDO12_SHIFT (12U) 5270 #define SIUL2_PGPDO9_PPDO12_WIDTH (1U) 5271 #define SIUL2_PGPDO9_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO12_SHIFT)) & SIUL2_PGPDO9_PPDO12_MASK) 5272 5273 #define SIUL2_PGPDO9_PPDO13_MASK (0x2000U) 5274 #define SIUL2_PGPDO9_PPDO13_SHIFT (13U) 5275 #define SIUL2_PGPDO9_PPDO13_WIDTH (1U) 5276 #define SIUL2_PGPDO9_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO13_SHIFT)) & SIUL2_PGPDO9_PPDO13_MASK) 5277 5278 #define SIUL2_PGPDO9_PPDO14_MASK (0x4000U) 5279 #define SIUL2_PGPDO9_PPDO14_SHIFT (14U) 5280 #define SIUL2_PGPDO9_PPDO14_WIDTH (1U) 5281 #define SIUL2_PGPDO9_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO14_SHIFT)) & SIUL2_PGPDO9_PPDO14_MASK) 5282 5283 #define SIUL2_PGPDO9_PPDO15_MASK (0x8000U) 5284 #define SIUL2_PGPDO9_PPDO15_SHIFT (15U) 5285 #define SIUL2_PGPDO9_PPDO15_WIDTH (1U) 5286 #define SIUL2_PGPDO9_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO9_PPDO15_SHIFT)) & SIUL2_PGPDO9_PPDO15_MASK) 5287 /*! @} */ 5288 5289 /*! @name PGPDO8 - SIUL2 Parallel GPIO Pad Data Out Register */ 5290 /*! @{ */ 5291 5292 #define SIUL2_PGPDO8_PPDO0_MASK (0x1U) 5293 #define SIUL2_PGPDO8_PPDO0_SHIFT (0U) 5294 #define SIUL2_PGPDO8_PPDO0_WIDTH (1U) 5295 #define SIUL2_PGPDO8_PPDO0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO0_SHIFT)) & SIUL2_PGPDO8_PPDO0_MASK) 5296 5297 #define SIUL2_PGPDO8_PPDO1_MASK (0x2U) 5298 #define SIUL2_PGPDO8_PPDO1_SHIFT (1U) 5299 #define SIUL2_PGPDO8_PPDO1_WIDTH (1U) 5300 #define SIUL2_PGPDO8_PPDO1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO1_SHIFT)) & SIUL2_PGPDO8_PPDO1_MASK) 5301 5302 #define SIUL2_PGPDO8_PPDO2_MASK (0x4U) 5303 #define SIUL2_PGPDO8_PPDO2_SHIFT (2U) 5304 #define SIUL2_PGPDO8_PPDO2_WIDTH (1U) 5305 #define SIUL2_PGPDO8_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO2_SHIFT)) & SIUL2_PGPDO8_PPDO2_MASK) 5306 5307 #define SIUL2_PGPDO8_PPDO3_MASK (0x8U) 5308 #define SIUL2_PGPDO8_PPDO3_SHIFT (3U) 5309 #define SIUL2_PGPDO8_PPDO3_WIDTH (1U) 5310 #define SIUL2_PGPDO8_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO3_SHIFT)) & SIUL2_PGPDO8_PPDO3_MASK) 5311 5312 #define SIUL2_PGPDO8_PPDO4_MASK (0x10U) 5313 #define SIUL2_PGPDO8_PPDO4_SHIFT (4U) 5314 #define SIUL2_PGPDO8_PPDO4_WIDTH (1U) 5315 #define SIUL2_PGPDO8_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO4_SHIFT)) & SIUL2_PGPDO8_PPDO4_MASK) 5316 5317 #define SIUL2_PGPDO8_PPDO5_MASK (0x20U) 5318 #define SIUL2_PGPDO8_PPDO5_SHIFT (5U) 5319 #define SIUL2_PGPDO8_PPDO5_WIDTH (1U) 5320 #define SIUL2_PGPDO8_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO5_SHIFT)) & SIUL2_PGPDO8_PPDO5_MASK) 5321 5322 #define SIUL2_PGPDO8_PPDO6_MASK (0x40U) 5323 #define SIUL2_PGPDO8_PPDO6_SHIFT (6U) 5324 #define SIUL2_PGPDO8_PPDO6_WIDTH (1U) 5325 #define SIUL2_PGPDO8_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO6_SHIFT)) & SIUL2_PGPDO8_PPDO6_MASK) 5326 5327 #define SIUL2_PGPDO8_PPDO7_MASK (0x80U) 5328 #define SIUL2_PGPDO8_PPDO7_SHIFT (7U) 5329 #define SIUL2_PGPDO8_PPDO7_WIDTH (1U) 5330 #define SIUL2_PGPDO8_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO7_SHIFT)) & SIUL2_PGPDO8_PPDO7_MASK) 5331 5332 #define SIUL2_PGPDO8_PPDO8_MASK (0x100U) 5333 #define SIUL2_PGPDO8_PPDO8_SHIFT (8U) 5334 #define SIUL2_PGPDO8_PPDO8_WIDTH (1U) 5335 #define SIUL2_PGPDO8_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO8_SHIFT)) & SIUL2_PGPDO8_PPDO8_MASK) 5336 5337 #define SIUL2_PGPDO8_PPDO9_MASK (0x200U) 5338 #define SIUL2_PGPDO8_PPDO9_SHIFT (9U) 5339 #define SIUL2_PGPDO8_PPDO9_WIDTH (1U) 5340 #define SIUL2_PGPDO8_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO9_SHIFT)) & SIUL2_PGPDO8_PPDO9_MASK) 5341 5342 #define SIUL2_PGPDO8_PPDO10_MASK (0x400U) 5343 #define SIUL2_PGPDO8_PPDO10_SHIFT (10U) 5344 #define SIUL2_PGPDO8_PPDO10_WIDTH (1U) 5345 #define SIUL2_PGPDO8_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO10_SHIFT)) & SIUL2_PGPDO8_PPDO10_MASK) 5346 5347 #define SIUL2_PGPDO8_PPDO11_MASK (0x800U) 5348 #define SIUL2_PGPDO8_PPDO11_SHIFT (11U) 5349 #define SIUL2_PGPDO8_PPDO11_WIDTH (1U) 5350 #define SIUL2_PGPDO8_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO11_SHIFT)) & SIUL2_PGPDO8_PPDO11_MASK) 5351 5352 #define SIUL2_PGPDO8_PPDO12_MASK (0x1000U) 5353 #define SIUL2_PGPDO8_PPDO12_SHIFT (12U) 5354 #define SIUL2_PGPDO8_PPDO12_WIDTH (1U) 5355 #define SIUL2_PGPDO8_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO12_SHIFT)) & SIUL2_PGPDO8_PPDO12_MASK) 5356 5357 #define SIUL2_PGPDO8_PPDO13_MASK (0x2000U) 5358 #define SIUL2_PGPDO8_PPDO13_SHIFT (13U) 5359 #define SIUL2_PGPDO8_PPDO13_WIDTH (1U) 5360 #define SIUL2_PGPDO8_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO13_SHIFT)) & SIUL2_PGPDO8_PPDO13_MASK) 5361 5362 #define SIUL2_PGPDO8_PPDO14_MASK (0x4000U) 5363 #define SIUL2_PGPDO8_PPDO14_SHIFT (14U) 5364 #define SIUL2_PGPDO8_PPDO14_WIDTH (1U) 5365 #define SIUL2_PGPDO8_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO14_SHIFT)) & SIUL2_PGPDO8_PPDO14_MASK) 5366 5367 #define SIUL2_PGPDO8_PPDO15_MASK (0x8000U) 5368 #define SIUL2_PGPDO8_PPDO15_SHIFT (15U) 5369 #define SIUL2_PGPDO8_PPDO15_WIDTH (1U) 5370 #define SIUL2_PGPDO8_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO8_PPDO15_SHIFT)) & SIUL2_PGPDO8_PPDO15_MASK) 5371 /*! @} */ 5372 5373 /*! @name PGPDO10 - SIUL2 Parallel GPIO Pad Data Out Register */ 5374 /*! @{ */ 5375 5376 #define SIUL2_PGPDO10_PPDO2_MASK (0x4U) 5377 #define SIUL2_PGPDO10_PPDO2_SHIFT (2U) 5378 #define SIUL2_PGPDO10_PPDO2_WIDTH (1U) 5379 #define SIUL2_PGPDO10_PPDO2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO2_SHIFT)) & SIUL2_PGPDO10_PPDO2_MASK) 5380 5381 #define SIUL2_PGPDO10_PPDO3_MASK (0x8U) 5382 #define SIUL2_PGPDO10_PPDO3_SHIFT (3U) 5383 #define SIUL2_PGPDO10_PPDO3_WIDTH (1U) 5384 #define SIUL2_PGPDO10_PPDO3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO3_SHIFT)) & SIUL2_PGPDO10_PPDO3_MASK) 5385 5386 #define SIUL2_PGPDO10_PPDO4_MASK (0x10U) 5387 #define SIUL2_PGPDO10_PPDO4_SHIFT (4U) 5388 #define SIUL2_PGPDO10_PPDO4_WIDTH (1U) 5389 #define SIUL2_PGPDO10_PPDO4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO4_SHIFT)) & SIUL2_PGPDO10_PPDO4_MASK) 5390 5391 #define SIUL2_PGPDO10_PPDO5_MASK (0x20U) 5392 #define SIUL2_PGPDO10_PPDO5_SHIFT (5U) 5393 #define SIUL2_PGPDO10_PPDO5_WIDTH (1U) 5394 #define SIUL2_PGPDO10_PPDO5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO5_SHIFT)) & SIUL2_PGPDO10_PPDO5_MASK) 5395 5396 #define SIUL2_PGPDO10_PPDO6_MASK (0x40U) 5397 #define SIUL2_PGPDO10_PPDO6_SHIFT (6U) 5398 #define SIUL2_PGPDO10_PPDO6_WIDTH (1U) 5399 #define SIUL2_PGPDO10_PPDO6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO6_SHIFT)) & SIUL2_PGPDO10_PPDO6_MASK) 5400 5401 #define SIUL2_PGPDO10_PPDO7_MASK (0x80U) 5402 #define SIUL2_PGPDO10_PPDO7_SHIFT (7U) 5403 #define SIUL2_PGPDO10_PPDO7_WIDTH (1U) 5404 #define SIUL2_PGPDO10_PPDO7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO7_SHIFT)) & SIUL2_PGPDO10_PPDO7_MASK) 5405 5406 #define SIUL2_PGPDO10_PPDO8_MASK (0x100U) 5407 #define SIUL2_PGPDO10_PPDO8_SHIFT (8U) 5408 #define SIUL2_PGPDO10_PPDO8_WIDTH (1U) 5409 #define SIUL2_PGPDO10_PPDO8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO8_SHIFT)) & SIUL2_PGPDO10_PPDO8_MASK) 5410 5411 #define SIUL2_PGPDO10_PPDO9_MASK (0x200U) 5412 #define SIUL2_PGPDO10_PPDO9_SHIFT (9U) 5413 #define SIUL2_PGPDO10_PPDO9_WIDTH (1U) 5414 #define SIUL2_PGPDO10_PPDO9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO9_SHIFT)) & SIUL2_PGPDO10_PPDO9_MASK) 5415 5416 #define SIUL2_PGPDO10_PPDO10_MASK (0x400U) 5417 #define SIUL2_PGPDO10_PPDO10_SHIFT (10U) 5418 #define SIUL2_PGPDO10_PPDO10_WIDTH (1U) 5419 #define SIUL2_PGPDO10_PPDO10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO10_SHIFT)) & SIUL2_PGPDO10_PPDO10_MASK) 5420 5421 #define SIUL2_PGPDO10_PPDO11_MASK (0x800U) 5422 #define SIUL2_PGPDO10_PPDO11_SHIFT (11U) 5423 #define SIUL2_PGPDO10_PPDO11_WIDTH (1U) 5424 #define SIUL2_PGPDO10_PPDO11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO11_SHIFT)) & SIUL2_PGPDO10_PPDO11_MASK) 5425 5426 #define SIUL2_PGPDO10_PPDO12_MASK (0x1000U) 5427 #define SIUL2_PGPDO10_PPDO12_SHIFT (12U) 5428 #define SIUL2_PGPDO10_PPDO12_WIDTH (1U) 5429 #define SIUL2_PGPDO10_PPDO12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO12_SHIFT)) & SIUL2_PGPDO10_PPDO12_MASK) 5430 5431 #define SIUL2_PGPDO10_PPDO13_MASK (0x2000U) 5432 #define SIUL2_PGPDO10_PPDO13_SHIFT (13U) 5433 #define SIUL2_PGPDO10_PPDO13_WIDTH (1U) 5434 #define SIUL2_PGPDO10_PPDO13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO13_SHIFT)) & SIUL2_PGPDO10_PPDO13_MASK) 5435 5436 #define SIUL2_PGPDO10_PPDO14_MASK (0x4000U) 5437 #define SIUL2_PGPDO10_PPDO14_SHIFT (14U) 5438 #define SIUL2_PGPDO10_PPDO14_WIDTH (1U) 5439 #define SIUL2_PGPDO10_PPDO14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO14_SHIFT)) & SIUL2_PGPDO10_PPDO14_MASK) 5440 5441 #define SIUL2_PGPDO10_PPDO15_MASK (0x8000U) 5442 #define SIUL2_PGPDO10_PPDO15_SHIFT (15U) 5443 #define SIUL2_PGPDO10_PPDO15_WIDTH (1U) 5444 #define SIUL2_PGPDO10_PPDO15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDO10_PPDO15_SHIFT)) & SIUL2_PGPDO10_PPDO15_MASK) 5445 /*! @} */ 5446 5447 /*! @name PGPDI1 - SIUL2 Parallel GPIO Pad Data In Register */ 5448 /*! @{ */ 5449 5450 #define SIUL2_PGPDI1_PPDI0_MASK (0x1U) 5451 #define SIUL2_PGPDI1_PPDI0_SHIFT (0U) 5452 #define SIUL2_PGPDI1_PPDI0_WIDTH (1U) 5453 #define SIUL2_PGPDI1_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI0_SHIFT)) & SIUL2_PGPDI1_PPDI0_MASK) 5454 5455 #define SIUL2_PGPDI1_PPDI1_MASK (0x2U) 5456 #define SIUL2_PGPDI1_PPDI1_SHIFT (1U) 5457 #define SIUL2_PGPDI1_PPDI1_WIDTH (1U) 5458 #define SIUL2_PGPDI1_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI1_SHIFT)) & SIUL2_PGPDI1_PPDI1_MASK) 5459 5460 #define SIUL2_PGPDI1_PPDI2_MASK (0x4U) 5461 #define SIUL2_PGPDI1_PPDI2_SHIFT (2U) 5462 #define SIUL2_PGPDI1_PPDI2_WIDTH (1U) 5463 #define SIUL2_PGPDI1_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI2_SHIFT)) & SIUL2_PGPDI1_PPDI2_MASK) 5464 5465 #define SIUL2_PGPDI1_PPDI3_MASK (0x8U) 5466 #define SIUL2_PGPDI1_PPDI3_SHIFT (3U) 5467 #define SIUL2_PGPDI1_PPDI3_WIDTH (1U) 5468 #define SIUL2_PGPDI1_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI3_SHIFT)) & SIUL2_PGPDI1_PPDI3_MASK) 5469 5470 #define SIUL2_PGPDI1_PPDI4_MASK (0x10U) 5471 #define SIUL2_PGPDI1_PPDI4_SHIFT (4U) 5472 #define SIUL2_PGPDI1_PPDI4_WIDTH (1U) 5473 #define SIUL2_PGPDI1_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI4_SHIFT)) & SIUL2_PGPDI1_PPDI4_MASK) 5474 5475 #define SIUL2_PGPDI1_PPDI5_MASK (0x20U) 5476 #define SIUL2_PGPDI1_PPDI5_SHIFT (5U) 5477 #define SIUL2_PGPDI1_PPDI5_WIDTH (1U) 5478 #define SIUL2_PGPDI1_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI5_SHIFT)) & SIUL2_PGPDI1_PPDI5_MASK) 5479 5480 #define SIUL2_PGPDI1_PPDI6_MASK (0x40U) 5481 #define SIUL2_PGPDI1_PPDI6_SHIFT (6U) 5482 #define SIUL2_PGPDI1_PPDI6_WIDTH (1U) 5483 #define SIUL2_PGPDI1_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI6_SHIFT)) & SIUL2_PGPDI1_PPDI6_MASK) 5484 5485 #define SIUL2_PGPDI1_PPDI7_MASK (0x80U) 5486 #define SIUL2_PGPDI1_PPDI7_SHIFT (7U) 5487 #define SIUL2_PGPDI1_PPDI7_WIDTH (1U) 5488 #define SIUL2_PGPDI1_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI7_SHIFT)) & SIUL2_PGPDI1_PPDI7_MASK) 5489 5490 #define SIUL2_PGPDI1_PPDI8_MASK (0x100U) 5491 #define SIUL2_PGPDI1_PPDI8_SHIFT (8U) 5492 #define SIUL2_PGPDI1_PPDI8_WIDTH (1U) 5493 #define SIUL2_PGPDI1_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI8_SHIFT)) & SIUL2_PGPDI1_PPDI8_MASK) 5494 5495 #define SIUL2_PGPDI1_PPDI9_MASK (0x200U) 5496 #define SIUL2_PGPDI1_PPDI9_SHIFT (9U) 5497 #define SIUL2_PGPDI1_PPDI9_WIDTH (1U) 5498 #define SIUL2_PGPDI1_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI9_SHIFT)) & SIUL2_PGPDI1_PPDI9_MASK) 5499 5500 #define SIUL2_PGPDI1_PPDI10_MASK (0x400U) 5501 #define SIUL2_PGPDI1_PPDI10_SHIFT (10U) 5502 #define SIUL2_PGPDI1_PPDI10_WIDTH (1U) 5503 #define SIUL2_PGPDI1_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI10_SHIFT)) & SIUL2_PGPDI1_PPDI10_MASK) 5504 5505 #define SIUL2_PGPDI1_PPDI11_MASK (0x800U) 5506 #define SIUL2_PGPDI1_PPDI11_SHIFT (11U) 5507 #define SIUL2_PGPDI1_PPDI11_WIDTH (1U) 5508 #define SIUL2_PGPDI1_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI11_SHIFT)) & SIUL2_PGPDI1_PPDI11_MASK) 5509 5510 #define SIUL2_PGPDI1_PPDI12_MASK (0x1000U) 5511 #define SIUL2_PGPDI1_PPDI12_SHIFT (12U) 5512 #define SIUL2_PGPDI1_PPDI12_WIDTH (1U) 5513 #define SIUL2_PGPDI1_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI12_SHIFT)) & SIUL2_PGPDI1_PPDI12_MASK) 5514 5515 #define SIUL2_PGPDI1_PPDI13_MASK (0x2000U) 5516 #define SIUL2_PGPDI1_PPDI13_SHIFT (13U) 5517 #define SIUL2_PGPDI1_PPDI13_WIDTH (1U) 5518 #define SIUL2_PGPDI1_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI13_SHIFT)) & SIUL2_PGPDI1_PPDI13_MASK) 5519 5520 #define SIUL2_PGPDI1_PPDI14_MASK (0x4000U) 5521 #define SIUL2_PGPDI1_PPDI14_SHIFT (14U) 5522 #define SIUL2_PGPDI1_PPDI14_WIDTH (1U) 5523 #define SIUL2_PGPDI1_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI14_SHIFT)) & SIUL2_PGPDI1_PPDI14_MASK) 5524 5525 #define SIUL2_PGPDI1_PPDI15_MASK (0x8000U) 5526 #define SIUL2_PGPDI1_PPDI15_SHIFT (15U) 5527 #define SIUL2_PGPDI1_PPDI15_WIDTH (1U) 5528 #define SIUL2_PGPDI1_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI1_PPDI15_SHIFT)) & SIUL2_PGPDI1_PPDI15_MASK) 5529 /*! @} */ 5530 5531 /*! @name PGPDI0 - SIUL2 Parallel GPIO Pad Data In Register */ 5532 /*! @{ */ 5533 5534 #define SIUL2_PGPDI0_PPDI0_MASK (0x1U) 5535 #define SIUL2_PGPDI0_PPDI0_SHIFT (0U) 5536 #define SIUL2_PGPDI0_PPDI0_WIDTH (1U) 5537 #define SIUL2_PGPDI0_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI0_SHIFT)) & SIUL2_PGPDI0_PPDI0_MASK) 5538 5539 #define SIUL2_PGPDI0_PPDI1_MASK (0x2U) 5540 #define SIUL2_PGPDI0_PPDI1_SHIFT (1U) 5541 #define SIUL2_PGPDI0_PPDI1_WIDTH (1U) 5542 #define SIUL2_PGPDI0_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI1_SHIFT)) & SIUL2_PGPDI0_PPDI1_MASK) 5543 5544 #define SIUL2_PGPDI0_PPDI2_MASK (0x4U) 5545 #define SIUL2_PGPDI0_PPDI2_SHIFT (2U) 5546 #define SIUL2_PGPDI0_PPDI2_WIDTH (1U) 5547 #define SIUL2_PGPDI0_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI2_SHIFT)) & SIUL2_PGPDI0_PPDI2_MASK) 5548 5549 #define SIUL2_PGPDI0_PPDI3_MASK (0x8U) 5550 #define SIUL2_PGPDI0_PPDI3_SHIFT (3U) 5551 #define SIUL2_PGPDI0_PPDI3_WIDTH (1U) 5552 #define SIUL2_PGPDI0_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI3_SHIFT)) & SIUL2_PGPDI0_PPDI3_MASK) 5553 5554 #define SIUL2_PGPDI0_PPDI4_MASK (0x10U) 5555 #define SIUL2_PGPDI0_PPDI4_SHIFT (4U) 5556 #define SIUL2_PGPDI0_PPDI4_WIDTH (1U) 5557 #define SIUL2_PGPDI0_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI4_SHIFT)) & SIUL2_PGPDI0_PPDI4_MASK) 5558 5559 #define SIUL2_PGPDI0_PPDI5_MASK (0x20U) 5560 #define SIUL2_PGPDI0_PPDI5_SHIFT (5U) 5561 #define SIUL2_PGPDI0_PPDI5_WIDTH (1U) 5562 #define SIUL2_PGPDI0_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI5_SHIFT)) & SIUL2_PGPDI0_PPDI5_MASK) 5563 5564 #define SIUL2_PGPDI0_PPDI6_MASK (0x40U) 5565 #define SIUL2_PGPDI0_PPDI6_SHIFT (6U) 5566 #define SIUL2_PGPDI0_PPDI6_WIDTH (1U) 5567 #define SIUL2_PGPDI0_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI6_SHIFT)) & SIUL2_PGPDI0_PPDI6_MASK) 5568 5569 #define SIUL2_PGPDI0_PPDI7_MASK (0x80U) 5570 #define SIUL2_PGPDI0_PPDI7_SHIFT (7U) 5571 #define SIUL2_PGPDI0_PPDI7_WIDTH (1U) 5572 #define SIUL2_PGPDI0_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI7_SHIFT)) & SIUL2_PGPDI0_PPDI7_MASK) 5573 5574 #define SIUL2_PGPDI0_PPDI8_MASK (0x100U) 5575 #define SIUL2_PGPDI0_PPDI8_SHIFT (8U) 5576 #define SIUL2_PGPDI0_PPDI8_WIDTH (1U) 5577 #define SIUL2_PGPDI0_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI8_SHIFT)) & SIUL2_PGPDI0_PPDI8_MASK) 5578 5579 #define SIUL2_PGPDI0_PPDI9_MASK (0x200U) 5580 #define SIUL2_PGPDI0_PPDI9_SHIFT (9U) 5581 #define SIUL2_PGPDI0_PPDI9_WIDTH (1U) 5582 #define SIUL2_PGPDI0_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI9_SHIFT)) & SIUL2_PGPDI0_PPDI9_MASK) 5583 5584 #define SIUL2_PGPDI0_PPDI10_MASK (0x400U) 5585 #define SIUL2_PGPDI0_PPDI10_SHIFT (10U) 5586 #define SIUL2_PGPDI0_PPDI10_WIDTH (1U) 5587 #define SIUL2_PGPDI0_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI10_SHIFT)) & SIUL2_PGPDI0_PPDI10_MASK) 5588 5589 #define SIUL2_PGPDI0_PPDI11_MASK (0x800U) 5590 #define SIUL2_PGPDI0_PPDI11_SHIFT (11U) 5591 #define SIUL2_PGPDI0_PPDI11_WIDTH (1U) 5592 #define SIUL2_PGPDI0_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI11_SHIFT)) & SIUL2_PGPDI0_PPDI11_MASK) 5593 5594 #define SIUL2_PGPDI0_PPDI12_MASK (0x1000U) 5595 #define SIUL2_PGPDI0_PPDI12_SHIFT (12U) 5596 #define SIUL2_PGPDI0_PPDI12_WIDTH (1U) 5597 #define SIUL2_PGPDI0_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI12_SHIFT)) & SIUL2_PGPDI0_PPDI12_MASK) 5598 5599 #define SIUL2_PGPDI0_PPDI13_MASK (0x2000U) 5600 #define SIUL2_PGPDI0_PPDI13_SHIFT (13U) 5601 #define SIUL2_PGPDI0_PPDI13_WIDTH (1U) 5602 #define SIUL2_PGPDI0_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI13_SHIFT)) & SIUL2_PGPDI0_PPDI13_MASK) 5603 5604 #define SIUL2_PGPDI0_PPDI14_MASK (0x4000U) 5605 #define SIUL2_PGPDI0_PPDI14_SHIFT (14U) 5606 #define SIUL2_PGPDI0_PPDI14_WIDTH (1U) 5607 #define SIUL2_PGPDI0_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI14_SHIFT)) & SIUL2_PGPDI0_PPDI14_MASK) 5608 5609 #define SIUL2_PGPDI0_PPDI15_MASK (0x8000U) 5610 #define SIUL2_PGPDI0_PPDI15_SHIFT (15U) 5611 #define SIUL2_PGPDI0_PPDI15_WIDTH (1U) 5612 #define SIUL2_PGPDI0_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI0_PPDI15_SHIFT)) & SIUL2_PGPDI0_PPDI15_MASK) 5613 /*! @} */ 5614 5615 /*! @name PGPDI3 - SIUL2 Parallel GPIO Pad Data In Register */ 5616 /*! @{ */ 5617 5618 #define SIUL2_PGPDI3_PPDI0_MASK (0x1U) 5619 #define SIUL2_PGPDI3_PPDI0_SHIFT (0U) 5620 #define SIUL2_PGPDI3_PPDI0_WIDTH (1U) 5621 #define SIUL2_PGPDI3_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI0_SHIFT)) & SIUL2_PGPDI3_PPDI0_MASK) 5622 5623 #define SIUL2_PGPDI3_PPDI1_MASK (0x2U) 5624 #define SIUL2_PGPDI3_PPDI1_SHIFT (1U) 5625 #define SIUL2_PGPDI3_PPDI1_WIDTH (1U) 5626 #define SIUL2_PGPDI3_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI1_SHIFT)) & SIUL2_PGPDI3_PPDI1_MASK) 5627 5628 #define SIUL2_PGPDI3_PPDI2_MASK (0x4U) 5629 #define SIUL2_PGPDI3_PPDI2_SHIFT (2U) 5630 #define SIUL2_PGPDI3_PPDI2_WIDTH (1U) 5631 #define SIUL2_PGPDI3_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI2_SHIFT)) & SIUL2_PGPDI3_PPDI2_MASK) 5632 5633 #define SIUL2_PGPDI3_PPDI3_MASK (0x8U) 5634 #define SIUL2_PGPDI3_PPDI3_SHIFT (3U) 5635 #define SIUL2_PGPDI3_PPDI3_WIDTH (1U) 5636 #define SIUL2_PGPDI3_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI3_SHIFT)) & SIUL2_PGPDI3_PPDI3_MASK) 5637 5638 #define SIUL2_PGPDI3_PPDI4_MASK (0x10U) 5639 #define SIUL2_PGPDI3_PPDI4_SHIFT (4U) 5640 #define SIUL2_PGPDI3_PPDI4_WIDTH (1U) 5641 #define SIUL2_PGPDI3_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI4_SHIFT)) & SIUL2_PGPDI3_PPDI4_MASK) 5642 5643 #define SIUL2_PGPDI3_PPDI5_MASK (0x20U) 5644 #define SIUL2_PGPDI3_PPDI5_SHIFT (5U) 5645 #define SIUL2_PGPDI3_PPDI5_WIDTH (1U) 5646 #define SIUL2_PGPDI3_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI5_SHIFT)) & SIUL2_PGPDI3_PPDI5_MASK) 5647 5648 #define SIUL2_PGPDI3_PPDI6_MASK (0x40U) 5649 #define SIUL2_PGPDI3_PPDI6_SHIFT (6U) 5650 #define SIUL2_PGPDI3_PPDI6_WIDTH (1U) 5651 #define SIUL2_PGPDI3_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI6_SHIFT)) & SIUL2_PGPDI3_PPDI6_MASK) 5652 5653 #define SIUL2_PGPDI3_PPDI7_MASK (0x80U) 5654 #define SIUL2_PGPDI3_PPDI7_SHIFT (7U) 5655 #define SIUL2_PGPDI3_PPDI7_WIDTH (1U) 5656 #define SIUL2_PGPDI3_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI7_SHIFT)) & SIUL2_PGPDI3_PPDI7_MASK) 5657 5658 #define SIUL2_PGPDI3_PPDI8_MASK (0x100U) 5659 #define SIUL2_PGPDI3_PPDI8_SHIFT (8U) 5660 #define SIUL2_PGPDI3_PPDI8_WIDTH (1U) 5661 #define SIUL2_PGPDI3_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI8_SHIFT)) & SIUL2_PGPDI3_PPDI8_MASK) 5662 5663 #define SIUL2_PGPDI3_PPDI9_MASK (0x200U) 5664 #define SIUL2_PGPDI3_PPDI9_SHIFT (9U) 5665 #define SIUL2_PGPDI3_PPDI9_WIDTH (1U) 5666 #define SIUL2_PGPDI3_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI9_SHIFT)) & SIUL2_PGPDI3_PPDI9_MASK) 5667 5668 #define SIUL2_PGPDI3_PPDI10_MASK (0x400U) 5669 #define SIUL2_PGPDI3_PPDI10_SHIFT (10U) 5670 #define SIUL2_PGPDI3_PPDI10_WIDTH (1U) 5671 #define SIUL2_PGPDI3_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI10_SHIFT)) & SIUL2_PGPDI3_PPDI10_MASK) 5672 5673 #define SIUL2_PGPDI3_PPDI11_MASK (0x800U) 5674 #define SIUL2_PGPDI3_PPDI11_SHIFT (11U) 5675 #define SIUL2_PGPDI3_PPDI11_WIDTH (1U) 5676 #define SIUL2_PGPDI3_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI11_SHIFT)) & SIUL2_PGPDI3_PPDI11_MASK) 5677 5678 #define SIUL2_PGPDI3_PPDI12_MASK (0x1000U) 5679 #define SIUL2_PGPDI3_PPDI12_SHIFT (12U) 5680 #define SIUL2_PGPDI3_PPDI12_WIDTH (1U) 5681 #define SIUL2_PGPDI3_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI12_SHIFT)) & SIUL2_PGPDI3_PPDI12_MASK) 5682 5683 #define SIUL2_PGPDI3_PPDI13_MASK (0x2000U) 5684 #define SIUL2_PGPDI3_PPDI13_SHIFT (13U) 5685 #define SIUL2_PGPDI3_PPDI13_WIDTH (1U) 5686 #define SIUL2_PGPDI3_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI13_SHIFT)) & SIUL2_PGPDI3_PPDI13_MASK) 5687 5688 #define SIUL2_PGPDI3_PPDI14_MASK (0x4000U) 5689 #define SIUL2_PGPDI3_PPDI14_SHIFT (14U) 5690 #define SIUL2_PGPDI3_PPDI14_WIDTH (1U) 5691 #define SIUL2_PGPDI3_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI14_SHIFT)) & SIUL2_PGPDI3_PPDI14_MASK) 5692 5693 #define SIUL2_PGPDI3_PPDI15_MASK (0x8000U) 5694 #define SIUL2_PGPDI3_PPDI15_SHIFT (15U) 5695 #define SIUL2_PGPDI3_PPDI15_WIDTH (1U) 5696 #define SIUL2_PGPDI3_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI3_PPDI15_SHIFT)) & SIUL2_PGPDI3_PPDI15_MASK) 5697 /*! @} */ 5698 5699 /*! @name PGPDI2 - SIUL2 Parallel GPIO Pad Data In Register */ 5700 /*! @{ */ 5701 5702 #define SIUL2_PGPDI2_PPDI0_MASK (0x1U) 5703 #define SIUL2_PGPDI2_PPDI0_SHIFT (0U) 5704 #define SIUL2_PGPDI2_PPDI0_WIDTH (1U) 5705 #define SIUL2_PGPDI2_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI0_SHIFT)) & SIUL2_PGPDI2_PPDI0_MASK) 5706 5707 #define SIUL2_PGPDI2_PPDI1_MASK (0x2U) 5708 #define SIUL2_PGPDI2_PPDI1_SHIFT (1U) 5709 #define SIUL2_PGPDI2_PPDI1_WIDTH (1U) 5710 #define SIUL2_PGPDI2_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI1_SHIFT)) & SIUL2_PGPDI2_PPDI1_MASK) 5711 5712 #define SIUL2_PGPDI2_PPDI2_MASK (0x4U) 5713 #define SIUL2_PGPDI2_PPDI2_SHIFT (2U) 5714 #define SIUL2_PGPDI2_PPDI2_WIDTH (1U) 5715 #define SIUL2_PGPDI2_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI2_SHIFT)) & SIUL2_PGPDI2_PPDI2_MASK) 5716 5717 #define SIUL2_PGPDI2_PPDI3_MASK (0x8U) 5718 #define SIUL2_PGPDI2_PPDI3_SHIFT (3U) 5719 #define SIUL2_PGPDI2_PPDI3_WIDTH (1U) 5720 #define SIUL2_PGPDI2_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI3_SHIFT)) & SIUL2_PGPDI2_PPDI3_MASK) 5721 5722 #define SIUL2_PGPDI2_PPDI4_MASK (0x10U) 5723 #define SIUL2_PGPDI2_PPDI4_SHIFT (4U) 5724 #define SIUL2_PGPDI2_PPDI4_WIDTH (1U) 5725 #define SIUL2_PGPDI2_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI4_SHIFT)) & SIUL2_PGPDI2_PPDI4_MASK) 5726 5727 #define SIUL2_PGPDI2_PPDI5_MASK (0x20U) 5728 #define SIUL2_PGPDI2_PPDI5_SHIFT (5U) 5729 #define SIUL2_PGPDI2_PPDI5_WIDTH (1U) 5730 #define SIUL2_PGPDI2_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI5_SHIFT)) & SIUL2_PGPDI2_PPDI5_MASK) 5731 5732 #define SIUL2_PGPDI2_PPDI6_MASK (0x40U) 5733 #define SIUL2_PGPDI2_PPDI6_SHIFT (6U) 5734 #define SIUL2_PGPDI2_PPDI6_WIDTH (1U) 5735 #define SIUL2_PGPDI2_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI6_SHIFT)) & SIUL2_PGPDI2_PPDI6_MASK) 5736 5737 #define SIUL2_PGPDI2_PPDI7_MASK (0x80U) 5738 #define SIUL2_PGPDI2_PPDI7_SHIFT (7U) 5739 #define SIUL2_PGPDI2_PPDI7_WIDTH (1U) 5740 #define SIUL2_PGPDI2_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI7_SHIFT)) & SIUL2_PGPDI2_PPDI7_MASK) 5741 5742 #define SIUL2_PGPDI2_PPDI8_MASK (0x100U) 5743 #define SIUL2_PGPDI2_PPDI8_SHIFT (8U) 5744 #define SIUL2_PGPDI2_PPDI8_WIDTH (1U) 5745 #define SIUL2_PGPDI2_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI8_SHIFT)) & SIUL2_PGPDI2_PPDI8_MASK) 5746 5747 #define SIUL2_PGPDI2_PPDI9_MASK (0x200U) 5748 #define SIUL2_PGPDI2_PPDI9_SHIFT (9U) 5749 #define SIUL2_PGPDI2_PPDI9_WIDTH (1U) 5750 #define SIUL2_PGPDI2_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI9_SHIFT)) & SIUL2_PGPDI2_PPDI9_MASK) 5751 5752 #define SIUL2_PGPDI2_PPDI10_MASK (0x400U) 5753 #define SIUL2_PGPDI2_PPDI10_SHIFT (10U) 5754 #define SIUL2_PGPDI2_PPDI10_WIDTH (1U) 5755 #define SIUL2_PGPDI2_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI10_SHIFT)) & SIUL2_PGPDI2_PPDI10_MASK) 5756 5757 #define SIUL2_PGPDI2_PPDI11_MASK (0x800U) 5758 #define SIUL2_PGPDI2_PPDI11_SHIFT (11U) 5759 #define SIUL2_PGPDI2_PPDI11_WIDTH (1U) 5760 #define SIUL2_PGPDI2_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI11_SHIFT)) & SIUL2_PGPDI2_PPDI11_MASK) 5761 5762 #define SIUL2_PGPDI2_PPDI12_MASK (0x1000U) 5763 #define SIUL2_PGPDI2_PPDI12_SHIFT (12U) 5764 #define SIUL2_PGPDI2_PPDI12_WIDTH (1U) 5765 #define SIUL2_PGPDI2_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI12_SHIFT)) & SIUL2_PGPDI2_PPDI12_MASK) 5766 5767 #define SIUL2_PGPDI2_PPDI13_MASK (0x2000U) 5768 #define SIUL2_PGPDI2_PPDI13_SHIFT (13U) 5769 #define SIUL2_PGPDI2_PPDI13_WIDTH (1U) 5770 #define SIUL2_PGPDI2_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI13_SHIFT)) & SIUL2_PGPDI2_PPDI13_MASK) 5771 5772 #define SIUL2_PGPDI2_PPDI14_MASK (0x4000U) 5773 #define SIUL2_PGPDI2_PPDI14_SHIFT (14U) 5774 #define SIUL2_PGPDI2_PPDI14_WIDTH (1U) 5775 #define SIUL2_PGPDI2_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI14_SHIFT)) & SIUL2_PGPDI2_PPDI14_MASK) 5776 5777 #define SIUL2_PGPDI2_PPDI15_MASK (0x8000U) 5778 #define SIUL2_PGPDI2_PPDI15_SHIFT (15U) 5779 #define SIUL2_PGPDI2_PPDI15_WIDTH (1U) 5780 #define SIUL2_PGPDI2_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI2_PPDI15_SHIFT)) & SIUL2_PGPDI2_PPDI15_MASK) 5781 /*! @} */ 5782 5783 /*! @name PGPDI5 - SIUL2 Parallel GPIO Pad Data In Register */ 5784 /*! @{ */ 5785 5786 #define SIUL2_PGPDI5_PPDI0_MASK (0x1U) 5787 #define SIUL2_PGPDI5_PPDI0_SHIFT (0U) 5788 #define SIUL2_PGPDI5_PPDI0_WIDTH (1U) 5789 #define SIUL2_PGPDI5_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI0_SHIFT)) & SIUL2_PGPDI5_PPDI0_MASK) 5790 5791 #define SIUL2_PGPDI5_PPDI1_MASK (0x2U) 5792 #define SIUL2_PGPDI5_PPDI1_SHIFT (1U) 5793 #define SIUL2_PGPDI5_PPDI1_WIDTH (1U) 5794 #define SIUL2_PGPDI5_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI1_SHIFT)) & SIUL2_PGPDI5_PPDI1_MASK) 5795 5796 #define SIUL2_PGPDI5_PPDI2_MASK (0x4U) 5797 #define SIUL2_PGPDI5_PPDI2_SHIFT (2U) 5798 #define SIUL2_PGPDI5_PPDI2_WIDTH (1U) 5799 #define SIUL2_PGPDI5_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI2_SHIFT)) & SIUL2_PGPDI5_PPDI2_MASK) 5800 5801 #define SIUL2_PGPDI5_PPDI3_MASK (0x8U) 5802 #define SIUL2_PGPDI5_PPDI3_SHIFT (3U) 5803 #define SIUL2_PGPDI5_PPDI3_WIDTH (1U) 5804 #define SIUL2_PGPDI5_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI3_SHIFT)) & SIUL2_PGPDI5_PPDI3_MASK) 5805 5806 #define SIUL2_PGPDI5_PPDI4_MASK (0x10U) 5807 #define SIUL2_PGPDI5_PPDI4_SHIFT (4U) 5808 #define SIUL2_PGPDI5_PPDI4_WIDTH (1U) 5809 #define SIUL2_PGPDI5_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI4_SHIFT)) & SIUL2_PGPDI5_PPDI4_MASK) 5810 5811 #define SIUL2_PGPDI5_PPDI5_MASK (0x20U) 5812 #define SIUL2_PGPDI5_PPDI5_SHIFT (5U) 5813 #define SIUL2_PGPDI5_PPDI5_WIDTH (1U) 5814 #define SIUL2_PGPDI5_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI5_SHIFT)) & SIUL2_PGPDI5_PPDI5_MASK) 5815 5816 #define SIUL2_PGPDI5_PPDI6_MASK (0x40U) 5817 #define SIUL2_PGPDI5_PPDI6_SHIFT (6U) 5818 #define SIUL2_PGPDI5_PPDI6_WIDTH (1U) 5819 #define SIUL2_PGPDI5_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI6_SHIFT)) & SIUL2_PGPDI5_PPDI6_MASK) 5820 5821 #define SIUL2_PGPDI5_PPDI7_MASK (0x80U) 5822 #define SIUL2_PGPDI5_PPDI7_SHIFT (7U) 5823 #define SIUL2_PGPDI5_PPDI7_WIDTH (1U) 5824 #define SIUL2_PGPDI5_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI7_SHIFT)) & SIUL2_PGPDI5_PPDI7_MASK) 5825 5826 #define SIUL2_PGPDI5_PPDI8_MASK (0x100U) 5827 #define SIUL2_PGPDI5_PPDI8_SHIFT (8U) 5828 #define SIUL2_PGPDI5_PPDI8_WIDTH (1U) 5829 #define SIUL2_PGPDI5_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI8_SHIFT)) & SIUL2_PGPDI5_PPDI8_MASK) 5830 5831 #define SIUL2_PGPDI5_PPDI9_MASK (0x200U) 5832 #define SIUL2_PGPDI5_PPDI9_SHIFT (9U) 5833 #define SIUL2_PGPDI5_PPDI9_WIDTH (1U) 5834 #define SIUL2_PGPDI5_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI9_SHIFT)) & SIUL2_PGPDI5_PPDI9_MASK) 5835 5836 #define SIUL2_PGPDI5_PPDI10_MASK (0x400U) 5837 #define SIUL2_PGPDI5_PPDI10_SHIFT (10U) 5838 #define SIUL2_PGPDI5_PPDI10_WIDTH (1U) 5839 #define SIUL2_PGPDI5_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI10_SHIFT)) & SIUL2_PGPDI5_PPDI10_MASK) 5840 5841 #define SIUL2_PGPDI5_PPDI11_MASK (0x800U) 5842 #define SIUL2_PGPDI5_PPDI11_SHIFT (11U) 5843 #define SIUL2_PGPDI5_PPDI11_WIDTH (1U) 5844 #define SIUL2_PGPDI5_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI11_SHIFT)) & SIUL2_PGPDI5_PPDI11_MASK) 5845 5846 #define SIUL2_PGPDI5_PPDI12_MASK (0x1000U) 5847 #define SIUL2_PGPDI5_PPDI12_SHIFT (12U) 5848 #define SIUL2_PGPDI5_PPDI12_WIDTH (1U) 5849 #define SIUL2_PGPDI5_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI12_SHIFT)) & SIUL2_PGPDI5_PPDI12_MASK) 5850 5851 #define SIUL2_PGPDI5_PPDI13_MASK (0x2000U) 5852 #define SIUL2_PGPDI5_PPDI13_SHIFT (13U) 5853 #define SIUL2_PGPDI5_PPDI13_WIDTH (1U) 5854 #define SIUL2_PGPDI5_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI13_SHIFT)) & SIUL2_PGPDI5_PPDI13_MASK) 5855 5856 #define SIUL2_PGPDI5_PPDI14_MASK (0x4000U) 5857 #define SIUL2_PGPDI5_PPDI14_SHIFT (14U) 5858 #define SIUL2_PGPDI5_PPDI14_WIDTH (1U) 5859 #define SIUL2_PGPDI5_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI14_SHIFT)) & SIUL2_PGPDI5_PPDI14_MASK) 5860 5861 #define SIUL2_PGPDI5_PPDI15_MASK (0x8000U) 5862 #define SIUL2_PGPDI5_PPDI15_SHIFT (15U) 5863 #define SIUL2_PGPDI5_PPDI15_WIDTH (1U) 5864 #define SIUL2_PGPDI5_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI5_PPDI15_SHIFT)) & SIUL2_PGPDI5_PPDI15_MASK) 5865 /*! @} */ 5866 5867 /*! @name PGPDI4 - SIUL2 Parallel GPIO Pad Data In Register */ 5868 /*! @{ */ 5869 5870 #define SIUL2_PGPDI4_PPDI0_MASK (0x1U) 5871 #define SIUL2_PGPDI4_PPDI0_SHIFT (0U) 5872 #define SIUL2_PGPDI4_PPDI0_WIDTH (1U) 5873 #define SIUL2_PGPDI4_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI0_SHIFT)) & SIUL2_PGPDI4_PPDI0_MASK) 5874 5875 #define SIUL2_PGPDI4_PPDI1_MASK (0x2U) 5876 #define SIUL2_PGPDI4_PPDI1_SHIFT (1U) 5877 #define SIUL2_PGPDI4_PPDI1_WIDTH (1U) 5878 #define SIUL2_PGPDI4_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI1_SHIFT)) & SIUL2_PGPDI4_PPDI1_MASK) 5879 5880 #define SIUL2_PGPDI4_PPDI2_MASK (0x4U) 5881 #define SIUL2_PGPDI4_PPDI2_SHIFT (2U) 5882 #define SIUL2_PGPDI4_PPDI2_WIDTH (1U) 5883 #define SIUL2_PGPDI4_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI2_SHIFT)) & SIUL2_PGPDI4_PPDI2_MASK) 5884 5885 #define SIUL2_PGPDI4_PPDI3_MASK (0x8U) 5886 #define SIUL2_PGPDI4_PPDI3_SHIFT (3U) 5887 #define SIUL2_PGPDI4_PPDI3_WIDTH (1U) 5888 #define SIUL2_PGPDI4_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI3_SHIFT)) & SIUL2_PGPDI4_PPDI3_MASK) 5889 5890 #define SIUL2_PGPDI4_PPDI4_MASK (0x10U) 5891 #define SIUL2_PGPDI4_PPDI4_SHIFT (4U) 5892 #define SIUL2_PGPDI4_PPDI4_WIDTH (1U) 5893 #define SIUL2_PGPDI4_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI4_SHIFT)) & SIUL2_PGPDI4_PPDI4_MASK) 5894 5895 #define SIUL2_PGPDI4_PPDI5_MASK (0x20U) 5896 #define SIUL2_PGPDI4_PPDI5_SHIFT (5U) 5897 #define SIUL2_PGPDI4_PPDI5_WIDTH (1U) 5898 #define SIUL2_PGPDI4_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI5_SHIFT)) & SIUL2_PGPDI4_PPDI5_MASK) 5899 5900 #define SIUL2_PGPDI4_PPDI6_MASK (0x40U) 5901 #define SIUL2_PGPDI4_PPDI6_SHIFT (6U) 5902 #define SIUL2_PGPDI4_PPDI6_WIDTH (1U) 5903 #define SIUL2_PGPDI4_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI6_SHIFT)) & SIUL2_PGPDI4_PPDI6_MASK) 5904 5905 #define SIUL2_PGPDI4_PPDI7_MASK (0x80U) 5906 #define SIUL2_PGPDI4_PPDI7_SHIFT (7U) 5907 #define SIUL2_PGPDI4_PPDI7_WIDTH (1U) 5908 #define SIUL2_PGPDI4_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI7_SHIFT)) & SIUL2_PGPDI4_PPDI7_MASK) 5909 5910 #define SIUL2_PGPDI4_PPDI8_MASK (0x100U) 5911 #define SIUL2_PGPDI4_PPDI8_SHIFT (8U) 5912 #define SIUL2_PGPDI4_PPDI8_WIDTH (1U) 5913 #define SIUL2_PGPDI4_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI8_SHIFT)) & SIUL2_PGPDI4_PPDI8_MASK) 5914 5915 #define SIUL2_PGPDI4_PPDI9_MASK (0x200U) 5916 #define SIUL2_PGPDI4_PPDI9_SHIFT (9U) 5917 #define SIUL2_PGPDI4_PPDI9_WIDTH (1U) 5918 #define SIUL2_PGPDI4_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI9_SHIFT)) & SIUL2_PGPDI4_PPDI9_MASK) 5919 5920 #define SIUL2_PGPDI4_PPDI10_MASK (0x400U) 5921 #define SIUL2_PGPDI4_PPDI10_SHIFT (10U) 5922 #define SIUL2_PGPDI4_PPDI10_WIDTH (1U) 5923 #define SIUL2_PGPDI4_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI10_SHIFT)) & SIUL2_PGPDI4_PPDI10_MASK) 5924 5925 #define SIUL2_PGPDI4_PPDI11_MASK (0x800U) 5926 #define SIUL2_PGPDI4_PPDI11_SHIFT (11U) 5927 #define SIUL2_PGPDI4_PPDI11_WIDTH (1U) 5928 #define SIUL2_PGPDI4_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI11_SHIFT)) & SIUL2_PGPDI4_PPDI11_MASK) 5929 5930 #define SIUL2_PGPDI4_PPDI12_MASK (0x1000U) 5931 #define SIUL2_PGPDI4_PPDI12_SHIFT (12U) 5932 #define SIUL2_PGPDI4_PPDI12_WIDTH (1U) 5933 #define SIUL2_PGPDI4_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI12_SHIFT)) & SIUL2_PGPDI4_PPDI12_MASK) 5934 5935 #define SIUL2_PGPDI4_PPDI13_MASK (0x2000U) 5936 #define SIUL2_PGPDI4_PPDI13_SHIFT (13U) 5937 #define SIUL2_PGPDI4_PPDI13_WIDTH (1U) 5938 #define SIUL2_PGPDI4_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI13_SHIFT)) & SIUL2_PGPDI4_PPDI13_MASK) 5939 5940 #define SIUL2_PGPDI4_PPDI14_MASK (0x4000U) 5941 #define SIUL2_PGPDI4_PPDI14_SHIFT (14U) 5942 #define SIUL2_PGPDI4_PPDI14_WIDTH (1U) 5943 #define SIUL2_PGPDI4_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI14_SHIFT)) & SIUL2_PGPDI4_PPDI14_MASK) 5944 5945 #define SIUL2_PGPDI4_PPDI15_MASK (0x8000U) 5946 #define SIUL2_PGPDI4_PPDI15_SHIFT (15U) 5947 #define SIUL2_PGPDI4_PPDI15_WIDTH (1U) 5948 #define SIUL2_PGPDI4_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI4_PPDI15_SHIFT)) & SIUL2_PGPDI4_PPDI15_MASK) 5949 /*! @} */ 5950 5951 /*! @name PGPDI7 - SIUL2 Parallel GPIO Pad Data In Register */ 5952 /*! @{ */ 5953 5954 #define SIUL2_PGPDI7_PPDI0_MASK (0x1U) 5955 #define SIUL2_PGPDI7_PPDI0_SHIFT (0U) 5956 #define SIUL2_PGPDI7_PPDI0_WIDTH (1U) 5957 #define SIUL2_PGPDI7_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI0_SHIFT)) & SIUL2_PGPDI7_PPDI0_MASK) 5958 5959 #define SIUL2_PGPDI7_PPDI1_MASK (0x2U) 5960 #define SIUL2_PGPDI7_PPDI1_SHIFT (1U) 5961 #define SIUL2_PGPDI7_PPDI1_WIDTH (1U) 5962 #define SIUL2_PGPDI7_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI1_SHIFT)) & SIUL2_PGPDI7_PPDI1_MASK) 5963 5964 #define SIUL2_PGPDI7_PPDI2_MASK (0x4U) 5965 #define SIUL2_PGPDI7_PPDI2_SHIFT (2U) 5966 #define SIUL2_PGPDI7_PPDI2_WIDTH (1U) 5967 #define SIUL2_PGPDI7_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI2_SHIFT)) & SIUL2_PGPDI7_PPDI2_MASK) 5968 5969 #define SIUL2_PGPDI7_PPDI3_MASK (0x8U) 5970 #define SIUL2_PGPDI7_PPDI3_SHIFT (3U) 5971 #define SIUL2_PGPDI7_PPDI3_WIDTH (1U) 5972 #define SIUL2_PGPDI7_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI3_SHIFT)) & SIUL2_PGPDI7_PPDI3_MASK) 5973 5974 #define SIUL2_PGPDI7_PPDI4_MASK (0x10U) 5975 #define SIUL2_PGPDI7_PPDI4_SHIFT (4U) 5976 #define SIUL2_PGPDI7_PPDI4_WIDTH (1U) 5977 #define SIUL2_PGPDI7_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI4_SHIFT)) & SIUL2_PGPDI7_PPDI4_MASK) 5978 5979 #define SIUL2_PGPDI7_PPDI5_MASK (0x20U) 5980 #define SIUL2_PGPDI7_PPDI5_SHIFT (5U) 5981 #define SIUL2_PGPDI7_PPDI5_WIDTH (1U) 5982 #define SIUL2_PGPDI7_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI5_SHIFT)) & SIUL2_PGPDI7_PPDI5_MASK) 5983 5984 #define SIUL2_PGPDI7_PPDI6_MASK (0x40U) 5985 #define SIUL2_PGPDI7_PPDI6_SHIFT (6U) 5986 #define SIUL2_PGPDI7_PPDI6_WIDTH (1U) 5987 #define SIUL2_PGPDI7_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI6_SHIFT)) & SIUL2_PGPDI7_PPDI6_MASK) 5988 5989 #define SIUL2_PGPDI7_PPDI7_MASK (0x80U) 5990 #define SIUL2_PGPDI7_PPDI7_SHIFT (7U) 5991 #define SIUL2_PGPDI7_PPDI7_WIDTH (1U) 5992 #define SIUL2_PGPDI7_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI7_SHIFT)) & SIUL2_PGPDI7_PPDI7_MASK) 5993 5994 #define SIUL2_PGPDI7_PPDI8_MASK (0x100U) 5995 #define SIUL2_PGPDI7_PPDI8_SHIFT (8U) 5996 #define SIUL2_PGPDI7_PPDI8_WIDTH (1U) 5997 #define SIUL2_PGPDI7_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI8_SHIFT)) & SIUL2_PGPDI7_PPDI8_MASK) 5998 5999 #define SIUL2_PGPDI7_PPDI9_MASK (0x200U) 6000 #define SIUL2_PGPDI7_PPDI9_SHIFT (9U) 6001 #define SIUL2_PGPDI7_PPDI9_WIDTH (1U) 6002 #define SIUL2_PGPDI7_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI9_SHIFT)) & SIUL2_PGPDI7_PPDI9_MASK) 6003 6004 #define SIUL2_PGPDI7_PPDI10_MASK (0x400U) 6005 #define SIUL2_PGPDI7_PPDI10_SHIFT (10U) 6006 #define SIUL2_PGPDI7_PPDI10_WIDTH (1U) 6007 #define SIUL2_PGPDI7_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI10_SHIFT)) & SIUL2_PGPDI7_PPDI10_MASK) 6008 6009 #define SIUL2_PGPDI7_PPDI11_MASK (0x800U) 6010 #define SIUL2_PGPDI7_PPDI11_SHIFT (11U) 6011 #define SIUL2_PGPDI7_PPDI11_WIDTH (1U) 6012 #define SIUL2_PGPDI7_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI11_SHIFT)) & SIUL2_PGPDI7_PPDI11_MASK) 6013 6014 #define SIUL2_PGPDI7_PPDI12_MASK (0x1000U) 6015 #define SIUL2_PGPDI7_PPDI12_SHIFT (12U) 6016 #define SIUL2_PGPDI7_PPDI12_WIDTH (1U) 6017 #define SIUL2_PGPDI7_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI12_SHIFT)) & SIUL2_PGPDI7_PPDI12_MASK) 6018 6019 #define SIUL2_PGPDI7_PPDI13_MASK (0x2000U) 6020 #define SIUL2_PGPDI7_PPDI13_SHIFT (13U) 6021 #define SIUL2_PGPDI7_PPDI13_WIDTH (1U) 6022 #define SIUL2_PGPDI7_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI13_SHIFT)) & SIUL2_PGPDI7_PPDI13_MASK) 6023 6024 #define SIUL2_PGPDI7_PPDI14_MASK (0x4000U) 6025 #define SIUL2_PGPDI7_PPDI14_SHIFT (14U) 6026 #define SIUL2_PGPDI7_PPDI14_WIDTH (1U) 6027 #define SIUL2_PGPDI7_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI14_SHIFT)) & SIUL2_PGPDI7_PPDI14_MASK) 6028 6029 #define SIUL2_PGPDI7_PPDI15_MASK (0x8000U) 6030 #define SIUL2_PGPDI7_PPDI15_SHIFT (15U) 6031 #define SIUL2_PGPDI7_PPDI15_WIDTH (1U) 6032 #define SIUL2_PGPDI7_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI7_PPDI15_SHIFT)) & SIUL2_PGPDI7_PPDI15_MASK) 6033 /*! @} */ 6034 6035 /*! @name PGPDI6 - SIUL2 Parallel GPIO Pad Data In Register */ 6036 /*! @{ */ 6037 6038 #define SIUL2_PGPDI6_PPDI0_MASK (0x1U) 6039 #define SIUL2_PGPDI6_PPDI0_SHIFT (0U) 6040 #define SIUL2_PGPDI6_PPDI0_WIDTH (1U) 6041 #define SIUL2_PGPDI6_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI0_SHIFT)) & SIUL2_PGPDI6_PPDI0_MASK) 6042 6043 #define SIUL2_PGPDI6_PPDI1_MASK (0x2U) 6044 #define SIUL2_PGPDI6_PPDI1_SHIFT (1U) 6045 #define SIUL2_PGPDI6_PPDI1_WIDTH (1U) 6046 #define SIUL2_PGPDI6_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI1_SHIFT)) & SIUL2_PGPDI6_PPDI1_MASK) 6047 6048 #define SIUL2_PGPDI6_PPDI2_MASK (0x4U) 6049 #define SIUL2_PGPDI6_PPDI2_SHIFT (2U) 6050 #define SIUL2_PGPDI6_PPDI2_WIDTH (1U) 6051 #define SIUL2_PGPDI6_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI2_SHIFT)) & SIUL2_PGPDI6_PPDI2_MASK) 6052 6053 #define SIUL2_PGPDI6_PPDI3_MASK (0x8U) 6054 #define SIUL2_PGPDI6_PPDI3_SHIFT (3U) 6055 #define SIUL2_PGPDI6_PPDI3_WIDTH (1U) 6056 #define SIUL2_PGPDI6_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI3_SHIFT)) & SIUL2_PGPDI6_PPDI3_MASK) 6057 6058 #define SIUL2_PGPDI6_PPDI4_MASK (0x10U) 6059 #define SIUL2_PGPDI6_PPDI4_SHIFT (4U) 6060 #define SIUL2_PGPDI6_PPDI4_WIDTH (1U) 6061 #define SIUL2_PGPDI6_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI4_SHIFT)) & SIUL2_PGPDI6_PPDI4_MASK) 6062 6063 #define SIUL2_PGPDI6_PPDI5_MASK (0x20U) 6064 #define SIUL2_PGPDI6_PPDI5_SHIFT (5U) 6065 #define SIUL2_PGPDI6_PPDI5_WIDTH (1U) 6066 #define SIUL2_PGPDI6_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI5_SHIFT)) & SIUL2_PGPDI6_PPDI5_MASK) 6067 6068 #define SIUL2_PGPDI6_PPDI6_MASK (0x40U) 6069 #define SIUL2_PGPDI6_PPDI6_SHIFT (6U) 6070 #define SIUL2_PGPDI6_PPDI6_WIDTH (1U) 6071 #define SIUL2_PGPDI6_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI6_SHIFT)) & SIUL2_PGPDI6_PPDI6_MASK) 6072 6073 #define SIUL2_PGPDI6_PPDI7_MASK (0x80U) 6074 #define SIUL2_PGPDI6_PPDI7_SHIFT (7U) 6075 #define SIUL2_PGPDI6_PPDI7_WIDTH (1U) 6076 #define SIUL2_PGPDI6_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI7_SHIFT)) & SIUL2_PGPDI6_PPDI7_MASK) 6077 6078 #define SIUL2_PGPDI6_PPDI8_MASK (0x100U) 6079 #define SIUL2_PGPDI6_PPDI8_SHIFT (8U) 6080 #define SIUL2_PGPDI6_PPDI8_WIDTH (1U) 6081 #define SIUL2_PGPDI6_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI8_SHIFT)) & SIUL2_PGPDI6_PPDI8_MASK) 6082 6083 #define SIUL2_PGPDI6_PPDI9_MASK (0x200U) 6084 #define SIUL2_PGPDI6_PPDI9_SHIFT (9U) 6085 #define SIUL2_PGPDI6_PPDI9_WIDTH (1U) 6086 #define SIUL2_PGPDI6_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI9_SHIFT)) & SIUL2_PGPDI6_PPDI9_MASK) 6087 6088 #define SIUL2_PGPDI6_PPDI10_MASK (0x400U) 6089 #define SIUL2_PGPDI6_PPDI10_SHIFT (10U) 6090 #define SIUL2_PGPDI6_PPDI10_WIDTH (1U) 6091 #define SIUL2_PGPDI6_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI10_SHIFT)) & SIUL2_PGPDI6_PPDI10_MASK) 6092 6093 #define SIUL2_PGPDI6_PPDI11_MASK (0x800U) 6094 #define SIUL2_PGPDI6_PPDI11_SHIFT (11U) 6095 #define SIUL2_PGPDI6_PPDI11_WIDTH (1U) 6096 #define SIUL2_PGPDI6_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI11_SHIFT)) & SIUL2_PGPDI6_PPDI11_MASK) 6097 6098 #define SIUL2_PGPDI6_PPDI12_MASK (0x1000U) 6099 #define SIUL2_PGPDI6_PPDI12_SHIFT (12U) 6100 #define SIUL2_PGPDI6_PPDI12_WIDTH (1U) 6101 #define SIUL2_PGPDI6_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI12_SHIFT)) & SIUL2_PGPDI6_PPDI12_MASK) 6102 6103 #define SIUL2_PGPDI6_PPDI13_MASK (0x2000U) 6104 #define SIUL2_PGPDI6_PPDI13_SHIFT (13U) 6105 #define SIUL2_PGPDI6_PPDI13_WIDTH (1U) 6106 #define SIUL2_PGPDI6_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI13_SHIFT)) & SIUL2_PGPDI6_PPDI13_MASK) 6107 6108 #define SIUL2_PGPDI6_PPDI14_MASK (0x4000U) 6109 #define SIUL2_PGPDI6_PPDI14_SHIFT (14U) 6110 #define SIUL2_PGPDI6_PPDI14_WIDTH (1U) 6111 #define SIUL2_PGPDI6_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI14_SHIFT)) & SIUL2_PGPDI6_PPDI14_MASK) 6112 6113 #define SIUL2_PGPDI6_PPDI15_MASK (0x8000U) 6114 #define SIUL2_PGPDI6_PPDI15_SHIFT (15U) 6115 #define SIUL2_PGPDI6_PPDI15_WIDTH (1U) 6116 #define SIUL2_PGPDI6_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI6_PPDI15_SHIFT)) & SIUL2_PGPDI6_PPDI15_MASK) 6117 /*! @} */ 6118 6119 /*! @name PGPDI9 - SIUL2 Parallel GPIO Pad Data In Register */ 6120 /*! @{ */ 6121 6122 #define SIUL2_PGPDI9_PPDI0_MASK (0x1U) 6123 #define SIUL2_PGPDI9_PPDI0_SHIFT (0U) 6124 #define SIUL2_PGPDI9_PPDI0_WIDTH (1U) 6125 #define SIUL2_PGPDI9_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI0_SHIFT)) & SIUL2_PGPDI9_PPDI0_MASK) 6126 6127 #define SIUL2_PGPDI9_PPDI1_MASK (0x2U) 6128 #define SIUL2_PGPDI9_PPDI1_SHIFT (1U) 6129 #define SIUL2_PGPDI9_PPDI1_WIDTH (1U) 6130 #define SIUL2_PGPDI9_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI1_SHIFT)) & SIUL2_PGPDI9_PPDI1_MASK) 6131 6132 #define SIUL2_PGPDI9_PPDI2_MASK (0x4U) 6133 #define SIUL2_PGPDI9_PPDI2_SHIFT (2U) 6134 #define SIUL2_PGPDI9_PPDI2_WIDTH (1U) 6135 #define SIUL2_PGPDI9_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI2_SHIFT)) & SIUL2_PGPDI9_PPDI2_MASK) 6136 6137 #define SIUL2_PGPDI9_PPDI3_MASK (0x8U) 6138 #define SIUL2_PGPDI9_PPDI3_SHIFT (3U) 6139 #define SIUL2_PGPDI9_PPDI3_WIDTH (1U) 6140 #define SIUL2_PGPDI9_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI3_SHIFT)) & SIUL2_PGPDI9_PPDI3_MASK) 6141 6142 #define SIUL2_PGPDI9_PPDI4_MASK (0x10U) 6143 #define SIUL2_PGPDI9_PPDI4_SHIFT (4U) 6144 #define SIUL2_PGPDI9_PPDI4_WIDTH (1U) 6145 #define SIUL2_PGPDI9_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI4_SHIFT)) & SIUL2_PGPDI9_PPDI4_MASK) 6146 6147 #define SIUL2_PGPDI9_PPDI5_MASK (0x20U) 6148 #define SIUL2_PGPDI9_PPDI5_SHIFT (5U) 6149 #define SIUL2_PGPDI9_PPDI5_WIDTH (1U) 6150 #define SIUL2_PGPDI9_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI5_SHIFT)) & SIUL2_PGPDI9_PPDI5_MASK) 6151 6152 #define SIUL2_PGPDI9_PPDI6_MASK (0x40U) 6153 #define SIUL2_PGPDI9_PPDI6_SHIFT (6U) 6154 #define SIUL2_PGPDI9_PPDI6_WIDTH (1U) 6155 #define SIUL2_PGPDI9_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI6_SHIFT)) & SIUL2_PGPDI9_PPDI6_MASK) 6156 6157 #define SIUL2_PGPDI9_PPDI7_MASK (0x80U) 6158 #define SIUL2_PGPDI9_PPDI7_SHIFT (7U) 6159 #define SIUL2_PGPDI9_PPDI7_WIDTH (1U) 6160 #define SIUL2_PGPDI9_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI7_SHIFT)) & SIUL2_PGPDI9_PPDI7_MASK) 6161 6162 #define SIUL2_PGPDI9_PPDI8_MASK (0x100U) 6163 #define SIUL2_PGPDI9_PPDI8_SHIFT (8U) 6164 #define SIUL2_PGPDI9_PPDI8_WIDTH (1U) 6165 #define SIUL2_PGPDI9_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI8_SHIFT)) & SIUL2_PGPDI9_PPDI8_MASK) 6166 6167 #define SIUL2_PGPDI9_PPDI9_MASK (0x200U) 6168 #define SIUL2_PGPDI9_PPDI9_SHIFT (9U) 6169 #define SIUL2_PGPDI9_PPDI9_WIDTH (1U) 6170 #define SIUL2_PGPDI9_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI9_SHIFT)) & SIUL2_PGPDI9_PPDI9_MASK) 6171 6172 #define SIUL2_PGPDI9_PPDI10_MASK (0x400U) 6173 #define SIUL2_PGPDI9_PPDI10_SHIFT (10U) 6174 #define SIUL2_PGPDI9_PPDI10_WIDTH (1U) 6175 #define SIUL2_PGPDI9_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI10_SHIFT)) & SIUL2_PGPDI9_PPDI10_MASK) 6176 6177 #define SIUL2_PGPDI9_PPDI11_MASK (0x800U) 6178 #define SIUL2_PGPDI9_PPDI11_SHIFT (11U) 6179 #define SIUL2_PGPDI9_PPDI11_WIDTH (1U) 6180 #define SIUL2_PGPDI9_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI11_SHIFT)) & SIUL2_PGPDI9_PPDI11_MASK) 6181 6182 #define SIUL2_PGPDI9_PPDI12_MASK (0x1000U) 6183 #define SIUL2_PGPDI9_PPDI12_SHIFT (12U) 6184 #define SIUL2_PGPDI9_PPDI12_WIDTH (1U) 6185 #define SIUL2_PGPDI9_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI12_SHIFT)) & SIUL2_PGPDI9_PPDI12_MASK) 6186 6187 #define SIUL2_PGPDI9_PPDI13_MASK (0x2000U) 6188 #define SIUL2_PGPDI9_PPDI13_SHIFT (13U) 6189 #define SIUL2_PGPDI9_PPDI13_WIDTH (1U) 6190 #define SIUL2_PGPDI9_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI13_SHIFT)) & SIUL2_PGPDI9_PPDI13_MASK) 6191 6192 #define SIUL2_PGPDI9_PPDI14_MASK (0x4000U) 6193 #define SIUL2_PGPDI9_PPDI14_SHIFT (14U) 6194 #define SIUL2_PGPDI9_PPDI14_WIDTH (1U) 6195 #define SIUL2_PGPDI9_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI14_SHIFT)) & SIUL2_PGPDI9_PPDI14_MASK) 6196 6197 #define SIUL2_PGPDI9_PPDI15_MASK (0x8000U) 6198 #define SIUL2_PGPDI9_PPDI15_SHIFT (15U) 6199 #define SIUL2_PGPDI9_PPDI15_WIDTH (1U) 6200 #define SIUL2_PGPDI9_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI9_PPDI15_SHIFT)) & SIUL2_PGPDI9_PPDI15_MASK) 6201 /*! @} */ 6202 6203 /*! @name PGPDI8 - SIUL2 Parallel GPIO Pad Data In Register */ 6204 /*! @{ */ 6205 6206 #define SIUL2_PGPDI8_PPDI0_MASK (0x1U) 6207 #define SIUL2_PGPDI8_PPDI0_SHIFT (0U) 6208 #define SIUL2_PGPDI8_PPDI0_WIDTH (1U) 6209 #define SIUL2_PGPDI8_PPDI0(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI0_SHIFT)) & SIUL2_PGPDI8_PPDI0_MASK) 6210 6211 #define SIUL2_PGPDI8_PPDI1_MASK (0x2U) 6212 #define SIUL2_PGPDI8_PPDI1_SHIFT (1U) 6213 #define SIUL2_PGPDI8_PPDI1_WIDTH (1U) 6214 #define SIUL2_PGPDI8_PPDI1(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI1_SHIFT)) & SIUL2_PGPDI8_PPDI1_MASK) 6215 6216 #define SIUL2_PGPDI8_PPDI2_MASK (0x4U) 6217 #define SIUL2_PGPDI8_PPDI2_SHIFT (2U) 6218 #define SIUL2_PGPDI8_PPDI2_WIDTH (1U) 6219 #define SIUL2_PGPDI8_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI2_SHIFT)) & SIUL2_PGPDI8_PPDI2_MASK) 6220 6221 #define SIUL2_PGPDI8_PPDI3_MASK (0x8U) 6222 #define SIUL2_PGPDI8_PPDI3_SHIFT (3U) 6223 #define SIUL2_PGPDI8_PPDI3_WIDTH (1U) 6224 #define SIUL2_PGPDI8_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI3_SHIFT)) & SIUL2_PGPDI8_PPDI3_MASK) 6225 6226 #define SIUL2_PGPDI8_PPDI4_MASK (0x10U) 6227 #define SIUL2_PGPDI8_PPDI4_SHIFT (4U) 6228 #define SIUL2_PGPDI8_PPDI4_WIDTH (1U) 6229 #define SIUL2_PGPDI8_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI4_SHIFT)) & SIUL2_PGPDI8_PPDI4_MASK) 6230 6231 #define SIUL2_PGPDI8_PPDI5_MASK (0x20U) 6232 #define SIUL2_PGPDI8_PPDI5_SHIFT (5U) 6233 #define SIUL2_PGPDI8_PPDI5_WIDTH (1U) 6234 #define SIUL2_PGPDI8_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI5_SHIFT)) & SIUL2_PGPDI8_PPDI5_MASK) 6235 6236 #define SIUL2_PGPDI8_PPDI6_MASK (0x40U) 6237 #define SIUL2_PGPDI8_PPDI6_SHIFT (6U) 6238 #define SIUL2_PGPDI8_PPDI6_WIDTH (1U) 6239 #define SIUL2_PGPDI8_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI6_SHIFT)) & SIUL2_PGPDI8_PPDI6_MASK) 6240 6241 #define SIUL2_PGPDI8_PPDI7_MASK (0x80U) 6242 #define SIUL2_PGPDI8_PPDI7_SHIFT (7U) 6243 #define SIUL2_PGPDI8_PPDI7_WIDTH (1U) 6244 #define SIUL2_PGPDI8_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI7_SHIFT)) & SIUL2_PGPDI8_PPDI7_MASK) 6245 6246 #define SIUL2_PGPDI8_PPDI8_MASK (0x100U) 6247 #define SIUL2_PGPDI8_PPDI8_SHIFT (8U) 6248 #define SIUL2_PGPDI8_PPDI8_WIDTH (1U) 6249 #define SIUL2_PGPDI8_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI8_SHIFT)) & SIUL2_PGPDI8_PPDI8_MASK) 6250 6251 #define SIUL2_PGPDI8_PPDI9_MASK (0x200U) 6252 #define SIUL2_PGPDI8_PPDI9_SHIFT (9U) 6253 #define SIUL2_PGPDI8_PPDI9_WIDTH (1U) 6254 #define SIUL2_PGPDI8_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI9_SHIFT)) & SIUL2_PGPDI8_PPDI9_MASK) 6255 6256 #define SIUL2_PGPDI8_PPDI10_MASK (0x400U) 6257 #define SIUL2_PGPDI8_PPDI10_SHIFT (10U) 6258 #define SIUL2_PGPDI8_PPDI10_WIDTH (1U) 6259 #define SIUL2_PGPDI8_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI10_SHIFT)) & SIUL2_PGPDI8_PPDI10_MASK) 6260 6261 #define SIUL2_PGPDI8_PPDI11_MASK (0x800U) 6262 #define SIUL2_PGPDI8_PPDI11_SHIFT (11U) 6263 #define SIUL2_PGPDI8_PPDI11_WIDTH (1U) 6264 #define SIUL2_PGPDI8_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI11_SHIFT)) & SIUL2_PGPDI8_PPDI11_MASK) 6265 6266 #define SIUL2_PGPDI8_PPDI12_MASK (0x1000U) 6267 #define SIUL2_PGPDI8_PPDI12_SHIFT (12U) 6268 #define SIUL2_PGPDI8_PPDI12_WIDTH (1U) 6269 #define SIUL2_PGPDI8_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI12_SHIFT)) & SIUL2_PGPDI8_PPDI12_MASK) 6270 6271 #define SIUL2_PGPDI8_PPDI13_MASK (0x2000U) 6272 #define SIUL2_PGPDI8_PPDI13_SHIFT (13U) 6273 #define SIUL2_PGPDI8_PPDI13_WIDTH (1U) 6274 #define SIUL2_PGPDI8_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI13_SHIFT)) & SIUL2_PGPDI8_PPDI13_MASK) 6275 6276 #define SIUL2_PGPDI8_PPDI14_MASK (0x4000U) 6277 #define SIUL2_PGPDI8_PPDI14_SHIFT (14U) 6278 #define SIUL2_PGPDI8_PPDI14_WIDTH (1U) 6279 #define SIUL2_PGPDI8_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI14_SHIFT)) & SIUL2_PGPDI8_PPDI14_MASK) 6280 6281 #define SIUL2_PGPDI8_PPDI15_MASK (0x8000U) 6282 #define SIUL2_PGPDI8_PPDI15_SHIFT (15U) 6283 #define SIUL2_PGPDI8_PPDI15_WIDTH (1U) 6284 #define SIUL2_PGPDI8_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI8_PPDI15_SHIFT)) & SIUL2_PGPDI8_PPDI15_MASK) 6285 /*! @} */ 6286 6287 /*! @name PGPDI10 - SIUL2 Parallel GPIO Pad Data In Register */ 6288 /*! @{ */ 6289 6290 #define SIUL2_PGPDI10_PPDI2_MASK (0x4U) 6291 #define SIUL2_PGPDI10_PPDI2_SHIFT (2U) 6292 #define SIUL2_PGPDI10_PPDI2_WIDTH (1U) 6293 #define SIUL2_PGPDI10_PPDI2(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI2_SHIFT)) & SIUL2_PGPDI10_PPDI2_MASK) 6294 6295 #define SIUL2_PGPDI10_PPDI3_MASK (0x8U) 6296 #define SIUL2_PGPDI10_PPDI3_SHIFT (3U) 6297 #define SIUL2_PGPDI10_PPDI3_WIDTH (1U) 6298 #define SIUL2_PGPDI10_PPDI3(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI3_SHIFT)) & SIUL2_PGPDI10_PPDI3_MASK) 6299 6300 #define SIUL2_PGPDI10_PPDI4_MASK (0x10U) 6301 #define SIUL2_PGPDI10_PPDI4_SHIFT (4U) 6302 #define SIUL2_PGPDI10_PPDI4_WIDTH (1U) 6303 #define SIUL2_PGPDI10_PPDI4(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI4_SHIFT)) & SIUL2_PGPDI10_PPDI4_MASK) 6304 6305 #define SIUL2_PGPDI10_PPDI5_MASK (0x20U) 6306 #define SIUL2_PGPDI10_PPDI5_SHIFT (5U) 6307 #define SIUL2_PGPDI10_PPDI5_WIDTH (1U) 6308 #define SIUL2_PGPDI10_PPDI5(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI5_SHIFT)) & SIUL2_PGPDI10_PPDI5_MASK) 6309 6310 #define SIUL2_PGPDI10_PPDI6_MASK (0x40U) 6311 #define SIUL2_PGPDI10_PPDI6_SHIFT (6U) 6312 #define SIUL2_PGPDI10_PPDI6_WIDTH (1U) 6313 #define SIUL2_PGPDI10_PPDI6(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI6_SHIFT)) & SIUL2_PGPDI10_PPDI6_MASK) 6314 6315 #define SIUL2_PGPDI10_PPDI7_MASK (0x80U) 6316 #define SIUL2_PGPDI10_PPDI7_SHIFT (7U) 6317 #define SIUL2_PGPDI10_PPDI7_WIDTH (1U) 6318 #define SIUL2_PGPDI10_PPDI7(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI7_SHIFT)) & SIUL2_PGPDI10_PPDI7_MASK) 6319 6320 #define SIUL2_PGPDI10_PPDI8_MASK (0x100U) 6321 #define SIUL2_PGPDI10_PPDI8_SHIFT (8U) 6322 #define SIUL2_PGPDI10_PPDI8_WIDTH (1U) 6323 #define SIUL2_PGPDI10_PPDI8(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI8_SHIFT)) & SIUL2_PGPDI10_PPDI8_MASK) 6324 6325 #define SIUL2_PGPDI10_PPDI9_MASK (0x200U) 6326 #define SIUL2_PGPDI10_PPDI9_SHIFT (9U) 6327 #define SIUL2_PGPDI10_PPDI9_WIDTH (1U) 6328 #define SIUL2_PGPDI10_PPDI9(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI9_SHIFT)) & SIUL2_PGPDI10_PPDI9_MASK) 6329 6330 #define SIUL2_PGPDI10_PPDI10_MASK (0x400U) 6331 #define SIUL2_PGPDI10_PPDI10_SHIFT (10U) 6332 #define SIUL2_PGPDI10_PPDI10_WIDTH (1U) 6333 #define SIUL2_PGPDI10_PPDI10(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI10_SHIFT)) & SIUL2_PGPDI10_PPDI10_MASK) 6334 6335 #define SIUL2_PGPDI10_PPDI11_MASK (0x800U) 6336 #define SIUL2_PGPDI10_PPDI11_SHIFT (11U) 6337 #define SIUL2_PGPDI10_PPDI11_WIDTH (1U) 6338 #define SIUL2_PGPDI10_PPDI11(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI11_SHIFT)) & SIUL2_PGPDI10_PPDI11_MASK) 6339 6340 #define SIUL2_PGPDI10_PPDI12_MASK (0x1000U) 6341 #define SIUL2_PGPDI10_PPDI12_SHIFT (12U) 6342 #define SIUL2_PGPDI10_PPDI12_WIDTH (1U) 6343 #define SIUL2_PGPDI10_PPDI12(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI12_SHIFT)) & SIUL2_PGPDI10_PPDI12_MASK) 6344 6345 #define SIUL2_PGPDI10_PPDI13_MASK (0x2000U) 6346 #define SIUL2_PGPDI10_PPDI13_SHIFT (13U) 6347 #define SIUL2_PGPDI10_PPDI13_WIDTH (1U) 6348 #define SIUL2_PGPDI10_PPDI13(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI13_SHIFT)) & SIUL2_PGPDI10_PPDI13_MASK) 6349 6350 #define SIUL2_PGPDI10_PPDI14_MASK (0x4000U) 6351 #define SIUL2_PGPDI10_PPDI14_SHIFT (14U) 6352 #define SIUL2_PGPDI10_PPDI14_WIDTH (1U) 6353 #define SIUL2_PGPDI10_PPDI14(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI14_SHIFT)) & SIUL2_PGPDI10_PPDI14_MASK) 6354 6355 #define SIUL2_PGPDI10_PPDI15_MASK (0x8000U) 6356 #define SIUL2_PGPDI10_PPDI15_SHIFT (15U) 6357 #define SIUL2_PGPDI10_PPDI15_WIDTH (1U) 6358 #define SIUL2_PGPDI10_PPDI15(x) (((uint16_t)(((uint16_t)(x)) << SIUL2_PGPDI10_PPDI15_SHIFT)) & SIUL2_PGPDI10_PPDI15_MASK) 6359 /*! @} */ 6360 6361 /*! @name MPGPDO - SIUL2 Masked Parallel GPIO Pad Data Out Register */ 6362 /*! @{ */ 6363 6364 #define SIUL2_MPGPDO_MPPDO0_MASK (0x1U) 6365 #define SIUL2_MPGPDO_MPPDO0_SHIFT (0U) 6366 #define SIUL2_MPGPDO_MPPDO0_WIDTH (1U) 6367 #define SIUL2_MPGPDO_MPPDO0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO0_SHIFT)) & SIUL2_MPGPDO_MPPDO0_MASK) 6368 6369 #define SIUL2_MPGPDO_MPPDO1_MASK (0x2U) 6370 #define SIUL2_MPGPDO_MPPDO1_SHIFT (1U) 6371 #define SIUL2_MPGPDO_MPPDO1_WIDTH (1U) 6372 #define SIUL2_MPGPDO_MPPDO1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO1_SHIFT)) & SIUL2_MPGPDO_MPPDO1_MASK) 6373 6374 #define SIUL2_MPGPDO_MPPDO2_MASK (0x4U) 6375 #define SIUL2_MPGPDO_MPPDO2_SHIFT (2U) 6376 #define SIUL2_MPGPDO_MPPDO2_WIDTH (1U) 6377 #define SIUL2_MPGPDO_MPPDO2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO2_SHIFT)) & SIUL2_MPGPDO_MPPDO2_MASK) 6378 6379 #define SIUL2_MPGPDO_MPPDO3_MASK (0x8U) 6380 #define SIUL2_MPGPDO_MPPDO3_SHIFT (3U) 6381 #define SIUL2_MPGPDO_MPPDO3_WIDTH (1U) 6382 #define SIUL2_MPGPDO_MPPDO3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO3_SHIFT)) & SIUL2_MPGPDO_MPPDO3_MASK) 6383 6384 #define SIUL2_MPGPDO_MPPDO4_MASK (0x10U) 6385 #define SIUL2_MPGPDO_MPPDO4_SHIFT (4U) 6386 #define SIUL2_MPGPDO_MPPDO4_WIDTH (1U) 6387 #define SIUL2_MPGPDO_MPPDO4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO4_SHIFT)) & SIUL2_MPGPDO_MPPDO4_MASK) 6388 6389 #define SIUL2_MPGPDO_MPPDO5_MASK (0x20U) 6390 #define SIUL2_MPGPDO_MPPDO5_SHIFT (5U) 6391 #define SIUL2_MPGPDO_MPPDO5_WIDTH (1U) 6392 #define SIUL2_MPGPDO_MPPDO5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO5_SHIFT)) & SIUL2_MPGPDO_MPPDO5_MASK) 6393 6394 #define SIUL2_MPGPDO_MPPDO6_MASK (0x40U) 6395 #define SIUL2_MPGPDO_MPPDO6_SHIFT (6U) 6396 #define SIUL2_MPGPDO_MPPDO6_WIDTH (1U) 6397 #define SIUL2_MPGPDO_MPPDO6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO6_SHIFT)) & SIUL2_MPGPDO_MPPDO6_MASK) 6398 6399 #define SIUL2_MPGPDO_MPPDO7_MASK (0x80U) 6400 #define SIUL2_MPGPDO_MPPDO7_SHIFT (7U) 6401 #define SIUL2_MPGPDO_MPPDO7_WIDTH (1U) 6402 #define SIUL2_MPGPDO_MPPDO7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO7_SHIFT)) & SIUL2_MPGPDO_MPPDO7_MASK) 6403 6404 #define SIUL2_MPGPDO_MPPDO8_MASK (0x100U) 6405 #define SIUL2_MPGPDO_MPPDO8_SHIFT (8U) 6406 #define SIUL2_MPGPDO_MPPDO8_WIDTH (1U) 6407 #define SIUL2_MPGPDO_MPPDO8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO8_SHIFT)) & SIUL2_MPGPDO_MPPDO8_MASK) 6408 6409 #define SIUL2_MPGPDO_MPPDO9_MASK (0x200U) 6410 #define SIUL2_MPGPDO_MPPDO9_SHIFT (9U) 6411 #define SIUL2_MPGPDO_MPPDO9_WIDTH (1U) 6412 #define SIUL2_MPGPDO_MPPDO9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO9_SHIFT)) & SIUL2_MPGPDO_MPPDO9_MASK) 6413 6414 #define SIUL2_MPGPDO_MPPDO10_MASK (0x400U) 6415 #define SIUL2_MPGPDO_MPPDO10_SHIFT (10U) 6416 #define SIUL2_MPGPDO_MPPDO10_WIDTH (1U) 6417 #define SIUL2_MPGPDO_MPPDO10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO10_SHIFT)) & SIUL2_MPGPDO_MPPDO10_MASK) 6418 6419 #define SIUL2_MPGPDO_MPPDO11_MASK (0x800U) 6420 #define SIUL2_MPGPDO_MPPDO11_SHIFT (11U) 6421 #define SIUL2_MPGPDO_MPPDO11_WIDTH (1U) 6422 #define SIUL2_MPGPDO_MPPDO11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO11_SHIFT)) & SIUL2_MPGPDO_MPPDO11_MASK) 6423 6424 #define SIUL2_MPGPDO_MPPDO12_MASK (0x1000U) 6425 #define SIUL2_MPGPDO_MPPDO12_SHIFT (12U) 6426 #define SIUL2_MPGPDO_MPPDO12_WIDTH (1U) 6427 #define SIUL2_MPGPDO_MPPDO12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO12_SHIFT)) & SIUL2_MPGPDO_MPPDO12_MASK) 6428 6429 #define SIUL2_MPGPDO_MPPDO13_MASK (0x2000U) 6430 #define SIUL2_MPGPDO_MPPDO13_SHIFT (13U) 6431 #define SIUL2_MPGPDO_MPPDO13_WIDTH (1U) 6432 #define SIUL2_MPGPDO_MPPDO13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO13_SHIFT)) & SIUL2_MPGPDO_MPPDO13_MASK) 6433 6434 #define SIUL2_MPGPDO_MPPDO14_MASK (0x4000U) 6435 #define SIUL2_MPGPDO_MPPDO14_SHIFT (14U) 6436 #define SIUL2_MPGPDO_MPPDO14_WIDTH (1U) 6437 #define SIUL2_MPGPDO_MPPDO14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO14_SHIFT)) & SIUL2_MPGPDO_MPPDO14_MASK) 6438 6439 #define SIUL2_MPGPDO_MPPDO15_MASK (0x8000U) 6440 #define SIUL2_MPGPDO_MPPDO15_SHIFT (15U) 6441 #define SIUL2_MPGPDO_MPPDO15_WIDTH (1U) 6442 #define SIUL2_MPGPDO_MPPDO15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MPPDO15_SHIFT)) & SIUL2_MPGPDO_MPPDO15_MASK) 6443 6444 #define SIUL2_MPGPDO_MASK0_MASK (0x10000U) 6445 #define SIUL2_MPGPDO_MASK0_SHIFT (16U) 6446 #define SIUL2_MPGPDO_MASK0_WIDTH (1U) 6447 #define SIUL2_MPGPDO_MASK0(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK0_SHIFT)) & SIUL2_MPGPDO_MASK0_MASK) 6448 6449 #define SIUL2_MPGPDO_MASK1_MASK (0x20000U) 6450 #define SIUL2_MPGPDO_MASK1_SHIFT (17U) 6451 #define SIUL2_MPGPDO_MASK1_WIDTH (1U) 6452 #define SIUL2_MPGPDO_MASK1(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK1_SHIFT)) & SIUL2_MPGPDO_MASK1_MASK) 6453 6454 #define SIUL2_MPGPDO_MASK2_MASK (0x40000U) 6455 #define SIUL2_MPGPDO_MASK2_SHIFT (18U) 6456 #define SIUL2_MPGPDO_MASK2_WIDTH (1U) 6457 #define SIUL2_MPGPDO_MASK2(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK2_SHIFT)) & SIUL2_MPGPDO_MASK2_MASK) 6458 6459 #define SIUL2_MPGPDO_MASK3_MASK (0x80000U) 6460 #define SIUL2_MPGPDO_MASK3_SHIFT (19U) 6461 #define SIUL2_MPGPDO_MASK3_WIDTH (1U) 6462 #define SIUL2_MPGPDO_MASK3(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK3_SHIFT)) & SIUL2_MPGPDO_MASK3_MASK) 6463 6464 #define SIUL2_MPGPDO_MASK4_MASK (0x100000U) 6465 #define SIUL2_MPGPDO_MASK4_SHIFT (20U) 6466 #define SIUL2_MPGPDO_MASK4_WIDTH (1U) 6467 #define SIUL2_MPGPDO_MASK4(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK4_SHIFT)) & SIUL2_MPGPDO_MASK4_MASK) 6468 6469 #define SIUL2_MPGPDO_MASK5_MASK (0x200000U) 6470 #define SIUL2_MPGPDO_MASK5_SHIFT (21U) 6471 #define SIUL2_MPGPDO_MASK5_WIDTH (1U) 6472 #define SIUL2_MPGPDO_MASK5(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK5_SHIFT)) & SIUL2_MPGPDO_MASK5_MASK) 6473 6474 #define SIUL2_MPGPDO_MASK6_MASK (0x400000U) 6475 #define SIUL2_MPGPDO_MASK6_SHIFT (22U) 6476 #define SIUL2_MPGPDO_MASK6_WIDTH (1U) 6477 #define SIUL2_MPGPDO_MASK6(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK6_SHIFT)) & SIUL2_MPGPDO_MASK6_MASK) 6478 6479 #define SIUL2_MPGPDO_MASK7_MASK (0x800000U) 6480 #define SIUL2_MPGPDO_MASK7_SHIFT (23U) 6481 #define SIUL2_MPGPDO_MASK7_WIDTH (1U) 6482 #define SIUL2_MPGPDO_MASK7(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK7_SHIFT)) & SIUL2_MPGPDO_MASK7_MASK) 6483 6484 #define SIUL2_MPGPDO_MASK8_MASK (0x1000000U) 6485 #define SIUL2_MPGPDO_MASK8_SHIFT (24U) 6486 #define SIUL2_MPGPDO_MASK8_WIDTH (1U) 6487 #define SIUL2_MPGPDO_MASK8(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK8_SHIFT)) & SIUL2_MPGPDO_MASK8_MASK) 6488 6489 #define SIUL2_MPGPDO_MASK9_MASK (0x2000000U) 6490 #define SIUL2_MPGPDO_MASK9_SHIFT (25U) 6491 #define SIUL2_MPGPDO_MASK9_WIDTH (1U) 6492 #define SIUL2_MPGPDO_MASK9(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK9_SHIFT)) & SIUL2_MPGPDO_MASK9_MASK) 6493 6494 #define SIUL2_MPGPDO_MASK10_MASK (0x4000000U) 6495 #define SIUL2_MPGPDO_MASK10_SHIFT (26U) 6496 #define SIUL2_MPGPDO_MASK10_WIDTH (1U) 6497 #define SIUL2_MPGPDO_MASK10(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK10_SHIFT)) & SIUL2_MPGPDO_MASK10_MASK) 6498 6499 #define SIUL2_MPGPDO_MASK11_MASK (0x8000000U) 6500 #define SIUL2_MPGPDO_MASK11_SHIFT (27U) 6501 #define SIUL2_MPGPDO_MASK11_WIDTH (1U) 6502 #define SIUL2_MPGPDO_MASK11(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK11_SHIFT)) & SIUL2_MPGPDO_MASK11_MASK) 6503 6504 #define SIUL2_MPGPDO_MASK12_MASK (0x10000000U) 6505 #define SIUL2_MPGPDO_MASK12_SHIFT (28U) 6506 #define SIUL2_MPGPDO_MASK12_WIDTH (1U) 6507 #define SIUL2_MPGPDO_MASK12(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK12_SHIFT)) & SIUL2_MPGPDO_MASK12_MASK) 6508 6509 #define SIUL2_MPGPDO_MASK13_MASK (0x20000000U) 6510 #define SIUL2_MPGPDO_MASK13_SHIFT (29U) 6511 #define SIUL2_MPGPDO_MASK13_WIDTH (1U) 6512 #define SIUL2_MPGPDO_MASK13(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK13_SHIFT)) & SIUL2_MPGPDO_MASK13_MASK) 6513 6514 #define SIUL2_MPGPDO_MASK14_MASK (0x40000000U) 6515 #define SIUL2_MPGPDO_MASK14_SHIFT (30U) 6516 #define SIUL2_MPGPDO_MASK14_WIDTH (1U) 6517 #define SIUL2_MPGPDO_MASK14(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK14_SHIFT)) & SIUL2_MPGPDO_MASK14_MASK) 6518 6519 #define SIUL2_MPGPDO_MASK15_MASK (0x80000000U) 6520 #define SIUL2_MPGPDO_MASK15_SHIFT (31U) 6521 #define SIUL2_MPGPDO_MASK15_WIDTH (1U) 6522 #define SIUL2_MPGPDO_MASK15(x) (((uint32_t)(((uint32_t)(x)) << SIUL2_MPGPDO_MASK15_SHIFT)) & SIUL2_MPGPDO_MASK15_MASK) 6523 /*! @} */ 6524 6525 /*! 6526 * @} 6527 */ /* end of group SIUL2_Register_Masks */ 6528 6529 /*! 6530 * @} 6531 */ /* end of group SIUL2_Peripheral_Access_Layer */ 6532 6533 #endif /* #if !defined(S32Z2_SIUL2_H_) */ 6534
