1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SRAMCTL.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_SRAMCTL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SRAMCTL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SRAMCTL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SRAMCTL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SRAMCTL_Peripheral_Access_Layer SRAMCTL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SRAMCTL - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ 74 __IO uint32_t RAMIAS; /**< RAM Initialization Address Start, offset: 0x4 */ 75 __IO uint32_t RAMIAE; /**< RAM Initialization Address End, offset: 0x8 */ 76 __IO uint32_t RAMSR; /**< RAM Status, offset: 0xC */ 77 __I uint32_t RAMMEMA; /**< RAM ECC Address, offset: 0x10 */ 78 uint8_t RESERVED_0[4]; 79 __I uint32_t RAMSYSA; /**< RAM System Address, offset: 0x18 */ 80 __IO uint32_t RAMECCNT; /**< RAM Correctable Error Count, offset: 0x1C */ 81 __IO uint32_t RAMEID0; /**< RAM Error Injection Data 0, offset: 0x20 */ 82 __IO uint32_t RAMEID1; /**< RAM Error Injection Data 1, offset: 0x24 */ 83 __IO uint32_t RAMEIDC; /**< RAM Error Injection Data Control, offset: 0x28 */ 84 uint8_t RESERVED_1[4]; 85 __IO uint32_t RAMEIA; /**< RAM Error Injection Base Address, offset: 0x30 */ 86 __IO uint32_t RAMEIAM; /**< RAM Error Injection Address Mask, offset: 0x34 */ 87 uint8_t RESERVED_2[8]; 88 __IO uint32_t RAMMAXA; /**< RAM Maximum-Value Address, offset: 0x40 */ 89 uint8_t RESERVED_3[60]; 90 __IO uint32_t RAMCR2; /**< RAM Control 2, offset: 0x80 */ 91 uint8_t RESERVED_4[124]; 92 __IO uint32_t RAMPC; /**< RAM Power Control, offset: 0x100 */ 93 } SRAMCTL_Type, *SRAMCTL_MemMapPtr; 94 95 /** Number of instances of the SRAMCTL module. */ 96 #define SRAMCTL_INSTANCE_COUNT (27u) 97 98 /* SRAMCTL - Peripheral instance base addresses */ 99 /** Peripheral CE_SRAMCTL_0 base address */ 100 #define IP_CE_SRAMCTL_0_BASE (0x44A60000u) 101 /** Peripheral CE_SRAMCTL_0 base pointer */ 102 #define IP_CE_SRAMCTL_0 ((SRAMCTL_Type *)IP_CE_SRAMCTL_0_BASE) 103 /** Peripheral CE_SRAMCTL_1 base address */ 104 #define IP_CE_SRAMCTL_1_BASE (0x44A64000u) 105 /** Peripheral CE_SRAMCTL_1 base pointer */ 106 #define IP_CE_SRAMCTL_1 ((SRAMCTL_Type *)IP_CE_SRAMCTL_1_BASE) 107 /** Peripheral CE_SRAMCTL_2 base address */ 108 #define IP_CE_SRAMCTL_2_BASE (0x44A68000u) 109 /** Peripheral CE_SRAMCTL_2 base pointer */ 110 #define IP_CE_SRAMCTL_2 ((SRAMCTL_Type *)IP_CE_SRAMCTL_2_BASE) 111 /** Peripheral RTU0__SRAMCTL_C0 base address */ 112 #define IP_RTU0__SRAMCTL_C0_BASE (0x760C0000u) 113 /** Peripheral RTU0__SRAMCTL_C0 base pointer */ 114 #define IP_RTU0__SRAMCTL_C0 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_C0_BASE) 115 /** Peripheral RTU0__SRAMCTL_C1 base address */ 116 #define IP_RTU0__SRAMCTL_C1_BASE (0x760D0000u) 117 /** Peripheral RTU0__SRAMCTL_C1 base pointer */ 118 #define IP_RTU0__SRAMCTL_C1 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_C1_BASE) 119 /** Peripheral RTU0__SRAMCTL_C2 base address */ 120 #define IP_RTU0__SRAMCTL_C2_BASE (0x760E0000u) 121 /** Peripheral RTU0__SRAMCTL_C2 base pointer */ 122 #define IP_RTU0__SRAMCTL_C2 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_C2_BASE) 123 /** Peripheral RTU0__SRAMCTL_C3 base address */ 124 #define IP_RTU0__SRAMCTL_C3_BASE (0x760F0000u) 125 /** Peripheral RTU0__SRAMCTL_C3 base pointer */ 126 #define IP_RTU0__SRAMCTL_C3 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_C3_BASE) 127 /** Peripheral RTU0__SRAMCTL_C4 base address */ 128 #define IP_RTU0__SRAMCTL_C4_BASE (0x76240000u) 129 /** Peripheral RTU0__SRAMCTL_C4 base pointer */ 130 #define IP_RTU0__SRAMCTL_C4 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_C4_BASE) 131 /** Peripheral RTU0__SRAMCTL_C5 base address */ 132 #define IP_RTU0__SRAMCTL_C5_BASE (0x76250000u) 133 /** Peripheral RTU0__SRAMCTL_C5 base pointer */ 134 #define IP_RTU0__SRAMCTL_C5 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_C5_BASE) 135 /** Peripheral RTU0__SRAMCTL_C6 base address */ 136 #define IP_RTU0__SRAMCTL_C6_BASE (0x76260000u) 137 /** Peripheral RTU0__SRAMCTL_C6 base pointer */ 138 #define IP_RTU0__SRAMCTL_C6 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_C6_BASE) 139 /** Peripheral RTU0__SRAMCTL_D0 base address */ 140 #define IP_RTU0__SRAMCTL_D0_BASE (0x761D0000u) 141 /** Peripheral RTU0__SRAMCTL_D0 base pointer */ 142 #define IP_RTU0__SRAMCTL_D0 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_D0_BASE) 143 /** Peripheral RTU0__SRAMCTL_D1 base address */ 144 #define IP_RTU0__SRAMCTL_D1_BASE (0x761E0000u) 145 /** Peripheral RTU0__SRAMCTL_D1 base pointer */ 146 #define IP_RTU0__SRAMCTL_D1 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_D1_BASE) 147 /** Peripheral RTU0__SRAMCTL_D2 base address */ 148 #define IP_RTU0__SRAMCTL_D2_BASE (0x761F0000u) 149 /** Peripheral RTU0__SRAMCTL_D2 base pointer */ 150 #define IP_RTU0__SRAMCTL_D2 ((SRAMCTL_Type *)IP_RTU0__SRAMCTL_D2_BASE) 151 /** Peripheral RTU1__SRAMCTL_C0 base address */ 152 #define IP_RTU1__SRAMCTL_C0_BASE (0x768C0000u) 153 /** Peripheral RTU1__SRAMCTL_C0 base pointer */ 154 #define IP_RTU1__SRAMCTL_C0 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_C0_BASE) 155 /** Peripheral RTU1__SRAMCTL_C1 base address */ 156 #define IP_RTU1__SRAMCTL_C1_BASE (0x768D0000u) 157 /** Peripheral RTU1__SRAMCTL_C1 base pointer */ 158 #define IP_RTU1__SRAMCTL_C1 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_C1_BASE) 159 /** Peripheral RTU1__SRAMCTL_C2 base address */ 160 #define IP_RTU1__SRAMCTL_C2_BASE (0x768E0000u) 161 /** Peripheral RTU1__SRAMCTL_C2 base pointer */ 162 #define IP_RTU1__SRAMCTL_C2 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_C2_BASE) 163 /** Peripheral RTU1__SRAMCTL_C3 base address */ 164 #define IP_RTU1__SRAMCTL_C3_BASE (0x768F0000u) 165 /** Peripheral RTU1__SRAMCTL_C3 base pointer */ 166 #define IP_RTU1__SRAMCTL_C3 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_C3_BASE) 167 /** Peripheral RTU1__SRAMCTL_C4 base address */ 168 #define IP_RTU1__SRAMCTL_C4_BASE (0x76A40000u) 169 /** Peripheral RTU1__SRAMCTL_C4 base pointer */ 170 #define IP_RTU1__SRAMCTL_C4 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_C4_BASE) 171 /** Peripheral RTU1__SRAMCTL_C5 base address */ 172 #define IP_RTU1__SRAMCTL_C5_BASE (0x76A50000u) 173 /** Peripheral RTU1__SRAMCTL_C5 base pointer */ 174 #define IP_RTU1__SRAMCTL_C5 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_C5_BASE) 175 /** Peripheral RTU1__SRAMCTL_C6 base address */ 176 #define IP_RTU1__SRAMCTL_C6_BASE (0x76A60000u) 177 /** Peripheral RTU1__SRAMCTL_C6 base pointer */ 178 #define IP_RTU1__SRAMCTL_C6 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_C6_BASE) 179 /** Peripheral RTU1__SRAMCTL_D0 base address */ 180 #define IP_RTU1__SRAMCTL_D0_BASE (0x769D0000u) 181 /** Peripheral RTU1__SRAMCTL_D0 base pointer */ 182 #define IP_RTU1__SRAMCTL_D0 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_D0_BASE) 183 /** Peripheral RTU1__SRAMCTL_D1 base address */ 184 #define IP_RTU1__SRAMCTL_D1_BASE (0x769E0000u) 185 /** Peripheral RTU1__SRAMCTL_D1 base pointer */ 186 #define IP_RTU1__SRAMCTL_D1 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_D1_BASE) 187 /** Peripheral RTU1__SRAMCTL_D2 base address */ 188 #define IP_RTU1__SRAMCTL_D2_BASE (0x769F0000u) 189 /** Peripheral RTU1__SRAMCTL_D2 base pointer */ 190 #define IP_RTU1__SRAMCTL_D2 ((SRAMCTL_Type *)IP_RTU1__SRAMCTL_D2_BASE) 191 /** Peripheral SMU__SRAMCTL_0 base address */ 192 #define IP_SMU__SRAMCTL_0_BASE (0x45260000u) 193 /** Peripheral SMU__SRAMCTL_0 base pointer */ 194 #define IP_SMU__SRAMCTL_0 ((SRAMCTL_Type *)IP_SMU__SRAMCTL_0_BASE) 195 /** Peripheral SMU__SRAMCTL_1 base address */ 196 #define IP_SMU__SRAMCTL_1_BASE (0x45264000u) 197 /** Peripheral SMU__SRAMCTL_1 base pointer */ 198 #define IP_SMU__SRAMCTL_1 ((SRAMCTL_Type *)IP_SMU__SRAMCTL_1_BASE) 199 /** Peripheral SMU__SRAMCTL_2 base address */ 200 #define IP_SMU__SRAMCTL_2_BASE (0x45268000u) 201 /** Peripheral SMU__SRAMCTL_2 base pointer */ 202 #define IP_SMU__SRAMCTL_2 ((SRAMCTL_Type *)IP_SMU__SRAMCTL_2_BASE) 203 /** Peripheral SMU__SRAMCTL_3 base address */ 204 #define IP_SMU__SRAMCTL_3_BASE (0x4526C000u) 205 /** Peripheral SMU__SRAMCTL_3 base pointer */ 206 #define IP_SMU__SRAMCTL_3 ((SRAMCTL_Type *)IP_SMU__SRAMCTL_3_BASE) 207 /** Array initializer of SRAMCTL peripheral base addresses */ 208 #define IP_SRAMCTL_BASE_ADDRS { IP_CE_SRAMCTL_0_BASE, IP_CE_SRAMCTL_1_BASE, IP_CE_SRAMCTL_2_BASE, IP_RTU0__SRAMCTL_C0_BASE, IP_RTU0__SRAMCTL_C1_BASE, IP_RTU0__SRAMCTL_C2_BASE, IP_RTU0__SRAMCTL_C3_BASE, IP_RTU0__SRAMCTL_C4_BASE, IP_RTU0__SRAMCTL_C5_BASE, IP_RTU0__SRAMCTL_C6_BASE, IP_RTU0__SRAMCTL_D0_BASE, IP_RTU0__SRAMCTL_D1_BASE, IP_RTU0__SRAMCTL_D2_BASE, IP_RTU1__SRAMCTL_C0_BASE, IP_RTU1__SRAMCTL_C1_BASE, IP_RTU1__SRAMCTL_C2_BASE, IP_RTU1__SRAMCTL_C3_BASE, IP_RTU1__SRAMCTL_C4_BASE, IP_RTU1__SRAMCTL_C5_BASE, IP_RTU1__SRAMCTL_C6_BASE, IP_RTU1__SRAMCTL_D0_BASE, IP_RTU1__SRAMCTL_D1_BASE, IP_RTU1__SRAMCTL_D2_BASE, IP_SMU__SRAMCTL_0_BASE, IP_SMU__SRAMCTL_1_BASE, IP_SMU__SRAMCTL_2_BASE, IP_SMU__SRAMCTL_3_BASE } 209 /** Array initializer of SRAMCTL peripheral base pointers */ 210 #define IP_SRAMCTL_BASE_PTRS { IP_CE_SRAMCTL_0, IP_CE_SRAMCTL_1, IP_CE_SRAMCTL_2, IP_RTU0__SRAMCTL_C0, IP_RTU0__SRAMCTL_C1, IP_RTU0__SRAMCTL_C2, IP_RTU0__SRAMCTL_C3, IP_RTU0__SRAMCTL_C4, IP_RTU0__SRAMCTL_C5, IP_RTU0__SRAMCTL_C6, IP_RTU0__SRAMCTL_D0, IP_RTU0__SRAMCTL_D1, IP_RTU0__SRAMCTL_D2, IP_RTU1__SRAMCTL_C0, IP_RTU1__SRAMCTL_C1, IP_RTU1__SRAMCTL_C2, IP_RTU1__SRAMCTL_C3, IP_RTU1__SRAMCTL_C4, IP_RTU1__SRAMCTL_C5, IP_RTU1__SRAMCTL_C6, IP_RTU1__SRAMCTL_D0, IP_RTU1__SRAMCTL_D1, IP_RTU1__SRAMCTL_D2, IP_SMU__SRAMCTL_0, IP_SMU__SRAMCTL_1, IP_SMU__SRAMCTL_2, IP_SMU__SRAMCTL_3 } 211 212 /* ---------------------------------------------------------------------------- 213 -- SRAMCTL Register Masks 214 ---------------------------------------------------------------------------- */ 215 216 /*! 217 * @addtogroup SRAMCTL_Register_Masks SRAMCTL Register Masks 218 * @{ 219 */ 220 221 /*! @name RAMCR - RAM Control */ 222 /*! @{ */ 223 224 #define SRAMCTL_RAMCR_INIT_MASK (0x1U) 225 #define SRAMCTL_RAMCR_INIT_SHIFT (0U) 226 #define SRAMCTL_RAMCR_INIT_WIDTH (1U) 227 #define SRAMCTL_RAMCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMCR_INIT_SHIFT)) & SRAMCTL_RAMCR_INIT_MASK) 228 229 #define SRAMCTL_RAMCR_IWS_MASK (0x6U) 230 #define SRAMCTL_RAMCR_IWS_SHIFT (1U) 231 #define SRAMCTL_RAMCR_IWS_WIDTH (2U) 232 #define SRAMCTL_RAMCR_IWS(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMCR_IWS_SHIFT)) & SRAMCTL_RAMCR_IWS_MASK) 233 234 #define SRAMCTL_RAMCR_INIT_SYSA_MASK (0x100U) 235 #define SRAMCTL_RAMCR_INIT_SYSA_SHIFT (8U) 236 #define SRAMCTL_RAMCR_INIT_SYSA_WIDTH (1U) 237 #define SRAMCTL_RAMCR_INIT_SYSA(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMCR_INIT_SYSA_SHIFT)) & SRAMCTL_RAMCR_INIT_SYSA_MASK) 238 /*! @} */ 239 240 /*! @name RAMIAS - RAM Initialization Address Start */ 241 /*! @{ */ 242 243 #define SRAMCTL_RAMIAS_IAS_MASK (0xFFFFFFFFU) 244 #define SRAMCTL_RAMIAS_IAS_SHIFT (0U) 245 #define SRAMCTL_RAMIAS_IAS_WIDTH (32U) 246 #define SRAMCTL_RAMIAS_IAS(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMIAS_IAS_SHIFT)) & SRAMCTL_RAMIAS_IAS_MASK) 247 /*! @} */ 248 249 /*! @name RAMIAE - RAM Initialization Address End */ 250 /*! @{ */ 251 252 #define SRAMCTL_RAMIAE_IAE_MASK (0xFFFFFFFFU) 253 #define SRAMCTL_RAMIAE_IAE_SHIFT (0U) 254 #define SRAMCTL_RAMIAE_IAE_WIDTH (32U) 255 #define SRAMCTL_RAMIAE_IAE(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMIAE_IAE_SHIFT)) & SRAMCTL_RAMIAE_IAE_MASK) 256 /*! @} */ 257 258 /*! @name RAMSR - RAM Status */ 259 /*! @{ */ 260 261 #define SRAMCTL_RAMSR_IDONE_MASK (0x1U) 262 #define SRAMCTL_RAMSR_IDONE_SHIFT (0U) 263 #define SRAMCTL_RAMSR_IDONE_WIDTH (1U) 264 #define SRAMCTL_RAMSR_IDONE(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_IDONE_SHIFT)) & SRAMCTL_RAMSR_IDONE_MASK) 265 266 #define SRAMCTL_RAMSR_BUSERR_MASK (0x2U) 267 #define SRAMCTL_RAMSR_BUSERR_SHIFT (1U) 268 #define SRAMCTL_RAMSR_BUSERR_WIDTH (1U) 269 #define SRAMCTL_RAMSR_BUSERR(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_BUSERR_SHIFT)) & SRAMCTL_RAMSR_BUSERR_MASK) 270 271 #define SRAMCTL_RAMSR_IPEND_MASK (0x4U) 272 #define SRAMCTL_RAMSR_IPEND_SHIFT (2U) 273 #define SRAMCTL_RAMSR_IPEND_WIDTH (1U) 274 #define SRAMCTL_RAMSR_IPEND(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_IPEND_SHIFT)) & SRAMCTL_RAMSR_IPEND_MASK) 275 276 #define SRAMCTL_RAMSR_AVALID_MASK (0x8U) 277 #define SRAMCTL_RAMSR_AVALID_SHIFT (3U) 278 #define SRAMCTL_RAMSR_AVALID_WIDTH (1U) 279 #define SRAMCTL_RAMSR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_AVALID_SHIFT)) & SRAMCTL_RAMSR_AVALID_MASK) 280 281 #define SRAMCTL_RAMSR_AERR_MASK (0x20U) 282 #define SRAMCTL_RAMSR_AERR_SHIFT (5U) 283 #define SRAMCTL_RAMSR_AERR_WIDTH (1U) 284 #define SRAMCTL_RAMSR_AERR(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_AERR_SHIFT)) & SRAMCTL_RAMSR_AERR_MASK) 285 286 #define SRAMCTL_RAMSR_MLTERR_MASK (0x40U) 287 #define SRAMCTL_RAMSR_MLTERR_SHIFT (6U) 288 #define SRAMCTL_RAMSR_MLTERR_WIDTH (1U) 289 #define SRAMCTL_RAMSR_MLTERR(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_MLTERR_SHIFT)) & SRAMCTL_RAMSR_MLTERR_MASK) 290 291 #define SRAMCTL_RAMSR_SGLERR_MASK (0x80U) 292 #define SRAMCTL_RAMSR_SGLERR_SHIFT (7U) 293 #define SRAMCTL_RAMSR_SGLERR_WIDTH (1U) 294 #define SRAMCTL_RAMSR_SGLERR(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_SGLERR_SHIFT)) & SRAMCTL_RAMSR_SGLERR_MASK) 295 296 #define SRAMCTL_RAMSR_SYND_MASK (0xFF00U) 297 #define SRAMCTL_RAMSR_SYND_SHIFT (8U) 298 #define SRAMCTL_RAMSR_SYND_WIDTH (8U) 299 #define SRAMCTL_RAMSR_SYND(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_SYND_SHIFT)) & SRAMCTL_RAMSR_SYND_MASK) 300 301 #define SRAMCTL_RAMSR_EINFO_MASK (0xFF0000U) 302 #define SRAMCTL_RAMSR_EINFO_SHIFT (16U) 303 #define SRAMCTL_RAMSR_EINFO_WIDTH (8U) 304 #define SRAMCTL_RAMSR_EINFO(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSR_EINFO_SHIFT)) & SRAMCTL_RAMSR_EINFO_MASK) 305 /*! @} */ 306 307 /*! @name RAMMEMA - RAM ECC Address */ 308 /*! @{ */ 309 310 #define SRAMCTL_RAMMEMA_MEMA_MASK (0x1FFFFU) 311 #define SRAMCTL_RAMMEMA_MEMA_SHIFT (0U) 312 #define SRAMCTL_RAMMEMA_MEMA_WIDTH (17U) 313 #define SRAMCTL_RAMMEMA_MEMA(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMMEMA_MEMA_SHIFT)) & SRAMCTL_RAMMEMA_MEMA_MASK) 314 315 #define SRAMCTL_RAMMEMA_BANK_MASK (0x1F00000U) 316 #define SRAMCTL_RAMMEMA_BANK_SHIFT (20U) 317 #define SRAMCTL_RAMMEMA_BANK_WIDTH (5U) 318 #define SRAMCTL_RAMMEMA_BANK(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMMEMA_BANK_SHIFT)) & SRAMCTL_RAMMEMA_BANK_MASK) 319 /*! @} */ 320 321 /*! @name RAMSYSA - RAM System Address */ 322 /*! @{ */ 323 324 #define SRAMCTL_RAMSYSA_SYSA_MASK (0xFFFFFFFFU) 325 #define SRAMCTL_RAMSYSA_SYSA_SHIFT (0U) 326 #define SRAMCTL_RAMSYSA_SYSA_WIDTH (32U) 327 #define SRAMCTL_RAMSYSA_SYSA(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMSYSA_SYSA_SHIFT)) & SRAMCTL_RAMSYSA_SYSA_MASK) 328 /*! @} */ 329 330 /*! @name RAMECCNT - RAM Correctable Error Count */ 331 /*! @{ */ 332 333 #define SRAMCTL_RAMECCNT_ECCNT_MASK (0xFFU) 334 #define SRAMCTL_RAMECCNT_ECCNT_SHIFT (0U) 335 #define SRAMCTL_RAMECCNT_ECCNT_WIDTH (8U) 336 #define SRAMCTL_RAMECCNT_ECCNT(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMECCNT_ECCNT_SHIFT)) & SRAMCTL_RAMECCNT_ECCNT_MASK) 337 /*! @} */ 338 339 /*! @name RAMEID0 - RAM Error Injection Data 0 */ 340 /*! @{ */ 341 342 #define SRAMCTL_RAMEID0_EID_W0_MASK (0xFFFFFFFFU) 343 #define SRAMCTL_RAMEID0_EID_W0_SHIFT (0U) 344 #define SRAMCTL_RAMEID0_EID_W0_WIDTH (32U) 345 #define SRAMCTL_RAMEID0_EID_W0(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMEID0_EID_W0_SHIFT)) & SRAMCTL_RAMEID0_EID_W0_MASK) 346 /*! @} */ 347 348 /*! @name RAMEID1 - RAM Error Injection Data 1 */ 349 /*! @{ */ 350 351 #define SRAMCTL_RAMEID1_EID_W1_MASK (0xFFFFFFFFU) 352 #define SRAMCTL_RAMEID1_EID_W1_SHIFT (0U) 353 #define SRAMCTL_RAMEID1_EID_W1_WIDTH (32U) 354 #define SRAMCTL_RAMEID1_EID_W1(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMEID1_EID_W1_SHIFT)) & SRAMCTL_RAMEID1_EID_W1_MASK) 355 /*! @} */ 356 357 /*! @name RAMEIDC - RAM Error Injection Data Control */ 358 /*! @{ */ 359 360 #define SRAMCTL_RAMEIDC_EID_CKB_MASK (0xFFU) 361 #define SRAMCTL_RAMEIDC_EID_CKB_SHIFT (0U) 362 #define SRAMCTL_RAMEIDC_EID_CKB_WIDTH (8U) 363 #define SRAMCTL_RAMEIDC_EID_CKB(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMEIDC_EID_CKB_SHIFT)) & SRAMCTL_RAMEIDC_EID_CKB_MASK) 364 365 #define SRAMCTL_RAMEIDC_EIP_EN_MASK (0x1000000U) 366 #define SRAMCTL_RAMEIDC_EIP_EN_SHIFT (24U) 367 #define SRAMCTL_RAMEIDC_EIP_EN_WIDTH (1U) 368 #define SRAMCTL_RAMEIDC_EIP_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMEIDC_EIP_EN_SHIFT)) & SRAMCTL_RAMEIDC_EIP_EN_MASK) 369 370 #define SRAMCTL_RAMEIDC_EIA_EN_MASK (0x40000000U) 371 #define SRAMCTL_RAMEIDC_EIA_EN_SHIFT (30U) 372 #define SRAMCTL_RAMEIDC_EIA_EN_WIDTH (1U) 373 #define SRAMCTL_RAMEIDC_EIA_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMEIDC_EIA_EN_SHIFT)) & SRAMCTL_RAMEIDC_EIA_EN_MASK) 374 375 #define SRAMCTL_RAMEIDC_EID_EN_MASK (0x80000000U) 376 #define SRAMCTL_RAMEIDC_EID_EN_SHIFT (31U) 377 #define SRAMCTL_RAMEIDC_EID_EN_WIDTH (1U) 378 #define SRAMCTL_RAMEIDC_EID_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMEIDC_EID_EN_SHIFT)) & SRAMCTL_RAMEIDC_EID_EN_MASK) 379 /*! @} */ 380 381 /*! @name RAMEIA - RAM Error Injection Base Address */ 382 /*! @{ */ 383 384 #define SRAMCTL_RAMEIA_EIA_MASK (0xFFFFFFFFU) 385 #define SRAMCTL_RAMEIA_EIA_SHIFT (0U) 386 #define SRAMCTL_RAMEIA_EIA_WIDTH (32U) 387 #define SRAMCTL_RAMEIA_EIA(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMEIA_EIA_SHIFT)) & SRAMCTL_RAMEIA_EIA_MASK) 388 /*! @} */ 389 390 /*! @name RAMEIAM - RAM Error Injection Address Mask */ 391 /*! @{ */ 392 393 #define SRAMCTL_RAMEIAM_EIAM_MASK (0xFFFFFFFFU) 394 #define SRAMCTL_RAMEIAM_EIAM_SHIFT (0U) 395 #define SRAMCTL_RAMEIAM_EIAM_WIDTH (32U) 396 #define SRAMCTL_RAMEIAM_EIAM(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMEIAM_EIAM_SHIFT)) & SRAMCTL_RAMEIAM_EIAM_MASK) 397 /*! @} */ 398 399 /*! @name RAMMAXA - RAM Maximum-Value Address */ 400 /*! @{ */ 401 402 #define SRAMCTL_RAMMAXA_MAXA_MASK (0xFFFFFFFFU) 403 #define SRAMCTL_RAMMAXA_MAXA_SHIFT (0U) 404 #define SRAMCTL_RAMMAXA_MAXA_WIDTH (32U) 405 #define SRAMCTL_RAMMAXA_MAXA(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMMAXA_MAXA_SHIFT)) & SRAMCTL_RAMMAXA_MAXA_MASK) 406 /*! @} */ 407 408 /*! @name RAMCR2 - RAM Control 2 */ 409 /*! @{ */ 410 411 #define SRAMCTL_RAMCR2_PREF_MASK (0x1U) 412 #define SRAMCTL_RAMCR2_PREF_SHIFT (0U) 413 #define SRAMCTL_RAMCR2_PREF_WIDTH (1U) 414 #define SRAMCTL_RAMCR2_PREF(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMCR2_PREF_SHIFT)) & SRAMCTL_RAMCR2_PREF_MASK) 415 416 #define SRAMCTL_RAMCR2_WBUF_MASK (0x6U) 417 #define SRAMCTL_RAMCR2_WBUF_SHIFT (1U) 418 #define SRAMCTL_RAMCR2_WBUF_WIDTH (2U) 419 #define SRAMCTL_RAMCR2_WBUF(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMCR2_WBUF_SHIFT)) & SRAMCTL_RAMCR2_WBUF_MASK) 420 421 #define SRAMCTL_RAMCR2_DEM_MASK (0x8U) 422 #define SRAMCTL_RAMCR2_DEM_SHIFT (3U) 423 #define SRAMCTL_RAMCR2_DEM_WIDTH (1U) 424 #define SRAMCTL_RAMCR2_DEM(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMCR2_DEM_SHIFT)) & SRAMCTL_RAMCR2_DEM_MASK) 425 /*! @} */ 426 427 /*! @name RAMPC - RAM Power Control */ 428 /*! @{ */ 429 430 #define SRAMCTL_RAMPC_PCUT_MASK (0xFFFFU) 431 #define SRAMCTL_RAMPC_PCUT_SHIFT (0U) 432 #define SRAMCTL_RAMPC_PCUT_WIDTH (16U) 433 #define SRAMCTL_RAMPC_PCUT(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMPC_PCUT_SHIFT)) & SRAMCTL_RAMPC_PCUT_MASK) 434 435 #define SRAMCTL_RAMPC_PCNT_MASK (0xF0000U) 436 #define SRAMCTL_RAMPC_PCNT_SHIFT (16U) 437 #define SRAMCTL_RAMPC_PCNT_WIDTH (4U) 438 #define SRAMCTL_RAMPC_PCNT(x) (((uint32_t)(((uint32_t)(x)) << SRAMCTL_RAMPC_PCNT_SHIFT)) & SRAMCTL_RAMPC_PCNT_MASK) 439 /*! @} */ 440 441 /*! 442 * @} 443 */ /* end of group SRAMCTL_Register_Masks */ 444 445 /*! 446 * @} 447 */ /* end of group SRAMCTL_Peripheral_Access_Layer */ 448 449 #endif /* #if !defined(S32Z2_SRAMCTL_H_) */ 450
