1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SW_PSEUDO_MAC_PORT2.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_SW_PSEUDO_MAC_PORT2 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SW_PSEUDO_MAC_PORT2_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SW_PSEUDO_MAC_PORT2_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SW_PSEUDO_MAC_PORT2 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SW_PSEUDO_MAC_PORT2_Peripheral_Access_Layer SW_PSEUDO_MAC_PORT2 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SW_PSEUDO_MAC_PORT2 - Size of Registers Arrays */ 72 #define SW_PSEUDO_MAC_PORT2_PPMROCR_COUNT 2u 73 #define SW_PSEUDO_MAC_PORT2_PPMRUFCR_COUNT 2u 74 #define SW_PSEUDO_MAC_PORT2_PPMRMFCR_COUNT 2u 75 #define SW_PSEUDO_MAC_PORT2_PPMRBFCR_COUNT 2u 76 #define SW_PSEUDO_MAC_PORT2_PPMTOCR_COUNT 2u 77 #define SW_PSEUDO_MAC_PORT2_PPMTUFCR_COUNT 2u 78 #define SW_PSEUDO_MAC_PORT2_PPMTMFCR_COUNT 2u 79 #define SW_PSEUDO_MAC_PORT2_PPMTBFCR_COUNT 2u 80 81 /** SW_PSEUDO_MAC_PORT2 - Register Layout Typedef */ 82 typedef struct { 83 uint8_t RESERVED_0[4096]; 84 __I uint32_t PPMSR; /**< Port pseudo MAC status register, offset: 0x1000 */ 85 uint8_t RESERVED_1[124]; 86 __I uint32_t PPMROCR[SW_PSEUDO_MAC_PORT2_PPMROCR_COUNT]; /**< Port pseudo MAC receive octets counter, array offset: 0x1080, array step: 0x4 */ 87 __I uint32_t PPMRUFCR[SW_PSEUDO_MAC_PORT2_PPMRUFCR_COUNT]; /**< Port pseudo MAC receive unicast frame counter register, array offset: 0x1088, array step: 0x4 */ 88 __I uint32_t PPMRMFCR[SW_PSEUDO_MAC_PORT2_PPMRMFCR_COUNT]; /**< Port pseudo MAC receive multicast frame counter register, array offset: 0x1090, array step: 0x4 */ 89 __I uint32_t PPMRBFCR[SW_PSEUDO_MAC_PORT2_PPMRBFCR_COUNT]; /**< Port pseudo MAC receive broadcast frame counter register, array offset: 0x1098, array step: 0x4 */ 90 uint8_t RESERVED_2[32]; 91 __I uint32_t PPMTOCR[SW_PSEUDO_MAC_PORT2_PPMTOCR_COUNT]; /**< Port pseudo MAC transmit octets counter, array offset: 0x10C0, array step: 0x4 */ 92 __I uint32_t PPMTUFCR[SW_PSEUDO_MAC_PORT2_PPMTUFCR_COUNT]; /**< Port pseudo MAC transmit unicast frame counter register, array offset: 0x10C8, array step: 0x4 */ 93 __I uint32_t PPMTMFCR[SW_PSEUDO_MAC_PORT2_PPMTMFCR_COUNT]; /**< Port pseudo MAC transmit multicast frame counter register, array offset: 0x10D0, array step: 0x4 */ 94 __I uint32_t PPMTBFCR[SW_PSEUDO_MAC_PORT2_PPMTBFCR_COUNT]; /**< Port pseudo MAC transmit broadcast frame counter register, array offset: 0x10D8, array step: 0x4 */ 95 } SW_PSEUDO_MAC_PORT2_Type, *SW_PSEUDO_MAC_PORT2_MemMapPtr; 96 97 /** Number of instances of the SW_PSEUDO_MAC_PORT2 module. */ 98 #define SW_PSEUDO_MAC_PORT2_INSTANCE_COUNT (1u) 99 100 /* SW_PSEUDO_MAC_PORT2 - Peripheral instance base addresses */ 101 /** Peripheral NETC__SW0_PSEUDO_MAC_PORT2 base address */ 102 #define IP_NETC__SW0_PSEUDO_MAC_PORT2_BASE (0x74A0C000u) 103 /** Peripheral NETC__SW0_PSEUDO_MAC_PORT2 base pointer */ 104 #define IP_NETC__SW0_PSEUDO_MAC_PORT2 ((SW_PSEUDO_MAC_PORT2_Type *)IP_NETC__SW0_PSEUDO_MAC_PORT2_BASE) 105 /** Array initializer of SW_PSEUDO_MAC_PORT2 peripheral base addresses */ 106 #define IP_SW_PSEUDO_MAC_PORT2_BASE_ADDRS { IP_NETC__SW0_PSEUDO_MAC_PORT2_BASE } 107 /** Array initializer of SW_PSEUDO_MAC_PORT2 peripheral base pointers */ 108 #define IP_SW_PSEUDO_MAC_PORT2_BASE_PTRS { IP_NETC__SW0_PSEUDO_MAC_PORT2 } 109 110 /* ---------------------------------------------------------------------------- 111 -- SW_PSEUDO_MAC_PORT2 Register Masks 112 ---------------------------------------------------------------------------- */ 113 114 /*! 115 * @addtogroup SW_PSEUDO_MAC_PORT2_Register_Masks SW_PSEUDO_MAC_PORT2 Register Masks 116 * @{ 117 */ 118 119 /*! @name PPMSR - Port pseudo MAC status register */ 120 /*! @{ */ 121 122 #define SW_PSEUDO_MAC_PORT2_PPMSR_LSTATE_MASK (0x1U) 123 #define SW_PSEUDO_MAC_PORT2_PPMSR_LSTATE_SHIFT (0U) 124 #define SW_PSEUDO_MAC_PORT2_PPMSR_LSTATE_WIDTH (1U) 125 #define SW_PSEUDO_MAC_PORT2_PPMSR_LSTATE(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMSR_LSTATE_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMSR_LSTATE_MASK) 126 127 #define SW_PSEUDO_MAC_PORT2_PPMSR_RSTATE_MASK (0x100U) 128 #define SW_PSEUDO_MAC_PORT2_PPMSR_RSTATE_SHIFT (8U) 129 #define SW_PSEUDO_MAC_PORT2_PPMSR_RSTATE_WIDTH (1U) 130 #define SW_PSEUDO_MAC_PORT2_PPMSR_RSTATE(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMSR_RSTATE_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMSR_RSTATE_MASK) 131 /*! @} */ 132 133 /*! @name PPMROCR - Port pseudo MAC receive octets counter */ 134 /*! @{ */ 135 136 #define SW_PSEUDO_MAC_PORT2_PPMROCR_ROCT_MASK (0xFFFFFFFFU) 137 #define SW_PSEUDO_MAC_PORT2_PPMROCR_ROCT_SHIFT (0U) 138 #define SW_PSEUDO_MAC_PORT2_PPMROCR_ROCT_WIDTH (32U) 139 #define SW_PSEUDO_MAC_PORT2_PPMROCR_ROCT(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMROCR_ROCT_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMROCR_ROCT_MASK) 140 /*! @} */ 141 142 /*! @name PPMRUFCR - Port pseudo MAC receive unicast frame counter register */ 143 /*! @{ */ 144 145 #define SW_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_MASK (0xFFFFFFFFU) 146 #define SW_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_SHIFT (0U) 147 #define SW_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_WIDTH (32U) 148 #define SW_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_MASK) 149 /*! @} */ 150 151 /*! @name PPMRMFCR - Port pseudo MAC receive multicast frame counter register */ 152 /*! @{ */ 153 154 #define SW_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_MASK (0xFFFFFFFFU) 155 #define SW_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_SHIFT (0U) 156 #define SW_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_WIDTH (32U) 157 #define SW_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_MASK) 158 /*! @} */ 159 160 /*! @name PPMRBFCR - Port pseudo MAC receive broadcast frame counter register */ 161 /*! @{ */ 162 163 #define SW_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_MASK (0xFFFFFFFFU) 164 #define SW_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_SHIFT (0U) 165 #define SW_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_WIDTH (32U) 166 #define SW_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_MASK) 167 /*! @} */ 168 169 /*! @name PPMTOCR - Port pseudo MAC transmit octets counter */ 170 /*! @{ */ 171 172 #define SW_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_MASK (0xFFFFFFFFU) 173 #define SW_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_SHIFT (0U) 174 #define SW_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_WIDTH (32U) 175 #define SW_PSEUDO_MAC_PORT2_PPMTOCR_TOCT(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_MASK) 176 /*! @} */ 177 178 /*! @name PPMTUFCR - Port pseudo MAC transmit unicast frame counter register */ 179 /*! @{ */ 180 181 #define SW_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_MASK (0xFFFFFFFFU) 182 #define SW_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_SHIFT (0U) 183 #define SW_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_WIDTH (32U) 184 #define SW_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_MASK) 185 /*! @} */ 186 187 /*! @name PPMTMFCR - Port pseudo MAC transmit multicast frame counter register */ 188 /*! @{ */ 189 190 #define SW_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_MASK (0xFFFFFFFFU) 191 #define SW_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_SHIFT (0U) 192 #define SW_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_WIDTH (32U) 193 #define SW_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_MASK) 194 /*! @} */ 195 196 /*! @name PPMTBFCR - Port pseudo MAC transmit broadcast frame counter register */ 197 /*! @{ */ 198 199 #define SW_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_MASK (0xFFFFFFFFU) 200 #define SW_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_SHIFT (0U) 201 #define SW_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_WIDTH (32U) 202 #define SW_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA(x) (((uint32_t)(((uint32_t)(x)) << SW_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_SHIFT)) & SW_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_MASK) 203 /*! @} */ 204 205 /*! 206 * @} 207 */ /* end of group SW_PSEUDO_MAC_PORT2_Register_Masks */ 208 209 /*! 210 * @} 211 */ /* end of group SW_PSEUDO_MAC_PORT2_Peripheral_Access_Layer */ 212 213 #endif /* #if !defined(S32Z2_SW_PSEUDO_MAC_PORT2_H_) */ 214
