1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SW_ETH_MAC_PORT0.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_SW_ETH_MAC_PORT0 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SW_ETH_MAC_PORT0_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SW_ETH_MAC_PORT0_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SW_ETH_MAC_PORT0 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SW_ETH_MAC_PORT0_Peripheral_Access_Layer SW_ETH_MAC_PORT0 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SW_ETH_MAC_PORT0 - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[4104]; 74 __IO uint32_t PM0_COMMAND_CONFIG; /**< Port MAC 0 Command and Configuration Register, offset: 0x1008 */ 75 __I uint32_t PM0_MAC_ADDR_0; /**< Port MAC 0 MAC Address Register 0, offset: 0x100C */ 76 __I uint32_t PM0_MAC_ADDR_1; /**< Port MAC 0 MAC Address Register 1, offset: 0x1010 */ 77 __IO uint32_t PM0_MAXFRM; /**< Port MAC 0 Maximum Frame Length Register, offset: 0x1014 */ 78 uint8_t RESERVED_1[40]; 79 __IO uint32_t PM0_IEVENT; /**< Port MAC 0 Interrupt Event Register, offset: 0x1040 */ 80 uint8_t RESERVED_2[8]; 81 __IO uint32_t PM0_IMASK; /**< Port MAC 0 Interrupt Mask Register(INT_MASK), offset: 0x104C */ 82 uint8_t RESERVED_3[4]; 83 __IO uint32_t PM0_PAUSE_QUANTA; /**< Port MAC 0 Pause Quanta Register, offset: 0x1054 */ 84 uint8_t RESERVED_4[12]; 85 __IO uint32_t PM0_PAUSE_THRESH; /**< Port MAC 0 Pause Quanta Threshold Register, offset: 0x1064 */ 86 uint8_t RESERVED_5[12]; 87 __I uint32_t PM0_RX_PAUSE_STATUS; /**< Port MAC 0 Receive Pause Status Register, offset: 0x1074 */ 88 uint8_t RESERVED_6[64]; 89 __IO uint32_t PM0_LPWAKE_TIMER; /**< Port MAC 0 EEE Low Power Wakeup Timer Register, offset: 0x10B8 */ 90 __IO uint32_t PM0_SLEEP_TIMER; /**< Port MAC 0 Transmit EEE Low Power Timer Register, offset: 0x10BC */ 91 __IO uint32_t PM0_SINGLE_STEP; /**< Port MAC 0 IEEE1588 Single-Step Control Register, offset: 0x10C0 */ 92 uint8_t RESERVED_7[12]; 93 __IO uint32_t PM0_HD_BACKOFF_ENTROPY; /**< Port MAC 0 half-duplex backoff entropy register, offset: 0x10D0 */ 94 uint8_t RESERVED_8[12]; 95 __IO uint32_t PM0_STATN_CONFIG; /**< Port MAC 0 Statistics Configuration Register, offset: 0x10E0 */ 96 uint8_t RESERVED_9[28]; 97 __I uint64_t PM0_REOCTN; /**< Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn), offset: 0x1100 */ 98 __I uint64_t PM0_ROCTN; /**< Port MAC 0 Receive Octets Counter(iflnOctetsn), offset: 0x1108 */ 99 uint8_t RESERVED_10[8]; 100 __I uint64_t PM0_RXPFN; /**< Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x1118 */ 101 __I uint64_t PM0_RFRMN; /**< Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn), offset: 0x1120 */ 102 __I uint64_t PM0_RFCSN; /**< Port MAC 0 Receive Frame Check Sequence Error Counter Register(), offset: 0x1128 */ 103 __I uint64_t PM0_RVLANN; /**< Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn), offset: 0x1130 */ 104 __I uint64_t PM0_RERRN; /**< Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn), offset: 0x1138 */ 105 __I uint64_t PM0_RUCAN; /**< Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn), offset: 0x1140 */ 106 __I uint64_t PM0_RMCAN; /**< Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn), offset: 0x1148 */ 107 __I uint64_t PM0_RBCAN; /**< Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn), offset: 0x1150 */ 108 __I uint64_t PM0_RDRPN; /**< Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn), offset: 0x1158 */ 109 __I uint64_t PM0_RPKTN; /**< Port MAC 0 Receive Packets Counter Register(etherStatsPktsn), offset: 0x1160 */ 110 __I uint64_t PM0_RUNDN; /**< Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x1168 */ 111 __I uint64_t PM0_R64N; /**< Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN), offset: 0x1170 */ 112 __I uint64_t PM0_R127N; /**< Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN), offset: 0x1178 */ 113 __I uint64_t PM0_R255N; /**< Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN), offset: 0x1180 */ 114 __I uint64_t PM0_R511N; /**< Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN), offset: 0x1188 */ 115 __I uint64_t PM0_R1023N; /**< Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN), offset: 0x1190 */ 116 __I uint64_t PM0_R1522N; /**< Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN), offset: 0x1198 */ 117 __I uint64_t PM0_R1523XN; /**< Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN), offset: 0x11A0 */ 118 __I uint64_t PM0_ROVRN; /**< Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn), offset: 0x11A8 */ 119 __I uint64_t PM0_RJBRN; /**< Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn), offset: 0x11B0 */ 120 __I uint64_t PM0_RFRGN; /**< Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn, offset: 0x11B8 */ 121 __I uint64_t PM0_RCNPN; /**< Port MAC 0 Receive Control Packet Counter Register, offset: 0x11C0 */ 122 __I uint64_t PM0_RDRNTPN; /**< Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn), offset: 0x11C8 */ 123 uint8_t RESERVED_11[48]; 124 __I uint64_t PM0_TEOCTN; /**< Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn), offset: 0x1200 */ 125 __I uint64_t PM0_TOCTN; /**< Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn), offset: 0x1208 */ 126 uint8_t RESERVED_12[8]; 127 __I uint64_t PM0_TXPFN; /**< Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x1218 */ 128 __I uint64_t PM0_TFRMN; /**< Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn), offset: 0x1220 */ 129 __I uint64_t PM0_TFCSN; /**< Port MAC 0 Transmit Frame Check Sequence Error Counter Register(), offset: 0x1228 */ 130 __I uint64_t PM0_TVLANN; /**< Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn), offset: 0x1230 */ 131 __I uint64_t PM0_TERRN; /**< Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn), offset: 0x1238 */ 132 __I uint64_t PM0_TUCAN; /**< Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn), offset: 0x1240 */ 133 __I uint64_t PM0_TMCAN; /**< Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn), offset: 0x1248 */ 134 __I uint64_t PM0_TBCAN; /**< Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn), offset: 0x1250 */ 135 uint8_t RESERVED_13[8]; 136 __I uint64_t PM0_TPKTN; /**< Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn), offset: 0x1260 */ 137 __I uint64_t PM0_TUNDN; /**< Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x1268 */ 138 __I uint64_t PM0_T64N; /**< Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN), offset: 0x1270 */ 139 __I uint64_t PM0_T127N; /**< Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN), offset: 0x1278 */ 140 __I uint64_t PM0_T255N; /**< Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN), offset: 0x1280 */ 141 __I uint64_t PM0_T511N; /**< Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN), offset: 0x1288 */ 142 __I uint64_t PM0_T1023N; /**< Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN), offset: 0x1290 */ 143 __I uint64_t PM0_T1522N; /**< Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN), offset: 0x1298 */ 144 __I uint64_t PM0_T1523XN; /**< Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN), offset: 0x12A0 */ 145 uint8_t RESERVED_14[24]; 146 __I uint64_t PM0_TCNPN; /**< Port MAC 0 Transmit Control Packet Counter Register, offset: 0x12C0 */ 147 uint8_t RESERVED_15[8]; 148 __I uint64_t PM0_TDFRN; /**< Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions), offset: 0x12D0 */ 149 __I uint64_t PM0_TMCOLN; /**< Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames), offset: 0x12D8 */ 150 __I uint64_t PM0_TSCOLN; /**< Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register, offset: 0x12E0 */ 151 __I uint64_t PM0_TLCOLN; /**< Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register, offset: 0x12E8 */ 152 __I uint64_t PM0_TECOLN; /**< Port MAC 0 Transmit Excessive Collisions Counter Register, offset: 0x12F0 */ 153 uint8_t RESERVED_16[8]; 154 __IO uint32_t PM0_IF_MODE; /**< Port MAC 0 Interface Mode Control Register, offset: 0x1300 */ 155 uint8_t RESERVED_17[260]; 156 __IO uint32_t PM1_COMMAND_CONFIG; /**< Port MAC 1 Command and Configuration Register, offset: 0x1408 */ 157 __I uint32_t PM1_MAC_ADDR_0; /**< Port MAC 1 MAC Address Register 0, offset: 0x140C */ 158 __I uint32_t PM1_MAC_ADDR_1; /**< Port MAC 1 MAC Address Register 1, offset: 0x1410 */ 159 __IO uint32_t PM1_MAXFRM; /**< Port MAC 1 Maximum Frame Length Register, offset: 0x1414 */ 160 uint8_t RESERVED_18[40]; 161 __IO uint32_t PM1_IEVENT; /**< Port MAC 1 Interrupt Event Register, offset: 0x1440 */ 162 uint8_t RESERVED_19[8]; 163 __IO uint32_t PM1_IMASK; /**< Port MAC 1 Interrupt Mask Register(INT_MASK), offset: 0x144C */ 164 uint8_t RESERVED_20[4]; 165 __IO uint32_t PM1_PAUSE_QUANTA; /**< Port MAC 1 Pause Quanta Register, offset: 0x1454 */ 166 uint8_t RESERVED_21[12]; 167 __IO uint32_t PM1_PAUSE_THRESH; /**< Port MAC 1 Pause Quanta Threshold Register, offset: 0x1464 */ 168 uint8_t RESERVED_22[12]; 169 __I uint32_t PM1_RX_PAUSE_STATUS; /**< Port MAC 1 Receive Pause Status Register, offset: 0x1474 */ 170 uint8_t RESERVED_23[64]; 171 __IO uint32_t PM1_LPWAKE_TIMER; /**< Port MAC 1 EEE Low Power Wakeup Timer Register, offset: 0x14B8 */ 172 __IO uint32_t PM1_SLEEP_TIMER; /**< Port MAC 1 Transmit EEE Low Power Timer Register, offset: 0x14BC */ 173 __IO uint32_t PM1_SINGLE_STEP; /**< Port MAC 1 IEEE1588 Single-Step Control Register, offset: 0x14C0 */ 174 uint8_t RESERVED_24[12]; 175 __IO uint32_t PM1_HD_BACKOFF_ENTROPY; /**< Port MAC 1 half-duplex backoff entropy register, offset: 0x14D0 */ 176 uint8_t RESERVED_25[12]; 177 __IO uint32_t PM1_STATN_CONFIG; /**< Port MAC 1 Statistics Configuration Register, offset: 0x14E0 */ 178 uint8_t RESERVED_26[28]; 179 __I uint64_t PM1_REOCTN; /**< Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn), offset: 0x1500 */ 180 __I uint64_t PM1_ROCTN; /**< Port MAC 1 Receive Octets Counter(iflnOctetsn), offset: 0x1508 */ 181 uint8_t RESERVED_27[8]; 182 __I uint64_t PM1_RXPFN; /**< Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x1518 */ 183 __I uint64_t PM1_RFRMN; /**< Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn), offset: 0x1520 */ 184 __I uint64_t PM1_RFCSN; /**< Port MAC 1 Receive Frame Check Sequence Error Counter Register(), offset: 0x1528 */ 185 __I uint64_t PM1_RVLANN; /**< Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn), offset: 0x1530 */ 186 __I uint64_t PM1_RERRN; /**< Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn), offset: 0x1538 */ 187 __I uint64_t PM1_RUCAN; /**< Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn), offset: 0x1540 */ 188 __I uint64_t PM1_RMCAN; /**< Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn), offset: 0x1548 */ 189 __I uint64_t PM1_RBCAN; /**< Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn), offset: 0x1550 */ 190 __I uint64_t PM1_RDRPN; /**< Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn), offset: 0x1558 */ 191 __I uint64_t PM1_RPKTN; /**< Port MAC 1 Receive Packets Counter Register(etherStatsPktsn), offset: 0x1560 */ 192 __I uint64_t PM1_RUNDN; /**< Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x1568 */ 193 __I uint64_t PM1_R64N; /**< Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN), offset: 0x1570 */ 194 __I uint64_t PM1_R127N; /**< Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN), offset: 0x1578 */ 195 __I uint64_t PM1_R255N; /**< Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN), offset: 0x1580 */ 196 __I uint64_t PM1_R511N; /**< Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN), offset: 0x1588 */ 197 __I uint64_t PM1_R1023N; /**< Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN), offset: 0x1590 */ 198 __I uint64_t PM1_R1522N; /**< Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN), offset: 0x1598 */ 199 __I uint64_t PM1_R1523XN; /**< Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN), offset: 0x15A0 */ 200 __I uint64_t PM1_ROVRN; /**< Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn), offset: 0x15A8 */ 201 __I uint64_t PM1_RJBRN; /**< Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn), offset: 0x15B0 */ 202 __I uint64_t PM1_RFRGN; /**< Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn, offset: 0x15B8 */ 203 __I uint64_t PM1_RCNPN; /**< Port MAC 1 Receive Control Packet Counter Register, offset: 0x15C0 */ 204 __I uint64_t PM1_RDRNTPN; /**< Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn), offset: 0x15C8 */ 205 uint8_t RESERVED_28[48]; 206 __I uint64_t PM1_TEOCTN; /**< Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn), offset: 0x1600 */ 207 __I uint64_t PM1_TOCTN; /**< Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn), offset: 0x1608 */ 208 uint8_t RESERVED_29[8]; 209 __I uint64_t PM1_TXPFN; /**< Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x1618 */ 210 __I uint64_t PM1_TFRMN; /**< Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn), offset: 0x1620 */ 211 __I uint64_t PM1_TFCSN; /**< Port MAC 1 Transmit Frame Check Sequence Error Counter Register(), offset: 0x1628 */ 212 __I uint64_t PM1_TVLANN; /**< Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn), offset: 0x1630 */ 213 __I uint64_t PM1_TERRN; /**< Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn), offset: 0x1638 */ 214 __I uint64_t PM1_TUCAN; /**< Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn), offset: 0x1640 */ 215 __I uint64_t PM1_TMCAN; /**< Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn), offset: 0x1648 */ 216 __I uint64_t PM1_TBCAN; /**< Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn), offset: 0x1650 */ 217 uint8_t RESERVED_30[8]; 218 __I uint64_t PM1_TPKTN; /**< Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn), offset: 0x1660 */ 219 __I uint64_t PM1_TUNDN; /**< Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x1668 */ 220 __I uint64_t PM1_T64N; /**< Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN), offset: 0x1670 */ 221 __I uint64_t PM1_T127N; /**< Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN), offset: 0x1678 */ 222 __I uint64_t PM1_T255N; /**< Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN), offset: 0x1680 */ 223 __I uint64_t PM1_T511N; /**< Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN), offset: 0x1688 */ 224 __I uint64_t PM1_T1023N; /**< Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN), offset: 0x1690 */ 225 __I uint64_t PM1_T1522N; /**< Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN), offset: 0x1698 */ 226 __I uint64_t PM1_T1523XN; /**< Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN), offset: 0x16A0 */ 227 uint8_t RESERVED_31[24]; 228 __I uint64_t PM1_TCNPN; /**< Port MAC 1 Transmit Control Packet Counter Register, offset: 0x16C0 */ 229 uint8_t RESERVED_32[8]; 230 __I uint64_t PM1_TDFRN; /**< Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions), offset: 0x16D0 */ 231 __I uint64_t PM1_TMCOLN; /**< Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames), offset: 0x16D8 */ 232 __I uint64_t PM1_TSCOLN; /**< Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register, offset: 0x16E0 */ 233 __I uint64_t PM1_TLCOLN; /**< Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register, offset: 0x16E8 */ 234 __I uint64_t PM1_TECOLN; /**< Port MAC 1 Transmit Excessive Collisions Counter Register, offset: 0x16F0 */ 235 uint8_t RESERVED_33[8]; 236 __IO uint32_t PM1_IF_MODE; /**< Port MAC 1 Interface Mode Control Register, offset: 0x1700 */ 237 uint8_t RESERVED_34[252]; 238 __IO uint32_t MAC_MERGE_MMCSR; /**< Port MAC Merge Control and Status Register, offset: 0x1800 */ 239 uint8_t RESERVED_35[4]; 240 __IO uint32_t MAC_MERGE_MMFAECR; /**< Port MAC Merge Frame Assembly Error Count Register, offset: 0x1808 */ 241 __IO uint32_t MAC_MERGE_MMFSECR; /**< Port MAC Merge Frame SMD Error Count Register, offset: 0x180C */ 242 __IO uint32_t MAC_MERGE_MMFAOCR; /**< Port MAC Merge Frame Assembly OK Count Register, offset: 0x1810 */ 243 __IO uint32_t MAC_MERGE_MMFCRXR; /**< Port MAC Merge Fragment Count RX Register, offset: 0x1814 */ 244 __IO uint32_t MAC_MERGE_MMFCTXR; /**< Port MAC Merge Fragment Count TX Register, offset: 0x1818 */ 245 __IO uint32_t MAC_MERGE_MMHCR; /**< Port MAC Merge Hold Count Register, offset: 0x181C */ 246 uint8_t RESERVED_36[992]; 247 __IO uint32_t PEMDIOCR; /**< Port external MDIO configuration register, offset: 0x1C00 */ 248 __IO uint32_t PEMDIOICR; /**< Port external MDIO interface control register, offset: 0x1C04 */ 249 __IO uint32_t PEMDIOIDR; /**< Port external MDIO interface data register, offset: 0x1C08 */ 250 __IO uint32_t PEMDIORAR; /**< Port external MDIO register address register, offset: 0x1C0C */ 251 __I uint32_t PEMDIOSR; /**< Port external MDIO status register, offset: 0x1C10 */ 252 uint8_t RESERVED_37[12]; 253 __IO uint32_t PPSCR; /**< PHY status configuration register, offset: 0x1C20 */ 254 __IO uint32_t PPSCTRLR; /**< Port PHY status control register, offset: 0x1C24 */ 255 __I uint32_t PPSDR; /**< Port PHY status data register, offset: 0x1C28 */ 256 __IO uint32_t PPSRAR; /**< Port PHY status register address register, offset: 0x1C2C */ 257 __IO uint32_t PPSER; /**< Port PHY status event register, offset: 0x1C30 */ 258 __IO uint32_t PPSMR; /**< Port PHY status mask register, offset: 0x1C34 */ 259 } SW_ETH_MAC_PORT0_Type, *SW_ETH_MAC_PORT0_MemMapPtr; 260 261 /** Number of instances of the SW_ETH_MAC_PORT0 module. */ 262 #define SW_ETH_MAC_PORT0_INSTANCE_COUNT (1u) 263 264 /* SW_ETH_MAC_PORT0 - Peripheral instance base addresses */ 265 /** Peripheral NETC__SW0_ETH_MAC_PORT0 base address */ 266 #define IP_NETC__SW0_ETH_MAC_PORT0_BASE (0x74A04000u) 267 /** Peripheral NETC__SW0_ETH_MAC_PORT0 base pointer */ 268 #define IP_NETC__SW0_ETH_MAC_PORT0 ((SW_ETH_MAC_PORT0_Type *)IP_NETC__SW0_ETH_MAC_PORT0_BASE) 269 /** Array initializer of SW_ETH_MAC_PORT0 peripheral base addresses */ 270 #define IP_SW_ETH_MAC_PORT0_BASE_ADDRS { IP_NETC__SW0_ETH_MAC_PORT0_BASE } 271 /** Array initializer of SW_ETH_MAC_PORT0 peripheral base pointers */ 272 #define IP_SW_ETH_MAC_PORT0_BASE_PTRS { IP_NETC__SW0_ETH_MAC_PORT0 } 273 274 /* ---------------------------------------------------------------------------- 275 -- SW_ETH_MAC_PORT0 Register Masks 276 ---------------------------------------------------------------------------- */ 277 278 /*! 279 * @addtogroup SW_ETH_MAC_PORT0_Register_Masks SW_ETH_MAC_PORT0 Register Masks 280 * @{ 281 */ 282 283 /*! @name PM0_COMMAND_CONFIG - Port MAC 0 Command and Configuration Register */ 284 /*! @{ */ 285 286 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_MASK (0x1U) 287 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_SHIFT (0U) 288 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_WIDTH (1U) 289 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_EN_MASK) 290 291 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_MASK (0x2U) 292 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_SHIFT (1U) 293 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_WIDTH (1U) 294 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_RX_EN_MASK) 295 296 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_MASK (0x80U) 297 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_SHIFT (7U) 298 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_WIDTH (1U) 299 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_FWD_MASK) 300 301 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_MASK (0x100U) 302 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_SHIFT (8U) 303 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_WIDTH (1U) 304 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_PAUSE_IGN_MASK) 305 306 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_MASK (0x200U) 307 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_SHIFT (9U) 308 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_WIDTH (1U) 309 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_ADDR_INS_MASK) 310 311 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_MASK (0x400U) 312 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_SHIFT (10U) 313 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_WIDTH (1U) 314 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_LOOP_ENA_MASK) 315 316 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_MASK (0x2000U) 317 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_SHIFT (13U) 318 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_WIDTH (1U) 319 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_CNT_FRM_EN_MASK) 320 321 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_MASK (0x8000U) 322 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_SHIFT (15U) 323 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_WIDTH (1U) 324 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TXP_MASK) 325 326 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_MASK (0x400000U) 327 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_SHIFT (22U) 328 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_WIDTH (1U) 329 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_FLUSH_MASK) 330 331 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_MASK (0x800000U) 332 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT (23U) 333 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_WIDTH (1U) 334 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TX_LOWP_ENA_MASK) 335 336 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_MASK (0x4000000U) 337 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_SHIFT (26U) 338 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_WIDTH (1U) 339 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_SWR_MASK) 340 341 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_MASK (0x40000000U) 342 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_SHIFT (30U) 343 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_WIDTH (1U) 344 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_TS_MODE_MASK) 345 346 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_MASK (0x80000000U) 347 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_SHIFT (31U) 348 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_WIDTH (1U) 349 #define SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_SHIFT)) & SW_ETH_MAC_PORT0_PM0_COMMAND_CONFIG_MG_MASK) 350 /*! @} */ 351 352 /*! @name PM0_MAC_ADDR_0 - Port MAC 0 MAC Address Register 0 */ 353 /*! @{ */ 354 355 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_MASK (0xFFFFFFFFU) 356 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_SHIFT (0U) 357 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_WIDTH (32U) 358 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_SHIFT)) & SW_ETH_MAC_PORT0_PM0_MAC_ADDR_0_MAC_ADDR_0_MASK) 359 /*! @} */ 360 361 /*! @name PM0_MAC_ADDR_1 - Port MAC 0 MAC Address Register 1 */ 362 /*! @{ */ 363 364 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_MASK (0xFFFFU) 365 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_SHIFT (0U) 366 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_WIDTH (16U) 367 #define SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_SHIFT)) & SW_ETH_MAC_PORT0_PM0_MAC_ADDR_1_MAC_ADDR_1_MASK) 368 /*! @} */ 369 370 /*! @name PM0_MAXFRM - Port MAC 0 Maximum Frame Length Register */ 371 /*! @{ */ 372 373 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_MASK (0xFFFFU) 374 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_SHIFT (0U) 375 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_WIDTH (16U) 376 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_SHIFT)) & SW_ETH_MAC_PORT0_PM0_MAXFRM_MAXFRM_MASK) 377 378 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_MASK (0xFFFF0000U) 379 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_SHIFT (16U) 380 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_WIDTH (16U) 381 #define SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_SHIFT)) & SW_ETH_MAC_PORT0_PM0_MAXFRM_TX_MTU_MASK) 382 /*! @} */ 383 384 /*! @name PM0_IEVENT - Port MAC 0 Interrupt Event Register */ 385 /*! @{ */ 386 387 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_LOWP_MASK (0x10U) 388 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_LOWP_SHIFT (4U) 389 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_LOWP_WIDTH (1U) 390 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_LOWP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_RX_LOWP_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_RX_LOWP_MASK) 391 392 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_MASK (0x20U) 393 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_SHIFT (5U) 394 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_WIDTH (1U) 395 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_TX_EMPTY_MASK) 396 397 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_MASK (0x40U) 398 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_SHIFT (6U) 399 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_WIDTH (1U) 400 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_RX_EMPTY_MASK) 401 402 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_MASK (0x400U) 403 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_SHIFT (10U) 404 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_WIDTH (1U) 405 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_TX_OVFL_MASK) 406 407 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_MASK (0x800U) 408 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_SHIFT (11U) 409 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_WIDTH (1U) 410 #define SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_TX_UNFL_MASK) 411 412 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_MASK (0x1000U) 413 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_SHIFT (12U) 414 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_WIDTH (1U) 415 #define SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_RX_OVFL_MASK) 416 417 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_MASK (0x4000U) 418 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_SHIFT (14U) 419 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_WIDTH (1U) 420 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MGI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_MGI_MASK) 421 422 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_SERR_MASK (0x8000000U) 423 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_SERR_SHIFT (27U) 424 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_SERR_WIDTH (1U) 425 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_SERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_SERR_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_SERR_MASK) 426 427 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_AERR_MASK (0x10000000U) 428 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_AERR_SHIFT (28U) 429 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_AERR_WIDTH (1U) 430 #define SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_AERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_AERR_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IEVENT_MRG_AERR_MASK) 431 /*! @} */ 432 433 /*! @name PM0_IMASK - Port MAC 0 Interrupt Mask Register(INT_MASK) */ 434 /*! @{ */ 435 436 #define SW_ETH_MAC_PORT0_PM0_IMASK_MGI_MASK (0x4000U) 437 #define SW_ETH_MAC_PORT0_PM0_IMASK_MGI_SHIFT (14U) 438 #define SW_ETH_MAC_PORT0_PM0_IMASK_MGI_WIDTH (1U) 439 #define SW_ETH_MAC_PORT0_PM0_IMASK_MGI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IMASK_MGI_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IMASK_MGI_MASK) 440 441 #define SW_ETH_MAC_PORT0_PM0_IMASK_MRG_SERR_MASK (0x8000000U) 442 #define SW_ETH_MAC_PORT0_PM0_IMASK_MRG_SERR_SHIFT (27U) 443 #define SW_ETH_MAC_PORT0_PM0_IMASK_MRG_SERR_WIDTH (1U) 444 #define SW_ETH_MAC_PORT0_PM0_IMASK_MRG_SERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IMASK_MRG_SERR_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IMASK_MRG_SERR_MASK) 445 446 #define SW_ETH_MAC_PORT0_PM0_IMASK_MRG_AERR_MASK (0x10000000U) 447 #define SW_ETH_MAC_PORT0_PM0_IMASK_MRG_AERR_SHIFT (28U) 448 #define SW_ETH_MAC_PORT0_PM0_IMASK_MRG_AERR_WIDTH (1U) 449 #define SW_ETH_MAC_PORT0_PM0_IMASK_MRG_AERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IMASK_MRG_AERR_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IMASK_MRG_AERR_MASK) 450 /*! @} */ 451 452 /*! @name PM0_PAUSE_QUANTA - Port MAC 0 Pause Quanta Register */ 453 /*! @{ */ 454 455 #define SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_MASK (0xFFFFU) 456 #define SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_SHIFT (0U) 457 #define SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_WIDTH (16U) 458 #define SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_SHIFT)) & SW_ETH_MAC_PORT0_PM0_PAUSE_QUANTA_PQNT_MASK) 459 /*! @} */ 460 461 /*! @name PM0_PAUSE_THRESH - Port MAC 0 Pause Quanta Threshold Register */ 462 /*! @{ */ 463 464 #define SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_MASK (0xFFFFU) 465 #define SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_SHIFT (0U) 466 #define SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_WIDTH (16U) 467 #define SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_SHIFT)) & SW_ETH_MAC_PORT0_PM0_PAUSE_THRESH_QTH_MASK) 468 /*! @} */ 469 470 /*! @name PM0_RX_PAUSE_STATUS - Port MAC 0 Receive Pause Status Register */ 471 /*! @{ */ 472 473 #define SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_MASK (0x1U) 474 #define SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_SHIFT (0U) 475 #define SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_WIDTH (1U) 476 #define SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RX_PAUSE_STATUS_PSTAT_MASK) 477 /*! @} */ 478 479 /*! @name PM0_LPWAKE_TIMER - Port MAC 0 EEE Low Power Wakeup Timer Register */ 480 /*! @{ */ 481 482 #define SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_MASK (0xFFFFFFU) 483 #define SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_SHIFT (0U) 484 #define SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_WIDTH (24U) 485 #define SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_SHIFT)) & SW_ETH_MAC_PORT0_PM0_LPWAKE_TIMER_TW_SYS_TX_MASK) 486 /*! @} */ 487 488 /*! @name PM0_SLEEP_TIMER - Port MAC 0 Transmit EEE Low Power Timer Register */ 489 /*! @{ */ 490 491 #define SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_MASK (0xFFFFFFU) 492 #define SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_SHIFT (0U) 493 #define SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_WIDTH (24U) 494 #define SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_SHIFT)) & SW_ETH_MAC_PORT0_PM0_SLEEP_TIMER_SLEEPT_MASK) 495 /*! @} */ 496 497 /*! @name PM0_SINGLE_STEP - Port MAC 0 IEEE1588 Single-Step Control Register */ 498 /*! @{ */ 499 500 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_CH_MASK (0x40U) 501 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_CH_SHIFT (6U) 502 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_CH_WIDTH (1U) 503 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_CH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_CH_SHIFT)) & SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_CH_MASK) 504 505 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_MASK (0xFF80U) 506 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_SHIFT (7U) 507 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_WIDTH (9U) 508 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_SHIFT)) & SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_OFFSET_MASK) 509 510 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_MASK (0x80000000U) 511 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_SHIFT (31U) 512 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_WIDTH (1U) 513 #define SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM0_SINGLE_STEP_EN_MASK) 514 /*! @} */ 515 516 /*! @name PM0_HD_BACKOFF_ENTROPY - Port MAC 0 half-duplex backoff entropy register */ 517 /*! @{ */ 518 519 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK (0x3FFU) 520 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT (0U) 521 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_WIDTH (10U) 522 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT)) & SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK) 523 524 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U) 525 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U) 526 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_WIDTH (1U) 527 #define SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & SW_ETH_MAC_PORT0_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK) 528 /*! @} */ 529 530 /*! @name PM0_STATN_CONFIG - Port MAC 0 Statistics Configuration Register */ 531 /*! @{ */ 532 533 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_MASK (0x1U) 534 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_SHIFT (0U) 535 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_WIDTH (1U) 536 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_SHIFT)) & SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_SAT_MASK) 537 538 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_MASK (0x2U) 539 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_SHIFT (1U) 540 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_WIDTH (1U) 541 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_SHIFT)) & SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_COD_MASK) 542 543 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_MASK (0x4U) 544 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_SHIFT (2U) 545 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_WIDTH (1U) 546 #define SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_SHIFT)) & SW_ETH_MAC_PORT0_PM0_STATN_CONFIG_CLR_MASK) 547 /*! @} */ 548 549 /*! @name PM0_REOCTN - Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn) */ 550 /*! @{ */ 551 552 #define SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 553 #define SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_SHIFT (0U) 554 #define SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_WIDTH (64U) 555 #define SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_REOCTN_REOCTn_MASK) 556 /*! @} */ 557 558 /*! @name PM0_ROCTN - Port MAC 0 Receive Octets Counter(iflnOctetsn) */ 559 /*! @{ */ 560 561 #define SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_MASK (0xFFFFFFFFFFFFFFFFU) 562 #define SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_SHIFT (0U) 563 #define SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_WIDTH (64U) 564 #define SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_ROCTN_ROCTn_MASK) 565 /*! @} */ 566 567 /*! @name PM0_RXPFN - Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ 568 /*! @{ */ 569 570 #define SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_MASK (0xFFFFFFFFFFFFFFFFU) 571 #define SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_SHIFT (0U) 572 #define SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_WIDTH (64U) 573 #define SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RXPFN_RXPFn_MASK) 574 /*! @} */ 575 576 /*! @name PM0_RFRMN - Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn) */ 577 /*! @{ */ 578 579 #define SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_MASK (0xFFFFFFFFFFFFFFFFU) 580 #define SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_SHIFT (0U) 581 #define SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_WIDTH (64U) 582 #define SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RFRMN_RFRMn_MASK) 583 /*! @} */ 584 585 /*! @name PM0_RFCSN - Port MAC 0 Receive Frame Check Sequence Error Counter Register() */ 586 /*! @{ */ 587 588 #define SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_MASK (0xFFFFFFFFFFFFFFFFU) 589 #define SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_SHIFT (0U) 590 #define SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_WIDTH (64U) 591 #define SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RFCSN_RFCSn_MASK) 592 /*! @} */ 593 594 /*! @name PM0_RVLANN - Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn) */ 595 /*! @{ */ 596 597 #define SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_MASK (0xFFFFFFFFFFFFFFFFU) 598 #define SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_SHIFT (0U) 599 #define SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_WIDTH (64U) 600 #define SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RVLANN_RVLANn_MASK) 601 /*! @} */ 602 603 /*! @name PM0_RERRN - Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn) */ 604 /*! @{ */ 605 606 #define SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_MASK (0xFFFFFFFFFFFFFFFFU) 607 #define SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_SHIFT (0U) 608 #define SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_WIDTH (64U) 609 #define SW_ETH_MAC_PORT0_PM0_RERRN_RERRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RERRN_RERRn_MASK) 610 /*! @} */ 611 612 /*! @name PM0_RUCAN - Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn) */ 613 /*! @{ */ 614 615 #define SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_MASK (0xFFFFFFFFFFFFFFFFU) 616 #define SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_SHIFT (0U) 617 #define SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_WIDTH (64U) 618 #define SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RUCAN_RUCAn_MASK) 619 /*! @} */ 620 621 /*! @name PM0_RMCAN - Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn) */ 622 /*! @{ */ 623 624 #define SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_MASK (0xFFFFFFFFFFFFFFFFU) 625 #define SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_SHIFT (0U) 626 #define SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_WIDTH (64U) 627 #define SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RMCAN_RMCAn_MASK) 628 /*! @} */ 629 630 /*! @name PM0_RBCAN - Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) */ 631 /*! @{ */ 632 633 #define SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_MASK (0xFFFFFFFFFFFFFFFFU) 634 #define SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_SHIFT (0U) 635 #define SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_WIDTH (64U) 636 #define SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RBCAN_RBCAn_MASK) 637 /*! @} */ 638 639 /*! @name PM0_RDRPN - Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn) */ 640 /*! @{ */ 641 642 #define SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_MASK (0xFFFFFFFFFFFFFFFFU) 643 #define SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_SHIFT (0U) 644 #define SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_WIDTH (64U) 645 #define SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RDRPN_RDRPn_MASK) 646 /*! @} */ 647 648 /*! @name PM0_RPKTN - Port MAC 0 Receive Packets Counter Register(etherStatsPktsn) */ 649 /*! @{ */ 650 651 #define SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_MASK (0xFFFFFFFFFFFFFFFFU) 652 #define SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_SHIFT (0U) 653 #define SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_WIDTH (64U) 654 #define SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RPKTN_RPKTn_MASK) 655 /*! @} */ 656 657 /*! @name PM0_RUNDN - Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) */ 658 /*! @{ */ 659 660 #define SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_MASK (0xFFFFFFFFFFFFFFFFU) 661 #define SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_SHIFT (0U) 662 #define SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_WIDTH (64U) 663 #define SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RUNDN_RUNDn_MASK) 664 /*! @} */ 665 666 /*! @name PM0_R64N - Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) */ 667 /*! @{ */ 668 669 #define SW_ETH_MAC_PORT0_PM0_R64N_R64n_MASK (0xFFFFFFFFFFFFFFFFU) 670 #define SW_ETH_MAC_PORT0_PM0_R64N_R64n_SHIFT (0U) 671 #define SW_ETH_MAC_PORT0_PM0_R64N_R64n_WIDTH (64U) 672 #define SW_ETH_MAC_PORT0_PM0_R64N_R64n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R64N_R64n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R64N_R64n_MASK) 673 /*! @} */ 674 675 /*! @name PM0_R127N - Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) */ 676 /*! @{ */ 677 678 #define SW_ETH_MAC_PORT0_PM0_R127N_R127n_MASK (0xFFFFFFFFFFFFFFFFU) 679 #define SW_ETH_MAC_PORT0_PM0_R127N_R127n_SHIFT (0U) 680 #define SW_ETH_MAC_PORT0_PM0_R127N_R127n_WIDTH (64U) 681 #define SW_ETH_MAC_PORT0_PM0_R127N_R127n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R127N_R127n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R127N_R127n_MASK) 682 /*! @} */ 683 684 /*! @name PM0_R255N - Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) */ 685 /*! @{ */ 686 687 #define SW_ETH_MAC_PORT0_PM0_R255N_R255n_MASK (0xFFFFFFFFFFFFFFFFU) 688 #define SW_ETH_MAC_PORT0_PM0_R255N_R255n_SHIFT (0U) 689 #define SW_ETH_MAC_PORT0_PM0_R255N_R255n_WIDTH (64U) 690 #define SW_ETH_MAC_PORT0_PM0_R255N_R255n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R255N_R255n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R255N_R255n_MASK) 691 /*! @} */ 692 693 /*! @name PM0_R511N - Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) */ 694 /*! @{ */ 695 696 #define SW_ETH_MAC_PORT0_PM0_R511N_R511n_MASK (0xFFFFFFFFFFFFFFFFU) 697 #define SW_ETH_MAC_PORT0_PM0_R511N_R511n_SHIFT (0U) 698 #define SW_ETH_MAC_PORT0_PM0_R511N_R511n_WIDTH (64U) 699 #define SW_ETH_MAC_PORT0_PM0_R511N_R511n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R511N_R511n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R511N_R511n_MASK) 700 /*! @} */ 701 702 /*! @name PM0_R1023N - Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) */ 703 /*! @{ */ 704 705 #define SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_MASK (0xFFFFFFFFFFFFFFFFU) 706 #define SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_SHIFT (0U) 707 #define SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_WIDTH (64U) 708 #define SW_ETH_MAC_PORT0_PM0_R1023N_R1023n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R1023N_R1023n_MASK) 709 /*! @} */ 710 711 /*! @name PM0_R1522N - Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) */ 712 /*! @{ */ 713 714 #define SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_MASK (0xFFFFFFFFFFFFFFFFU) 715 #define SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_SHIFT (0U) 716 #define SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_WIDTH (64U) 717 #define SW_ETH_MAC_PORT0_PM0_R1522N_R1522n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R1522N_R1522n_MASK) 718 /*! @} */ 719 720 /*! @name PM0_R1523XN - Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) */ 721 /*! @{ */ 722 723 #define SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) 724 #define SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_SHIFT (0U) 725 #define SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_WIDTH (64U) 726 #define SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_R1523XN_R1523Xn_MASK) 727 /*! @} */ 728 729 /*! @name PM0_ROVRN - Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) */ 730 /*! @{ */ 731 732 #define SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_MASK (0xFFFFFFFFFFFFFFFFU) 733 #define SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_SHIFT (0U) 734 #define SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_WIDTH (64U) 735 #define SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_ROVRN_ROVRn_MASK) 736 /*! @} */ 737 738 /*! @name PM0_RJBRN - Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn) */ 739 /*! @{ */ 740 741 #define SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_MASK (0xFFFFFFFFFFFFFFFFU) 742 #define SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_SHIFT (0U) 743 #define SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_WIDTH (64U) 744 #define SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RJBRN_RJBRn_MASK) 745 /*! @} */ 746 747 /*! @name PM0_RFRGN - Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn */ 748 /*! @{ */ 749 750 #define SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_MASK (0xFFFFFFFFFFFFFFFFU) 751 #define SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_SHIFT (0U) 752 #define SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_WIDTH (64U) 753 #define SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RFRGN_RFRGn_MASK) 754 /*! @} */ 755 756 /*! @name PM0_RCNPN - Port MAC 0 Receive Control Packet Counter Register */ 757 /*! @{ */ 758 759 #define SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_MASK (0xFFFFFFFFFFFFFFFFU) 760 #define SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_SHIFT (0U) 761 #define SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_WIDTH (64U) 762 #define SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RCNPN_RCNPn_MASK) 763 /*! @} */ 764 765 /*! @name PM0_RDRNTPN - Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) */ 766 /*! @{ */ 767 768 #define SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_MASK (0xFFFFFFFFFFFFFFFFU) 769 #define SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_SHIFT (0U) 770 #define SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_WIDTH (64U) 771 #define SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_RDRNTPN_RDRNTPn_MASK) 772 /*! @} */ 773 774 /*! @name PM0_TEOCTN - Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn) */ 775 /*! @{ */ 776 777 #define SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 778 #define SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_SHIFT (0U) 779 #define SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_WIDTH (64U) 780 #define SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TEOCTN_TEOCTn_MASK) 781 /*! @} */ 782 783 /*! @name PM0_TOCTN - Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn) */ 784 /*! @{ */ 785 786 #define SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 787 #define SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_SHIFT (0U) 788 #define SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_WIDTH (64U) 789 #define SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TOCTN_TOCTn_MASK) 790 /*! @} */ 791 792 /*! @name PM0_TXPFN - Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ 793 /*! @{ */ 794 795 #define SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_MASK (0xFFFFFFFFFFFFFFFFU) 796 #define SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_SHIFT (0U) 797 #define SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_WIDTH (64U) 798 #define SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TXPFN_TXPFn_MASK) 799 /*! @} */ 800 801 /*! @name PM0_TFRMN - Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn) */ 802 /*! @{ */ 803 804 #define SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_MASK (0xFFFFFFFFFFFFFFFFU) 805 #define SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_SHIFT (0U) 806 #define SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_WIDTH (64U) 807 #define SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TFRMN_TFRMn_MASK) 808 /*! @} */ 809 810 /*! @name PM0_TFCSN - Port MAC 0 Transmit Frame Check Sequence Error Counter Register() */ 811 /*! @{ */ 812 813 #define SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_MASK (0xFFFFFFFFFFFFFFFFU) 814 #define SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_SHIFT (0U) 815 #define SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_WIDTH (64U) 816 #define SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TFCSN_TFCSn_MASK) 817 /*! @} */ 818 819 /*! @name PM0_TVLANN - Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) */ 820 /*! @{ */ 821 822 #define SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_MASK (0xFFFFFFFFFFFFFFFFU) 823 #define SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_SHIFT (0U) 824 #define SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_WIDTH (64U) 825 #define SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TVLANN_TVLANn_MASK) 826 /*! @} */ 827 828 /*! @name PM0_TERRN - Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn) */ 829 /*! @{ */ 830 831 #define SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_MASK (0xFFFFFFFFFFFFFFFFU) 832 #define SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_SHIFT (0U) 833 #define SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_WIDTH (64U) 834 #define SW_ETH_MAC_PORT0_PM0_TERRN_TERRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TERRN_TERRn_MASK) 835 /*! @} */ 836 837 /*! @name PM0_TUCAN - Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) */ 838 /*! @{ */ 839 840 #define SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_MASK (0xFFFFFFFFFFFFFFFFU) 841 #define SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_SHIFT (0U) 842 #define SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_WIDTH (64U) 843 #define SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TUCAN_TUCAn_MASK) 844 /*! @} */ 845 846 /*! @name PM0_TMCAN - Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) */ 847 /*! @{ */ 848 849 #define SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_MASK (0xFFFFFFFFFFFFFFFFU) 850 #define SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_SHIFT (0U) 851 #define SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_WIDTH (64U) 852 #define SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TMCAN_TMCAn_MASK) 853 /*! @} */ 854 855 /*! @name PM0_TBCAN - Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) */ 856 /*! @{ */ 857 858 #define SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_MASK (0xFFFFFFFFFFFFFFFFU) 859 #define SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_SHIFT (0U) 860 #define SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_WIDTH (64U) 861 #define SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TBCAN_TBCAn_MASK) 862 /*! @} */ 863 864 /*! @name PM0_TPKTN - Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn) */ 865 /*! @{ */ 866 867 #define SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_MASK (0xFFFFFFFFFFFFFFFFU) 868 #define SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_SHIFT (0U) 869 #define SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_WIDTH (64U) 870 #define SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TPKTN_TPKTn_MASK) 871 /*! @} */ 872 873 /*! @name PM0_TUNDN - Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) */ 874 /*! @{ */ 875 876 #define SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_MASK (0xFFFFFFFFFFFFFFFFU) 877 #define SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_SHIFT (0U) 878 #define SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_WIDTH (64U) 879 #define SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TUNDN_TUNDn_MASK) 880 /*! @} */ 881 882 /*! @name PM0_T64N - Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) */ 883 /*! @{ */ 884 885 #define SW_ETH_MAC_PORT0_PM0_T64N_T64n_MASK (0xFFFFFFFFFFFFFFFFU) 886 #define SW_ETH_MAC_PORT0_PM0_T64N_T64n_SHIFT (0U) 887 #define SW_ETH_MAC_PORT0_PM0_T64N_T64n_WIDTH (64U) 888 #define SW_ETH_MAC_PORT0_PM0_T64N_T64n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T64N_T64n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T64N_T64n_MASK) 889 /*! @} */ 890 891 /*! @name PM0_T127N - Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) */ 892 /*! @{ */ 893 894 #define SW_ETH_MAC_PORT0_PM0_T127N_T127n_MASK (0xFFFFFFFFFFFFFFFFU) 895 #define SW_ETH_MAC_PORT0_PM0_T127N_T127n_SHIFT (0U) 896 #define SW_ETH_MAC_PORT0_PM0_T127N_T127n_WIDTH (64U) 897 #define SW_ETH_MAC_PORT0_PM0_T127N_T127n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T127N_T127n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T127N_T127n_MASK) 898 /*! @} */ 899 900 /*! @name PM0_T255N - Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) */ 901 /*! @{ */ 902 903 #define SW_ETH_MAC_PORT0_PM0_T255N_T255n_MASK (0xFFFFFFFFFFFFFFFFU) 904 #define SW_ETH_MAC_PORT0_PM0_T255N_T255n_SHIFT (0U) 905 #define SW_ETH_MAC_PORT0_PM0_T255N_T255n_WIDTH (64U) 906 #define SW_ETH_MAC_PORT0_PM0_T255N_T255n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T255N_T255n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T255N_T255n_MASK) 907 /*! @} */ 908 909 /*! @name PM0_T511N - Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) */ 910 /*! @{ */ 911 912 #define SW_ETH_MAC_PORT0_PM0_T511N_T511n_MASK (0xFFFFFFFFFFFFFFFFU) 913 #define SW_ETH_MAC_PORT0_PM0_T511N_T511n_SHIFT (0U) 914 #define SW_ETH_MAC_PORT0_PM0_T511N_T511n_WIDTH (64U) 915 #define SW_ETH_MAC_PORT0_PM0_T511N_T511n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T511N_T511n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T511N_T511n_MASK) 916 /*! @} */ 917 918 /*! @name PM0_T1023N - Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) */ 919 /*! @{ */ 920 921 #define SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_MASK (0xFFFFFFFFFFFFFFFFU) 922 #define SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_SHIFT (0U) 923 #define SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_WIDTH (64U) 924 #define SW_ETH_MAC_PORT0_PM0_T1023N_T1023n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T1023N_T1023n_MASK) 925 /*! @} */ 926 927 /*! @name PM0_T1522N - Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) */ 928 /*! @{ */ 929 930 #define SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_MASK (0xFFFFFFFFFFFFFFFFU) 931 #define SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_SHIFT (0U) 932 #define SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_WIDTH (64U) 933 #define SW_ETH_MAC_PORT0_PM0_T1522N_T1522n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T1522N_T1522n_MASK) 934 /*! @} */ 935 936 /*! @name PM0_T1523XN - Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) */ 937 /*! @{ */ 938 939 #define SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) 940 #define SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_SHIFT (0U) 941 #define SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_WIDTH (64U) 942 #define SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_T1523XN_T1523Xn_MASK) 943 /*! @} */ 944 945 /*! @name PM0_TCNPN - Port MAC 0 Transmit Control Packet Counter Register */ 946 /*! @{ */ 947 948 #define SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_MASK (0xFFFFFFFFFFFFFFFFU) 949 #define SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_SHIFT (0U) 950 #define SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_WIDTH (64U) 951 #define SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TCNPN_TCNPn_MASK) 952 /*! @} */ 953 954 /*! @name PM0_TDFRN - Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) */ 955 /*! @{ */ 956 957 #define SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_MASK (0xFFFFFFFFFFFFFFFFU) 958 #define SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_SHIFT (0U) 959 #define SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_WIDTH (64U) 960 #define SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TDFRN_TDFRn_MASK) 961 /*! @} */ 962 963 /*! @name PM0_TMCOLN - Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) */ 964 /*! @{ */ 965 966 #define SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 967 #define SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_SHIFT (0U) 968 #define SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_WIDTH (64U) 969 #define SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TMCOLN_TMCOLn_MASK) 970 /*! @} */ 971 972 /*! @name PM0_TSCOLN - Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register */ 973 /*! @{ */ 974 975 #define SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 976 #define SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_SHIFT (0U) 977 #define SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_WIDTH (64U) 978 #define SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TSCOLN_TSCOLn_MASK) 979 /*! @} */ 980 981 /*! @name PM0_TLCOLN - Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register */ 982 /*! @{ */ 983 984 #define SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 985 #define SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_SHIFT (0U) 986 #define SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_WIDTH (64U) 987 #define SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TLCOLN_TLCOLn_MASK) 988 /*! @} */ 989 990 /*! @name PM0_TECOLN - Port MAC 0 Transmit Excessive Collisions Counter Register */ 991 /*! @{ */ 992 993 #define SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_MASK (0xFFFFFFFFFFFFFFFFU) 994 #define SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_SHIFT (0U) 995 #define SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_WIDTH (64U) 996 #define SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM0_TECOLN_TECOLn_MASK) 997 /*! @} */ 998 999 /*! @name PM0_IF_MODE - Port MAC 0 Interface Mode Control Register */ 1000 /*! @{ */ 1001 1002 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_MASK (0x7U) 1003 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_SHIFT (0U) 1004 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_WIDTH (3U) 1005 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_IFMODE_MASK) 1006 1007 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_MASK (0x8U) 1008 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_SHIFT (3U) 1009 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_WIDTH (1U) 1010 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_REVMII_MASK) 1011 1012 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_MASK (0x10U) 1013 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_SHIFT (4U) 1014 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_WIDTH (1U) 1015 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_M10(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_M10_MASK) 1016 1017 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_MASK (0x40U) 1018 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_SHIFT (6U) 1019 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_WIDTH (1U) 1020 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_HD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_HD_MASK) 1021 1022 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SFD_MASK (0x1000U) 1023 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SFD_SHIFT (12U) 1024 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SFD_WIDTH (1U) 1025 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SFD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_SFD_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_SFD_MASK) 1026 1027 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_MASK (0x6000U) 1028 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_SHIFT (13U) 1029 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_WIDTH (2U) 1030 #define SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_SHIFT)) & SW_ETH_MAC_PORT0_PM0_IF_MODE_SSP_MASK) 1031 /*! @} */ 1032 1033 /*! @name PM1_COMMAND_CONFIG - Port MAC 1 Command and Configuration Register */ 1034 /*! @{ */ 1035 1036 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_MASK (0x1U) 1037 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_SHIFT (0U) 1038 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_WIDTH (1U) 1039 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_EN_MASK) 1040 1041 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_MASK (0x2U) 1042 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_SHIFT (1U) 1043 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_WIDTH (1U) 1044 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_RX_EN_MASK) 1045 1046 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_MASK (0x80U) 1047 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_SHIFT (7U) 1048 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_WIDTH (1U) 1049 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_FWD_MASK) 1050 1051 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_MASK (0x100U) 1052 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_SHIFT (8U) 1053 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_WIDTH (1U) 1054 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_PAUSE_IGN_MASK) 1055 1056 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_MASK (0x200U) 1057 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_SHIFT (9U) 1058 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_WIDTH (1U) 1059 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_ADDR_INS_MASK) 1060 1061 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_MASK (0x400U) 1062 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_SHIFT (10U) 1063 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_WIDTH (1U) 1064 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_LOOP_ENA_MASK) 1065 1066 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_MASK (0x2000U) 1067 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_SHIFT (13U) 1068 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_WIDTH (1U) 1069 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_CNT_FRM_EN_MASK) 1070 1071 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_MASK (0x8000U) 1072 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_SHIFT (15U) 1073 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_WIDTH (1U) 1074 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TXP_MASK) 1075 1076 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_MASK (0x400000U) 1077 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_SHIFT (22U) 1078 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_WIDTH (1U) 1079 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_FLUSH_MASK) 1080 1081 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_MASK (0x800000U) 1082 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT (23U) 1083 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_WIDTH (1U) 1084 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TX_LOWP_ENA_MASK) 1085 1086 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_MASK (0x4000000U) 1087 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_SHIFT (26U) 1088 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_WIDTH (1U) 1089 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_SWR_MASK) 1090 1091 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_MASK (0x40000000U) 1092 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_SHIFT (30U) 1093 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_WIDTH (1U) 1094 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_TS_MODE_MASK) 1095 1096 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_MASK (0x80000000U) 1097 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_SHIFT (31U) 1098 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_WIDTH (1U) 1099 #define SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_SHIFT)) & SW_ETH_MAC_PORT0_PM1_COMMAND_CONFIG_MG_MASK) 1100 /*! @} */ 1101 1102 /*! @name PM1_MAC_ADDR_0 - Port MAC 1 MAC Address Register 0 */ 1103 /*! @{ */ 1104 1105 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_MASK (0xFFFFFFFFU) 1106 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_SHIFT (0U) 1107 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_WIDTH (32U) 1108 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_SHIFT)) & SW_ETH_MAC_PORT0_PM1_MAC_ADDR_0_MAC_ADDR_0_MASK) 1109 /*! @} */ 1110 1111 /*! @name PM1_MAC_ADDR_1 - Port MAC 1 MAC Address Register 1 */ 1112 /*! @{ */ 1113 1114 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_MASK (0xFFFFU) 1115 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_SHIFT (0U) 1116 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_WIDTH (16U) 1117 #define SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_SHIFT)) & SW_ETH_MAC_PORT0_PM1_MAC_ADDR_1_MAC_ADDR_1_MASK) 1118 /*! @} */ 1119 1120 /*! @name PM1_MAXFRM - Port MAC 1 Maximum Frame Length Register */ 1121 /*! @{ */ 1122 1123 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_MASK (0xFFFFU) 1124 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_SHIFT (0U) 1125 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_WIDTH (16U) 1126 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_SHIFT)) & SW_ETH_MAC_PORT0_PM1_MAXFRM_MAXFRM_MASK) 1127 1128 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_MASK (0xFFFF0000U) 1129 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_SHIFT (16U) 1130 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_WIDTH (16U) 1131 #define SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_SHIFT)) & SW_ETH_MAC_PORT0_PM1_MAXFRM_TX_MTU_MASK) 1132 /*! @} */ 1133 1134 /*! @name PM1_IEVENT - Port MAC 1 Interrupt Event Register */ 1135 /*! @{ */ 1136 1137 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_LOWP_MASK (0x10U) 1138 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_LOWP_SHIFT (4U) 1139 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_LOWP_WIDTH (1U) 1140 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_LOWP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_RX_LOWP_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_RX_LOWP_MASK) 1141 1142 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_MASK (0x20U) 1143 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_SHIFT (5U) 1144 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_WIDTH (1U) 1145 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_TX_EMPTY_MASK) 1146 1147 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_MASK (0x40U) 1148 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_SHIFT (6U) 1149 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_WIDTH (1U) 1150 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_RX_EMPTY_MASK) 1151 1152 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_MASK (0x400U) 1153 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_SHIFT (10U) 1154 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_WIDTH (1U) 1155 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_TX_OVFL_MASK) 1156 1157 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_MASK (0x800U) 1158 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_SHIFT (11U) 1159 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_WIDTH (1U) 1160 #define SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_TX_UNFL_MASK) 1161 1162 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_MASK (0x1000U) 1163 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_SHIFT (12U) 1164 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_WIDTH (1U) 1165 #define SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_RX_OVFL_MASK) 1166 1167 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_MASK (0x4000U) 1168 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_SHIFT (14U) 1169 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_WIDTH (1U) 1170 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MGI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_MGI_MASK) 1171 1172 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_SERR_MASK (0x8000000U) 1173 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_SERR_SHIFT (27U) 1174 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_SERR_WIDTH (1U) 1175 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_SERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_SERR_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_SERR_MASK) 1176 1177 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_AERR_MASK (0x10000000U) 1178 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_AERR_SHIFT (28U) 1179 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_AERR_WIDTH (1U) 1180 #define SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_AERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_AERR_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IEVENT_MRG_AERR_MASK) 1181 /*! @} */ 1182 1183 /*! @name PM1_IMASK - Port MAC 1 Interrupt Mask Register(INT_MASK) */ 1184 /*! @{ */ 1185 1186 #define SW_ETH_MAC_PORT0_PM1_IMASK_MGI_MASK (0x4000U) 1187 #define SW_ETH_MAC_PORT0_PM1_IMASK_MGI_SHIFT (14U) 1188 #define SW_ETH_MAC_PORT0_PM1_IMASK_MGI_WIDTH (1U) 1189 #define SW_ETH_MAC_PORT0_PM1_IMASK_MGI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IMASK_MGI_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IMASK_MGI_MASK) 1190 1191 #define SW_ETH_MAC_PORT0_PM1_IMASK_MRG_SERR_MASK (0x8000000U) 1192 #define SW_ETH_MAC_PORT0_PM1_IMASK_MRG_SERR_SHIFT (27U) 1193 #define SW_ETH_MAC_PORT0_PM1_IMASK_MRG_SERR_WIDTH (1U) 1194 #define SW_ETH_MAC_PORT0_PM1_IMASK_MRG_SERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IMASK_MRG_SERR_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IMASK_MRG_SERR_MASK) 1195 1196 #define SW_ETH_MAC_PORT0_PM1_IMASK_MRG_AERR_MASK (0x10000000U) 1197 #define SW_ETH_MAC_PORT0_PM1_IMASK_MRG_AERR_SHIFT (28U) 1198 #define SW_ETH_MAC_PORT0_PM1_IMASK_MRG_AERR_WIDTH (1U) 1199 #define SW_ETH_MAC_PORT0_PM1_IMASK_MRG_AERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IMASK_MRG_AERR_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IMASK_MRG_AERR_MASK) 1200 /*! @} */ 1201 1202 /*! @name PM1_PAUSE_QUANTA - Port MAC 1 Pause Quanta Register */ 1203 /*! @{ */ 1204 1205 #define SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_MASK (0xFFFFU) 1206 #define SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_SHIFT (0U) 1207 #define SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_WIDTH (16U) 1208 #define SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_SHIFT)) & SW_ETH_MAC_PORT0_PM1_PAUSE_QUANTA_PQNT_MASK) 1209 /*! @} */ 1210 1211 /*! @name PM1_PAUSE_THRESH - Port MAC 1 Pause Quanta Threshold Register */ 1212 /*! @{ */ 1213 1214 #define SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_MASK (0xFFFFU) 1215 #define SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_SHIFT (0U) 1216 #define SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_WIDTH (16U) 1217 #define SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_SHIFT)) & SW_ETH_MAC_PORT0_PM1_PAUSE_THRESH_QTH_MASK) 1218 /*! @} */ 1219 1220 /*! @name PM1_RX_PAUSE_STATUS - Port MAC 1 Receive Pause Status Register */ 1221 /*! @{ */ 1222 1223 #define SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_MASK (0x1U) 1224 #define SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_SHIFT (0U) 1225 #define SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_WIDTH (1U) 1226 #define SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RX_PAUSE_STATUS_PSTAT_MASK) 1227 /*! @} */ 1228 1229 /*! @name PM1_LPWAKE_TIMER - Port MAC 1 EEE Low Power Wakeup Timer Register */ 1230 /*! @{ */ 1231 1232 #define SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_MASK (0xFFFFFFU) 1233 #define SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_SHIFT (0U) 1234 #define SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_WIDTH (24U) 1235 #define SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_SHIFT)) & SW_ETH_MAC_PORT0_PM1_LPWAKE_TIMER_TW_SYS_TX_MASK) 1236 /*! @} */ 1237 1238 /*! @name PM1_SLEEP_TIMER - Port MAC 1 Transmit EEE Low Power Timer Register */ 1239 /*! @{ */ 1240 1241 #define SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_MASK (0xFFFFFFU) 1242 #define SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_SHIFT (0U) 1243 #define SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_WIDTH (24U) 1244 #define SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_SHIFT)) & SW_ETH_MAC_PORT0_PM1_SLEEP_TIMER_SLEEPT_MASK) 1245 /*! @} */ 1246 1247 /*! @name PM1_SINGLE_STEP - Port MAC 1 IEEE1588 Single-Step Control Register */ 1248 /*! @{ */ 1249 1250 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_CH_MASK (0x40U) 1251 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_CH_SHIFT (6U) 1252 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_CH_WIDTH (1U) 1253 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_CH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_CH_SHIFT)) & SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_CH_MASK) 1254 1255 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_MASK (0xFF80U) 1256 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_SHIFT (7U) 1257 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_WIDTH (9U) 1258 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_SHIFT)) & SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_OFFSET_MASK) 1259 1260 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_MASK (0x80000000U) 1261 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_SHIFT (31U) 1262 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_WIDTH (1U) 1263 #define SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_SHIFT)) & SW_ETH_MAC_PORT0_PM1_SINGLE_STEP_EN_MASK) 1264 /*! @} */ 1265 1266 /*! @name PM1_HD_BACKOFF_ENTROPY - Port MAC 1 half-duplex backoff entropy register */ 1267 /*! @{ */ 1268 1269 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK (0x3FFU) 1270 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT (0U) 1271 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_WIDTH (10U) 1272 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT)) & SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK) 1273 1274 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U) 1275 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U) 1276 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_WIDTH (1U) 1277 #define SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & SW_ETH_MAC_PORT0_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK) 1278 /*! @} */ 1279 1280 /*! @name PM1_STATN_CONFIG - Port MAC 1 Statistics Configuration Register */ 1281 /*! @{ */ 1282 1283 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_MASK (0x1U) 1284 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_SHIFT (0U) 1285 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_WIDTH (1U) 1286 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_SHIFT)) & SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_SAT_MASK) 1287 1288 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_MASK (0x2U) 1289 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_SHIFT (1U) 1290 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_WIDTH (1U) 1291 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_SHIFT)) & SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_COD_MASK) 1292 1293 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_MASK (0x4U) 1294 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_SHIFT (2U) 1295 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_WIDTH (1U) 1296 #define SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_SHIFT)) & SW_ETH_MAC_PORT0_PM1_STATN_CONFIG_CLR_MASK) 1297 /*! @} */ 1298 1299 /*! @name PM1_REOCTN - Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn) */ 1300 /*! @{ */ 1301 1302 #define SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 1303 #define SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_SHIFT (0U) 1304 #define SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_WIDTH (64U) 1305 #define SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_REOCTN_REOCTn_MASK) 1306 /*! @} */ 1307 1308 /*! @name PM1_ROCTN - Port MAC 1 Receive Octets Counter(iflnOctetsn) */ 1309 /*! @{ */ 1310 1311 #define SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_MASK (0xFFFFFFFFFFFFFFFFU) 1312 #define SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_SHIFT (0U) 1313 #define SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_WIDTH (64U) 1314 #define SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_ROCTN_ROCTn_MASK) 1315 /*! @} */ 1316 1317 /*! @name PM1_RXPFN - Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ 1318 /*! @{ */ 1319 1320 #define SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_MASK (0xFFFFFFFFFFFFFFFFU) 1321 #define SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_SHIFT (0U) 1322 #define SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_WIDTH (64U) 1323 #define SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RXPFN_RXPFn_MASK) 1324 /*! @} */ 1325 1326 /*! @name PM1_RFRMN - Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn) */ 1327 /*! @{ */ 1328 1329 #define SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_MASK (0xFFFFFFFFFFFFFFFFU) 1330 #define SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_SHIFT (0U) 1331 #define SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_WIDTH (64U) 1332 #define SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RFRMN_RFRMn_MASK) 1333 /*! @} */ 1334 1335 /*! @name PM1_RFCSN - Port MAC 1 Receive Frame Check Sequence Error Counter Register() */ 1336 /*! @{ */ 1337 1338 #define SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_MASK (0xFFFFFFFFFFFFFFFFU) 1339 #define SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_SHIFT (0U) 1340 #define SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_WIDTH (64U) 1341 #define SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RFCSN_RFCSn_MASK) 1342 /*! @} */ 1343 1344 /*! @name PM1_RVLANN - Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn) */ 1345 /*! @{ */ 1346 1347 #define SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_MASK (0xFFFFFFFFFFFFFFFFU) 1348 #define SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_SHIFT (0U) 1349 #define SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_WIDTH (64U) 1350 #define SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RVLANN_RVLANn_MASK) 1351 /*! @} */ 1352 1353 /*! @name PM1_RERRN - Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn) */ 1354 /*! @{ */ 1355 1356 #define SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_MASK (0xFFFFFFFFFFFFFFFFU) 1357 #define SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_SHIFT (0U) 1358 #define SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_WIDTH (64U) 1359 #define SW_ETH_MAC_PORT0_PM1_RERRN_RERRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RERRN_RERRn_MASK) 1360 /*! @} */ 1361 1362 /*! @name PM1_RUCAN - Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn) */ 1363 /*! @{ */ 1364 1365 #define SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1366 #define SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_SHIFT (0U) 1367 #define SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_WIDTH (64U) 1368 #define SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RUCAN_RUCAn_MASK) 1369 /*! @} */ 1370 1371 /*! @name PM1_RMCAN - Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn) */ 1372 /*! @{ */ 1373 1374 #define SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1375 #define SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_SHIFT (0U) 1376 #define SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_WIDTH (64U) 1377 #define SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RMCAN_RMCAn_MASK) 1378 /*! @} */ 1379 1380 /*! @name PM1_RBCAN - Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) */ 1381 /*! @{ */ 1382 1383 #define SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1384 #define SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_SHIFT (0U) 1385 #define SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_WIDTH (64U) 1386 #define SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RBCAN_RBCAn_MASK) 1387 /*! @} */ 1388 1389 /*! @name PM1_RDRPN - Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn) */ 1390 /*! @{ */ 1391 1392 #define SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_MASK (0xFFFFFFFFFFFFFFFFU) 1393 #define SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_SHIFT (0U) 1394 #define SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_WIDTH (64U) 1395 #define SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RDRPN_RDRPn_MASK) 1396 /*! @} */ 1397 1398 /*! @name PM1_RPKTN - Port MAC 1 Receive Packets Counter Register(etherStatsPktsn) */ 1399 /*! @{ */ 1400 1401 #define SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_MASK (0xFFFFFFFFFFFFFFFFU) 1402 #define SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_SHIFT (0U) 1403 #define SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_WIDTH (64U) 1404 #define SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RPKTN_RPKTn_MASK) 1405 /*! @} */ 1406 1407 /*! @name PM1_RUNDN - Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) */ 1408 /*! @{ */ 1409 1410 #define SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_MASK (0xFFFFFFFFFFFFFFFFU) 1411 #define SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_SHIFT (0U) 1412 #define SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_WIDTH (64U) 1413 #define SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RUNDN_RUNDn_MASK) 1414 /*! @} */ 1415 1416 /*! @name PM1_R64N - Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) */ 1417 /*! @{ */ 1418 1419 #define SW_ETH_MAC_PORT0_PM1_R64N_R64n_MASK (0xFFFFFFFFFFFFFFFFU) 1420 #define SW_ETH_MAC_PORT0_PM1_R64N_R64n_SHIFT (0U) 1421 #define SW_ETH_MAC_PORT0_PM1_R64N_R64n_WIDTH (64U) 1422 #define SW_ETH_MAC_PORT0_PM1_R64N_R64n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R64N_R64n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R64N_R64n_MASK) 1423 /*! @} */ 1424 1425 /*! @name PM1_R127N - Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) */ 1426 /*! @{ */ 1427 1428 #define SW_ETH_MAC_PORT0_PM1_R127N_R127n_MASK (0xFFFFFFFFFFFFFFFFU) 1429 #define SW_ETH_MAC_PORT0_PM1_R127N_R127n_SHIFT (0U) 1430 #define SW_ETH_MAC_PORT0_PM1_R127N_R127n_WIDTH (64U) 1431 #define SW_ETH_MAC_PORT0_PM1_R127N_R127n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R127N_R127n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R127N_R127n_MASK) 1432 /*! @} */ 1433 1434 /*! @name PM1_R255N - Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) */ 1435 /*! @{ */ 1436 1437 #define SW_ETH_MAC_PORT0_PM1_R255N_R255n_MASK (0xFFFFFFFFFFFFFFFFU) 1438 #define SW_ETH_MAC_PORT0_PM1_R255N_R255n_SHIFT (0U) 1439 #define SW_ETH_MAC_PORT0_PM1_R255N_R255n_WIDTH (64U) 1440 #define SW_ETH_MAC_PORT0_PM1_R255N_R255n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R255N_R255n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R255N_R255n_MASK) 1441 /*! @} */ 1442 1443 /*! @name PM1_R511N - Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) */ 1444 /*! @{ */ 1445 1446 #define SW_ETH_MAC_PORT0_PM1_R511N_R511n_MASK (0xFFFFFFFFFFFFFFFFU) 1447 #define SW_ETH_MAC_PORT0_PM1_R511N_R511n_SHIFT (0U) 1448 #define SW_ETH_MAC_PORT0_PM1_R511N_R511n_WIDTH (64U) 1449 #define SW_ETH_MAC_PORT0_PM1_R511N_R511n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R511N_R511n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R511N_R511n_MASK) 1450 /*! @} */ 1451 1452 /*! @name PM1_R1023N - Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) */ 1453 /*! @{ */ 1454 1455 #define SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_MASK (0xFFFFFFFFFFFFFFFFU) 1456 #define SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_SHIFT (0U) 1457 #define SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_WIDTH (64U) 1458 #define SW_ETH_MAC_PORT0_PM1_R1023N_R1023n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R1023N_R1023n_MASK) 1459 /*! @} */ 1460 1461 /*! @name PM1_R1522N - Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) */ 1462 /*! @{ */ 1463 1464 #define SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_MASK (0xFFFFFFFFFFFFFFFFU) 1465 #define SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_SHIFT (0U) 1466 #define SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_WIDTH (64U) 1467 #define SW_ETH_MAC_PORT0_PM1_R1522N_R1522n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R1522N_R1522n_MASK) 1468 /*! @} */ 1469 1470 /*! @name PM1_R1523XN - Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) */ 1471 /*! @{ */ 1472 1473 #define SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) 1474 #define SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_SHIFT (0U) 1475 #define SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_WIDTH (64U) 1476 #define SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_R1523XN_R1523Xn_MASK) 1477 /*! @} */ 1478 1479 /*! @name PM1_ROVRN - Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) */ 1480 /*! @{ */ 1481 1482 #define SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_MASK (0xFFFFFFFFFFFFFFFFU) 1483 #define SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_SHIFT (0U) 1484 #define SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_WIDTH (64U) 1485 #define SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_ROVRN_ROVRn_MASK) 1486 /*! @} */ 1487 1488 /*! @name PM1_RJBRN - Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn) */ 1489 /*! @{ */ 1490 1491 #define SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_MASK (0xFFFFFFFFFFFFFFFFU) 1492 #define SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_SHIFT (0U) 1493 #define SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_WIDTH (64U) 1494 #define SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RJBRN_RJBRn_MASK) 1495 /*! @} */ 1496 1497 /*! @name PM1_RFRGN - Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn */ 1498 /*! @{ */ 1499 1500 #define SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_MASK (0xFFFFFFFFFFFFFFFFU) 1501 #define SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_SHIFT (0U) 1502 #define SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_WIDTH (64U) 1503 #define SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RFRGN_RFRGn_MASK) 1504 /*! @} */ 1505 1506 /*! @name PM1_RCNPN - Port MAC 1 Receive Control Packet Counter Register */ 1507 /*! @{ */ 1508 1509 #define SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_MASK (0xFFFFFFFFFFFFFFFFU) 1510 #define SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_SHIFT (0U) 1511 #define SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_WIDTH (64U) 1512 #define SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RCNPN_RCNPn_MASK) 1513 /*! @} */ 1514 1515 /*! @name PM1_RDRNTPN - Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) */ 1516 /*! @{ */ 1517 1518 #define SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_MASK (0xFFFFFFFFFFFFFFFFU) 1519 #define SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_SHIFT (0U) 1520 #define SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_WIDTH (64U) 1521 #define SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_RDRNTPN_RDRNTPn_MASK) 1522 /*! @} */ 1523 1524 /*! @name PM1_TEOCTN - Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn) */ 1525 /*! @{ */ 1526 1527 #define SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 1528 #define SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_SHIFT (0U) 1529 #define SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_WIDTH (64U) 1530 #define SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TEOCTN_TEOCTn_MASK) 1531 /*! @} */ 1532 1533 /*! @name PM1_TOCTN - Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn) */ 1534 /*! @{ */ 1535 1536 #define SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_MASK (0xFFFFFFFFFFFFFFFFU) 1537 #define SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_SHIFT (0U) 1538 #define SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_WIDTH (64U) 1539 #define SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TOCTN_TOCTn_MASK) 1540 /*! @} */ 1541 1542 /*! @name PM1_TXPFN - Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ 1543 /*! @{ */ 1544 1545 #define SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_MASK (0xFFFFFFFFFFFFFFFFU) 1546 #define SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_SHIFT (0U) 1547 #define SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_WIDTH (64U) 1548 #define SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TXPFN_TXPFn_MASK) 1549 /*! @} */ 1550 1551 /*! @name PM1_TFRMN - Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn) */ 1552 /*! @{ */ 1553 1554 #define SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_MASK (0xFFFFFFFFFFFFFFFFU) 1555 #define SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_SHIFT (0U) 1556 #define SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_WIDTH (64U) 1557 #define SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TFRMN_TFRMn_MASK) 1558 /*! @} */ 1559 1560 /*! @name PM1_TFCSN - Port MAC 1 Transmit Frame Check Sequence Error Counter Register() */ 1561 /*! @{ */ 1562 1563 #define SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_MASK (0xFFFFFFFFFFFFFFFFU) 1564 #define SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_SHIFT (0U) 1565 #define SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_WIDTH (64U) 1566 #define SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TFCSN_TFCSn_MASK) 1567 /*! @} */ 1568 1569 /*! @name PM1_TVLANN - Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) */ 1570 /*! @{ */ 1571 1572 #define SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_MASK (0xFFFFFFFFFFFFFFFFU) 1573 #define SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_SHIFT (0U) 1574 #define SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_WIDTH (64U) 1575 #define SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TVLANN_TVLANn_MASK) 1576 /*! @} */ 1577 1578 /*! @name PM1_TERRN - Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn) */ 1579 /*! @{ */ 1580 1581 #define SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_MASK (0xFFFFFFFFFFFFFFFFU) 1582 #define SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_SHIFT (0U) 1583 #define SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_WIDTH (64U) 1584 #define SW_ETH_MAC_PORT0_PM1_TERRN_TERRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TERRN_TERRn_MASK) 1585 /*! @} */ 1586 1587 /*! @name PM1_TUCAN - Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) */ 1588 /*! @{ */ 1589 1590 #define SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1591 #define SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_SHIFT (0U) 1592 #define SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_WIDTH (64U) 1593 #define SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TUCAN_TUCAn_MASK) 1594 /*! @} */ 1595 1596 /*! @name PM1_TMCAN - Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) */ 1597 /*! @{ */ 1598 1599 #define SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1600 #define SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_SHIFT (0U) 1601 #define SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_WIDTH (64U) 1602 #define SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TMCAN_TMCAn_MASK) 1603 /*! @} */ 1604 1605 /*! @name PM1_TBCAN - Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) */ 1606 /*! @{ */ 1607 1608 #define SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_MASK (0xFFFFFFFFFFFFFFFFU) 1609 #define SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_SHIFT (0U) 1610 #define SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_WIDTH (64U) 1611 #define SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TBCAN_TBCAn_MASK) 1612 /*! @} */ 1613 1614 /*! @name PM1_TPKTN - Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn) */ 1615 /*! @{ */ 1616 1617 #define SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_MASK (0xFFFFFFFFFFFFFFFFU) 1618 #define SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_SHIFT (0U) 1619 #define SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_WIDTH (64U) 1620 #define SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TPKTN_TPKTn_MASK) 1621 /*! @} */ 1622 1623 /*! @name PM1_TUNDN - Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) */ 1624 /*! @{ */ 1625 1626 #define SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_MASK (0xFFFFFFFFFFFFFFFFU) 1627 #define SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_SHIFT (0U) 1628 #define SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_WIDTH (64U) 1629 #define SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TUNDN_TUNDn_MASK) 1630 /*! @} */ 1631 1632 /*! @name PM1_T64N - Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) */ 1633 /*! @{ */ 1634 1635 #define SW_ETH_MAC_PORT0_PM1_T64N_T64n_MASK (0xFFFFFFFFFFFFFFFFU) 1636 #define SW_ETH_MAC_PORT0_PM1_T64N_T64n_SHIFT (0U) 1637 #define SW_ETH_MAC_PORT0_PM1_T64N_T64n_WIDTH (64U) 1638 #define SW_ETH_MAC_PORT0_PM1_T64N_T64n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T64N_T64n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T64N_T64n_MASK) 1639 /*! @} */ 1640 1641 /*! @name PM1_T127N - Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) */ 1642 /*! @{ */ 1643 1644 #define SW_ETH_MAC_PORT0_PM1_T127N_T127n_MASK (0xFFFFFFFFFFFFFFFFU) 1645 #define SW_ETH_MAC_PORT0_PM1_T127N_T127n_SHIFT (0U) 1646 #define SW_ETH_MAC_PORT0_PM1_T127N_T127n_WIDTH (64U) 1647 #define SW_ETH_MAC_PORT0_PM1_T127N_T127n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T127N_T127n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T127N_T127n_MASK) 1648 /*! @} */ 1649 1650 /*! @name PM1_T255N - Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) */ 1651 /*! @{ */ 1652 1653 #define SW_ETH_MAC_PORT0_PM1_T255N_T255n_MASK (0xFFFFFFFFFFFFFFFFU) 1654 #define SW_ETH_MAC_PORT0_PM1_T255N_T255n_SHIFT (0U) 1655 #define SW_ETH_MAC_PORT0_PM1_T255N_T255n_WIDTH (64U) 1656 #define SW_ETH_MAC_PORT0_PM1_T255N_T255n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T255N_T255n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T255N_T255n_MASK) 1657 /*! @} */ 1658 1659 /*! @name PM1_T511N - Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) */ 1660 /*! @{ */ 1661 1662 #define SW_ETH_MAC_PORT0_PM1_T511N_T511n_MASK (0xFFFFFFFFFFFFFFFFU) 1663 #define SW_ETH_MAC_PORT0_PM1_T511N_T511n_SHIFT (0U) 1664 #define SW_ETH_MAC_PORT0_PM1_T511N_T511n_WIDTH (64U) 1665 #define SW_ETH_MAC_PORT0_PM1_T511N_T511n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T511N_T511n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T511N_T511n_MASK) 1666 /*! @} */ 1667 1668 /*! @name PM1_T1023N - Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) */ 1669 /*! @{ */ 1670 1671 #define SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_MASK (0xFFFFFFFFFFFFFFFFU) 1672 #define SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_SHIFT (0U) 1673 #define SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_WIDTH (64U) 1674 #define SW_ETH_MAC_PORT0_PM1_T1023N_T1023n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T1023N_T1023n_MASK) 1675 /*! @} */ 1676 1677 /*! @name PM1_T1522N - Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) */ 1678 /*! @{ */ 1679 1680 #define SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_MASK (0xFFFFFFFFFFFFFFFFU) 1681 #define SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_SHIFT (0U) 1682 #define SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_WIDTH (64U) 1683 #define SW_ETH_MAC_PORT0_PM1_T1522N_T1522n(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T1522N_T1522n_MASK) 1684 /*! @} */ 1685 1686 /*! @name PM1_T1523XN - Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) */ 1687 /*! @{ */ 1688 1689 #define SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) 1690 #define SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_SHIFT (0U) 1691 #define SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_WIDTH (64U) 1692 #define SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_T1523XN_T1523Xn_MASK) 1693 /*! @} */ 1694 1695 /*! @name PM1_TCNPN - Port MAC 1 Transmit Control Packet Counter Register */ 1696 /*! @{ */ 1697 1698 #define SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_MASK (0xFFFFFFFFFFFFFFFFU) 1699 #define SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_SHIFT (0U) 1700 #define SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_WIDTH (64U) 1701 #define SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TCNPN_TCNPn_MASK) 1702 /*! @} */ 1703 1704 /*! @name PM1_TDFRN - Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) */ 1705 /*! @{ */ 1706 1707 #define SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_MASK (0xFFFFFFFFFFFFFFFFU) 1708 #define SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_SHIFT (0U) 1709 #define SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_WIDTH (64U) 1710 #define SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TDFRN_TDFRn_MASK) 1711 /*! @} */ 1712 1713 /*! @name PM1_TMCOLN - Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) */ 1714 /*! @{ */ 1715 1716 #define SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 1717 #define SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_SHIFT (0U) 1718 #define SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_WIDTH (64U) 1719 #define SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TMCOLN_TMCOLn_MASK) 1720 /*! @} */ 1721 1722 /*! @name PM1_TSCOLN - Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register */ 1723 /*! @{ */ 1724 1725 #define SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 1726 #define SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_SHIFT (0U) 1727 #define SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_WIDTH (64U) 1728 #define SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TSCOLN_TSCOLn_MASK) 1729 /*! @} */ 1730 1731 /*! @name PM1_TLCOLN - Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register */ 1732 /*! @{ */ 1733 1734 #define SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_MASK (0xFFFFFFFFFFFFFFFFU) 1735 #define SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_SHIFT (0U) 1736 #define SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_WIDTH (64U) 1737 #define SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TLCOLN_TLCOLn_MASK) 1738 /*! @} */ 1739 1740 /*! @name PM1_TECOLN - Port MAC 1 Transmit Excessive Collisions Counter Register */ 1741 /*! @{ */ 1742 1743 #define SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_MASK (0xFFFFFFFFFFFFFFFFU) 1744 #define SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_SHIFT (0U) 1745 #define SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_WIDTH (64U) 1746 #define SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn(x) (((uint64_t)(((uint64_t)(x)) << SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_SHIFT)) & SW_ETH_MAC_PORT0_PM1_TECOLN_TECOLn_MASK) 1747 /*! @} */ 1748 1749 /*! @name PM1_IF_MODE - Port MAC 1 Interface Mode Control Register */ 1750 /*! @{ */ 1751 1752 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_MASK (0x7U) 1753 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_SHIFT (0U) 1754 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_WIDTH (3U) 1755 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_IFMODE_MASK) 1756 1757 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_MASK (0x8U) 1758 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_SHIFT (3U) 1759 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_WIDTH (1U) 1760 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_REVMII_MASK) 1761 1762 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_MASK (0x10U) 1763 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_SHIFT (4U) 1764 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_WIDTH (1U) 1765 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_M10(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_M10_MASK) 1766 1767 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_MASK (0x40U) 1768 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_SHIFT (6U) 1769 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_WIDTH (1U) 1770 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_HD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_HD_MASK) 1771 1772 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SFD_MASK (0x1000U) 1773 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SFD_SHIFT (12U) 1774 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SFD_WIDTH (1U) 1775 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SFD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_SFD_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_SFD_MASK) 1776 1777 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_MASK (0x6000U) 1778 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_SHIFT (13U) 1779 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_WIDTH (2U) 1780 #define SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_SHIFT)) & SW_ETH_MAC_PORT0_PM1_IF_MODE_SSP_MASK) 1781 /*! @} */ 1782 1783 /*! @name MAC_MERGE_MMCSR - Port MAC Merge Control and Status Register */ 1784 /*! @{ */ 1785 1786 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_MASK (0x1U) 1787 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_SHIFT (0U) 1788 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_WIDTH (1U) 1789 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPS_MASK) 1790 1791 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_MASK (0x2U) 1792 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_SHIFT (1U) 1793 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_WIDTH (1U) 1794 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPE_MASK) 1795 1796 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_MASK (0x4U) 1797 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_SHIFT (2U) 1798 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_WIDTH (1U) 1799 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LPA_MASK) 1800 1801 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_MASK (0x18U) 1802 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_SHIFT (3U) 1803 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_WIDTH (2U) 1804 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LAFS_MASK) 1805 1806 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_MASK (0x20U) 1807 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_SHIFT (5U) 1808 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_WIDTH (1U) 1809 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPS_MASK) 1810 1811 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_MASK (0x40U) 1812 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_SHIFT (6U) 1813 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_WIDTH (1U) 1814 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPE_MASK) 1815 1816 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_MASK (0x80U) 1817 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_SHIFT (7U) 1818 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_WIDTH (1U) 1819 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RPA_MASK) 1820 1821 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_MASK (0x300U) 1822 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_SHIFT (8U) 1823 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_WIDTH (2U) 1824 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_RAFS_MASK) 1825 1826 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_MASK (0x18000U) 1827 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_SHIFT (15U) 1828 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_WIDTH (2U) 1829 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_ME_MASK) 1830 1831 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_MASK (0x20000U) 1832 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_SHIFT (17U) 1833 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_WIDTH (1U) 1834 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VDIS_MASK) 1835 1836 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_MASK (0x1C0000U) 1837 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_SHIFT (18U) 1838 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_WIDTH (3U) 1839 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VSTS_MASK) 1840 1841 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_MASK (0x600000U) 1842 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_SHIFT (21U) 1843 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_WIDTH (2U) 1844 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_TXSTS_MASK) 1845 1846 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_MASK (0x3F800000U) 1847 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_SHIFT (23U) 1848 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_WIDTH (7U) 1849 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_VT_MASK) 1850 1851 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_MASK (0x80000000U) 1852 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_SHIFT (31U) 1853 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_WIDTH (1U) 1854 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMCSR_LINK_FAIL_MASK) 1855 /*! @} */ 1856 1857 /*! @name MAC_MERGE_MMFAECR - Port MAC Merge Frame Assembly Error Count Register */ 1858 /*! @{ */ 1859 1860 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_MASK (0xFFFFFFFFU) 1861 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_SHIFT (0U) 1862 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_WIDTH (32U) 1863 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFAECR_MMFAEC_MASK) 1864 /*! @} */ 1865 1866 /*! @name MAC_MERGE_MMFSECR - Port MAC Merge Frame SMD Error Count Register */ 1867 /*! @{ */ 1868 1869 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_MASK (0xFFFFFFFFU) 1870 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_SHIFT (0U) 1871 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_WIDTH (32U) 1872 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFSECR_MMFSEC_MASK) 1873 /*! @} */ 1874 1875 /*! @name MAC_MERGE_MMFAOCR - Port MAC Merge Frame Assembly OK Count Register */ 1876 /*! @{ */ 1877 1878 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_MASK (0xFFFFFFFFU) 1879 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_SHIFT (0U) 1880 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_WIDTH (32U) 1881 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFAOCR_MMFAOC_MASK) 1882 /*! @} */ 1883 1884 /*! @name MAC_MERGE_MMFCRXR - Port MAC Merge Fragment Count RX Register */ 1885 /*! @{ */ 1886 1887 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_MASK (0xFFFFFFFFU) 1888 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_SHIFT (0U) 1889 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_WIDTH (32U) 1890 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFCRXR_MMFCRX_MASK) 1891 /*! @} */ 1892 1893 /*! @name MAC_MERGE_MMFCTXR - Port MAC Merge Fragment Count TX Register */ 1894 /*! @{ */ 1895 1896 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_MASK (0xFFFFFFFFU) 1897 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_SHIFT (0U) 1898 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_WIDTH (32U) 1899 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMFCTXR_MMFCTX_MASK) 1900 /*! @} */ 1901 1902 /*! @name MAC_MERGE_MMHCR - Port MAC Merge Hold Count Register */ 1903 /*! @{ */ 1904 1905 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_MASK (0xFFFFFFFFU) 1906 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_SHIFT (0U) 1907 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_WIDTH (32U) 1908 #define SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_SHIFT)) & SW_ETH_MAC_PORT0_MAC_MERGE_MMHCR_MMHC_MASK) 1909 /*! @} */ 1910 1911 /*! @name PEMDIOCR - Port external MDIO configuration register */ 1912 /*! @{ */ 1913 1914 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_MASK (0x1U) 1915 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_SHIFT (0U) 1916 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_WIDTH (1U) 1917 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY2(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_BSY2_MASK) 1918 1919 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_MASK (0x2U) 1920 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_SHIFT (1U) 1921 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_WIDTH (1U) 1922 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_RD_ER_MASK) 1923 1924 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_MASK (0x1CU) 1925 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_SHIFT (2U) 1926 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_WIDTH (3U) 1927 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_HOLD_MASK) 1928 1929 #define SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_MASK (0x20U) 1930 #define SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_SHIFT (5U) 1931 #define SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_WIDTH (1U) 1932 #define SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_PRE_DIS_MASK) 1933 1934 #define SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_MASK (0x40U) 1935 #define SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_SHIFT (6U) 1936 #define SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_WIDTH (1U) 1937 #define SW_ETH_MAC_PORT0_PEMDIOCR_ENC45(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_ENC45_MASK) 1938 1939 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_MASK (0xFF80U) 1940 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_SHIFT (7U) 1941 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_WIDTH (9U) 1942 #define SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_MDIO_CLK_DIV_MASK) 1943 1944 #define SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_MASK (0x70000U) 1945 #define SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_SHIFT (16U) 1946 #define SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_WIDTH (3U) 1947 #define SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_WHOAMI_MASK) 1948 1949 #define SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_MASK (0x400000U) 1950 #define SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_SHIFT (22U) 1951 #define SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_WIDTH (1U) 1952 #define SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_EHOLD_MASK) 1953 1954 #define SW_ETH_MAC_PORT0_PEMDIOCR_NEG_MASK (0x800000U) 1955 #define SW_ETH_MAC_PORT0_PEMDIOCR_NEG_SHIFT (23U) 1956 #define SW_ETH_MAC_PORT0_PEMDIOCR_NEG_WIDTH (1U) 1957 #define SW_ETH_MAC_PORT0_PEMDIOCR_NEG(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_NEG_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_NEG_MASK) 1958 1959 #define SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_MASK (0x10000000U) 1960 #define SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_SHIFT (28U) 1961 #define SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_WIDTH (1U) 1962 #define SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_ADDR_ERR_MASK) 1963 1964 #define SW_ETH_MAC_PORT0_PEMDIOCR_CIM_MASK (0x20000000U) 1965 #define SW_ETH_MAC_PORT0_PEMDIOCR_CIM_SHIFT (29U) 1966 #define SW_ETH_MAC_PORT0_PEMDIOCR_CIM_WIDTH (1U) 1967 #define SW_ETH_MAC_PORT0_PEMDIOCR_CIM(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_CIM_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_CIM_MASK) 1968 1969 #define SW_ETH_MAC_PORT0_PEMDIOCR_CMP_MASK (0x40000000U) 1970 #define SW_ETH_MAC_PORT0_PEMDIOCR_CMP_SHIFT (30U) 1971 #define SW_ETH_MAC_PORT0_PEMDIOCR_CMP_WIDTH (1U) 1972 #define SW_ETH_MAC_PORT0_PEMDIOCR_CMP(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_CMP_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_CMP_MASK) 1973 1974 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_MASK (0x80000000U) 1975 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_SHIFT (31U) 1976 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_WIDTH (1U) 1977 #define SW_ETH_MAC_PORT0_PEMDIOCR_BSY1(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOCR_BSY1_MASK) 1978 /*! @} */ 1979 1980 /*! @name PEMDIOICR - Port external MDIO interface control register */ 1981 /*! @{ */ 1982 1983 #define SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_MASK (0x1FU) 1984 #define SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_SHIFT (0U) 1985 #define SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_WIDTH (5U) 1986 #define SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_DEV_ADDR_MASK) 1987 1988 #define SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_MASK (0x3E0U) 1989 #define SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_SHIFT (5U) 1990 #define SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_WIDTH (5U) 1991 #define SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_PORT_ADDR_MASK) 1992 1993 #define SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_MASK (0x4000U) 1994 #define SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_SHIFT (14U) 1995 #define SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_WIDTH (1U) 1996 #define SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_POST_INC_MASK) 1997 1998 #define SW_ETH_MAC_PORT0_PEMDIOICR_READ_MASK (0x8000U) 1999 #define SW_ETH_MAC_PORT0_PEMDIOICR_READ_SHIFT (15U) 2000 #define SW_ETH_MAC_PORT0_PEMDIOICR_READ_WIDTH (1U) 2001 #define SW_ETH_MAC_PORT0_PEMDIOICR_READ(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_READ_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_READ_MASK) 2002 2003 #define SW_ETH_MAC_PORT0_PEMDIOICR_BSY_MASK (0x80000000U) 2004 #define SW_ETH_MAC_PORT0_PEMDIOICR_BSY_SHIFT (31U) 2005 #define SW_ETH_MAC_PORT0_PEMDIOICR_BSY_WIDTH (1U) 2006 #define SW_ETH_MAC_PORT0_PEMDIOICR_BSY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOICR_BSY_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOICR_BSY_MASK) 2007 /*! @} */ 2008 2009 /*! @name PEMDIOIDR - Port external MDIO interface data register */ 2010 /*! @{ */ 2011 2012 #define SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_MASK (0xFFFFU) 2013 #define SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_SHIFT (0U) 2014 #define SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_WIDTH (16U) 2015 #define SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOIDR_MDIO_DATA_MASK) 2016 /*! @} */ 2017 2018 /*! @name PEMDIORAR - Port external MDIO register address register */ 2019 /*! @{ */ 2020 2021 #define SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_MASK (0xFFFFU) 2022 #define SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_SHIFT (0U) 2023 #define SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_WIDTH (16U) 2024 #define SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIORAR_REGADDR_MASK) 2025 /*! @} */ 2026 2027 /*! @name PEMDIOSR - Port external MDIO status register */ 2028 /*! @{ */ 2029 2030 #define SW_ETH_MAC_PORT0_PEMDIOSR_BSY_MASK (0x1U) 2031 #define SW_ETH_MAC_PORT0_PEMDIOSR_BSY_SHIFT (0U) 2032 #define SW_ETH_MAC_PORT0_PEMDIOSR_BSY_WIDTH (1U) 2033 #define SW_ETH_MAC_PORT0_PEMDIOSR_BSY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_BSY_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_BSY_MASK) 2034 2035 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_MASK (0x1F00U) 2036 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_SHIFT (8U) 2037 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_WIDTH (5U) 2038 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_MASK) 2039 2040 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_MASK (0x8000U) 2041 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_SHIFT (15U) 2042 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_WIDTH (1U) 2043 #define SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_WHT_LIST_ENA_MASK) 2044 2045 #define SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_MASK (0x70000U) 2046 #define SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_SHIFT (16U) 2047 #define SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_WIDTH (3U) 2048 #define SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_PORT_ID_MASK) 2049 2050 #define SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_MASK (0x80000U) 2051 #define SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_SHIFT (19U) 2052 #define SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_WIDTH (1U) 2053 #define SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_SHIFT)) & SW_ETH_MAC_PORT0_PEMDIOSR_REQ_TYPE_MASK) 2054 /*! @} */ 2055 2056 /*! @name PPSCR - PHY status configuration register */ 2057 /*! @{ */ 2058 2059 #define SW_ETH_MAC_PORT0_PPSCR_BSY_MASK (0x1U) 2060 #define SW_ETH_MAC_PORT0_PPSCR_BSY_SHIFT (0U) 2061 #define SW_ETH_MAC_PORT0_PPSCR_BSY_WIDTH (1U) 2062 #define SW_ETH_MAC_PORT0_PPSCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCR_BSY_SHIFT)) & SW_ETH_MAC_PORT0_PPSCR_BSY_MASK) 2063 2064 #define SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_MASK (0x2U) 2065 #define SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_SHIFT (1U) 2066 #define SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_WIDTH (1U) 2067 #define SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_SHIFT)) & SW_ETH_MAC_PORT0_PPSCR_MDIO_RD_ER_MASK) 2068 2069 #define SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_MASK (0xFFFF0000U) 2070 #define SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_SHIFT (16U) 2071 #define SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_WIDTH (16U) 2072 #define SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_SHIFT)) & SW_ETH_MAC_PORT0_PPSCR_STATUS_INTERVAL_MASK) 2073 /*! @} */ 2074 2075 /*! @name PPSCTRLR - Port PHY status control register */ 2076 /*! @{ */ 2077 2078 #define SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_MASK (0x1FU) 2079 #define SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_SHIFT (0U) 2080 #define SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_WIDTH (5U) 2081 #define SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_SHIFT)) & SW_ETH_MAC_PORT0_PPSCTRLR_DEV_ADDR_MASK) 2082 2083 #define SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_MASK (0x3E0U) 2084 #define SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_SHIFT (5U) 2085 #define SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_WIDTH (5U) 2086 #define SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_SHIFT)) & SW_ETH_MAC_PORT0_PPSCTRLR_PORT_ADDR_MASK) 2087 /*! @} */ 2088 2089 /*! @name PPSDR - Port PHY status data register */ 2090 /*! @{ */ 2091 2092 #define SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_MASK (0xFFFFU) 2093 #define SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_SHIFT (0U) 2094 #define SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_WIDTH (16U) 2095 #define SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_SHIFT)) & SW_ETH_MAC_PORT0_PPSDR_MDIO_DATA_MASK) 2096 2097 #define SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_MASK (0xFFFF0000U) 2098 #define SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_SHIFT (16U) 2099 #define SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_WIDTH (16U) 2100 #define SW_ETH_MAC_PORT0_PPSDR_CURR_CNT(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_SHIFT)) & SW_ETH_MAC_PORT0_PPSDR_CURR_CNT_MASK) 2101 /*! @} */ 2102 2103 /*! @name PPSRAR - Port PHY status register address register */ 2104 /*! @{ */ 2105 2106 #define SW_ETH_MAC_PORT0_PPSRAR_REGADDR_MASK (0xFFFFU) 2107 #define SW_ETH_MAC_PORT0_PPSRAR_REGADDR_SHIFT (0U) 2108 #define SW_ETH_MAC_PORT0_PPSRAR_REGADDR_WIDTH (16U) 2109 #define SW_ETH_MAC_PORT0_PPSRAR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSRAR_REGADDR_SHIFT)) & SW_ETH_MAC_PORT0_PPSRAR_REGADDR_MASK) 2110 /*! @} */ 2111 2112 /*! @name PPSER - Port PHY status event register */ 2113 /*! @{ */ 2114 2115 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_MASK (0xFFFFU) 2116 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_SHIFT (0U) 2117 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_WIDTH (16U) 2118 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_SHIFT)) & SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_HL_MASK) 2119 2120 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_MASK (0xFFFF0000U) 2121 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_SHIFT (16U) 2122 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_WIDTH (16U) 2123 #define SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_SHIFT)) & SW_ETH_MAC_PORT0_PPSER_STATUS_EVENT_LH_MASK) 2124 /*! @} */ 2125 2126 /*! @name PPSMR - Port PHY status mask register */ 2127 /*! @{ */ 2128 2129 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_MASK (0xFFFFU) 2130 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_SHIFT (0U) 2131 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_WIDTH (16U) 2132 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_SHIFT)) & SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_HL_MASK) 2133 2134 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_MASK (0xFFFF0000U) 2135 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_SHIFT (16U) 2136 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_WIDTH (16U) 2137 #define SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH(x) (((uint32_t)(((uint32_t)(x)) << SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_SHIFT)) & SW_ETH_MAC_PORT0_PPSMR_STATUS_MASK_LH_MASK) 2138 /*! @} */ 2139 2140 /*! 2141 * @} 2142 */ /* end of group SW_ETH_MAC_PORT0_Register_Masks */ 2143 2144 /*! 2145 * @} 2146 */ /* end of group SW_ETH_MAC_PORT0_Peripheral_Access_Layer */ 2147 2148 #endif /* #if !defined(S32Z2_SW_ETH_MAC_PORT0_H_) */ 2149
