1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_LPUART.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_LPUART 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_LPUART_H_) /* Check if memory map has not been already included */ 58 #define S32K344_LPUART_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPUART Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPUART - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ 76 __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ 77 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ 78 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ 79 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ 80 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ 81 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ 82 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ 83 __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ 84 __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ 85 __I uint32_t DATARO; /**< Data read-only Register, offset: 0x30 */ 86 } LPUART_Type, *LPUART_MemMapPtr; 87 88 /** Number of instances of the LPUART module. */ 89 #define LPUART_INSTANCE_COUNT (16u) 90 91 /* LPUART - Peripheral instance base addresses */ 92 /** Peripheral LPUART_0 base address */ 93 #define IP_LPUART_0_BASE (0x40328000u) 94 /** Peripheral LPUART_0 base pointer */ 95 #define IP_LPUART_0 ((LPUART_Type *)IP_LPUART_0_BASE) 96 /** Peripheral LPUART_1 base address */ 97 #define IP_LPUART_1_BASE (0x4032C000u) 98 /** Peripheral LPUART_1 base pointer */ 99 #define IP_LPUART_1 ((LPUART_Type *)IP_LPUART_1_BASE) 100 /** Peripheral LPUART_2 base address */ 101 #define IP_LPUART_2_BASE (0x40330000u) 102 /** Peripheral LPUART_2 base pointer */ 103 #define IP_LPUART_2 ((LPUART_Type *)IP_LPUART_2_BASE) 104 /** Peripheral LPUART_3 base address */ 105 #define IP_LPUART_3_BASE (0x40334000u) 106 /** Peripheral LPUART_3 base pointer */ 107 #define IP_LPUART_3 ((LPUART_Type *)IP_LPUART_3_BASE) 108 /** Peripheral LPUART_4 base address */ 109 #define IP_LPUART_4_BASE (0x40338000u) 110 /** Peripheral LPUART_4 base pointer */ 111 #define IP_LPUART_4 ((LPUART_Type *)IP_LPUART_4_BASE) 112 /** Peripheral LPUART_5 base address */ 113 #define IP_LPUART_5_BASE (0x4033C000u) 114 /** Peripheral LPUART_5 base pointer */ 115 #define IP_LPUART_5 ((LPUART_Type *)IP_LPUART_5_BASE) 116 /** Peripheral LPUART_6 base address */ 117 #define IP_LPUART_6_BASE (0x40340000u) 118 /** Peripheral LPUART_6 base pointer */ 119 #define IP_LPUART_6 ((LPUART_Type *)IP_LPUART_6_BASE) 120 /** Peripheral LPUART_7 base address */ 121 #define IP_LPUART_7_BASE (0x40344000u) 122 /** Peripheral LPUART_7 base pointer */ 123 #define IP_LPUART_7 ((LPUART_Type *)IP_LPUART_7_BASE) 124 /** Peripheral LPUART_8 base address */ 125 #define IP_LPUART_8_BASE (0x4048C000u) 126 /** Peripheral LPUART_8 base pointer */ 127 #define IP_LPUART_8 ((LPUART_Type *)IP_LPUART_8_BASE) 128 /** Peripheral LPUART_9 base address */ 129 #define IP_LPUART_9_BASE (0x40490000u) 130 /** Peripheral LPUART_9 base pointer */ 131 #define IP_LPUART_9 ((LPUART_Type *)IP_LPUART_9_BASE) 132 /** Peripheral LPUART_10 base address */ 133 #define IP_LPUART_10_BASE (0x40494000u) 134 /** Peripheral LPUART_10 base pointer */ 135 #define IP_LPUART_10 ((LPUART_Type *)IP_LPUART_10_BASE) 136 /** Peripheral LPUART_11 base address */ 137 #define IP_LPUART_11_BASE (0x40498000u) 138 /** Peripheral LPUART_11 base pointer */ 139 #define IP_LPUART_11 ((LPUART_Type *)IP_LPUART_11_BASE) 140 /** Peripheral LPUART_12 base address */ 141 #define IP_LPUART_12_BASE (0x4049C000u) 142 /** Peripheral LPUART_12 base pointer */ 143 #define IP_LPUART_12 ((LPUART_Type *)IP_LPUART_12_BASE) 144 /** Peripheral LPUART_13 base address */ 145 #define IP_LPUART_13_BASE (0x404A0000u) 146 /** Peripheral LPUART_13 base pointer */ 147 #define IP_LPUART_13 ((LPUART_Type *)IP_LPUART_13_BASE) 148 /** Peripheral LPUART_14 base address */ 149 #define IP_LPUART_14_BASE (0x404A4000u) 150 /** Peripheral LPUART_14 base pointer */ 151 #define IP_LPUART_14 ((LPUART_Type *)IP_LPUART_14_BASE) 152 /** Peripheral LPUART_15 base address */ 153 #define IP_LPUART_15_BASE (0x404A8000u) 154 /** Peripheral LPUART_15 base pointer */ 155 #define IP_LPUART_15 ((LPUART_Type *)IP_LPUART_15_BASE) 156 /** Array initializer of LPUART peripheral base addresses */ 157 #define IP_LPUART_BASE_ADDRS { IP_LPUART_0_BASE, IP_LPUART_1_BASE, IP_LPUART_2_BASE, IP_LPUART_3_BASE, IP_LPUART_4_BASE, IP_LPUART_5_BASE, IP_LPUART_6_BASE, IP_LPUART_7_BASE, IP_LPUART_8_BASE, IP_LPUART_9_BASE, IP_LPUART_10_BASE, IP_LPUART_11_BASE, IP_LPUART_12_BASE, IP_LPUART_13_BASE, IP_LPUART_14_BASE, IP_LPUART_15_BASE } 158 /** Array initializer of LPUART peripheral base pointers */ 159 #define IP_LPUART_BASE_PTRS { IP_LPUART_0, IP_LPUART_1, IP_LPUART_2, IP_LPUART_3, IP_LPUART_4, IP_LPUART_5, IP_LPUART_6, IP_LPUART_7, IP_LPUART_8, IP_LPUART_9, IP_LPUART_10, IP_LPUART_11, IP_LPUART_12, IP_LPUART_13, IP_LPUART_14, IP_LPUART_15 } 160 161 /* ---------------------------------------------------------------------------- 162 -- LPUART Register Masks 163 ---------------------------------------------------------------------------- */ 164 165 /*! 166 * @addtogroup LPUART_Register_Masks LPUART Register Masks 167 * @{ 168 */ 169 170 /*! @name VERID - Version ID Register */ 171 /*! @{ */ 172 173 #define LPUART_VERID_FEATURE_MASK (0xFFFFU) 174 #define LPUART_VERID_FEATURE_SHIFT (0U) 175 #define LPUART_VERID_FEATURE_WIDTH (16U) 176 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) 177 178 #define LPUART_VERID_MINOR_MASK (0xFF0000U) 179 #define LPUART_VERID_MINOR_SHIFT (16U) 180 #define LPUART_VERID_MINOR_WIDTH (8U) 181 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) 182 183 #define LPUART_VERID_MAJOR_MASK (0xFF000000U) 184 #define LPUART_VERID_MAJOR_SHIFT (24U) 185 #define LPUART_VERID_MAJOR_WIDTH (8U) 186 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) 187 /*! @} */ 188 189 /*! @name PARAM - Parameter Register */ 190 /*! @{ */ 191 192 #define LPUART_PARAM_TXFIFO_MASK (0xFFU) 193 #define LPUART_PARAM_TXFIFO_SHIFT (0U) 194 #define LPUART_PARAM_TXFIFO_WIDTH (8U) 195 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) 196 197 #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) 198 #define LPUART_PARAM_RXFIFO_SHIFT (8U) 199 #define LPUART_PARAM_RXFIFO_WIDTH (8U) 200 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) 201 /*! @} */ 202 203 /*! @name GLOBAL - LPUART Global Register */ 204 /*! @{ */ 205 206 #define LPUART_GLOBAL_RST_MASK (0x2U) 207 #define LPUART_GLOBAL_RST_SHIFT (1U) 208 #define LPUART_GLOBAL_RST_WIDTH (1U) 209 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) 210 /*! @} */ 211 212 /*! @name PINCFG - LPUART Pin Configuration Register */ 213 /*! @{ */ 214 215 #define LPUART_PINCFG_TRGSEL_MASK (0x3U) 216 #define LPUART_PINCFG_TRGSEL_SHIFT (0U) 217 #define LPUART_PINCFG_TRGSEL_WIDTH (2U) 218 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) 219 /*! @} */ 220 221 /*! @name BAUD - LPUART Baud Rate Register */ 222 /*! @{ */ 223 224 #define LPUART_BAUD_SBR_MASK (0x1FFFU) 225 #define LPUART_BAUD_SBR_SHIFT (0U) 226 #define LPUART_BAUD_SBR_WIDTH (13U) 227 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) 228 229 #define LPUART_BAUD_SBNS_MASK (0x2000U) 230 #define LPUART_BAUD_SBNS_SHIFT (13U) 231 #define LPUART_BAUD_SBNS_WIDTH (1U) 232 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) 233 234 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) 235 #define LPUART_BAUD_RXEDGIE_SHIFT (14U) 236 #define LPUART_BAUD_RXEDGIE_WIDTH (1U) 237 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) 238 239 #define LPUART_BAUD_LBKDIE_MASK (0x8000U) 240 #define LPUART_BAUD_LBKDIE_SHIFT (15U) 241 #define LPUART_BAUD_LBKDIE_WIDTH (1U) 242 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) 243 244 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) 245 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) 246 #define LPUART_BAUD_RESYNCDIS_WIDTH (1U) 247 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) 248 249 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) 250 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) 251 #define LPUART_BAUD_BOTHEDGE_WIDTH (1U) 252 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) 253 254 #define LPUART_BAUD_MATCFG_MASK (0xC0000U) 255 #define LPUART_BAUD_MATCFG_SHIFT (18U) 256 #define LPUART_BAUD_MATCFG_WIDTH (2U) 257 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) 258 259 #define LPUART_BAUD_RDMAE_MASK (0x200000U) 260 #define LPUART_BAUD_RDMAE_SHIFT (21U) 261 #define LPUART_BAUD_RDMAE_WIDTH (1U) 262 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) 263 264 #define LPUART_BAUD_TDMAE_MASK (0x800000U) 265 #define LPUART_BAUD_TDMAE_SHIFT (23U) 266 #define LPUART_BAUD_TDMAE_WIDTH (1U) 267 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) 268 269 #define LPUART_BAUD_OSR_MASK (0x1F000000U) 270 #define LPUART_BAUD_OSR_SHIFT (24U) 271 #define LPUART_BAUD_OSR_WIDTH (5U) 272 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) 273 274 #define LPUART_BAUD_M10_MASK (0x20000000U) 275 #define LPUART_BAUD_M10_SHIFT (29U) 276 #define LPUART_BAUD_M10_WIDTH (1U) 277 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) 278 279 #define LPUART_BAUD_MAEN2_MASK (0x40000000U) 280 #define LPUART_BAUD_MAEN2_SHIFT (30U) 281 #define LPUART_BAUD_MAEN2_WIDTH (1U) 282 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) 283 284 #define LPUART_BAUD_MAEN1_MASK (0x80000000U) 285 #define LPUART_BAUD_MAEN1_SHIFT (31U) 286 #define LPUART_BAUD_MAEN1_WIDTH (1U) 287 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) 288 /*! @} */ 289 290 /*! @name STAT - LPUART Status Register */ 291 /*! @{ */ 292 293 #define LPUART_STAT_LBKFE_MASK (0x1U) 294 #define LPUART_STAT_LBKFE_SHIFT (0U) 295 #define LPUART_STAT_LBKFE_WIDTH (1U) 296 #define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) 297 298 #define LPUART_STAT_AME_MASK (0x2U) 299 #define LPUART_STAT_AME_SHIFT (1U) 300 #define LPUART_STAT_AME_WIDTH (1U) 301 #define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) 302 303 #define LPUART_STAT_MA2F_MASK (0x4000U) 304 #define LPUART_STAT_MA2F_SHIFT (14U) 305 #define LPUART_STAT_MA2F_WIDTH (1U) 306 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) 307 308 #define LPUART_STAT_MA1F_MASK (0x8000U) 309 #define LPUART_STAT_MA1F_SHIFT (15U) 310 #define LPUART_STAT_MA1F_WIDTH (1U) 311 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) 312 313 #define LPUART_STAT_PF_MASK (0x10000U) 314 #define LPUART_STAT_PF_SHIFT (16U) 315 #define LPUART_STAT_PF_WIDTH (1U) 316 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) 317 318 #define LPUART_STAT_FE_MASK (0x20000U) 319 #define LPUART_STAT_FE_SHIFT (17U) 320 #define LPUART_STAT_FE_WIDTH (1U) 321 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) 322 323 #define LPUART_STAT_NF_MASK (0x40000U) 324 #define LPUART_STAT_NF_SHIFT (18U) 325 #define LPUART_STAT_NF_WIDTH (1U) 326 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) 327 328 #define LPUART_STAT_OR_MASK (0x80000U) 329 #define LPUART_STAT_OR_SHIFT (19U) 330 #define LPUART_STAT_OR_WIDTH (1U) 331 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) 332 333 #define LPUART_STAT_IDLE_MASK (0x100000U) 334 #define LPUART_STAT_IDLE_SHIFT (20U) 335 #define LPUART_STAT_IDLE_WIDTH (1U) 336 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) 337 338 #define LPUART_STAT_RDRF_MASK (0x200000U) 339 #define LPUART_STAT_RDRF_SHIFT (21U) 340 #define LPUART_STAT_RDRF_WIDTH (1U) 341 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) 342 343 #define LPUART_STAT_TC_MASK (0x400000U) 344 #define LPUART_STAT_TC_SHIFT (22U) 345 #define LPUART_STAT_TC_WIDTH (1U) 346 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) 347 348 #define LPUART_STAT_TDRE_MASK (0x800000U) 349 #define LPUART_STAT_TDRE_SHIFT (23U) 350 #define LPUART_STAT_TDRE_WIDTH (1U) 351 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) 352 353 #define LPUART_STAT_RAF_MASK (0x1000000U) 354 #define LPUART_STAT_RAF_SHIFT (24U) 355 #define LPUART_STAT_RAF_WIDTH (1U) 356 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) 357 358 #define LPUART_STAT_LBKDE_MASK (0x2000000U) 359 #define LPUART_STAT_LBKDE_SHIFT (25U) 360 #define LPUART_STAT_LBKDE_WIDTH (1U) 361 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) 362 363 #define LPUART_STAT_BRK13_MASK (0x4000000U) 364 #define LPUART_STAT_BRK13_SHIFT (26U) 365 #define LPUART_STAT_BRK13_WIDTH (1U) 366 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) 367 368 #define LPUART_STAT_RWUID_MASK (0x8000000U) 369 #define LPUART_STAT_RWUID_SHIFT (27U) 370 #define LPUART_STAT_RWUID_WIDTH (1U) 371 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) 372 373 #define LPUART_STAT_RXINV_MASK (0x10000000U) 374 #define LPUART_STAT_RXINV_SHIFT (28U) 375 #define LPUART_STAT_RXINV_WIDTH (1U) 376 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) 377 378 #define LPUART_STAT_MSBF_MASK (0x20000000U) 379 #define LPUART_STAT_MSBF_SHIFT (29U) 380 #define LPUART_STAT_MSBF_WIDTH (1U) 381 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) 382 383 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) 384 #define LPUART_STAT_RXEDGIF_SHIFT (30U) 385 #define LPUART_STAT_RXEDGIF_WIDTH (1U) 386 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) 387 388 #define LPUART_STAT_LBKDIF_MASK (0x80000000U) 389 #define LPUART_STAT_LBKDIF_SHIFT (31U) 390 #define LPUART_STAT_LBKDIF_WIDTH (1U) 391 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) 392 /*! @} */ 393 394 /*! @name CTRL - LPUART Control Register */ 395 /*! @{ */ 396 397 #define LPUART_CTRL_PT_MASK (0x1U) 398 #define LPUART_CTRL_PT_SHIFT (0U) 399 #define LPUART_CTRL_PT_WIDTH (1U) 400 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) 401 402 #define LPUART_CTRL_PE_MASK (0x2U) 403 #define LPUART_CTRL_PE_SHIFT (1U) 404 #define LPUART_CTRL_PE_WIDTH (1U) 405 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) 406 407 #define LPUART_CTRL_ILT_MASK (0x4U) 408 #define LPUART_CTRL_ILT_SHIFT (2U) 409 #define LPUART_CTRL_ILT_WIDTH (1U) 410 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) 411 412 #define LPUART_CTRL_WAKE_MASK (0x8U) 413 #define LPUART_CTRL_WAKE_SHIFT (3U) 414 #define LPUART_CTRL_WAKE_WIDTH (1U) 415 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) 416 417 #define LPUART_CTRL_M_MASK (0x10U) 418 #define LPUART_CTRL_M_SHIFT (4U) 419 #define LPUART_CTRL_M_WIDTH (1U) 420 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) 421 422 #define LPUART_CTRL_RSRC_MASK (0x20U) 423 #define LPUART_CTRL_RSRC_SHIFT (5U) 424 #define LPUART_CTRL_RSRC_WIDTH (1U) 425 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) 426 427 #define LPUART_CTRL_DOZEEN_MASK (0x40U) 428 #define LPUART_CTRL_DOZEEN_SHIFT (6U) 429 #define LPUART_CTRL_DOZEEN_WIDTH (1U) 430 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) 431 432 #define LPUART_CTRL_LOOPS_MASK (0x80U) 433 #define LPUART_CTRL_LOOPS_SHIFT (7U) 434 #define LPUART_CTRL_LOOPS_WIDTH (1U) 435 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) 436 437 #define LPUART_CTRL_IDLECFG_MASK (0x700U) 438 #define LPUART_CTRL_IDLECFG_SHIFT (8U) 439 #define LPUART_CTRL_IDLECFG_WIDTH (3U) 440 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) 441 442 #define LPUART_CTRL_M7_MASK (0x800U) 443 #define LPUART_CTRL_M7_SHIFT (11U) 444 #define LPUART_CTRL_M7_WIDTH (1U) 445 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) 446 447 #define LPUART_CTRL_MA2IE_MASK (0x4000U) 448 #define LPUART_CTRL_MA2IE_SHIFT (14U) 449 #define LPUART_CTRL_MA2IE_WIDTH (1U) 450 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) 451 452 #define LPUART_CTRL_MA1IE_MASK (0x8000U) 453 #define LPUART_CTRL_MA1IE_SHIFT (15U) 454 #define LPUART_CTRL_MA1IE_WIDTH (1U) 455 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) 456 457 #define LPUART_CTRL_SBK_MASK (0x10000U) 458 #define LPUART_CTRL_SBK_SHIFT (16U) 459 #define LPUART_CTRL_SBK_WIDTH (1U) 460 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) 461 462 #define LPUART_CTRL_RWU_MASK (0x20000U) 463 #define LPUART_CTRL_RWU_SHIFT (17U) 464 #define LPUART_CTRL_RWU_WIDTH (1U) 465 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) 466 467 #define LPUART_CTRL_RE_MASK (0x40000U) 468 #define LPUART_CTRL_RE_SHIFT (18U) 469 #define LPUART_CTRL_RE_WIDTH (1U) 470 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) 471 472 #define LPUART_CTRL_TE_MASK (0x80000U) 473 #define LPUART_CTRL_TE_SHIFT (19U) 474 #define LPUART_CTRL_TE_WIDTH (1U) 475 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) 476 477 #define LPUART_CTRL_ILIE_MASK (0x100000U) 478 #define LPUART_CTRL_ILIE_SHIFT (20U) 479 #define LPUART_CTRL_ILIE_WIDTH (1U) 480 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) 481 482 #define LPUART_CTRL_RIE_MASK (0x200000U) 483 #define LPUART_CTRL_RIE_SHIFT (21U) 484 #define LPUART_CTRL_RIE_WIDTH (1U) 485 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) 486 487 #define LPUART_CTRL_TCIE_MASK (0x400000U) 488 #define LPUART_CTRL_TCIE_SHIFT (22U) 489 #define LPUART_CTRL_TCIE_WIDTH (1U) 490 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) 491 492 #define LPUART_CTRL_TIE_MASK (0x800000U) 493 #define LPUART_CTRL_TIE_SHIFT (23U) 494 #define LPUART_CTRL_TIE_WIDTH (1U) 495 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) 496 497 #define LPUART_CTRL_PEIE_MASK (0x1000000U) 498 #define LPUART_CTRL_PEIE_SHIFT (24U) 499 #define LPUART_CTRL_PEIE_WIDTH (1U) 500 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) 501 502 #define LPUART_CTRL_FEIE_MASK (0x2000000U) 503 #define LPUART_CTRL_FEIE_SHIFT (25U) 504 #define LPUART_CTRL_FEIE_WIDTH (1U) 505 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) 506 507 #define LPUART_CTRL_NEIE_MASK (0x4000000U) 508 #define LPUART_CTRL_NEIE_SHIFT (26U) 509 #define LPUART_CTRL_NEIE_WIDTH (1U) 510 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) 511 512 #define LPUART_CTRL_ORIE_MASK (0x8000000U) 513 #define LPUART_CTRL_ORIE_SHIFT (27U) 514 #define LPUART_CTRL_ORIE_WIDTH (1U) 515 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) 516 517 #define LPUART_CTRL_TXINV_MASK (0x10000000U) 518 #define LPUART_CTRL_TXINV_SHIFT (28U) 519 #define LPUART_CTRL_TXINV_WIDTH (1U) 520 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) 521 522 #define LPUART_CTRL_TXDIR_MASK (0x20000000U) 523 #define LPUART_CTRL_TXDIR_SHIFT (29U) 524 #define LPUART_CTRL_TXDIR_WIDTH (1U) 525 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) 526 527 #define LPUART_CTRL_R9T8_MASK (0x40000000U) 528 #define LPUART_CTRL_R9T8_SHIFT (30U) 529 #define LPUART_CTRL_R9T8_WIDTH (1U) 530 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) 531 532 #define LPUART_CTRL_R8T9_MASK (0x80000000U) 533 #define LPUART_CTRL_R8T9_SHIFT (31U) 534 #define LPUART_CTRL_R8T9_WIDTH (1U) 535 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) 536 /*! @} */ 537 538 /*! @name DATA - LPUART Data Register */ 539 /*! @{ */ 540 541 #define LPUART_DATA_R0T0_MASK (0x1U) 542 #define LPUART_DATA_R0T0_SHIFT (0U) 543 #define LPUART_DATA_R0T0_WIDTH (1U) 544 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) 545 546 #define LPUART_DATA_R1T1_MASK (0x2U) 547 #define LPUART_DATA_R1T1_SHIFT (1U) 548 #define LPUART_DATA_R1T1_WIDTH (1U) 549 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) 550 551 #define LPUART_DATA_R2T2_MASK (0x4U) 552 #define LPUART_DATA_R2T2_SHIFT (2U) 553 #define LPUART_DATA_R2T2_WIDTH (1U) 554 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) 555 556 #define LPUART_DATA_R3T3_MASK (0x8U) 557 #define LPUART_DATA_R3T3_SHIFT (3U) 558 #define LPUART_DATA_R3T3_WIDTH (1U) 559 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) 560 561 #define LPUART_DATA_R4T4_MASK (0x10U) 562 #define LPUART_DATA_R4T4_SHIFT (4U) 563 #define LPUART_DATA_R4T4_WIDTH (1U) 564 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) 565 566 #define LPUART_DATA_R5T5_MASK (0x20U) 567 #define LPUART_DATA_R5T5_SHIFT (5U) 568 #define LPUART_DATA_R5T5_WIDTH (1U) 569 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) 570 571 #define LPUART_DATA_R6T6_MASK (0x40U) 572 #define LPUART_DATA_R6T6_SHIFT (6U) 573 #define LPUART_DATA_R6T6_WIDTH (1U) 574 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) 575 576 #define LPUART_DATA_R7T7_MASK (0x80U) 577 #define LPUART_DATA_R7T7_SHIFT (7U) 578 #define LPUART_DATA_R7T7_WIDTH (1U) 579 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) 580 581 #define LPUART_DATA_R8T8_MASK (0x100U) 582 #define LPUART_DATA_R8T8_SHIFT (8U) 583 #define LPUART_DATA_R8T8_WIDTH (1U) 584 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) 585 586 #define LPUART_DATA_R9T9_MASK (0x200U) 587 #define LPUART_DATA_R9T9_SHIFT (9U) 588 #define LPUART_DATA_R9T9_WIDTH (1U) 589 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) 590 591 #define LPUART_DATA_LINBRK_MASK (0x400U) 592 #define LPUART_DATA_LINBRK_SHIFT (10U) 593 #define LPUART_DATA_LINBRK_WIDTH (1U) 594 #define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) 595 596 #define LPUART_DATA_IDLINE_MASK (0x800U) 597 #define LPUART_DATA_IDLINE_SHIFT (11U) 598 #define LPUART_DATA_IDLINE_WIDTH (1U) 599 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) 600 601 #define LPUART_DATA_RXEMPT_MASK (0x1000U) 602 #define LPUART_DATA_RXEMPT_SHIFT (12U) 603 #define LPUART_DATA_RXEMPT_WIDTH (1U) 604 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) 605 606 #define LPUART_DATA_FRETSC_MASK (0x2000U) 607 #define LPUART_DATA_FRETSC_SHIFT (13U) 608 #define LPUART_DATA_FRETSC_WIDTH (1U) 609 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) 610 611 #define LPUART_DATA_PARITYE_MASK (0x4000U) 612 #define LPUART_DATA_PARITYE_SHIFT (14U) 613 #define LPUART_DATA_PARITYE_WIDTH (1U) 614 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) 615 616 #define LPUART_DATA_NOISY_MASK (0x8000U) 617 #define LPUART_DATA_NOISY_SHIFT (15U) 618 #define LPUART_DATA_NOISY_WIDTH (1U) 619 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) 620 /*! @} */ 621 622 /*! @name MATCH - LPUART Match Address Register */ 623 /*! @{ */ 624 625 #define LPUART_MATCH_MA1_MASK (0x3FFU) 626 #define LPUART_MATCH_MA1_SHIFT (0U) 627 #define LPUART_MATCH_MA1_WIDTH (10U) 628 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) 629 630 #define LPUART_MATCH_MA2_MASK (0x3FF0000U) 631 #define LPUART_MATCH_MA2_SHIFT (16U) 632 #define LPUART_MATCH_MA2_WIDTH (10U) 633 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) 634 /*! @} */ 635 636 /*! @name MODIR - LPUART Modem IrDA Register */ 637 /*! @{ */ 638 639 #define LPUART_MODIR_TXCTSE_MASK (0x1U) 640 #define LPUART_MODIR_TXCTSE_SHIFT (0U) 641 #define LPUART_MODIR_TXCTSE_WIDTH (1U) 642 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) 643 644 #define LPUART_MODIR_TXRTSE_MASK (0x2U) 645 #define LPUART_MODIR_TXRTSE_SHIFT (1U) 646 #define LPUART_MODIR_TXRTSE_WIDTH (1U) 647 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) 648 649 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) 650 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) 651 #define LPUART_MODIR_TXRTSPOL_WIDTH (1U) 652 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) 653 654 #define LPUART_MODIR_RXRTSE_MASK (0x8U) 655 #define LPUART_MODIR_RXRTSE_SHIFT (3U) 656 #define LPUART_MODIR_RXRTSE_WIDTH (1U) 657 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) 658 659 #define LPUART_MODIR_TXCTSC_MASK (0x10U) 660 #define LPUART_MODIR_TXCTSC_SHIFT (4U) 661 #define LPUART_MODIR_TXCTSC_WIDTH (1U) 662 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) 663 664 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) 665 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) 666 #define LPUART_MODIR_TXCTSSRC_WIDTH (1U) 667 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) 668 669 #define LPUART_MODIR_RTSWATER_MASK (0x300U) 670 #define LPUART_MODIR_RTSWATER_SHIFT (8U) 671 #define LPUART_MODIR_RTSWATER_WIDTH (2U) 672 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) 673 674 #define LPUART_MODIR_TNP_MASK (0x30000U) 675 #define LPUART_MODIR_TNP_SHIFT (16U) 676 #define LPUART_MODIR_TNP_WIDTH (2U) 677 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) 678 679 #define LPUART_MODIR_IREN_MASK (0x40000U) 680 #define LPUART_MODIR_IREN_SHIFT (18U) 681 #define LPUART_MODIR_IREN_WIDTH (1U) 682 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) 683 /*! @} */ 684 685 /*! @name FIFO - LPUART FIFO Register */ 686 /*! @{ */ 687 688 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) 689 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) 690 #define LPUART_FIFO_RXFIFOSIZE_WIDTH (3U) 691 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) 692 693 #define LPUART_FIFO_RXFE_MASK (0x8U) 694 #define LPUART_FIFO_RXFE_SHIFT (3U) 695 #define LPUART_FIFO_RXFE_WIDTH (1U) 696 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) 697 698 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) 699 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) 700 #define LPUART_FIFO_TXFIFOSIZE_WIDTH (3U) 701 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) 702 703 #define LPUART_FIFO_TXFE_MASK (0x80U) 704 #define LPUART_FIFO_TXFE_SHIFT (7U) 705 #define LPUART_FIFO_TXFE_WIDTH (1U) 706 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) 707 708 #define LPUART_FIFO_RXUFE_MASK (0x100U) 709 #define LPUART_FIFO_RXUFE_SHIFT (8U) 710 #define LPUART_FIFO_RXUFE_WIDTH (1U) 711 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) 712 713 #define LPUART_FIFO_TXOFE_MASK (0x200U) 714 #define LPUART_FIFO_TXOFE_SHIFT (9U) 715 #define LPUART_FIFO_TXOFE_WIDTH (1U) 716 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) 717 718 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) 719 #define LPUART_FIFO_RXIDEN_SHIFT (10U) 720 #define LPUART_FIFO_RXIDEN_WIDTH (3U) 721 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) 722 723 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) 724 #define LPUART_FIFO_RXFLUSH_SHIFT (14U) 725 #define LPUART_FIFO_RXFLUSH_WIDTH (1U) 726 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) 727 728 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) 729 #define LPUART_FIFO_TXFLUSH_SHIFT (15U) 730 #define LPUART_FIFO_TXFLUSH_WIDTH (1U) 731 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) 732 733 #define LPUART_FIFO_RXUF_MASK (0x10000U) 734 #define LPUART_FIFO_RXUF_SHIFT (16U) 735 #define LPUART_FIFO_RXUF_WIDTH (1U) 736 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) 737 738 #define LPUART_FIFO_TXOF_MASK (0x20000U) 739 #define LPUART_FIFO_TXOF_SHIFT (17U) 740 #define LPUART_FIFO_TXOF_WIDTH (1U) 741 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) 742 743 #define LPUART_FIFO_RXEMPT_MASK (0x400000U) 744 #define LPUART_FIFO_RXEMPT_SHIFT (22U) 745 #define LPUART_FIFO_RXEMPT_WIDTH (1U) 746 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) 747 748 #define LPUART_FIFO_TXEMPT_MASK (0x800000U) 749 #define LPUART_FIFO_TXEMPT_SHIFT (23U) 750 #define LPUART_FIFO_TXEMPT_WIDTH (1U) 751 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) 752 /*! @} */ 753 754 /*! @name WATER - LPUART Watermark Register */ 755 /*! @{ */ 756 757 #define LPUART_WATER_TXWATER_MASK (0x3U) 758 #define LPUART_WATER_TXWATER_SHIFT (0U) 759 #define LPUART_WATER_TXWATER_WIDTH (2U) 760 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) 761 762 #define LPUART_WATER_TXCOUNT_MASK (0x700U) 763 #define LPUART_WATER_TXCOUNT_SHIFT (8U) 764 #define LPUART_WATER_TXCOUNT_WIDTH (3U) 765 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) 766 767 #define LPUART_WATER_RXWATER_MASK (0x30000U) 768 #define LPUART_WATER_RXWATER_SHIFT (16U) 769 #define LPUART_WATER_RXWATER_WIDTH (2U) 770 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) 771 772 #define LPUART_WATER_RXCOUNT_MASK (0x7000000U) 773 #define LPUART_WATER_RXCOUNT_SHIFT (24U) 774 #define LPUART_WATER_RXCOUNT_WIDTH (3U) 775 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) 776 /*! @} */ 777 778 /*! @name DATARO - Data read-only Register */ 779 /*! @{ */ 780 781 #define LPUART_DATARO_DATA_MASK (0xFFFFU) 782 #define LPUART_DATARO_DATA_SHIFT (0U) 783 #define LPUART_DATARO_DATA_WIDTH (16U) 784 #define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) 785 /*! @} */ 786 787 /*! 788 * @} 789 */ /* end of group LPUART_Register_Masks */ 790 791 /*! 792 * @} 793 */ /* end of group LPUART_Peripheral_Access_Layer */ 794 795 #endif /* #if !defined(S32K344_LPUART_H_) */ 796
