1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_LPI2C.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_LPI2C 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_LPI2C_H_) /* Check if memory map has not been already included */ 58 #define S32K344_LPI2C_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPI2C Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPI2C - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __IO uint32_t MCR; /**< Master Control, offset: 0x10 */ 77 __IO uint32_t MSR; /**< Master Status, offset: 0x14 */ 78 __IO uint32_t MIER; /**< Master Interrupt Enable, offset: 0x18 */ 79 __IO uint32_t MDER; /**< Master DMA Enable, offset: 0x1C */ 80 __IO uint32_t MCFGR0; /**< Master Configuration 0, offset: 0x20 */ 81 __IO uint32_t MCFGR1; /**< Master Configuration 1, offset: 0x24 */ 82 __IO uint32_t MCFGR2; /**< Master Configuration 2, offset: 0x28 */ 83 __IO uint32_t MCFGR3; /**< Master Configuration 3, offset: 0x2C */ 84 uint8_t RESERVED_1[16]; 85 __IO uint32_t MDMR; /**< Master Data Match, offset: 0x40 */ 86 uint8_t RESERVED_2[4]; 87 __IO uint32_t MCCR0; /**< Master Clock Configuration 0, offset: 0x48 */ 88 uint8_t RESERVED_3[4]; 89 __IO uint32_t MCCR1; /**< Master Clock Configuration 1, offset: 0x50 */ 90 uint8_t RESERVED_4[4]; 91 __IO uint32_t MFCR; /**< Master FIFO Control, offset: 0x58 */ 92 __I uint32_t MFSR; /**< Master FIFO Status, offset: 0x5C */ 93 __O uint32_t MTDR; /**< Master Transmit Data, offset: 0x60 */ 94 uint8_t RESERVED_5[12]; 95 __I uint32_t MRDR; /**< Master Receive Data, offset: 0x70 */ 96 uint8_t RESERVED_6[156]; 97 __IO uint32_t SCR; /**< Slave Control, offset: 0x110 */ 98 __IO uint32_t SSR; /**< Slave Status, offset: 0x114 */ 99 __IO uint32_t SIER; /**< Slave Interrupt Enable, offset: 0x118 */ 100 __IO uint32_t SDER; /**< Slave DMA Enable, offset: 0x11C */ 101 uint8_t RESERVED_7[4]; 102 __IO uint32_t SCFGR1; /**< Slave Configuration 1, offset: 0x124 */ 103 __IO uint32_t SCFGR2; /**< Slave Configuration 2, offset: 0x128 */ 104 uint8_t RESERVED_8[20]; 105 __IO uint32_t SAMR; /**< Slave Address Match, offset: 0x140 */ 106 uint8_t RESERVED_9[12]; 107 __I uint32_t SASR; /**< Slave Address Status, offset: 0x150 */ 108 __IO uint32_t STAR; /**< Slave Transmit ACK, offset: 0x154 */ 109 uint8_t RESERVED_10[8]; 110 __O uint32_t STDR; /**< Slave Transmit Data, offset: 0x160 */ 111 uint8_t RESERVED_11[12]; 112 __I uint32_t SRDR; /**< Slave Receive Data, offset: 0x170 */ 113 } LPI2C_Type, *LPI2C_MemMapPtr; 114 115 /** Number of instances of the LPI2C module. */ 116 #define LPI2C_INSTANCE_COUNT (2u) 117 118 /* LPI2C - Peripheral instance base addresses */ 119 /** Peripheral LPI2C_0 base address */ 120 #define IP_LPI2C_0_BASE (0x40350000u) 121 /** Peripheral LPI2C_0 base pointer */ 122 #define IP_LPI2C_0 ((LPI2C_Type *)IP_LPI2C_0_BASE) 123 /** Peripheral LPI2C_1 base address */ 124 #define IP_LPI2C_1_BASE (0x40354000u) 125 /** Peripheral LPI2C_1 base pointer */ 126 #define IP_LPI2C_1 ((LPI2C_Type *)IP_LPI2C_1_BASE) 127 /** Array initializer of LPI2C peripheral base addresses */ 128 #define IP_LPI2C_BASE_ADDRS { IP_LPI2C_0_BASE, IP_LPI2C_1_BASE } 129 /** Array initializer of LPI2C peripheral base pointers */ 130 #define IP_LPI2C_BASE_PTRS { IP_LPI2C_0, IP_LPI2C_1 } 131 132 /* ---------------------------------------------------------------------------- 133 -- LPI2C Register Masks 134 ---------------------------------------------------------------------------- */ 135 136 /*! 137 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks 138 * @{ 139 */ 140 141 /*! @name VERID - Version ID */ 142 /*! @{ */ 143 144 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) 145 #define LPI2C_VERID_FEATURE_SHIFT (0U) 146 #define LPI2C_VERID_FEATURE_WIDTH (16U) 147 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) 148 149 #define LPI2C_VERID_MINOR_MASK (0xFF0000U) 150 #define LPI2C_VERID_MINOR_SHIFT (16U) 151 #define LPI2C_VERID_MINOR_WIDTH (8U) 152 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) 153 154 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) 155 #define LPI2C_VERID_MAJOR_SHIFT (24U) 156 #define LPI2C_VERID_MAJOR_WIDTH (8U) 157 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) 158 /*! @} */ 159 160 /*! @name PARAM - Parameter */ 161 /*! @{ */ 162 163 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) 164 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) 165 #define LPI2C_PARAM_MTXFIFO_WIDTH (4U) 166 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) 167 168 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) 169 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) 170 #define LPI2C_PARAM_MRXFIFO_WIDTH (4U) 171 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) 172 /*! @} */ 173 174 /*! @name MCR - Master Control */ 175 /*! @{ */ 176 177 #define LPI2C_MCR_MEN_MASK (0x1U) 178 #define LPI2C_MCR_MEN_SHIFT (0U) 179 #define LPI2C_MCR_MEN_WIDTH (1U) 180 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) 181 182 #define LPI2C_MCR_RST_MASK (0x2U) 183 #define LPI2C_MCR_RST_SHIFT (1U) 184 #define LPI2C_MCR_RST_WIDTH (1U) 185 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) 186 187 #define LPI2C_MCR_DOZEN_MASK (0x4U) 188 #define LPI2C_MCR_DOZEN_SHIFT (2U) 189 #define LPI2C_MCR_DOZEN_WIDTH (1U) 190 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) 191 192 #define LPI2C_MCR_DBGEN_MASK (0x8U) 193 #define LPI2C_MCR_DBGEN_SHIFT (3U) 194 #define LPI2C_MCR_DBGEN_WIDTH (1U) 195 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) 196 197 #define LPI2C_MCR_RTF_MASK (0x100U) 198 #define LPI2C_MCR_RTF_SHIFT (8U) 199 #define LPI2C_MCR_RTF_WIDTH (1U) 200 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) 201 202 #define LPI2C_MCR_RRF_MASK (0x200U) 203 #define LPI2C_MCR_RRF_SHIFT (9U) 204 #define LPI2C_MCR_RRF_WIDTH (1U) 205 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) 206 /*! @} */ 207 208 /*! @name MSR - Master Status */ 209 /*! @{ */ 210 211 #define LPI2C_MSR_TDF_MASK (0x1U) 212 #define LPI2C_MSR_TDF_SHIFT (0U) 213 #define LPI2C_MSR_TDF_WIDTH (1U) 214 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) 215 216 #define LPI2C_MSR_RDF_MASK (0x2U) 217 #define LPI2C_MSR_RDF_SHIFT (1U) 218 #define LPI2C_MSR_RDF_WIDTH (1U) 219 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) 220 221 #define LPI2C_MSR_EPF_MASK (0x100U) 222 #define LPI2C_MSR_EPF_SHIFT (8U) 223 #define LPI2C_MSR_EPF_WIDTH (1U) 224 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) 225 226 #define LPI2C_MSR_SDF_MASK (0x200U) 227 #define LPI2C_MSR_SDF_SHIFT (9U) 228 #define LPI2C_MSR_SDF_WIDTH (1U) 229 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) 230 231 #define LPI2C_MSR_NDF_MASK (0x400U) 232 #define LPI2C_MSR_NDF_SHIFT (10U) 233 #define LPI2C_MSR_NDF_WIDTH (1U) 234 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) 235 236 #define LPI2C_MSR_ALF_MASK (0x800U) 237 #define LPI2C_MSR_ALF_SHIFT (11U) 238 #define LPI2C_MSR_ALF_WIDTH (1U) 239 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) 240 241 #define LPI2C_MSR_FEF_MASK (0x1000U) 242 #define LPI2C_MSR_FEF_SHIFT (12U) 243 #define LPI2C_MSR_FEF_WIDTH (1U) 244 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) 245 246 #define LPI2C_MSR_PLTF_MASK (0x2000U) 247 #define LPI2C_MSR_PLTF_SHIFT (13U) 248 #define LPI2C_MSR_PLTF_WIDTH (1U) 249 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) 250 251 #define LPI2C_MSR_DMF_MASK (0x4000U) 252 #define LPI2C_MSR_DMF_SHIFT (14U) 253 #define LPI2C_MSR_DMF_WIDTH (1U) 254 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) 255 256 #define LPI2C_MSR_MBF_MASK (0x1000000U) 257 #define LPI2C_MSR_MBF_SHIFT (24U) 258 #define LPI2C_MSR_MBF_WIDTH (1U) 259 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) 260 261 #define LPI2C_MSR_BBF_MASK (0x2000000U) 262 #define LPI2C_MSR_BBF_SHIFT (25U) 263 #define LPI2C_MSR_BBF_WIDTH (1U) 264 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) 265 /*! @} */ 266 267 /*! @name MIER - Master Interrupt Enable */ 268 /*! @{ */ 269 270 #define LPI2C_MIER_TDIE_MASK (0x1U) 271 #define LPI2C_MIER_TDIE_SHIFT (0U) 272 #define LPI2C_MIER_TDIE_WIDTH (1U) 273 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) 274 275 #define LPI2C_MIER_RDIE_MASK (0x2U) 276 #define LPI2C_MIER_RDIE_SHIFT (1U) 277 #define LPI2C_MIER_RDIE_WIDTH (1U) 278 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) 279 280 #define LPI2C_MIER_EPIE_MASK (0x100U) 281 #define LPI2C_MIER_EPIE_SHIFT (8U) 282 #define LPI2C_MIER_EPIE_WIDTH (1U) 283 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) 284 285 #define LPI2C_MIER_SDIE_MASK (0x200U) 286 #define LPI2C_MIER_SDIE_SHIFT (9U) 287 #define LPI2C_MIER_SDIE_WIDTH (1U) 288 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) 289 290 #define LPI2C_MIER_NDIE_MASK (0x400U) 291 #define LPI2C_MIER_NDIE_SHIFT (10U) 292 #define LPI2C_MIER_NDIE_WIDTH (1U) 293 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) 294 295 #define LPI2C_MIER_ALIE_MASK (0x800U) 296 #define LPI2C_MIER_ALIE_SHIFT (11U) 297 #define LPI2C_MIER_ALIE_WIDTH (1U) 298 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) 299 300 #define LPI2C_MIER_FEIE_MASK (0x1000U) 301 #define LPI2C_MIER_FEIE_SHIFT (12U) 302 #define LPI2C_MIER_FEIE_WIDTH (1U) 303 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) 304 305 #define LPI2C_MIER_PLTIE_MASK (0x2000U) 306 #define LPI2C_MIER_PLTIE_SHIFT (13U) 307 #define LPI2C_MIER_PLTIE_WIDTH (1U) 308 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) 309 310 #define LPI2C_MIER_DMIE_MASK (0x4000U) 311 #define LPI2C_MIER_DMIE_SHIFT (14U) 312 #define LPI2C_MIER_DMIE_WIDTH (1U) 313 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) 314 /*! @} */ 315 316 /*! @name MDER - Master DMA Enable */ 317 /*! @{ */ 318 319 #define LPI2C_MDER_TDDE_MASK (0x1U) 320 #define LPI2C_MDER_TDDE_SHIFT (0U) 321 #define LPI2C_MDER_TDDE_WIDTH (1U) 322 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) 323 324 #define LPI2C_MDER_RDDE_MASK (0x2U) 325 #define LPI2C_MDER_RDDE_SHIFT (1U) 326 #define LPI2C_MDER_RDDE_WIDTH (1U) 327 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) 328 /*! @} */ 329 330 /*! @name MCFGR0 - Master Configuration 0 */ 331 /*! @{ */ 332 333 #define LPI2C_MCFGR0_HREN_MASK (0x1U) 334 #define LPI2C_MCFGR0_HREN_SHIFT (0U) 335 #define LPI2C_MCFGR0_HREN_WIDTH (1U) 336 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) 337 338 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) 339 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) 340 #define LPI2C_MCFGR0_HRPOL_WIDTH (1U) 341 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) 342 343 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) 344 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) 345 #define LPI2C_MCFGR0_HRSEL_WIDTH (1U) 346 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) 347 348 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) 349 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) 350 #define LPI2C_MCFGR0_CIRFIFO_WIDTH (1U) 351 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) 352 353 #define LPI2C_MCFGR0_RDMO_MASK (0x200U) 354 #define LPI2C_MCFGR0_RDMO_SHIFT (9U) 355 #define LPI2C_MCFGR0_RDMO_WIDTH (1U) 356 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) 357 /*! @} */ 358 359 /*! @name MCFGR1 - Master Configuration 1 */ 360 /*! @{ */ 361 362 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) 363 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) 364 #define LPI2C_MCFGR1_PRESCALE_WIDTH (3U) 365 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) 366 367 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) 368 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) 369 #define LPI2C_MCFGR1_AUTOSTOP_WIDTH (1U) 370 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) 371 372 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) 373 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) 374 #define LPI2C_MCFGR1_IGNACK_WIDTH (1U) 375 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) 376 377 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) 378 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) 379 #define LPI2C_MCFGR1_TIMECFG_WIDTH (1U) 380 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) 381 382 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) 383 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) 384 #define LPI2C_MCFGR1_MATCFG_WIDTH (3U) 385 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) 386 387 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) 388 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) 389 #define LPI2C_MCFGR1_PINCFG_WIDTH (3U) 390 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) 391 392 #define LPI2C_MCFGR1_FRCHS_MASK (0x8000000U) 393 #define LPI2C_MCFGR1_FRCHS_SHIFT (27U) 394 #define LPI2C_MCFGR1_FRCHS_WIDTH (1U) 395 #define LPI2C_MCFGR1_FRCHS(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_FRCHS_SHIFT)) & LPI2C_MCFGR1_FRCHS_MASK) 396 /*! @} */ 397 398 /*! @name MCFGR2 - Master Configuration 2 */ 399 /*! @{ */ 400 401 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) 402 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) 403 #define LPI2C_MCFGR2_BUSIDLE_WIDTH (12U) 404 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) 405 406 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) 407 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) 408 #define LPI2C_MCFGR2_FILTSCL_WIDTH (4U) 409 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) 410 411 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) 412 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) 413 #define LPI2C_MCFGR2_FILTSDA_WIDTH (4U) 414 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) 415 /*! @} */ 416 417 /*! @name MCFGR3 - Master Configuration 3 */ 418 /*! @{ */ 419 420 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) 421 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) 422 #define LPI2C_MCFGR3_PINLOW_WIDTH (12U) 423 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) 424 /*! @} */ 425 426 /*! @name MDMR - Master Data Match */ 427 /*! @{ */ 428 429 #define LPI2C_MDMR_MATCH0_MASK (0xFFU) 430 #define LPI2C_MDMR_MATCH0_SHIFT (0U) 431 #define LPI2C_MDMR_MATCH0_WIDTH (8U) 432 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) 433 434 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) 435 #define LPI2C_MDMR_MATCH1_SHIFT (16U) 436 #define LPI2C_MDMR_MATCH1_WIDTH (8U) 437 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) 438 /*! @} */ 439 440 /*! @name MCCR0 - Master Clock Configuration 0 */ 441 /*! @{ */ 442 443 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) 444 #define LPI2C_MCCR0_CLKLO_SHIFT (0U) 445 #define LPI2C_MCCR0_CLKLO_WIDTH (6U) 446 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) 447 448 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) 449 #define LPI2C_MCCR0_CLKHI_SHIFT (8U) 450 #define LPI2C_MCCR0_CLKHI_WIDTH (6U) 451 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) 452 453 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) 454 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) 455 #define LPI2C_MCCR0_SETHOLD_WIDTH (6U) 456 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) 457 458 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) 459 #define LPI2C_MCCR0_DATAVD_SHIFT (24U) 460 #define LPI2C_MCCR0_DATAVD_WIDTH (6U) 461 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) 462 /*! @} */ 463 464 /*! @name MCCR1 - Master Clock Configuration 1 */ 465 /*! @{ */ 466 467 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) 468 #define LPI2C_MCCR1_CLKLO_SHIFT (0U) 469 #define LPI2C_MCCR1_CLKLO_WIDTH (6U) 470 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) 471 472 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) 473 #define LPI2C_MCCR1_CLKHI_SHIFT (8U) 474 #define LPI2C_MCCR1_CLKHI_WIDTH (6U) 475 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) 476 477 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) 478 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) 479 #define LPI2C_MCCR1_SETHOLD_WIDTH (6U) 480 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) 481 482 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) 483 #define LPI2C_MCCR1_DATAVD_SHIFT (24U) 484 #define LPI2C_MCCR1_DATAVD_WIDTH (6U) 485 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) 486 /*! @} */ 487 488 /*! @name MFCR - Master FIFO Control */ 489 /*! @{ */ 490 491 #define LPI2C_MFCR_TXWATER_MASK (0x3U) 492 #define LPI2C_MFCR_TXWATER_SHIFT (0U) 493 #define LPI2C_MFCR_TXWATER_WIDTH (2U) 494 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) 495 496 #define LPI2C_MFCR_RXWATER_MASK (0x30000U) 497 #define LPI2C_MFCR_RXWATER_SHIFT (16U) 498 #define LPI2C_MFCR_RXWATER_WIDTH (2U) 499 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) 500 /*! @} */ 501 502 /*! @name MFSR - Master FIFO Status */ 503 /*! @{ */ 504 505 #define LPI2C_MFSR_TXCOUNT_MASK (0x7U) 506 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) 507 #define LPI2C_MFSR_TXCOUNT_WIDTH (3U) 508 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) 509 510 #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) 511 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) 512 #define LPI2C_MFSR_RXCOUNT_WIDTH (3U) 513 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) 514 /*! @} */ 515 516 /*! @name MTDR - Master Transmit Data */ 517 /*! @{ */ 518 519 #define LPI2C_MTDR_DATA_MASK (0xFFU) 520 #define LPI2C_MTDR_DATA_SHIFT (0U) 521 #define LPI2C_MTDR_DATA_WIDTH (8U) 522 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) 523 524 #define LPI2C_MTDR_CMD_MASK (0x700U) 525 #define LPI2C_MTDR_CMD_SHIFT (8U) 526 #define LPI2C_MTDR_CMD_WIDTH (3U) 527 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) 528 /*! @} */ 529 530 /*! @name MRDR - Master Receive Data */ 531 /*! @{ */ 532 533 #define LPI2C_MRDR_DATA_MASK (0xFFU) 534 #define LPI2C_MRDR_DATA_SHIFT (0U) 535 #define LPI2C_MRDR_DATA_WIDTH (8U) 536 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) 537 538 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) 539 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) 540 #define LPI2C_MRDR_RXEMPTY_WIDTH (1U) 541 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) 542 /*! @} */ 543 544 /*! @name SCR - Slave Control */ 545 /*! @{ */ 546 547 #define LPI2C_SCR_SEN_MASK (0x1U) 548 #define LPI2C_SCR_SEN_SHIFT (0U) 549 #define LPI2C_SCR_SEN_WIDTH (1U) 550 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) 551 552 #define LPI2C_SCR_RST_MASK (0x2U) 553 #define LPI2C_SCR_RST_SHIFT (1U) 554 #define LPI2C_SCR_RST_WIDTH (1U) 555 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) 556 557 #define LPI2C_SCR_FILTEN_MASK (0x10U) 558 #define LPI2C_SCR_FILTEN_SHIFT (4U) 559 #define LPI2C_SCR_FILTEN_WIDTH (1U) 560 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) 561 562 #define LPI2C_SCR_FILTDZ_MASK (0x20U) 563 #define LPI2C_SCR_FILTDZ_SHIFT (5U) 564 #define LPI2C_SCR_FILTDZ_WIDTH (1U) 565 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) 566 567 #define LPI2C_SCR_RTF_MASK (0x100U) 568 #define LPI2C_SCR_RTF_SHIFT (8U) 569 #define LPI2C_SCR_RTF_WIDTH (1U) 570 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) 571 572 #define LPI2C_SCR_RRF_MASK (0x200U) 573 #define LPI2C_SCR_RRF_SHIFT (9U) 574 #define LPI2C_SCR_RRF_WIDTH (1U) 575 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) 576 /*! @} */ 577 578 /*! @name SSR - Slave Status */ 579 /*! @{ */ 580 581 #define LPI2C_SSR_TDF_MASK (0x1U) 582 #define LPI2C_SSR_TDF_SHIFT (0U) 583 #define LPI2C_SSR_TDF_WIDTH (1U) 584 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) 585 586 #define LPI2C_SSR_RDF_MASK (0x2U) 587 #define LPI2C_SSR_RDF_SHIFT (1U) 588 #define LPI2C_SSR_RDF_WIDTH (1U) 589 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) 590 591 #define LPI2C_SSR_AVF_MASK (0x4U) 592 #define LPI2C_SSR_AVF_SHIFT (2U) 593 #define LPI2C_SSR_AVF_WIDTH (1U) 594 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) 595 596 #define LPI2C_SSR_TAF_MASK (0x8U) 597 #define LPI2C_SSR_TAF_SHIFT (3U) 598 #define LPI2C_SSR_TAF_WIDTH (1U) 599 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) 600 601 #define LPI2C_SSR_RSF_MASK (0x100U) 602 #define LPI2C_SSR_RSF_SHIFT (8U) 603 #define LPI2C_SSR_RSF_WIDTH (1U) 604 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) 605 606 #define LPI2C_SSR_SDF_MASK (0x200U) 607 #define LPI2C_SSR_SDF_SHIFT (9U) 608 #define LPI2C_SSR_SDF_WIDTH (1U) 609 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) 610 611 #define LPI2C_SSR_BEF_MASK (0x400U) 612 #define LPI2C_SSR_BEF_SHIFT (10U) 613 #define LPI2C_SSR_BEF_WIDTH (1U) 614 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) 615 616 #define LPI2C_SSR_FEF_MASK (0x800U) 617 #define LPI2C_SSR_FEF_SHIFT (11U) 618 #define LPI2C_SSR_FEF_WIDTH (1U) 619 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) 620 621 #define LPI2C_SSR_AM0F_MASK (0x1000U) 622 #define LPI2C_SSR_AM0F_SHIFT (12U) 623 #define LPI2C_SSR_AM0F_WIDTH (1U) 624 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) 625 626 #define LPI2C_SSR_AM1F_MASK (0x2000U) 627 #define LPI2C_SSR_AM1F_SHIFT (13U) 628 #define LPI2C_SSR_AM1F_WIDTH (1U) 629 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) 630 631 #define LPI2C_SSR_GCF_MASK (0x4000U) 632 #define LPI2C_SSR_GCF_SHIFT (14U) 633 #define LPI2C_SSR_GCF_WIDTH (1U) 634 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) 635 636 #define LPI2C_SSR_SARF_MASK (0x8000U) 637 #define LPI2C_SSR_SARF_SHIFT (15U) 638 #define LPI2C_SSR_SARF_WIDTH (1U) 639 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) 640 641 #define LPI2C_SSR_SBF_MASK (0x1000000U) 642 #define LPI2C_SSR_SBF_SHIFT (24U) 643 #define LPI2C_SSR_SBF_WIDTH (1U) 644 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) 645 646 #define LPI2C_SSR_BBF_MASK (0x2000000U) 647 #define LPI2C_SSR_BBF_SHIFT (25U) 648 #define LPI2C_SSR_BBF_WIDTH (1U) 649 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) 650 /*! @} */ 651 652 /*! @name SIER - Slave Interrupt Enable */ 653 /*! @{ */ 654 655 #define LPI2C_SIER_TDIE_MASK (0x1U) 656 #define LPI2C_SIER_TDIE_SHIFT (0U) 657 #define LPI2C_SIER_TDIE_WIDTH (1U) 658 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) 659 660 #define LPI2C_SIER_RDIE_MASK (0x2U) 661 #define LPI2C_SIER_RDIE_SHIFT (1U) 662 #define LPI2C_SIER_RDIE_WIDTH (1U) 663 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) 664 665 #define LPI2C_SIER_AVIE_MASK (0x4U) 666 #define LPI2C_SIER_AVIE_SHIFT (2U) 667 #define LPI2C_SIER_AVIE_WIDTH (1U) 668 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) 669 670 #define LPI2C_SIER_TAIE_MASK (0x8U) 671 #define LPI2C_SIER_TAIE_SHIFT (3U) 672 #define LPI2C_SIER_TAIE_WIDTH (1U) 673 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) 674 675 #define LPI2C_SIER_RSIE_MASK (0x100U) 676 #define LPI2C_SIER_RSIE_SHIFT (8U) 677 #define LPI2C_SIER_RSIE_WIDTH (1U) 678 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) 679 680 #define LPI2C_SIER_SDIE_MASK (0x200U) 681 #define LPI2C_SIER_SDIE_SHIFT (9U) 682 #define LPI2C_SIER_SDIE_WIDTH (1U) 683 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) 684 685 #define LPI2C_SIER_BEIE_MASK (0x400U) 686 #define LPI2C_SIER_BEIE_SHIFT (10U) 687 #define LPI2C_SIER_BEIE_WIDTH (1U) 688 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) 689 690 #define LPI2C_SIER_FEIE_MASK (0x800U) 691 #define LPI2C_SIER_FEIE_SHIFT (11U) 692 #define LPI2C_SIER_FEIE_WIDTH (1U) 693 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) 694 695 #define LPI2C_SIER_AM0IE_MASK (0x1000U) 696 #define LPI2C_SIER_AM0IE_SHIFT (12U) 697 #define LPI2C_SIER_AM0IE_WIDTH (1U) 698 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) 699 700 #define LPI2C_SIER_AM1IE_MASK (0x2000U) 701 #define LPI2C_SIER_AM1IE_SHIFT (13U) 702 #define LPI2C_SIER_AM1IE_WIDTH (1U) 703 #define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) 704 705 #define LPI2C_SIER_GCIE_MASK (0x4000U) 706 #define LPI2C_SIER_GCIE_SHIFT (14U) 707 #define LPI2C_SIER_GCIE_WIDTH (1U) 708 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) 709 710 #define LPI2C_SIER_SARIE_MASK (0x8000U) 711 #define LPI2C_SIER_SARIE_SHIFT (15U) 712 #define LPI2C_SIER_SARIE_WIDTH (1U) 713 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) 714 /*! @} */ 715 716 /*! @name SDER - Slave DMA Enable */ 717 /*! @{ */ 718 719 #define LPI2C_SDER_TDDE_MASK (0x1U) 720 #define LPI2C_SDER_TDDE_SHIFT (0U) 721 #define LPI2C_SDER_TDDE_WIDTH (1U) 722 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) 723 724 #define LPI2C_SDER_RDDE_MASK (0x2U) 725 #define LPI2C_SDER_RDDE_SHIFT (1U) 726 #define LPI2C_SDER_RDDE_WIDTH (1U) 727 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) 728 729 #define LPI2C_SDER_AVDE_MASK (0x4U) 730 #define LPI2C_SDER_AVDE_SHIFT (2U) 731 #define LPI2C_SDER_AVDE_WIDTH (1U) 732 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) 733 /*! @} */ 734 735 /*! @name SCFGR1 - Slave Configuration 1 */ 736 /*! @{ */ 737 738 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) 739 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) 740 #define LPI2C_SCFGR1_ADRSTALL_WIDTH (1U) 741 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) 742 743 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) 744 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) 745 #define LPI2C_SCFGR1_RXSTALL_WIDTH (1U) 746 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) 747 748 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) 749 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) 750 #define LPI2C_SCFGR1_TXDSTALL_WIDTH (1U) 751 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) 752 753 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) 754 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) 755 #define LPI2C_SCFGR1_ACKSTALL_WIDTH (1U) 756 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) 757 758 #define LPI2C_SCFGR1_GCEN_MASK (0x100U) 759 #define LPI2C_SCFGR1_GCEN_SHIFT (8U) 760 #define LPI2C_SCFGR1_GCEN_WIDTH (1U) 761 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) 762 763 #define LPI2C_SCFGR1_SAEN_MASK (0x200U) 764 #define LPI2C_SCFGR1_SAEN_SHIFT (9U) 765 #define LPI2C_SCFGR1_SAEN_WIDTH (1U) 766 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) 767 768 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) 769 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) 770 #define LPI2C_SCFGR1_TXCFG_WIDTH (1U) 771 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) 772 773 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) 774 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) 775 #define LPI2C_SCFGR1_RXCFG_WIDTH (1U) 776 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) 777 778 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) 779 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) 780 #define LPI2C_SCFGR1_IGNACK_WIDTH (1U) 781 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) 782 783 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) 784 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) 785 #define LPI2C_SCFGR1_HSMEN_WIDTH (1U) 786 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) 787 788 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) 789 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) 790 #define LPI2C_SCFGR1_ADDRCFG_WIDTH (3U) 791 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) 792 /*! @} */ 793 794 /*! @name SCFGR2 - Slave Configuration 2 */ 795 /*! @{ */ 796 797 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) 798 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) 799 #define LPI2C_SCFGR2_CLKHOLD_WIDTH (4U) 800 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) 801 802 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) 803 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) 804 #define LPI2C_SCFGR2_DATAVD_WIDTH (6U) 805 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) 806 807 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) 808 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) 809 #define LPI2C_SCFGR2_FILTSCL_WIDTH (4U) 810 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) 811 812 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) 813 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) 814 #define LPI2C_SCFGR2_FILTSDA_WIDTH (4U) 815 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) 816 /*! @} */ 817 818 /*! @name SAMR - Slave Address Match */ 819 /*! @{ */ 820 821 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) 822 #define LPI2C_SAMR_ADDR0_SHIFT (1U) 823 #define LPI2C_SAMR_ADDR0_WIDTH (10U) 824 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) 825 826 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) 827 #define LPI2C_SAMR_ADDR1_SHIFT (17U) 828 #define LPI2C_SAMR_ADDR1_WIDTH (10U) 829 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) 830 /*! @} */ 831 832 /*! @name SASR - Slave Address Status */ 833 /*! @{ */ 834 835 #define LPI2C_SASR_RADDR_MASK (0x7FFU) 836 #define LPI2C_SASR_RADDR_SHIFT (0U) 837 #define LPI2C_SASR_RADDR_WIDTH (11U) 838 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) 839 840 #define LPI2C_SASR_ANV_MASK (0x4000U) 841 #define LPI2C_SASR_ANV_SHIFT (14U) 842 #define LPI2C_SASR_ANV_WIDTH (1U) 843 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) 844 /*! @} */ 845 846 /*! @name STAR - Slave Transmit ACK */ 847 /*! @{ */ 848 849 #define LPI2C_STAR_TXNACK_MASK (0x1U) 850 #define LPI2C_STAR_TXNACK_SHIFT (0U) 851 #define LPI2C_STAR_TXNACK_WIDTH (1U) 852 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) 853 /*! @} */ 854 855 /*! @name STDR - Slave Transmit Data */ 856 /*! @{ */ 857 858 #define LPI2C_STDR_DATA_MASK (0xFFU) 859 #define LPI2C_STDR_DATA_SHIFT (0U) 860 #define LPI2C_STDR_DATA_WIDTH (8U) 861 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) 862 /*! @} */ 863 864 /*! @name SRDR - Slave Receive Data */ 865 /*! @{ */ 866 867 #define LPI2C_SRDR_DATA_MASK (0xFFU) 868 #define LPI2C_SRDR_DATA_SHIFT (0U) 869 #define LPI2C_SRDR_DATA_WIDTH (8U) 870 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) 871 872 #define LPI2C_SRDR_RADDR_MASK (0x700U) 873 #define LPI2C_SRDR_RADDR_SHIFT (8U) 874 #define LPI2C_SRDR_RADDR_WIDTH (3U) 875 #define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) 876 877 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) 878 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) 879 #define LPI2C_SRDR_RXEMPTY_WIDTH (1U) 880 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) 881 882 #define LPI2C_SRDR_SOF_MASK (0x8000U) 883 #define LPI2C_SRDR_SOF_SHIFT (15U) 884 #define LPI2C_SRDR_SOF_WIDTH (1U) 885 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) 886 /*! @} */ 887 888 /*! 889 * @} 890 */ /* end of group LPI2C_Register_Masks */ 891 892 /*! 893 * @} 894 */ /* end of group LPI2C_Peripheral_Access_Layer */ 895 896 #endif /* #if !defined(S32K344_LPI2C_H_) */ 897
