1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_DMA.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_DMA 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_DMA_H_) /* Check if memory map has not been already included */ 58 #define S32K344_DMA_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- eDMA Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup eDMA_Peripheral_Access_Layer eDMA Peripheral Access Layer 68 * @{ 69 */ 70 71 /** eDMA - Size of Registers Arrays */ 72 #define eDMA_MP_GRPRI_COUNT 32u 73 74 /** eDMA - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t CSR; /**< Management Page Control, offset: 0x0 */ 77 __I uint32_t ES; /**< Management Page Error Status, offset: 0x4 */ 78 __I uint32_t INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ 79 __I uint32_t HRS; /**< Management Page Hardware Request Status, offset: 0xC */ 80 uint8_t RESERVED_0[240]; 81 __IO uint32_t CH_GRPRI[eDMA_MP_GRPRI_COUNT]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ 82 } eDMA_Type, *eDMA_MemMapPtr; 83 84 /** Number of instances of the eDMA module. */ 85 #define eDMA_INSTANCE_COUNT (1u) 86 87 /* eDMA - Peripheral instance base addresses */ 88 /** Peripheral EDMA base address */ 89 #define IP_EDMA_BASE (0x4020C000u) 90 /** Peripheral EDMA base pointer */ 91 #define IP_EDMA ((eDMA_Type *)IP_EDMA_BASE) 92 /** Array initializer of eDMA peripheral base addresses */ 93 #define IP_eDMA_BASE_ADDRS { IP_EDMA_BASE } 94 /** Array initializer of eDMA peripheral base pointers */ 95 #define IP_eDMA_BASE_PTRS { IP_EDMA } 96 97 /* ---------------------------------------------------------------------------- 98 -- eDMA Register Masks 99 ---------------------------------------------------------------------------- */ 100 101 /*! 102 * @addtogroup eDMA_Register_Masks eDMA Register Masks 103 * @{ 104 */ 105 106 /*! @name CSR - Management Page Control */ 107 /*! @{ */ 108 109 #define eDMA_CSR_EDBG_MASK (0x2U) 110 #define eDMA_CSR_EDBG_SHIFT (1U) 111 #define eDMA_CSR_EDBG_WIDTH (1U) 112 #define eDMA_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_EDBG_SHIFT)) & eDMA_CSR_EDBG_MASK) 113 114 #define eDMA_CSR_ERCA_MASK (0x4U) 115 #define eDMA_CSR_ERCA_SHIFT (2U) 116 #define eDMA_CSR_ERCA_WIDTH (1U) 117 #define eDMA_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_ERCA_SHIFT)) & eDMA_CSR_ERCA_MASK) 118 119 #define eDMA_CSR_HAE_MASK (0x10U) 120 #define eDMA_CSR_HAE_SHIFT (4U) 121 #define eDMA_CSR_HAE_WIDTH (1U) 122 #define eDMA_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_HAE_SHIFT)) & eDMA_CSR_HAE_MASK) 123 124 #define eDMA_CSR_HALT_MASK (0x20U) 125 #define eDMA_CSR_HALT_SHIFT (5U) 126 #define eDMA_CSR_HALT_WIDTH (1U) 127 #define eDMA_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_HALT_SHIFT)) & eDMA_CSR_HALT_MASK) 128 129 #define eDMA_CSR_GCLC_MASK (0x40U) 130 #define eDMA_CSR_GCLC_SHIFT (6U) 131 #define eDMA_CSR_GCLC_WIDTH (1U) 132 #define eDMA_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_GCLC_SHIFT)) & eDMA_CSR_GCLC_MASK) 133 134 #define eDMA_CSR_GMRC_MASK (0x80U) 135 #define eDMA_CSR_GMRC_SHIFT (7U) 136 #define eDMA_CSR_GMRC_WIDTH (1U) 137 #define eDMA_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_GMRC_SHIFT)) & eDMA_CSR_GMRC_MASK) 138 139 #define eDMA_CSR_ECX_MASK (0x100U) 140 #define eDMA_CSR_ECX_SHIFT (8U) 141 #define eDMA_CSR_ECX_WIDTH (1U) 142 #define eDMA_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_ECX_SHIFT)) & eDMA_CSR_ECX_MASK) 143 144 #define eDMA_CSR_CX_MASK (0x200U) 145 #define eDMA_CSR_CX_SHIFT (9U) 146 #define eDMA_CSR_CX_WIDTH (1U) 147 #define eDMA_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_CX_SHIFT)) & eDMA_CSR_CX_MASK) 148 149 #define eDMA_CSR_ACTIVE_ID_MASK (0x1F000000U) 150 #define eDMA_CSR_ACTIVE_ID_SHIFT (24U) 151 #define eDMA_CSR_ACTIVE_ID_WIDTH (5U) 152 #define eDMA_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_ACTIVE_ID_SHIFT)) & eDMA_CSR_ACTIVE_ID_MASK) 153 154 #define eDMA_CSR_ACTIVE_MASK (0x80000000U) 155 #define eDMA_CSR_ACTIVE_SHIFT (31U) 156 #define eDMA_CSR_ACTIVE_WIDTH (1U) 157 #define eDMA_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CSR_ACTIVE_SHIFT)) & eDMA_CSR_ACTIVE_MASK) 158 /*! @} */ 159 160 /*! @name ES - Management Page Error Status */ 161 /*! @{ */ 162 163 #define eDMA_ES_DBE_MASK (0x1U) 164 #define eDMA_ES_DBE_SHIFT (0U) 165 #define eDMA_ES_DBE_WIDTH (1U) 166 #define eDMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_DBE_SHIFT)) & eDMA_ES_DBE_MASK) 167 168 #define eDMA_ES_SBE_MASK (0x2U) 169 #define eDMA_ES_SBE_SHIFT (1U) 170 #define eDMA_ES_SBE_WIDTH (1U) 171 #define eDMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_SBE_SHIFT)) & eDMA_ES_SBE_MASK) 172 173 #define eDMA_ES_SGE_MASK (0x4U) 174 #define eDMA_ES_SGE_SHIFT (2U) 175 #define eDMA_ES_SGE_WIDTH (1U) 176 #define eDMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_SGE_SHIFT)) & eDMA_ES_SGE_MASK) 177 178 #define eDMA_ES_NCE_MASK (0x8U) 179 #define eDMA_ES_NCE_SHIFT (3U) 180 #define eDMA_ES_NCE_WIDTH (1U) 181 #define eDMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_NCE_SHIFT)) & eDMA_ES_NCE_MASK) 182 183 #define eDMA_ES_DOE_MASK (0x10U) 184 #define eDMA_ES_DOE_SHIFT (4U) 185 #define eDMA_ES_DOE_WIDTH (1U) 186 #define eDMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_DOE_SHIFT)) & eDMA_ES_DOE_MASK) 187 188 #define eDMA_ES_DAE_MASK (0x20U) 189 #define eDMA_ES_DAE_SHIFT (5U) 190 #define eDMA_ES_DAE_WIDTH (1U) 191 #define eDMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_DAE_SHIFT)) & eDMA_ES_DAE_MASK) 192 193 #define eDMA_ES_SOE_MASK (0x40U) 194 #define eDMA_ES_SOE_SHIFT (6U) 195 #define eDMA_ES_SOE_WIDTH (1U) 196 #define eDMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_SOE_SHIFT)) & eDMA_ES_SOE_MASK) 197 198 #define eDMA_ES_SAE_MASK (0x80U) 199 #define eDMA_ES_SAE_SHIFT (7U) 200 #define eDMA_ES_SAE_WIDTH (1U) 201 #define eDMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_SAE_SHIFT)) & eDMA_ES_SAE_MASK) 202 203 #define eDMA_ES_ECX_MASK (0x100U) 204 #define eDMA_ES_ECX_SHIFT (8U) 205 #define eDMA_ES_ECX_WIDTH (1U) 206 #define eDMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_ECX_SHIFT)) & eDMA_ES_ECX_MASK) 207 208 #define eDMA_ES_UCE_MASK (0x200U) 209 #define eDMA_ES_UCE_SHIFT (9U) 210 #define eDMA_ES_UCE_WIDTH (1U) 211 #define eDMA_ES_UCE(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_UCE_SHIFT)) & eDMA_ES_UCE_MASK) 212 213 #define eDMA_ES_ERRCHN_MASK (0x1F000000U) 214 #define eDMA_ES_ERRCHN_SHIFT (24U) 215 #define eDMA_ES_ERRCHN_WIDTH (5U) 216 #define eDMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_ERRCHN_SHIFT)) & eDMA_ES_ERRCHN_MASK) 217 218 #define eDMA_ES_VLD_MASK (0x80000000U) 219 #define eDMA_ES_VLD_SHIFT (31U) 220 #define eDMA_ES_VLD_WIDTH (1U) 221 #define eDMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << eDMA_ES_VLD_SHIFT)) & eDMA_ES_VLD_MASK) 222 /*! @} */ 223 224 /*! @name INT - Management Page Interrupt Request Status */ 225 /*! @{ */ 226 227 #define eDMA_INT_INT_MASK (0xFFFFFFFFU) 228 #define eDMA_INT_INT_SHIFT (0U) 229 #define eDMA_INT_INT_WIDTH (32U) 230 #define eDMA_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << eDMA_INT_INT_SHIFT)) & eDMA_INT_INT_MASK) 231 /*! @} */ 232 233 /*! @name HRS - Management Page Hardware Request Status */ 234 /*! @{ */ 235 236 #define eDMA_HRS_HRS_MASK (0xFFFFFFFFU) 237 #define eDMA_HRS_HRS_SHIFT (0U) 238 #define eDMA_HRS_HRS_WIDTH (32U) 239 #define eDMA_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << eDMA_HRS_HRS_SHIFT)) & eDMA_HRS_HRS_MASK) 240 /*! @} */ 241 242 /*! @name CH_GRPRI - Channel Arbitration Group */ 243 /*! @{ */ 244 245 #define eDMA_CH_GRPRI_GRPRI_MASK (0x1FU) 246 #define eDMA_CH_GRPRI_GRPRI_SHIFT (0U) 247 #define eDMA_CH_GRPRI_GRPRI_WIDTH (5U) 248 #define eDMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << eDMA_CH_GRPRI_GRPRI_SHIFT)) & eDMA_CH_GRPRI_GRPRI_MASK) 249 /*! @} */ 250 251 /*! 252 * @} 253 */ /* end of group eDMA_Register_Masks */ 254 255 /*! 256 * @} 257 */ /* end of group eDMA_Peripheral_Access_Layer */ 258 259 #endif /* #if !defined(S32K344_DMA_H_) */ 260
