1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_DMAMUX.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_DMAMUX 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_DMAMUX_H_) /* Check if memory map has not been already included */ 58 #define S32K344_DMAMUX_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DMAMUX Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DMAMUX - Size of Registers Arrays */ 72 #define DMAMUX_CHCFG_COUNT 16u 73 74 /** DMAMUX - Register Layout Typedef */ 75 typedef struct { 76 __IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 77 } DMAMUX_Type, *DMAMUX_MemMapPtr; 78 79 /** Number of instances of the DMAMUX module. */ 80 #define DMAMUX_INSTANCE_COUNT (2u) 81 82 /* DMAMUX - Peripheral instance base addresses */ 83 /** Peripheral DMAMUX_0 base address */ 84 #define IP_DMAMUX_0_BASE (0x40280000u) 85 /** Peripheral DMAMUX_0 base pointer */ 86 #define IP_DMAMUX_0 ((DMAMUX_Type *)IP_DMAMUX_0_BASE) 87 /** Peripheral DMAMUX_1 base address */ 88 #define IP_DMAMUX_1_BASE (0x40284000u) 89 /** Peripheral DMAMUX_1 base pointer */ 90 #define IP_DMAMUX_1 ((DMAMUX_Type *)IP_DMAMUX_1_BASE) 91 /** Array initializer of DMAMUX peripheral base addresses */ 92 #define IP_DMAMUX_BASE_ADDRS { IP_DMAMUX_0_BASE, IP_DMAMUX_1_BASE } 93 /** Array initializer of DMAMUX peripheral base pointers */ 94 #define IP_DMAMUX_BASE_PTRS { IP_DMAMUX_0, IP_DMAMUX_1 } 95 96 /* ---------------------------------------------------------------------------- 97 -- DMAMUX Register Masks 98 ---------------------------------------------------------------------------- */ 99 100 /*! 101 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 102 * @{ 103 */ 104 105 /*! @name CHCFG - Channel Configuration register */ 106 /*! @{ */ 107 108 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) 109 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) 110 #define DMAMUX_CHCFG_SOURCE_WIDTH (6U) 111 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) 112 113 #define DMAMUX_CHCFG_TRIG_MASK (0x40U) 114 #define DMAMUX_CHCFG_TRIG_SHIFT (6U) 115 #define DMAMUX_CHCFG_TRIG_WIDTH (1U) 116 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) 117 118 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) 119 #define DMAMUX_CHCFG_ENBL_SHIFT (7U) 120 #define DMAMUX_CHCFG_ENBL_WIDTH (1U) 121 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) 122 /*! @} */ 123 124 /*! 125 * @} 126 */ /* end of group DMAMUX_Register_Masks */ 127 128 /*! 129 * @} 130 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 131 132 #endif /* #if !defined(S32K344_DMAMUX_H_) */ 133
