1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CMU_FC.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_CMU_FC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CMU_FC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CMU_FC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CMU_FC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CMU_FC_Peripheral_Access_Layer CMU_FC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CMU_FC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ 74 __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ 75 __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ 76 __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ 77 __IO uint32_t SR; /**< Status Register, offset: 0x10 */ 78 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ 79 } CMU_FC_Type, *CMU_FC_MemMapPtr; 80 81 /** Number of instances of the CMU_FC module. */ 82 #define CMU_FC_INSTANCE_COUNT (27u) 83 84 /* CMU_FC - Peripheral instance base addresses */ 85 /** Peripheral CE_CMU_FC_0 base address */ 86 #define IP_CE_CMU_FC_0_BASE (0x44854000u) 87 /** Peripheral CE_CMU_FC_0 base pointer */ 88 #define IP_CE_CMU_FC_0 ((CMU_FC_Type *)IP_CE_CMU_FC_0_BASE) 89 /** Peripheral CE_CMU_FC_1 base address */ 90 #define IP_CE_CMU_FC_1_BASE (0x44A54000u) 91 /** Peripheral CE_CMU_FC_1 base pointer */ 92 #define IP_CE_CMU_FC_1 ((CMU_FC_Type *)IP_CE_CMU_FC_1_BASE) 93 /** Peripheral CE_CMU_FC_2 base address */ 94 #define IP_CE_CMU_FC_2_BASE (0x44E10000u) 95 /** Peripheral CE_CMU_FC_2 base pointer */ 96 #define IP_CE_CMU_FC_2 ((CMU_FC_Type *)IP_CE_CMU_FC_2_BASE) 97 /** Peripheral CMU_FC_0 base address */ 98 #define IP_CMU_FC_0_BASE (0x40040000u) 99 /** Peripheral CMU_FC_0 base pointer */ 100 #define IP_CMU_FC_0 ((CMU_FC_Type *)IP_CMU_FC_0_BASE) 101 /** Peripheral CMU_FC_1 base address */ 102 #define IP_CMU_FC_1_BASE (0x40840000u) 103 /** Peripheral CMU_FC_1 base pointer */ 104 #define IP_CMU_FC_1 ((CMU_FC_Type *)IP_CMU_FC_1_BASE) 105 /** Peripheral CMU_FC_2A base address */ 106 #define IP_CMU_FC_2A_BASE (0x41040000u) 107 /** Peripheral CMU_FC_2A base pointer */ 108 #define IP_CMU_FC_2A ((CMU_FC_Type *)IP_CMU_FC_2A_BASE) 109 /** Peripheral CMU_FC_2B base address */ 110 #define IP_CMU_FC_2B_BASE (0x410A0000u) 111 /** Peripheral CMU_FC_2B base pointer */ 112 #define IP_CMU_FC_2B ((CMU_FC_Type *)IP_CMU_FC_2B_BASE) 113 /** Peripheral CMU_FC_2C base address */ 114 #define IP_CMU_FC_2C_BASE (0x410B0000u) 115 /** Peripheral CMU_FC_2C base pointer */ 116 #define IP_CMU_FC_2C ((CMU_FC_Type *)IP_CMU_FC_2C_BASE) 117 /** Peripheral CMU_FC_2D base address */ 118 #define IP_CMU_FC_2D_BASE (0x410C0000u) 119 /** Peripheral CMU_FC_2D base pointer */ 120 #define IP_CMU_FC_2D ((CMU_FC_Type *)IP_CMU_FC_2D_BASE) 121 /** Peripheral CMU_FC_3 base address */ 122 #define IP_CMU_FC_3_BASE (0x41840000u) 123 /** Peripheral CMU_FC_3 base pointer */ 124 #define IP_CMU_FC_3 ((CMU_FC_Type *)IP_CMU_FC_3_BASE) 125 /** Peripheral CMU_FC_4 base address */ 126 #define IP_CMU_FC_4_BASE (0x42040000u) 127 /** Peripheral CMU_FC_4 base pointer */ 128 #define IP_CMU_FC_4 ((CMU_FC_Type *)IP_CMU_FC_4_BASE) 129 /** Peripheral CMU_FC_5 base address */ 130 #define IP_CMU_FC_5_BASE (0x42840000u) 131 /** Peripheral CMU_FC_5 base pointer */ 132 #define IP_CMU_FC_5 ((CMU_FC_Type *)IP_CMU_FC_5_BASE) 133 /** Peripheral CMU_FC_6 base address */ 134 #define IP_CMU_FC_6_BASE (0x44040000u) 135 /** Peripheral CMU_FC_6 base pointer */ 136 #define IP_CMU_FC_6 ((CMU_FC_Type *)IP_CMU_FC_6_BASE) 137 /** Peripheral CMU_FC_DEBUG_1 base address */ 138 #define IP_CMU_FC_DEBUG_1_BASE (0x40050000u) 139 /** Peripheral CMU_FC_DEBUG_1 base pointer */ 140 #define IP_CMU_FC_DEBUG_1 ((CMU_FC_Type *)IP_CMU_FC_DEBUG_1_BASE) 141 /** Peripheral CMU_FC_DEBUG_2 base address */ 142 #define IP_CMU_FC_DEBUG_2_BASE (0x40850000u) 143 /** Peripheral CMU_FC_DEBUG_2 base pointer */ 144 #define IP_CMU_FC_DEBUG_2 ((CMU_FC_Type *)IP_CMU_FC_DEBUG_2_BASE) 145 /** Peripheral AES__CMU_FC base address */ 146 #define IP_AES__CMU_FC_BASE (0x472B0000u) 147 /** Peripheral AES__CMU_FC base pointer */ 148 #define IP_AES__CMU_FC ((CMU_FC_Type *)IP_AES__CMU_FC_BASE) 149 /** Peripheral RTU0__CMU_FC_0 base address */ 150 #define IP_RTU0__CMU_FC_0_BASE (0x76080000u) 151 /** Peripheral RTU0__CMU_FC_0 base pointer */ 152 #define IP_RTU0__CMU_FC_0 ((CMU_FC_Type *)IP_RTU0__CMU_FC_0_BASE) 153 /** Peripheral RTU0__CMU_FC_1 base address */ 154 #define IP_RTU0__CMU_FC_1_BASE (0x760A0000u) 155 /** Peripheral RTU0__CMU_FC_1 base pointer */ 156 #define IP_RTU0__CMU_FC_1 ((CMU_FC_Type *)IP_RTU0__CMU_FC_1_BASE) 157 /** Peripheral RTU0__CMU_FC_2 base address */ 158 #define IP_RTU0__CMU_FC_2_BASE (0x760B0000u) 159 /** Peripheral RTU0__CMU_FC_2 base pointer */ 160 #define IP_RTU0__CMU_FC_2 ((CMU_FC_Type *)IP_RTU0__CMU_FC_2_BASE) 161 /** Peripheral RTU0__CMU_FC_3 base address */ 162 #define IP_RTU0__CMU_FC_3_BASE (0x76160000u) 163 /** Peripheral RTU0__CMU_FC_3 base pointer */ 164 #define IP_RTU0__CMU_FC_3 ((CMU_FC_Type *)IP_RTU0__CMU_FC_3_BASE) 165 /** Peripheral RTU0__CMU_FC_4 base address */ 166 #define IP_RTU0__CMU_FC_4_BASE (0x76170000u) 167 /** Peripheral RTU0__CMU_FC_4 base pointer */ 168 #define IP_RTU0__CMU_FC_4 ((CMU_FC_Type *)IP_RTU0__CMU_FC_4_BASE) 169 /** Peripheral RTU1__CMU_FC_0 base address */ 170 #define IP_RTU1__CMU_FC_0_BASE (0x76880000u) 171 /** Peripheral RTU1__CMU_FC_0 base pointer */ 172 #define IP_RTU1__CMU_FC_0 ((CMU_FC_Type *)IP_RTU1__CMU_FC_0_BASE) 173 /** Peripheral RTU1__CMU_FC_1 base address */ 174 #define IP_RTU1__CMU_FC_1_BASE (0x768A0000u) 175 /** Peripheral RTU1__CMU_FC_1 base pointer */ 176 #define IP_RTU1__CMU_FC_1 ((CMU_FC_Type *)IP_RTU1__CMU_FC_1_BASE) 177 /** Peripheral RTU1__CMU_FC_2 base address */ 178 #define IP_RTU1__CMU_FC_2_BASE (0x768B0000u) 179 /** Peripheral RTU1__CMU_FC_2 base pointer */ 180 #define IP_RTU1__CMU_FC_2 ((CMU_FC_Type *)IP_RTU1__CMU_FC_2_BASE) 181 /** Peripheral RTU1__CMU_FC_3 base address */ 182 #define IP_RTU1__CMU_FC_3_BASE (0x76960000u) 183 /** Peripheral RTU1__CMU_FC_3 base pointer */ 184 #define IP_RTU1__CMU_FC_3 ((CMU_FC_Type *)IP_RTU1__CMU_FC_3_BASE) 185 /** Peripheral RTU1__CMU_FC_4 base address */ 186 #define IP_RTU1__CMU_FC_4_BASE (0x76970000u) 187 /** Peripheral RTU1__CMU_FC_4 base pointer */ 188 #define IP_RTU1__CMU_FC_4 ((CMU_FC_Type *)IP_RTU1__CMU_FC_4_BASE) 189 /** Peripheral SMU__CMU_FC base address */ 190 #define IP_SMU__CMU_FC_BASE (0x45054000u) 191 /** Peripheral SMU__CMU_FC base pointer */ 192 #define IP_SMU__CMU_FC ((CMU_FC_Type *)IP_SMU__CMU_FC_BASE) 193 /** Array initializer of CMU_FC peripheral base addresses */ 194 #define IP_CMU_FC_BASE_ADDRS { IP_CE_CMU_FC_0_BASE, IP_CE_CMU_FC_1_BASE, IP_CE_CMU_FC_2_BASE, IP_CMU_FC_0_BASE, IP_CMU_FC_1_BASE, IP_CMU_FC_2A_BASE, IP_CMU_FC_2B_BASE, IP_CMU_FC_2C_BASE, IP_CMU_FC_2D_BASE, IP_CMU_FC_3_BASE, IP_CMU_FC_4_BASE, IP_CMU_FC_5_BASE, IP_CMU_FC_6_BASE, IP_CMU_FC_DEBUG_1_BASE, IP_CMU_FC_DEBUG_2_BASE, IP_AES__CMU_FC_BASE, IP_RTU0__CMU_FC_0_BASE, IP_RTU0__CMU_FC_1_BASE, IP_RTU0__CMU_FC_2_BASE, IP_RTU0__CMU_FC_3_BASE, IP_RTU0__CMU_FC_4_BASE, IP_RTU1__CMU_FC_0_BASE, IP_RTU1__CMU_FC_1_BASE, IP_RTU1__CMU_FC_2_BASE, IP_RTU1__CMU_FC_3_BASE, IP_RTU1__CMU_FC_4_BASE, IP_SMU__CMU_FC_BASE } 195 /** Array initializer of CMU_FC peripheral base pointers */ 196 #define IP_CMU_FC_BASE_PTRS { IP_CE_CMU_FC_0, IP_CE_CMU_FC_1, IP_CE_CMU_FC_2, IP_CMU_FC_0, IP_CMU_FC_1, IP_CMU_FC_2A, IP_CMU_FC_2B, IP_CMU_FC_2C, IP_CMU_FC_2D, IP_CMU_FC_3, IP_CMU_FC_4, IP_CMU_FC_5, IP_CMU_FC_6, IP_CMU_FC_DEBUG_1, IP_CMU_FC_DEBUG_2, IP_AES__CMU_FC, IP_RTU0__CMU_FC_0, IP_RTU0__CMU_FC_1, IP_RTU0__CMU_FC_2, IP_RTU0__CMU_FC_3, IP_RTU0__CMU_FC_4, IP_RTU1__CMU_FC_0, IP_RTU1__CMU_FC_1, IP_RTU1__CMU_FC_2, IP_RTU1__CMU_FC_3, IP_RTU1__CMU_FC_4, IP_SMU__CMU_FC } 197 198 /* ---------------------------------------------------------------------------- 199 -- CMU_FC Register Masks 200 ---------------------------------------------------------------------------- */ 201 202 /*! 203 * @addtogroup CMU_FC_Register_Masks CMU_FC Register Masks 204 * @{ 205 */ 206 207 /*! @name GCR - Global Configuration Register */ 208 /*! @{ */ 209 210 #define CMU_FC_GCR_FCE_MASK (0x1U) 211 #define CMU_FC_GCR_FCE_SHIFT (0U) 212 #define CMU_FC_GCR_FCE_WIDTH (1U) 213 #define CMU_FC_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FCE_SHIFT)) & CMU_FC_GCR_FCE_MASK) 214 215 #define CMU_FC_GCR_FI_SCE_MASK (0x100U) 216 #define CMU_FC_GCR_FI_SCE_SHIFT (8U) 217 #define CMU_FC_GCR_FI_SCE_WIDTH (1U) 218 #define CMU_FC_GCR_FI_SCE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FI_SCE_SHIFT)) & CMU_FC_GCR_FI_SCE_MASK) 219 220 #define CMU_FC_GCR_FI_START_MASK (0x200U) 221 #define CMU_FC_GCR_FI_START_SHIFT (9U) 222 #define CMU_FC_GCR_FI_START_WIDTH (1U) 223 #define CMU_FC_GCR_FI_START(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FI_START_SHIFT)) & CMU_FC_GCR_FI_START_MASK) 224 225 #define CMU_FC_GCR_FI_AUTO_EN_MASK (0x400U) 226 #define CMU_FC_GCR_FI_AUTO_EN_SHIFT (10U) 227 #define CMU_FC_GCR_FI_AUTO_EN_WIDTH (1U) 228 #define CMU_FC_GCR_FI_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FI_AUTO_EN_SHIFT)) & CMU_FC_GCR_FI_AUTO_EN_MASK) 229 230 #define CMU_FC_GCR_FI_INT_MASK_MASK (0x800U) 231 #define CMU_FC_GCR_FI_INT_MASK_SHIFT (11U) 232 #define CMU_FC_GCR_FI_INT_MASK_WIDTH (1U) 233 #define CMU_FC_GCR_FI_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FI_INT_MASK_SHIFT)) & CMU_FC_GCR_FI_INT_MASK_MASK) 234 235 #define CMU_FC_GCR_FI_AUTO_RCOUNT_MASK (0xFFFF0000U) 236 #define CMU_FC_GCR_FI_AUTO_RCOUNT_SHIFT (16U) 237 #define CMU_FC_GCR_FI_AUTO_RCOUNT_WIDTH (16U) 238 #define CMU_FC_GCR_FI_AUTO_RCOUNT(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FI_AUTO_RCOUNT_SHIFT)) & CMU_FC_GCR_FI_AUTO_RCOUNT_MASK) 239 /*! @} */ 240 241 /*! @name RCCR - Reference Count Configuration Register */ 242 /*! @{ */ 243 244 #define CMU_FC_RCCR_REF_CNT_MASK (0xFFFFU) 245 #define CMU_FC_RCCR_REF_CNT_SHIFT (0U) 246 #define CMU_FC_RCCR_REF_CNT_WIDTH (16U) 247 #define CMU_FC_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_RCCR_REF_CNT_SHIFT)) & CMU_FC_RCCR_REF_CNT_MASK) 248 /*! @} */ 249 250 /*! @name HTCR - High Threshold Configuration Register */ 251 /*! @{ */ 252 253 #define CMU_FC_HTCR_HFREF_MASK (0xFFFFFFU) 254 #define CMU_FC_HTCR_HFREF_SHIFT (0U) 255 #define CMU_FC_HTCR_HFREF_WIDTH (24U) 256 #define CMU_FC_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_HTCR_HFREF_SHIFT)) & CMU_FC_HTCR_HFREF_MASK) 257 /*! @} */ 258 259 /*! @name LTCR - Low Threshold Configuration Register */ 260 /*! @{ */ 261 262 #define CMU_FC_LTCR_LFREF_MASK (0xFFFFFFU) 263 #define CMU_FC_LTCR_LFREF_SHIFT (0U) 264 #define CMU_FC_LTCR_LFREF_WIDTH (24U) 265 #define CMU_FC_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_LTCR_LFREF_SHIFT)) & CMU_FC_LTCR_LFREF_MASK) 266 /*! @} */ 267 268 /*! @name SR - Status Register */ 269 /*! @{ */ 270 271 #define CMU_FC_SR_FLL_MASK (0x1U) 272 #define CMU_FC_SR_FLL_SHIFT (0U) 273 #define CMU_FC_SR_FLL_WIDTH (1U) 274 #define CMU_FC_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_FLL_SHIFT)) & CMU_FC_SR_FLL_MASK) 275 276 #define CMU_FC_SR_FHH_MASK (0x2U) 277 #define CMU_FC_SR_FHH_SHIFT (1U) 278 #define CMU_FC_SR_FHH_WIDTH (1U) 279 #define CMU_FC_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_FHH_SHIFT)) & CMU_FC_SR_FHH_MASK) 280 281 #define CMU_FC_SR_RS_MASK (0x10U) 282 #define CMU_FC_SR_RS_SHIFT (4U) 283 #define CMU_FC_SR_RS_WIDTH (1U) 284 #define CMU_FC_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_RS_SHIFT)) & CMU_FC_SR_RS_MASK) 285 286 #define CMU_FC_SR_AFI_FAIL_MASK (0x10000U) 287 #define CMU_FC_SR_AFI_FAIL_SHIFT (16U) 288 #define CMU_FC_SR_AFI_FAIL_WIDTH (1U) 289 #define CMU_FC_SR_AFI_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_AFI_FAIL_SHIFT)) & CMU_FC_SR_AFI_FAIL_MASK) 290 291 #define CMU_FC_SR_FI_PASS_MASK (0x100000U) 292 #define CMU_FC_SR_FI_PASS_SHIFT (20U) 293 #define CMU_FC_SR_FI_PASS_WIDTH (1U) 294 #define CMU_FC_SR_FI_PASS(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_FI_PASS_SHIFT)) & CMU_FC_SR_FI_PASS_MASK) 295 296 #define CMU_FC_SR_FI_COMP_MASK (0x800000U) 297 #define CMU_FC_SR_FI_COMP_SHIFT (23U) 298 #define CMU_FC_SR_FI_COMP_WIDTH (1U) 299 #define CMU_FC_SR_FI_COMP(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_FI_COMP_SHIFT)) & CMU_FC_SR_FI_COMP_MASK) 300 /*! @} */ 301 302 /*! @name IER - Interrupt Enable Register */ 303 /*! @{ */ 304 305 #define CMU_FC_IER_FLLIE_MASK (0x1U) 306 #define CMU_FC_IER_FLLIE_SHIFT (0U) 307 #define CMU_FC_IER_FLLIE_WIDTH (1U) 308 #define CMU_FC_IER_FLLIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FLLIE_SHIFT)) & CMU_FC_IER_FLLIE_MASK) 309 310 #define CMU_FC_IER_FHHIE_MASK (0x2U) 311 #define CMU_FC_IER_FHHIE_SHIFT (1U) 312 #define CMU_FC_IER_FHHIE_WIDTH (1U) 313 #define CMU_FC_IER_FHHIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FHHIE_SHIFT)) & CMU_FC_IER_FHHIE_MASK) 314 315 #define CMU_FC_IER_FLLAIE_MASK (0x4U) 316 #define CMU_FC_IER_FLLAIE_SHIFT (2U) 317 #define CMU_FC_IER_FLLAIE_WIDTH (1U) 318 #define CMU_FC_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FLLAIE_SHIFT)) & CMU_FC_IER_FLLAIE_MASK) 319 320 #define CMU_FC_IER_FHHAIE_MASK (0x8U) 321 #define CMU_FC_IER_FHHAIE_SHIFT (3U) 322 #define CMU_FC_IER_FHHAIE_WIDTH (1U) 323 #define CMU_FC_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FHHAIE_SHIFT)) & CMU_FC_IER_FHHAIE_MASK) 324 325 #define CMU_FC_IER_AFIFIE_MASK (0x10000U) 326 #define CMU_FC_IER_AFIFIE_SHIFT (16U) 327 #define CMU_FC_IER_AFIFIE_WIDTH (1U) 328 #define CMU_FC_IER_AFIFIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_AFIFIE_SHIFT)) & CMU_FC_IER_AFIFIE_MASK) 329 330 #define CMU_FC_IER_AFIAFIE_MASK (0x20000U) 331 #define CMU_FC_IER_AFIAFIE_SHIFT (17U) 332 #define CMU_FC_IER_AFIAFIE_WIDTH (1U) 333 #define CMU_FC_IER_AFIAFIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_AFIAFIE_SHIFT)) & CMU_FC_IER_AFIAFIE_MASK) 334 335 #define CMU_FC_IER_FIPIE_MASK (0x100000U) 336 #define CMU_FC_IER_FIPIE_SHIFT (20U) 337 #define CMU_FC_IER_FIPIE_WIDTH (1U) 338 #define CMU_FC_IER_FIPIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FIPIE_SHIFT)) & CMU_FC_IER_FIPIE_MASK) 339 340 #define CMU_FC_IER_FIAPIE_MASK (0x200000U) 341 #define CMU_FC_IER_FIAPIE_SHIFT (21U) 342 #define CMU_FC_IER_FIAPIE_WIDTH (1U) 343 #define CMU_FC_IER_FIAPIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FIAPIE_SHIFT)) & CMU_FC_IER_FIAPIE_MASK) 344 345 #define CMU_FC_IER_FICIE_MASK (0x800000U) 346 #define CMU_FC_IER_FICIE_SHIFT (23U) 347 #define CMU_FC_IER_FICIE_WIDTH (1U) 348 #define CMU_FC_IER_FICIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FICIE_SHIFT)) & CMU_FC_IER_FICIE_MASK) 349 /*! @} */ 350 351 /*! 352 * @} 353 */ /* end of group CMU_FC_Register_Masks */ 354 355 /*! 356 * @} 357 */ /* end of group CMU_FC_Peripheral_Access_Layer */ 358 359 #endif /* #if !defined(S32Z2_CMU_FC_H_) */ 360
