1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2017 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 * Rander Wang <rander.wang@intel.com> 8 */ 9 10 #ifdef __SOF_LIB_MEMORY_H__ 11 12 #ifndef __PLATFORM_LIB_MEMORY_H__ 13 #define __PLATFORM_LIB_MEMORY_H__ 14 15 #include <cavs/lib/memory.h> 16 #include <sof/lib/cpu.h> 17 18 /* prioritize definitions in Zephyr SoC layer */ 19 #ifdef __ZEPHYR__ 20 #include <adsp_memory.h> 21 #endif 22 23 /* physical DSP addresses */ 24 25 /* shim */ 26 #define SHIM_BASE 0x00071F00 27 #define SHIM_SIZE 0x00000100 28 29 /* Digital Mic Shim Registers */ 30 #define DMIC_SHIM_BASE 0x00071E80 31 #define DMICLCTL_OFFSET 0x04 32 #define DMICLCTL (DMIC_SHIM_BASE + DMICLCTL_OFFSET) 33 34 /* cmd IO to audio codecs */ 35 #define CMD_BASE 0x00001100 36 #define CMD_SIZE 0x00000010 37 38 /* resource allocation */ 39 #define RES_BASE 0x00001110 40 #define RES_SIZE 0x00000010 41 42 /* IPC to the host */ 43 #define IPC_HOST_BASE 0x00071E00 44 #define IPC_HOST_SIZE 0x00000020 45 46 /* intra DSP IPC */ 47 #define IPC_DSP_SIZE 0x00000080 48 #define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE) 49 50 /* SRAM window for HOST */ 51 #define HOST_WIN_SIZE 0x00000008 52 #define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE) 53 54 /* IRQ controller */ 55 #define IRQ_BASE 0x00078800 56 #define IRQ_SIZE 0x00000200 57 58 /* time stamping */ 59 #define TIME_BASE 0x00071800 60 #define TIME_SIZE 0x00000200 61 62 /* M/N dividers */ 63 #define MN_BASE 0x00078C00 64 #define MN_SIZE 0x00000200 65 66 /* low power DMA position */ 67 #define LP_GP_DMA_LINK_SIZE 0x00000010 68 #define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE) 69 70 /* high performance DMA position */ 71 #define HP_GP_DMA_LINK_SIZE 0x00000010 72 #define HP_GP_DMA_LINK_BASE(x) (0x00001D00 + x * HP_GP_DMA_LINK_SIZE) 73 74 /* link DMAC stream */ 75 #define GTW_LINK_OUT_STREAM_SIZE 0x00000020 76 #define GTW_LINK_OUT_STREAM_BASE(x) \ 77 (0x00072400 + x * GTW_LINK_OUT_STREAM_SIZE) 78 79 #define GTW_LINK_IN_STREAM_SIZE 0x00000020 80 #define GTW_LINK_IN_STREAM_BASE(x) \ 81 (0x00072600 + x * GTW_LINK_IN_STREAM_SIZE) 82 83 /* host DMAC stream */ 84 #define GTW_HOST_OUT_STREAM_SIZE 0x00000040 85 #define GTW_HOST_OUT_STREAM_BASE(x) \ 86 (0x00072800 + x * GTW_HOST_OUT_STREAM_SIZE) 87 88 #define GTW_HOST_IN_STREAM_SIZE 0x00000040 89 #define GTW_HOST_IN_STREAM_BASE(x) \ 90 (0x00072C00 + x * GTW_HOST_IN_STREAM_SIZE) 91 92 /* code loader */ 93 #define GTW_CODE_LDR_SIZE 0x00000040 94 #define GTW_CODE_LDR_BASE 0x00002BC0 95 96 /* L2 TLBs */ 97 #define L2_HP_SRAM_TLB_SIZE 0x00001000 98 #define L2_HP_SRAM_TLB_BASE 0x00003000 99 100 /* DMICs */ 101 #define DMIC_BASE 0x00010000 102 #define DMIC_SIZE 0x00008000 103 104 /* SSP */ 105 #define SSP_BASE(x) (0x00077000 + x * SSP_SIZE) 106 #define SSP_SIZE 0x0000200 107 108 /* ALH */ 109 #define ALH_BASE 0x000071000 110 #define ALH_TXDA_OFFSET 0x000000400 111 #define ALH_RXDA_OFFSET 0x000000500 112 #define ALH_STREAM_OFFSET 0x000000004 113 114 /* Timestamping */ 115 #define TIMESTAMP_BASE 0x00071800 116 117 /* low power DMACs */ 118 #define LP_GP_DMA_SIZE 0x00001000 119 #define LP_GP_DMA_BASE(x) (0x0007C000 + x * LP_GP_DMA_SIZE) 120 121 /* high performance DMACs */ 122 #define HP_GP_DMA_SIZE 0x00001000 123 #define HP_GP_DMA_BASE(x) (0x0000E000 + x * HP_GP_DMA_SIZE) 124 125 /* ROM */ 126 #define ROM_BASE 0xBEFE0000 127 #define ROM_SIZE 0x00002000 128 129 #define L2_VECTOR_SIZE 0x1000 130 131 #define UUID_ENTRY_ELF_BASE 0x1FFFA000 132 #define UUID_ENTRY_ELF_SIZE 0x6000 133 134 #define LOG_ENTRY_ELF_BASE 0x20000000 135 #define LOG_ENTRY_ELF_SIZE 0x2000000 136 137 #define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) 138 #define EXT_MANIFEST_ELF_SIZE 0x2000000 139 140 /* 141 * The HP SRAM Region on Tigerlake is organised like this :- 142 * +----------------------------------------------------------------------------+ 143 * | Offset | Region | Size | 144 * +--------------------+-------------------------+-----------------------------+ 145 * | SRAM_SW_REG_BASE | SW Registers W0 | SRAM_SW_REG_SIZE | 146 * +--------------------+-------------------------+-----------------------------+ 147 * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_OUTBOX_SIZE | 148 * +--------------------+-------------------------+-----------------------------+ 149 * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | 150 * +--------------------+-------------------------+-----------------------------+ 151 * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | 152 * +--------------------+-------------------------+-----------------------------+ 153 * | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE | 154 * +--------------------+-------------------------+-----------------------------+ 155 * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE | 156 * +--------------------+-------------------------+-----------------------------+ 157 * | SRAM_TRACE_BASE | Trace Buffer W3 | SRAM_TRACE_SIZE | 158 * +--------------------+-------------------------+-----------------------------+ 159 * | HEAP_HP_BUFFER_BASE| DMA | HEAP_HP_BUFFER_SIZE | 160 * +--------------------+-------------------------+-----------------------------+ 161 * | SOF_FW_START | text | | 162 * | | data | | 163 * | | BSS | | 164 * +--------------------+-------------------------+-----------------------------+ 165 * | | Runtime Heap | HEAP_RUNTIME_SIZE | 166 * +--------------------+-------------------------+-----------------------------+ 167 * | | Runtime shared Heap | HEAP_RUNTIME_SHARED_SIZE | 168 * | |-------------------------+-----------------------------+ 169 * | | System shared Heap | HEAP_SYSTEM_SHARED_SIZE | 170 * | |-------------------------+-----------------------------+ 171 * | | Module Buffers | HEAP_BUFFER_SIZE | 172 * +--------------------+-------------------------+-----------------------------+ 173 * | | Primary core Sys Heap | HEAP_SYSTEM_M_SIZE | 174 * +--------------------+-------------------------+-----------------------------+ 175 * | | Pri. Sys Runtime Heap | HEAP_SYS_RUNTIME_M_SIZE | 176 * +--------------------+-------------------------+-----------------------------+ 177 * | | Primary core Stack | SOF_STACK_SIZE | 178 * +--------------------+-------------------------+-----------------------------+ 179 * | | Sec. core Sys Heap | SOF_CORE_S_T_SIZE | 180 * | | Sec. Sys Runtime Heap | | 181 * | | Secondary core Stack | | 182 * +--------------------+-------------------------+-----------------------------+ 183 */ 184 185 /* HP SRAM */ 186 #define HP_SRAM_BASE 0xBE000000 187 188 /* HP SRAM windows */ 189 /* window 0 */ 190 #define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000) 191 #define SRAM_SW_REG_SIZE 0x1000 192 193 #define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) 194 #define SRAM_OUTBOX_SIZE 0x1000 195 196 /* window 1 */ 197 #define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) 198 #define SRAM_INBOX_SIZE 0x2000 199 /* window 2 */ 200 #define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) 201 #define SRAM_DEBUG_SIZE 0x800 202 203 #define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) 204 #define SRAM_EXCEPT_SIZE 0x800 205 206 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) 207 #define SRAM_STREAM_SIZE 0x1000 208 209 /* window 3 */ 210 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) 211 #if CONFIG_TRACE 212 #define SRAM_TRACE_SIZE 0x2000 213 #else 214 #define SRAM_TRACE_SIZE 0x0 215 #endif 216 217 #define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE 218 #define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) 219 #define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE 220 #define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE 221 #define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE 222 #define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \ 223 SRAM_STREAM_SIZE) 224 #define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE 225 #define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE 226 227 #define HEAP_HP_BUFFER_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) 228 #define HEAP_HP_BUFFER_SIZE 0x20000 229 #define HEAP_HP_BUFFER_BLOCK_SIZE 0x180 230 #define HEAP_HP_BUFFER_COUNT \ 231 (HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE) 232 233 /* HP SRAM Base */ 234 #define HP_SRAM_VECBASE_RESET (HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE) 235 236 /* text and data share the same HP L2 SRAM on Tigerlake */ 237 #define SOF_FW_START (HP_SRAM_VECBASE_RESET + 0x400) 238 #define SOF_FW_BASE (SOF_FW_START) 239 240 /* max size for all var-size sections (text/rodata/bss) */ 241 #define SOF_FW_MAX_SIZE (HP_SRAM_BASE + HP_SRAM_SIZE - SOF_FW_BASE) 242 243 #define SOF_FW_END (HP_SRAM_BASE + HP_SRAM_SIZE) 244 245 #define SOF_TEXT_START (SOF_FW_START) 246 #define SOF_TEXT_BASE (SOF_FW_START) 247 248 /* Heap section sizes for system runtime heap for primary core */ 249 #define HEAP_SYS_RT_0_COUNT64 128 250 #define HEAP_SYS_RT_0_COUNT512 16 251 #define HEAP_SYS_RT_0_COUNT1024 4 252 253 /* Heap section sizes for system runtime heap for secondary core */ 254 #define HEAP_SYS_RT_X_COUNT64 64 255 #define HEAP_SYS_RT_X_COUNT512 8 256 #define HEAP_SYS_RT_X_COUNT1024 4 257 258 /* Heap section counts base */ 259 #define HEAP_COUNT64 128 260 #define HEAP_COUNT128 128 261 #define HEAP_COUNT256 96 262 #define HEAP_COUNT512 8 263 #define HEAP_COUNT1024 4 264 #define HEAP_COUNT2048 2 265 #define HEAP_COUNT4096 1 266 267 #if HP_SRAM_SIZE < 0x200000 268 #define RT_TIMES 3 269 #define RT_SHARED_TIMES 6 270 #else 271 /* Reserve more memory for RTNR */ 272 #if defined(CONFIG_COMP_RTNR) || defined(CONFIG_COMP_GOOGLE_RTC_AUDIO_PROCESSING) 273 #define RT_TIMES 2 274 #define RT_SHARED_TIMES 4 275 #else 276 #define RT_TIMES 8 277 #define RT_SHARED_TIMES 16 278 #endif /* CONFIG_COMP_RTNR */ 279 #endif 280 281 /* Heap section sizes for module pool */ 282 #define HEAP_RT_COUNT64 (HEAP_COUNT64 * RT_TIMES) 283 #define HEAP_RT_COUNT128 (HEAP_COUNT128 * RT_TIMES) 284 #define HEAP_RT_COUNT256 (HEAP_COUNT256 * RT_TIMES) 285 #define HEAP_RT_COUNT512 (HEAP_COUNT512 * RT_TIMES) 286 #define HEAP_RT_COUNT1024 (HEAP_COUNT1024 * RT_TIMES) 287 #define HEAP_RT_COUNT2048 (HEAP_COUNT2048 * RT_TIMES) 288 #define HEAP_RT_COUNT4096 (HEAP_COUNT4096 * RT_TIMES) 289 290 /* Heap configuration */ 291 #define HEAP_RUNTIME_SIZE \ 292 (HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \ 293 HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \ 294 HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + \ 295 HEAP_RT_COUNT4096 * 4096) 296 297 /* Heap section sizes for runtime shared heap */ 298 #define HEAP_RUNTIME_SHARED_COUNT64 (HEAP_COUNT64 * RT_SHARED_TIMES) 299 #define HEAP_RUNTIME_SHARED_COUNT128 (HEAP_COUNT128 * RT_SHARED_TIMES) 300 #define HEAP_RUNTIME_SHARED_COUNT256 (HEAP_COUNT256 * RT_SHARED_TIMES) 301 #define HEAP_RUNTIME_SHARED_COUNT512 (HEAP_COUNT512 * RT_SHARED_TIMES) 302 #define HEAP_RUNTIME_SHARED_COUNT1024 (HEAP_COUNT1024 * RT_SHARED_TIMES) 303 304 #define HEAP_RUNTIME_SHARED_SIZE \ 305 (HEAP_RUNTIME_SHARED_COUNT64 * 64 + HEAP_RUNTIME_SHARED_COUNT128 * 128 + \ 306 HEAP_RUNTIME_SHARED_COUNT256 * 256 + HEAP_RUNTIME_SHARED_COUNT512 * 512 + \ 307 HEAP_RUNTIME_SHARED_COUNT1024 * 1024) 308 309 /* Heap section sizes for system shared heap */ 310 #define HEAP_SYSTEM_SHARED_SIZE 0x1500 311 312 #define HEAP_BUFFER_BLOCK_SIZE 0x100 313 #define HEAP_BUFFER_COUNT_MAX (HP_SRAM_SIZE / HEAP_BUFFER_BLOCK_SIZE) 314 315 #define HEAP_SYSTEM_M_SIZE 0x8000 /* heap primary core size */ 316 #define HEAP_SYSTEM_S_SIZE 0x6000 /* heap secondary core size */ 317 #define HEAP_SYSTEM_T_SIZE \ 318 (HEAP_SYSTEM_M_SIZE + ((CONFIG_CORE_COUNT - 1) * HEAP_SYSTEM_S_SIZE)) 319 320 #define HEAP_SYS_RUNTIME_M_SIZE \ 321 (HEAP_SYS_RT_0_COUNT64 * 64 + HEAP_SYS_RT_0_COUNT512 * 512 + \ 322 HEAP_SYS_RT_0_COUNT1024 * 1024) 323 324 #define HEAP_SYS_RUNTIME_S_SIZE \ 325 (HEAP_SYS_RT_X_COUNT64 * 64 + HEAP_SYS_RT_X_COUNT512 * 512 + \ 326 HEAP_SYS_RT_X_COUNT1024 * 1024) 327 328 #define HEAP_SYS_RUNTIME_T_SIZE \ 329 (HEAP_SYS_RUNTIME_M_SIZE + ((CONFIG_CORE_COUNT - 1) * \ 330 HEAP_SYS_RUNTIME_S_SIZE)) 331 332 /* Stack configuration */ 333 #define SOF_STACK_SIZE (CONFIG_SOF_STACK_SIZE) 334 #define SOF_STACK_TOTAL_SIZE (CONFIG_CORE_COUNT * SOF_STACK_SIZE) 335 336 /* SOF Core S configuration */ 337 #define SOF_CORE_S_SIZE \ 338 ALIGN((HEAP_SYSTEM_S_SIZE + HEAP_SYS_RUNTIME_S_SIZE + SOF_STACK_SIZE),\ 339 SRAM_BANK_SIZE) 340 #define SOF_CORE_S_T_SIZE ((CONFIG_CORE_COUNT - 1) * SOF_CORE_S_SIZE) 341 342 /* 343 * The LP SRAM Heap and Stack on Tigerlake are organised like this :- 344 * 345 * +--------------------------------------------------------------------------+ 346 * | Offset | Region | Size | 347 * +---------------------+----------------+-----------------------------------+ 348 * | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE | 349 * | | Data | | 350 * | | BSS | | 351 * +---------------------+----------------+-----------------------------------+ 352 * | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE | 353 * +---------------------+----------------+-----------------------------------+ 354 * | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE | 355 * +---------------------+----------------+-----------------------------------+ 356 * | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE | 357 * +---------------------+----------------+-----------------------------------+ 358 * | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE | 359 * +---------------------+----------------+-----------------------------------+ 360 * | SOF_STACK_BASE | | | 361 * +---------------------+----------------+-----------------------------------+ 362 */ 363 364 /* LP SRAM */ 365 #ifndef __ZEPHYR__ 366 #define LP_SRAM_BASE 0xBE800000 367 #endif 368 369 #if CONFIG_MULTICORE 370 /* alternate reset vector */ 371 #define LP_SRAM_ALT_RESET_VEC_BASE LP_SRAM_BASE 372 #define LP_SRAM_ALT_RESET_VEC_SIZE 0x180 373 374 #define LP_SRAM_ALT_RESET_INT_VEC_BASE (LP_SRAM_ALT_RESET_VEC_BASE + \ 375 LP_SRAM_ALT_RESET_VEC_SIZE) 376 #define LP_SRAM_ALT_RESET_INT_VEC_SIZE 0x10 377 378 #define LP_SRAM_CODE_BASE (LP_SRAM_ALT_RESET_INT_VEC_BASE + \ 379 LP_SRAM_ALT_RESET_INT_VEC_SIZE) 380 #define LP_SRAM_CODE_SIZE 0x220 381 382 #define LP_SRAM_START (LP_SRAM_CODE_BASE + LP_SRAM_CODE_SIZE) 383 #else 384 #define LP_SRAM_START LP_SRAM_BASE 385 #endif 386 387 #if (CONFIG_CAVS_LPS) 388 #define LPS_RESTORE_VECTOR_OFFSET 0x1000 389 #define LPS_RESTORE_VECTOR_SIZE 0x800 390 #define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET) 391 #define HEAP_LP_BUFFER_BASE (LPS_RESTORE_VECTOR_ADDR + LPS_RESTORE_VECTOR_SIZE) 392 #define HEAP_LP_BUFFER_SIZE (LP_SRAM_SIZE - LPS_RESTORE_VECTOR_SIZE -\ 393 LPS_RESTORE_VECTOR_OFFSET) 394 #else 395 #define HEAP_LP_BUFFER_BASE LP_SRAM_START 396 #define HEAP_LP_BUFFER_SIZE (LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)) 397 #endif 398 399 #define HEAP_LP_BUFFER_BLOCK_SIZE 0x180 400 401 #if CONFIG_LP_MEMORY_BANKS 402 #define HEAP_LP_BUFFER_COUNT \ 403 (HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE) 404 #else 405 #define HEAP_LP_BUFFER_COUNT 0 406 #endif 407 408 #define PLATFORM_HEAP_SYSTEM CONFIG_CORE_COUNT /* one per core */ 409 #define PLATFORM_HEAP_SYSTEM_RUNTIME CONFIG_CORE_COUNT /* one per core */ 410 #define PLATFORM_HEAP_RUNTIME 1 411 #define PLATFORM_HEAP_RUNTIME_SHARED 1 412 #define PLATFORM_HEAP_SYSTEM_SHARED 1 413 #define PLATFORM_HEAP_BUFFER 2 414 415 /* Stack configuration */ 416 #define SOF_LP_STACK_SIZE 0x1000 417 #define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE) 418 #define SOF_LP_STACK_END (SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE) 419 420 421 /* Vector and literal sizes - do not use core-isa.h */ 422 #define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET 423 #define SOF_MEM_VECT_LIT_SIZE 0x8 424 #define SOF_MEM_VECT_TEXT_SIZE 0x38 425 #define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + \ 426 SOF_MEM_VECT_LIT_SIZE) 427 428 /* Size of dynamic vectors unpacked from WindowOverflow4 */ 429 #define SOF_DYNAMIC_VECTORS_SIZE 0x400 430 431 #define SOF_MEM_ERROR_TEXT_SIZE 0x180 432 #define SOF_MEM_ERROR_LIT_SIZE 0x8 433 434 #define SOF_MEM_RESET_TEXT_SIZE 0x268 435 #define SOF_MEM_RESET_LIT_SIZE 0x8 436 #define SOF_MEM_VECBASE_LIT_SIZE 0x178 437 438 #define SOF_MEM_RO_SIZE 0x8 439 440 /* VM ROM sizes */ 441 #define ROM_RESET_TEXT_SIZE 0x400 442 #define ROM_RESET_LIT_SIZE 0x200 443 444 /* boot loader in IMR */ 445 446 #ifndef __ZEPHYR__ 447 #define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 448 #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 449 450 #ifndef IMR_BOOT_LDR_TEXT_ENTRY_BASE 451 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000 452 #endif 453 454 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x120 455 #endif 456 457 #define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \ 458 IMR_BOOT_LDR_TEXT_ENTRY_SIZE) 459 #define IMR_BOOT_LDR_LIT_SIZE 0x22 460 #define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + \ 461 IMR_BOOT_LDR_LIT_SIZE) 462 #define IMR_BOOT_LDR_TEXT_SIZE 0x1C00 463 #define IMR_BOOT_LDR_DATA_BASE 0xB0039000 464 #define IMR_BOOT_LDR_DATA_SIZE 0x1000 465 #define IMR_BOOT_LDR_BSS_BASE 0xB0100000 466 #define IMR_BOOT_LDR_BSS_SIZE 0x10000 467 468 /* Temporary stack place for boot_ldr */ 469 #define BOOT_LDR_STACK_BASE HEAP_HP_BUFFER_BASE 470 #define BOOT_LDR_STACK_SIZE SOF_STACK_TOTAL_SIZE 471 472 /* L1 memory */ 473 #define L1_MEM_BASE 0x9F000000 474 #define L1_DRAM_SIZE (CONFIG_L1_DRAM_BANKS * CONFIG_L1_DRAM_BANK_SIZE) 475 #define L1_MEM_REG_BASE 0x9F080000 476 #define L1_MEM_CAP (L1_MEM_REG_BASE + 0x00) 477 #define L1_MEM_DRAM_PGCTL (L1_MEM_REG_BASE + 0x20) 478 #define L1_MEM_DRAM_PGISTS (L1_MEM_REG_BASE + 0x28) 479 480 /* L1 init */ 481 #define L1CC_ADDR (0x9F080080) 482 #define CxL1CCAP (L1CC_ADDR + 0x0000) 483 #define CxL1CCFG (L1CC_ADDR + 0x0004) 484 #define CxL1PCFG (L1CC_ADDR + 0x0008) 485 486 #define L1_CACHE_ALL_DATA_WAY_ENABLED_MASK (BIT(XCHAL_DCACHE_WAYS) - 1) 487 #define L1_CACHE_ALL_INSTR_WAY_ENABLED_MASK ((BIT(XCHAL_ICACHE_WAYS) - 1) << 8) 488 #define L1_CACHE_ALL_WAY_ENABLED_MASK ((L1_CACHE_ALL_DATA_WAY_ENABLED_MASK) \ 489 | (L1_CACHE_ALL_INSTR_WAY_ENABLED_MASK)) 490 #define L1_CACHE_ALL_WAY_ACTIVE_MASK (L1_CACHE_ALL_WAY_ENABLED_MASK << 16) 491 492 #define L1_CACHE_ONE_DATA_WAY_ENABLED_MASK BIT(0) 493 #define L1_CACHE_ONE_INSTR_WAY_ENABLED_MASK BIT(8) 494 #define L1_CACHE_ONE_WAY_ENABLED_MASK (L1_CACHE_ONE_DATA_WAY_ENABLED_MASK \ 495 | L1_CACHE_ONE_INSTR_WAY_ENABLED_MASK) 496 #define L1_CACHE_ONE_WAY_ACTIVE_MASK (L1_CACHE_ONE_WAY_ENABLED_MASK << 16) 497 498 #define L1_CACHE_PREFETCHER_ENABLED 1 499 #define L1_CACHE_PREFETCHER_ACTIVE 0x10000 500 501 #define L1_CACHE_PREFCTL_VALUE 0x1038 502 503 #define host_to_local(addr) (addr) 504 #define local_to_host(addr) (addr) 505 506 #endif /* __PLATFORM_LIB_MEMORY_H__ */ 507 508 #else 509 510 #error "This file shouldn't be included from outside of sof/lib/memory.h" 511 512 #endif /* __SOF_LIB_MEMORY_H__ */ 513
