1 /*! 2 \file gd32f4xx.h 3 \brief general definitions for GD32F4xx 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F4XX_H 38 #define GD32F4XX_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* define GD32F4xx */ 45 #if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) 46 /* #define GD32F450 */ 47 /* #define GD32F405 */ 48 /* #define GD32F407 */ 49 /* #define GD32F470 */ 50 /* #define GD32F425 */ 51 /* #define GD32F427 */ 52 #endif /* define GD32F4xx */ 53 54 #if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) 55 #error "Please select the target GD32F4xx device in gd32f4xx.h file" 56 #endif /* undefine GD32F4xx tip */ 57 58 /* define value of high speed crystal oscillator (HXTAL) in Hz */ 59 #if !defined (HXTAL_VALUE) 60 #define HXTAL_VALUE ((uint32_t)25000000) 61 #endif /* high speed crystal oscillator value */ 62 63 /* define startup timeout value of high speed crystal oscillator (HXTAL) */ 64 #if !defined (HXTAL_STARTUP_TIMEOUT) 65 #define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) 66 #endif /* high speed crystal oscillator startup timeout */ 67 68 /* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ 69 #if !defined (IRC16M_VALUE) 70 #define IRC16M_VALUE ((uint32_t)16000000) 71 #endif /* internal 16MHz RC oscillator value */ 72 73 /* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */ 74 #if !defined (IRC16M_STARTUP_TIMEOUT) 75 #define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500) 76 #endif /* internal 16MHz RC oscillator startup timeout */ 77 78 /* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ 79 #if !defined (IRC32K_VALUE) 80 #define IRC32K_VALUE ((uint32_t)32000) 81 #endif /* internal 32KHz RC oscillator value */ 82 83 /* define value of low speed crystal oscillator (LXTAL)in Hz */ 84 #if !defined (LXTAL_VALUE) 85 #define LXTAL_VALUE ((uint32_t)32768) 86 #endif /* low speed crystal oscillator value */ 87 88 /* I2S external clock in selection */ 89 //#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U 90 91 /* GD32F4xx firmware library version number V1.0 */ 92 #define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ 93 #define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ 94 #define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ 95 #define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ 96 #define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\ 97 |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\ 98 |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\ 99 |(__GD32F4xx_STDPERIPH_VERSION_RC)) 100 101 /* configuration of the cortex-M4 processor and core peripherals */ 102 #define __CM4_REV 0x0001 /*!< core revision r0p1 */ 103 #define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */ 104 #define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */ 105 #define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ 106 #define __FPU_PRESENT 1 /*!< FPU present */ 107 /* define interrupt number */ 108 typedef enum IRQn 109 { 110 /* cortex-M4 processor exceptions numbers */ 111 NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ 112 MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */ 113 BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */ 114 UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */ 115 SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */ 116 DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */ 117 PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */ 118 SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */ 119 /* interruput numbers */ 120 WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ 121 LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ 122 TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */ 123 RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */ 124 FMC_IRQn = 4, /*!< FMC interrupt */ 125 RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ 126 EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ 127 EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ 128 EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ 129 EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ 130 EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ 131 DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */ 132 DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */ 133 DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ 134 DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ 135 DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ 136 DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ 137 DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ 138 ADC_IRQn = 18, /*!< ADC interrupt */ 139 CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */ 140 CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */ 141 CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ 142 CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ 143 EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ 144 TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ 145 TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ 146 TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ 147 TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ 148 TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ 149 TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ 150 TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ 151 I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ 152 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 153 I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ 154 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 155 SPI0_IRQn = 35, /*!< SPI0 interrupt */ 156 SPI1_IRQn = 36, /*!< SPI1 interrupt */ 157 USART0_IRQn = 37, /*!< USART0 interrupt */ 158 USART1_IRQn = 38, /*!< USART1 interrupt */ 159 USART2_IRQn = 39, /*!< USART2 interrupt */ 160 EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ 161 RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ 162 USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ 163 TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ 164 TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ 165 TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ 166 TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ 167 DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ 168 169 #if defined (GD32F450) || defined (GD32F470) 170 EXMC_IRQn = 48, /*!< EXMC interrupt */ 171 SDIO_IRQn = 49, /*!< SDIO interrupt */ 172 TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ 173 SPI2_IRQn = 51, /*!< SPI2 interrupt */ 174 UART3_IRQn = 52, /*!< UART3 interrupt */ 175 UART4_IRQn = 53, /*!< UART4 interrupt */ 176 TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ 177 TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ 178 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ 179 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ 180 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ 181 DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ 182 DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ 183 ENET_IRQn = 61, /*!< ENET interrupt */ 184 ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ 185 CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ 186 CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ 187 CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ 188 CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ 189 USBFS_IRQn = 67, /*!< USBFS interrupt */ 190 DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ 191 DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ 192 DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ 193 USART5_IRQn = 71, /*!< USART5 interrupt */ 194 I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ 195 I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ 196 USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ 197 USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ 198 USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ 199 USBHS_IRQn = 77, /*!< USBHS interrupt */ 200 DCI_IRQn = 78, /*!< DCI interrupt */ 201 TRNG_IRQn = 80, /*!< TRNG interrupt */ 202 FPU_IRQn = 81, /*!< FPU interrupt */ 203 UART6_IRQn = 82, /*!< UART6 interrupt */ 204 UART7_IRQn = 83, /*!< UART7 interrupt */ 205 SPI3_IRQn = 84, /*!< SPI3 interrupt */ 206 SPI4_IRQn = 85, /*!< SPI4 interrupt */ 207 SPI5_IRQn = 86, /*!< SPI5 interrupt */ 208 TLI_IRQn = 88, /*!< TLI interrupt */ 209 TLI_ER_IRQn = 89, /*!< TLI error interrupt */ 210 IPA_IRQn = 90, /*!< IPA interrupt */ 211 #endif /* GD32F450 and GD32F470 */ 212 213 #if defined (GD32F405) || defined (GD32F425) 214 SDIO_IRQn = 49, /*!< SDIO interrupt */ 215 TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ 216 SPI2_IRQn = 51, /*!< SPI2 interrupt */ 217 UART3_IRQn = 52, /*!< UART3 interrupt */ 218 UART4_IRQn = 53, /*!< UART4 interrupt */ 219 TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ 220 TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ 221 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ 222 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ 223 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ 224 DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ 225 DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ 226 CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ 227 CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ 228 CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ 229 CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ 230 USBFS_IRQn = 67, /*!< USBFS interrupt */ 231 DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ 232 DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ 233 DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ 234 USART5_IRQn = 71, /*!< USART5 interrupt */ 235 I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ 236 I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ 237 USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */ 238 USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ 239 USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ 240 USBHS_IRQn = 77, /*!< USBHS interrupt */ 241 DCI_IRQn = 78, /*!< DCI interrupt */ 242 TRNG_IRQn = 80, /*!< TRNG interrupt */ 243 FPU_IRQn = 81, /*!< FPU interrupt */ 244 #endif /* GD32F405 and GD32F425 */ 245 246 #if defined (GD32F407) || defined (GD32F427) 247 EXMC_IRQn = 48, /*!< EXMC interrupt */ 248 SDIO_IRQn = 49, /*!< SDIO interrupt */ 249 TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ 250 SPI2_IRQn = 51, /*!< SPI2 interrupt */ 251 UART3_IRQn = 52, /*!< UART3 interrupt */ 252 UART4_IRQn = 53, /*!< UART4 interrupt */ 253 TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ 254 TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ 255 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ 256 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ 257 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ 258 DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ 259 DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ 260 ENET_IRQn = 61, /*!< ENET interrupt */ 261 ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ 262 CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ 263 CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ 264 CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ 265 CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ 266 USBFS_IRQn = 67, /*!< USBFS interrupt */ 267 DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ 268 DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ 269 DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ 270 USART5_IRQn = 71, /*!< USART5 interrupt */ 271 I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ 272 I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ 273 USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ 274 USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ 275 USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ 276 USBHS_IRQn = 77, /*!< USBHS interrupt */ 277 DCI_IRQn = 78, /*!< DCI interrupt */ 278 TRNG_IRQn = 80, /*!< TRNG interrupt */ 279 FPU_IRQn = 81, /*!< FPU interrupt */ 280 #endif /* GD32F407 and GD32F427 */ 281 282 } IRQn_Type; 283 284 /* includes */ 285 #include "core_cm4.h" 286 #include "system_gd32f4xx.h" 287 #include <stdint.h> 288 289 /* enum definitions */ 290 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; 291 typedef enum {RESET = 0, SET = !RESET} FlagStatus; 292 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; 293 294 /* bit operations */ 295 #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) 296 #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) 297 #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) 298 #ifndef BIT 299 #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) 300 #endif /* BIT */ 301 #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 302 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) 303 304 /* main flash and SRAM memory map */ 305 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ 306 #define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */ 307 #define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */ 308 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ 309 310 /* peripheral memory map */ 311 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ 312 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ 313 #define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ 314 #define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */ 315 316 /* EXMC memory map */ 317 #define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ 318 319 /* advanced peripheral bus 1 memory map */ 320 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ 321 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ 322 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ 323 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ 324 #define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */ 325 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ 326 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ 327 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ 328 #define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ 329 #define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */ 330 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ 331 #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ 332 #define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */ 333 334 /* advanced peripheral bus 2 memory map */ 335 #define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */ 336 #define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */ 337 #define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */ 338 #define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */ 339 #define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */ 340 /* advanced high performance bus 1 memory map */ 341 #define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */ 342 #define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ 343 #define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */ 344 #define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */ 345 #define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */ 346 #define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */ 347 #define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */ 348 #define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */ 349 #define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */ 350 351 /* advanced high performance bus 2 memory map */ 352 #define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */ 353 #define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */ 354 #define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */ 355 /* option byte and debug memory map */ 356 #define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */ 357 #define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ 358 359 /* define marco USE_STDPERIPH_DRIVER */ 360 #if !defined USE_STDPERIPH_DRIVER 361 #define USE_STDPERIPH_DRIVER 362 #endif 363 #ifdef USE_STDPERIPH_DRIVER 364 #include "gd32f4xx_libopt.h" 365 #endif /* USE_STDPERIPH_DRIVER */ 366 367 #ifdef __cplusplus 368 } 369 #endif 370 #endif 371
