1 // Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #pragma once 15 16 #include "soc.h" 17 18 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ 19 /* Output enable in sleep mode */ 20 #define SLP_OE (BIT(0)) 21 #define SLP_OE_M (BIT(0)) 22 #define SLP_OE_V 1 23 #define SLP_OE_S 0 24 /* Pin used for wakeup from sleep */ 25 #define SLP_SEL (BIT(1)) 26 #define SLP_SEL_M (BIT(1)) 27 #define SLP_SEL_V 1 28 #define SLP_SEL_S 1 29 /* Pulldown enable in sleep mode */ 30 #define SLP_PD (BIT(2)) 31 #define SLP_PD_M (BIT(2)) 32 #define SLP_PD_V 1 33 #define SLP_PD_S 2 34 /* Pullup enable in sleep mode */ 35 #define SLP_PU (BIT(3)) 36 #define SLP_PU_M (BIT(3)) 37 #define SLP_PU_V 1 38 #define SLP_PU_S 3 39 /* Input enable in sleep mode */ 40 #define SLP_IE (BIT(4)) 41 #define SLP_IE_M (BIT(4)) 42 #define SLP_IE_V 1 43 #define SLP_IE_S 4 44 /* Drive strength in sleep mode */ 45 #define SLP_DRV 0x3 46 #define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) 47 #define SLP_DRV_V 0x3 48 #define SLP_DRV_S 5 49 /* Pulldown enable */ 50 #define FUN_PD (BIT(7)) 51 #define FUN_PD_M (BIT(7)) 52 #define FUN_PD_V 1 53 #define FUN_PD_S 7 54 /* Pullup enable */ 55 #define FUN_PU (BIT(8)) 56 #define FUN_PU_M (BIT(8)) 57 #define FUN_PU_V 1 58 #define FUN_PU_S 8 59 /* Input enable */ 60 #define FUN_IE (BIT(9)) 61 #define FUN_IE_M (FUN_IE_V << FUN_IE_S) 62 #define FUN_IE_V 1 63 #define FUN_IE_S 9 64 /* Drive strength */ 65 #define FUN_DRV 0x3 66 #define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) 67 #define FUN_DRV_V 0x3 68 #define FUN_DRV_S 10 69 /* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ 70 #define MCU_SEL 0x7 71 #define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) 72 #define MCU_SEL_V 0x7 73 #define MCU_SEL_S 12 74 75 #define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) 76 #define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) 77 #define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) 78 #define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) 79 #define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) 80 #define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) 81 #define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) 82 #define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) 83 #define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) 84 #define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) 85 86 #define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) 87 #define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) 88 #define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); 89 #define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) 90 #define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) 91 #define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) 92 #define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) 93 #define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) 94 95 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U 96 #define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U 97 #define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U 98 #define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U 99 #define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U 100 #define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U 101 #define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U 102 #define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U 103 #define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U 104 #define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U 105 #define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U 106 #define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U 107 #define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U 108 #define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U 109 #define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U 110 #define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U 111 #define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U 112 #define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U 113 #define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U 114 #define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U 115 #define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U 116 #define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U 117 #define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U 118 #define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U 119 #define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U 120 #define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U 121 #define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U 122 #define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U 123 #define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U 124 #define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U 125 #define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U 126 #define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U 127 #define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U 128 #define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U 129 #define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U 130 #define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U 131 #define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U 132 #define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U 133 #define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U 134 #define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U 135 #define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U 136 #define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U 137 #define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U 138 #define IO_MUX_GPIO47_REG PERIPHS_IO_MUX_SPICLK_P_U 139 #define IO_MUX_GPIO48_REG PERIPHS_IO_MUX_SPICLK_N_U 140 141 #define FUNC_GPIO_GPIO 1 142 #define PIN_FUNC_GPIO 1 143 144 #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) 145 #define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) 146 #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) 147 148 #define SPI_CS1_GPIO_NUM 26 149 #define SPI_HD_GPIO_NUM 27 150 #define SPI_WP_GPIO_NUM 28 151 #define SPI_CS0_GPIO_NUM 29 152 #define SPI_CLK_GPIO_NUM 30 153 #define SPI_Q_GPIO_NUM 31 154 #define SPI_D_GPIO_NUM 32 155 #define SPI_D4_GPIO_NUM 33 156 #define SPI_D5_GPIO_NUM 34 157 #define SPI_D6_GPIO_NUM 35 158 #define SPI_D7_GPIO_NUM 36 159 #define SPI_DQS_GPIO_NUM 37 160 #define SD_CLK_GPIO_NUM 12 161 #define SD_CMD_GPIO_NUM 11 162 #define SD_DATA0_GPIO_NUM 13 163 #define SD_DATA1_GPIO_NUM 14 164 #define SD_DATA2_GPIO_NUM 9 165 #define SD_DATA3_GPIO_NUM 10 166 167 #define MAX_RTC_GPIO_NUM 21 168 #define MAX_PAD_GPIO_NUM 48 169 #define MAX_GPIO_NUM 53 170 171 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE 172 #define PIN_CTRL (REG_IO_MUX_BASE +0x00) 173 #define PAD_POWER_SEL BIT(15) 174 #define PAD_POWER_SEL_V 0x1 175 #define PAD_POWER_SEL_M BIT(15) 176 #define PAD_POWER_SEL_S 15 177 178 179 #define PAD_POWER_SWITCH_DELAY 0x7 180 #define PAD_POWER_SWITCH_DELAY_V 0x7 181 #define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) 182 #define PAD_POWER_SWITCH_DELAY_S 12 183 184 185 #define CLK_OUT3 0xf 186 #define CLK_OUT3_V CLK_OUT3 187 #define CLK_OUT3_S 8 188 #define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) 189 #define CLK_OUT2 0xf 190 #define CLK_OUT2_V CLK_OUT2 191 #define CLK_OUT2_S 4 192 #define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) 193 #define CLK_OUT1 0xf 194 #define CLK_OUT1_V CLK_OUT1 195 #define CLK_OUT1_S 0 196 #define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) 197 198 #define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04) 199 #define FUNC_GPIO0_GPIO0 1 200 #define FUNC_GPIO0_GPIO0_0 0 201 202 #define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08) 203 #define FUNC_GPIO1_GPIO1 1 204 #define FUNC_GPIO1_GPIO1_0 0 205 206 #define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c) 207 #define FUNC_GPIO2_GPIO2 1 208 #define FUNC_GPIO2_GPIO2_0 0 209 210 #define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10) 211 #define FUNC_GPIO3_GPIO3 1 212 #define FUNC_GPIO3_GPIO3_0 0 213 214 #define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14) 215 #define FUNC_GPIO4_GPIO4 1 216 #define FUNC_GPIO4_GPIO4_0 0 217 218 #define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18) 219 #define FUNC_GPIO5_GPIO5 1 220 #define FUNC_GPIO5_GPIO5_0 0 221 222 #define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c) 223 #define FUNC_GPIO6_GPIO6 1 224 #define FUNC_GPIO6_GPIO6_0 0 225 226 #define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20) 227 #define FUNC_GPIO7_GPIO7 1 228 #define FUNC_GPIO7_GPIO7_0 0 229 230 #define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24) 231 #define FUNC_GPIO8_SUBSPICS1 3 232 #define FUNC_GPIO8_GPIO8 1 233 #define FUNC_GPIO8_GPIO8_0 0 234 235 #define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28) 236 #define FUNC_GPIO9_FSPIHD 4 237 #define FUNC_GPIO9_SUBSPIHD 3 238 #define FUNC_GPIO9_GPIO9 1 239 #define FUNC_GPIO9_GPIO9_0 0 240 241 #define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c) 242 #define FUNC_GPIO10_FSPICS0 4 243 #define FUNC_GPIO10_SUBSPICS0 3 244 #define FUNC_GPIO10_FSPIIO4 2 245 #define FUNC_GPIO10_GPIO10 1 246 #define FUNC_GPIO10_GPIO10_0 0 247 248 #define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30) 249 #define FUNC_GPIO11_FSPID 4 250 #define FUNC_GPIO11_SUBSPID 3 251 #define FUNC_GPIO11_FSPIIO5 2 252 #define FUNC_GPIO11_GPIO11 1 253 #define FUNC_GPIO11_GPIO11_0 0 254 255 #define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34) 256 #define FUNC_GPIO12_FSPICLK 4 257 #define FUNC_GPIO12_SUBSPICLK 3 258 #define FUNC_GPIO12_FSPIIO6 2 259 #define FUNC_GPIO12_GPIO12 1 260 #define FUNC_GPIO12_GPIO12_0 0 261 262 #define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38) 263 #define FUNC_GPIO13_FSPIQ 4 264 #define FUNC_GPIO13_SUBSPIQ 3 265 #define FUNC_GPIO13_FSPIIO7 2 266 #define FUNC_GPIO13_GPIO13 1 267 #define FUNC_GPIO13_GPIO13_0 0 268 269 #define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c) 270 #define FUNC_GPIO14_FSPIWP 4 271 #define FUNC_GPIO14_SUBSPIWP 3 272 #define FUNC_GPIO14_FSPIDQS 2 273 #define FUNC_GPIO14_GPIO14 1 274 #define FUNC_GPIO14_GPIO14_0 0 275 276 #define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40) 277 #define FUNC_XTAL_32K_P_U0RTS 2 278 #define FUNC_XTAL_32K_P_GPIO15 1 279 #define FUNC_XTAL_32K_P_GPIO15_0 0 280 281 #define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44) 282 #define FUNC_XTAL_32K_N_U0CTS 2 283 #define FUNC_XTAL_32K_N_GPIO16 1 284 #define FUNC_XTAL_32K_N_GPIO16_0 0 285 286 #define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48) 287 #define FUNC_DAC_1_U1TXD 2 288 #define FUNC_DAC_1_GPIO17 1 289 #define FUNC_DAC_1_GPIO17_0 0 290 291 #define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c) 292 #define FUNC_DAC_2_CLK_OUT3 3 293 #define FUNC_DAC_2_U1RXD 2 294 #define FUNC_DAC_2_GPIO18 1 295 #define FUNC_DAC_2_GPIO18_0 0 296 297 #define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50) 298 #define FUNC_GPIO19_CLK_OUT2 3 299 #define FUNC_GPIO19_U1RTS 2 300 #define FUNC_GPIO19_GPIO19 1 301 #define FUNC_GPIO19_GPIO19_0 0 302 303 #define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54) 304 #define FUNC_GPIO20_CLK_OUT1 3 305 #define FUNC_GPIO20_U1CTS 2 306 #define FUNC_GPIO20_GPIO20 1 307 #define FUNC_GPIO20_GPIO20_0 0 308 309 #define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58) 310 #define FUNC_GPIO21_GPIO21 1 311 #define FUNC_GPIO21_GPIO21_0 0 312 313 #define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c) 314 #define FUNC_SPICS1_GPIO26 1 315 #define FUNC_SPICS1_SPICS1 0 316 317 #define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70) 318 #define FUNC_SPIHD_GPIO27 1 319 #define FUNC_SPIHD_SPIHD 0 320 321 #define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74) 322 #define FUNC_SPIWP_GPIO28 1 323 #define FUNC_SPIWP_SPIWP 0 324 325 #define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78) 326 #define FUNC_SPICS0_GPIO29 1 327 #define FUNC_SPICS0_SPICS0 0 328 329 #define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c) 330 #define FUNC_SPICLK_GPIO30 1 331 #define FUNC_SPICLK_SPICLK 0 332 333 #define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80) 334 #define FUNC_SPIQ_GPIO31 1 335 #define FUNC_SPIQ_SPIQ 0 336 337 #define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84) 338 #define FUNC_SPID_GPIO32 1 339 #define FUNC_SPID_SPID 0 340 341 #define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88) 342 #define FUNC_GPIO33_SPIIO4 4 343 #define FUNC_GPIO33_SUBSPIHD 3 344 #define FUNC_GPIO33_FSPIHD 2 345 #define FUNC_GPIO33_GPIO33 1 346 #define FUNC_GPIO33_GPIO33_0 0 347 348 #define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c) 349 #define FUNC_GPIO34_SPIIO5 4 350 #define FUNC_GPIO34_SUBSPICS0 3 351 #define FUNC_GPIO34_FSPICS0 2 352 #define FUNC_GPIO34_GPIO34 1 353 #define FUNC_GPIO34_GPIO34_0 0 354 355 #define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90) 356 #define FUNC_GPIO35_SPIIO6 4 357 #define FUNC_GPIO35_SUBSPID 3 358 #define FUNC_GPIO35_FSPID 2 359 #define FUNC_GPIO35_GPIO35 1 360 #define FUNC_GPIO35_GPIO35_0 0 361 362 #define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94) 363 #define FUNC_GPIO36_SPIIO7 4 364 #define FUNC_GPIO36_SUBSPICLK 3 365 #define FUNC_GPIO36_FSPICLK 2 366 #define FUNC_GPIO36_GPIO36 1 367 #define FUNC_GPIO36_GPIO36_0 0 368 369 #define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98) 370 #define FUNC_GPIO37_SPIDQS 4 371 #define FUNC_GPIO37_SUBSPIQ 3 372 #define FUNC_GPIO37_FSPIQ 2 373 #define FUNC_GPIO37_GPIO37 1 374 #define FUNC_GPIO37_GPIO37_0 0 375 376 #define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c) 377 #define FUNC_GPIO38_SUBSPIWP 3 378 #define FUNC_GPIO38_FSPIWP 2 379 #define FUNC_GPIO38_GPIO38 1 380 #define FUNC_GPIO38_GPIO38_0 0 381 382 #define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0) 383 #define FUNC_MTCK_SUBSPICS1 3 384 #define FUNC_MTCK_CLK_OUT3 2 385 #define FUNC_MTCK_GPIO39 1 386 #define FUNC_MTCK_MTCK 0 387 388 #define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4) 389 #define FUNC_MTDO_CLK_OUT2 2 390 #define FUNC_MTDO_GPIO40 1 391 #define FUNC_MTDO_MTDO 0 392 393 #define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8) 394 #define FUNC_MTDI_CLK_OUT1 2 395 #define FUNC_MTDI_GPIO41 1 396 #define FUNC_MTDI_MTDI 0 397 398 #define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac) 399 #define FUNC_MTMS_GPIO42 1 400 #define FUNC_MTMS_MTMS 0 401 402 #define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0) 403 #define FUNC_U0TXD_CLK_OUT1 2 404 #define FUNC_U0TXD_GPIO43 1 405 #define FUNC_U0TXD_U0TXD 0 406 407 #define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4) 408 #define FUNC_U0RXD_CLK_OUT2 2 409 #define FUNC_U0RXD_GPIO44 1 410 #define FUNC_U0RXD_U0RXD 0 411 412 #define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8) 413 #define FUNC_GPIO45_GPIO45 1 414 #define FUNC_GPIO45_GPIO45_0 0 415 416 #define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc) 417 #define FUNC_GPIO46_GPIO46 1 418 #define FUNC_GPIO46_GPIO46_0 0 419 420 #define PERIPHS_IO_MUX_SPICLK_P_U (REG_IO_MUX_BASE +0xc0) 421 #define FUNC_SPICLK_P_SUBSPICLK_DIFF 2 422 #define FUNC_SPICLK_P_GPIO47 1 423 #define FUNC_SPICLK_P_SPICLK_DIFF 0 424 425 #define PERIPHS_IO_MUX_SPICLK_N_U (REG_IO_MUX_BASE +0xc4) 426 #define FUNC_SPICLK_N_SUBSPICLK_DIFF 2 427 #define FUNC_SPICLK_N_GPIO48 1 428 #define FUNC_SPICLK_N_SPICLK_DIFF 0 429 430 431 #define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) 432 #define IO_MUX_DATE 0xFFFFFFFF 433 #define IO_MUX_DATE_S 0 434 #define IO_MUX_DATE_VERSION 0x1907160 435
