1 /****************************************************************************** 2 * * 3 * License Agreement * 4 * * 5 * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * 6 * All rights reserved. * 7 * * 8 * Permission is hereby granted, free of charge, to any person obtaining a * 9 * copy of this software and associated documentation files (the "Software"), * 10 * to deal in the Software without restriction, including without limitation * 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 12 * and/or sell copies of the Software, and to permit persons to whom the * 13 * Software is furnished to do so, subject to the following conditions: * 14 * * 15 * The above copyright notice and this permission notice shall be included in * 16 * all copies or substantial portions of the Software. * 17 * * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 24 * DEALINGS IN THE SOFTWARE. * 25 * * 26 * * 27 ******************************************************************************/ 28 29 #ifndef __ALTERA_AVALON_TIMER_REGS_H__ 30 #define __ALTERA_AVALON_TIMER_REGS_H__ 31 32 #include <io.h> 33 34 /* STATUS register */ 35 #define ALTERA_AVALON_TIMER_STATUS_REG 0 36 #define IOADDR_ALTERA_AVALON_TIMER_STATUS(base) \ 37 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_STATUS_REG) 38 #define IORD_ALTERA_AVALON_TIMER_STATUS(base) \ 39 IORD(base, ALTERA_AVALON_TIMER_STATUS_REG) 40 #define IOWR_ALTERA_AVALON_TIMER_STATUS(base, data) \ 41 IOWR(base, ALTERA_AVALON_TIMER_STATUS_REG, data) 42 #define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1) 43 #define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0) 44 #define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2) 45 #define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1) 46 47 /* CONTROL register */ 48 #define ALTERA_AVALON_TIMER_CONTROL_REG 1 49 #define IOADDR_ALTERA_AVALON_TIMER_CONTROL(base) \ 50 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_CONTROL_REG) 51 #define IORD_ALTERA_AVALON_TIMER_CONTROL(base) \ 52 IORD(base, ALTERA_AVALON_TIMER_CONTROL_REG) 53 #define IOWR_ALTERA_AVALON_TIMER_CONTROL(base, data) \ 54 IOWR(base, ALTERA_AVALON_TIMER_CONTROL_REG, data) 55 #define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1) 56 #define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0) 57 #define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2) 58 #define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1) 59 #define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4) 60 #define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2) 61 #define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8) 62 #define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3) 63 64 /* Period and SnapShot Register for COUNTER_SIZE = 32 */ 65 /*----------------------------------------------------*/ 66 /* PERIODL register */ 67 #define ALTERA_AVALON_TIMER_PERIODL_REG 2 68 #define IOADDR_ALTERA_AVALON_TIMER_PERIODL(base) \ 69 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODL_REG) 70 #define IORD_ALTERA_AVALON_TIMER_PERIODL(base) \ 71 IORD(base, ALTERA_AVALON_TIMER_PERIODL_REG) 72 #define IOWR_ALTERA_AVALON_TIMER_PERIODL(base, data) \ 73 IOWR(base, ALTERA_AVALON_TIMER_PERIODL_REG, data) 74 #define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF) 75 #define ALTERA_AVALON_TIMER_PERIODL_OFST (0) 76 77 /* PERIODH register */ 78 #define ALTERA_AVALON_TIMER_PERIODH_REG 3 79 #define IOADDR_ALTERA_AVALON_TIMER_PERIODH(base) \ 80 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODH_REG) 81 #define IORD_ALTERA_AVALON_TIMER_PERIODH(base) \ 82 IORD(base, ALTERA_AVALON_TIMER_PERIODH_REG) 83 #define IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data) \ 84 IOWR(base, ALTERA_AVALON_TIMER_PERIODH_REG, data) 85 #define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF) 86 #define ALTERA_AVALON_TIMER_PERIODH_OFST (0) 87 88 /* SNAPL register */ 89 #define ALTERA_AVALON_TIMER_SNAPL_REG 4 90 #define IOADDR_ALTERA_AVALON_TIMER_SNAPL(base) \ 91 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPL_REG) 92 #define IORD_ALTERA_AVALON_TIMER_SNAPL(base) \ 93 IORD(base, ALTERA_AVALON_TIMER_SNAPL_REG) 94 #define IOWR_ALTERA_AVALON_TIMER_SNAPL(base, data) \ 95 IOWR(base, ALTERA_AVALON_TIMER_SNAPL_REG, data) 96 #define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF) 97 #define ALTERA_AVALON_TIMER_SNAPL_OFST (0) 98 99 /* SNAPH register */ 100 #define ALTERA_AVALON_TIMER_SNAPH_REG 5 101 #define IOADDR_ALTERA_AVALON_TIMER_SNAPH(base) \ 102 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPH_REG) 103 #define IORD_ALTERA_AVALON_TIMER_SNAPH(base) \ 104 IORD(base, ALTERA_AVALON_TIMER_SNAPH_REG) 105 #define IOWR_ALTERA_AVALON_TIMER_SNAPH(base, data) \ 106 IOWR(base, ALTERA_AVALON_TIMER_SNAPH_REG, data) 107 #define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF) 108 #define ALTERA_AVALON_TIMER_SNAPH_OFST (0) 109 110 /* Period and SnapShot Register for COUNTER_SIZE = 64 */ 111 /*----------------------------------------------------*/ 112 /* PERIOD_0 register */ 113 #define ALTERA_AVALON_TIMER_PERIOD_0_REG 2 114 #define IOADDR_ALTERA_AVALON_TIMER_PERIOD_0(base) \ 115 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_0_REG) 116 #define IORD_ALTERA_AVALON_TIMER_PERIOD_0(base) \ 117 IORD(base, ALTERA_AVALON_TIMER_PERIOD_0_REG) 118 #define IOWR_ALTERA_AVALON_TIMER_PERIOD_0(base, data) \ 119 IOWR(base, ALTERA_AVALON_TIMER_PERIOD_0_REG, data) 120 #define ALTERA_AVALON_TIMER_PERIOD_0_MSK (0xFFFF) 121 #define ALTERA_AVALON_TIMER_PERIOD_0_OFST (0) 122 123 /* PERIOD_1 register */ 124 #define ALTERA_AVALON_TIMER_PERIOD_1_REG 3 125 #define IOADDR_ALTERA_AVALON_TIMER_PERIOD_1(base) \ 126 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_1_REG) 127 #define IORD_ALTERA_AVALON_TIMER_PERIOD_1(base) \ 128 IORD(base, ALTERA_AVALON_TIMER_PERIOD_1_REG) 129 #define IOWR_ALTERA_AVALON_TIMER_PERIOD_1(base, data) \ 130 IOWR(base, ALTERA_AVALON_TIMER_PERIOD_1_REG, data) 131 #define ALTERA_AVALON_TIMER_PERIOD_1_MSK (0xFFFF) 132 #define ALTERA_AVALON_TIMER_PERIOD_1_OFST (0) 133 134 /* PERIOD_2 register */ 135 #define ALTERA_AVALON_TIMER_PERIOD_2_REG 4 136 #define IOADDR_ALTERA_AVALON_TIMER_PERIOD_2(base) \ 137 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_2_REG) 138 #define IORD_ALTERA_AVALON_TIMER_PERIOD_2(base) \ 139 IORD(base, ALTERA_AVALON_TIMER_PERIOD_2_REG) 140 #define IOWR_ALTERA_AVALON_TIMER_PERIOD_2(base, data) \ 141 IOWR(base, ALTERA_AVALON_TIMER_PERIOD_2_REG, data) 142 #define ALTERA_AVALON_TIMER_PERIOD_2_MSK (0xFFFF) 143 #define ALTERA_AVALON_TIMER_PERIOD_2_OFST (0) 144 145 /* PERIOD_3 register */ 146 #define ALTERA_AVALON_TIMER_PERIOD_3_REG 5 147 #define IOADDR_ALTERA_AVALON_TIMER_PERIOD_3(base) \ 148 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_3_REG) 149 #define IORD_ALTERA_AVALON_TIMER_PERIOD_3(base) \ 150 IORD(base, ALTERA_AVALON_TIMER_PERIOD_3_REG) 151 #define IOWR_ALTERA_AVALON_TIMER_PERIOD_3(base, data) \ 152 IOWR(base, ALTERA_AVALON_TIMER_PERIOD_3_REG, data) 153 #define ALTERA_AVALON_TIMER_PERIOD_3_MSK (0xFFFF) 154 #define ALTERA_AVALON_TIMER_PERIOD_3_OFST (0) 155 156 /* SNAP_0 register */ 157 #define ALTERA_AVALON_TIMER_SNAP_0_REG 6 158 #define IOADDR_ALTERA_AVALON_TIMER_SNAP_0(base) \ 159 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_0_REG) 160 #define IORD_ALTERA_AVALON_TIMER_SNAP_0(base) \ 161 IORD(base, ALTERA_AVALON_TIMER_SNAP_0_REG) 162 #define IOWR_ALTERA_AVALON_TIMER_SNAP_0(base, data) \ 163 IOWR(base, ALTERA_AVALON_TIMER_SNAP_0_REG, data) 164 #define ALTERA_AVALON_TIMER_SNAP_0_MSK (0xFFFF) 165 #define ALTERA_AVALON_TIMER_SNAP_0_OFST (0) 166 167 /* SNAP_1 register */ 168 #define ALTERA_AVALON_TIMER_SNAP_1_REG 7 169 #define IOADDR_ALTERA_AVALON_TIMER_SNAP_1(base) \ 170 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_1_REG) 171 #define IORD_ALTERA_AVALON_TIMER_SNAP_1(base) \ 172 IORD(base, ALTERA_AVALON_TIMER_SNAP_1_REG) 173 #define IOWR_ALTERA_AVALON_TIMER_SNAP_1(base, data) \ 174 IOWR(base, ALTERA_AVALON_TIMER_SNAP_1_REG, data) 175 #define ALTERA_AVALON_TIMER_SNAP_1_MSK (0xFFFF) 176 #define ALTERA_AVALON_TIMER_SNAP_1_OFST (0) 177 178 /* SNAP_2 register */ 179 #define ALTERA_AVALON_TIMER_SNAP_2_REG 8 180 #define IOADDR_ALTERA_AVALON_TIMER_SNAP_2(base) \ 181 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_2_REG) 182 #define IORD_ALTERA_AVALON_TIMER_SNAP_2(base) \ 183 IORD(base, ALTERA_AVALON_TIMER_SNAP_2_REG) 184 #define IOWR_ALTERA_AVALON_TIMER_SNAP_2(base, data) \ 185 IOWR(base, ALTERA_AVALON_TIMER_SNAP_2_REG, data) 186 #define ALTERA_AVALON_TIMER_SNAP_2_MSK (0xFFFF) 187 #define ALTERA_AVALON_TIMER_SNAP_2_OFST (0) 188 189 /* SNAP_3 register */ 190 #define ALTERA_AVALON_TIMER_SNAP_3_REG 9 191 #define IOADDR_ALTERA_AVALON_TIMER_SNAP_3(base) \ 192 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_3_REG) 193 #define IORD_ALTERA_AVALON_TIMER_SNAP_3(base) \ 194 IORD(base, ALTERA_AVALON_TIMER_SNAP_3_REG) 195 #define IOWR_ALTERA_AVALON_TIMER_SNAP_3(base, data) \ 196 IOWR(base, ALTERA_AVALON_TIMER_SNAP_3_REG, data) 197 #define ALTERA_AVALON_TIMER_SNAP_3_MSK (0xFFFF) 198 #define ALTERA_AVALON_TIMER_SNAP_3_OFST (0) 199 200 #endif /* __ALTERA_AVALON_TIMER_REGS_H__ */ 201
